CN118099043A - Automatic packaging system based on leadless packaging chip - Google Patents
Automatic packaging system based on leadless packaging chip Download PDFInfo
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Abstract
The invention discloses an automatic packaging system based on a pin-free packaging chip, which comprises a packaging chip image acquisition end, an image processing end and a central information analysis end, relates to the technical field of chip automatic packaging, and solves the technical problems that the existing defects are not well positioned and analyzed, the defects of the chip are not analyzed for functional influence and production waste are caused.
Description
Technical Field
The invention relates to the technical field of chip automatic packaging, in particular to an automatic packaging system based on a leadless packaged chip.
Background
Before the integrated circuit chip is assembled, the integrated circuit chip needs to be packaged in different packaging modes for protecting the chip and enhancing the electrothermal performance, the chip packaging defect detection necessity exists, and the detection source mainly aims at internal defects and surface defects.
According to the patent display with the application number of CN202311186315.5, fixing a packaging chip to be detected in a positioning area and generating a positioning completion signal, activating a miniature industrial camera to acquire a surface image of the packaging body, activating an ultrasonic detector to acquire an internal ultrasonic waveform image, and performing defect detection on the surface image of the packaging body by matching with a packaging chip template to acquire surface defect information; and performing defect detection on the internal ultrasonic waveform image by matching the waveform baseline information to obtain internal defect information.
The above-mentioned patent is through carrying out inside and outside dual detection to the chip, realize improving the defect detection rate on the basis of guaranteeing the detection accuracy, but partial current automatic packaging system of chip, when carrying out encapsulation and detection to the chip, although can realize the detection to the chip, but can not pinpoint the position of defect, secondly after confirming the defect, the influence that causes to the defect does not carry out fine analysis, further can't carry out the accuracy judgement to the chip function, can cause the production waste of chip, and simultaneously to the mechanical equipment that the encapsulation exists the defect, do not combine production data to carry out reasonable analysis to mechanical equipment, thereby inconvenient follow-up improvement to encapsulation machinery.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides an automatic packaging system based on a leadless packaging chip, which solves the problems that the existing defects are not well positioned and analyzed, and meanwhile, the defects of the chip are not analyzed for functional influence, so that the production waste is caused.
In order to achieve the above purpose, the invention is realized by the following technical scheme: the automatic packaging system based on the leadless packaged chip comprises a packaged chip image acquisition end, an image processing end, an edge information analysis end, a central information analysis end and a display end.
The image acquisition end of the packaged chip firstly acquires the image of the packaged chip, simultaneously generates image information according to the acquired image in an integrating way, transmits the image information to the image processing end, and the acquired image shoots the whole packaged chip through the high-definition camera.
The image processing end analyzes the acquired image information, judges whether the packaged chip has defects or not by identifying the image, and the specific analysis mode is as follows:
The method comprises the steps of obtaining an encapsulated chip image, carrying out four equal division on the encapsulated chip image, wherein the dividing standard is that the encapsulated chip image is subjected to four equal division in the transverse direction and the longitudinal direction by taking the center of the encapsulated chip as an origin, obtaining four equal division images after equal division, and obtaining a standard image, wherein the standard image represents an encapsulated chip high-definition image without any defect, and carrying out four equal division on the standard image to obtain a standard equal division image;
respectively carrying out label processing on the average image and the standard average image, simultaneously carrying out matching on two groups of images with the same label, for example, carrying out label marking on four average images obtained after the average of the packaged chip images as 1,2, 3 and 4 according to clockwise, carrying out label marking on the picture at the upper left corner as 1, and the like, carrying out the same label processing on the average standard image, then carrying out matching on the average image with the label as 1 and the standard average image, and the like, judging whether two groups of images with the same label have differences, if the two groups of images with the same label do not have differences, indicating that the corresponding area of the packaged chip does not have defects, classifying the average image into normal images, if the two groups of images with the same label have differences, indicating that the corresponding area of the packaged chip has defects, classifying the average image into abnormal images, and simultaneously comparing and screening the four images according to the matching mode.
And classifying the packaged chips by screening the equipartition images, classifying the packaged chips into defective products if abnormal images exist in the four equipartition images, otherwise classifying the packaged chips into normal products if all the four equipartition images are normal images, and not performing any treatment if the packaged chips are normal products.
Acquiring an image of a packaged chip corresponding to a defective product, establishing a rectangular coordinate system by taking a central point as an origin, simultaneously marking all the defective points on the image of the packaged chip, generating a defective area of the defective product by using all the defective points, analyzing the position of the defective area, judging whether the defective area is positioned at the edge position or the central position of the defective product, indicating that the defect is a central defect and generating central position information if the defective area is positioned at the central area of the packaged chip, otherwise, indicating that the defect is an edge defect if the defective area is not positioned at the central area, simultaneously generating edge position information, transmitting the edge position information to an edge information analysis end, and transmitting the central position information to a central information analysis end.
The central information analysis end acquires the transmitted central position information and judges whether the current position defect is generated to influence the whole chip or not, and the specific judging mode is as follows:
Obtaining voltage and current corresponding to a defective product in a time period t, judging the change condition of the voltage and current corresponding to the defective product in the time period t, classifying the change condition into a stable condition and an unstable condition, wherein the classification standard is that the change amplitude of the voltage and the current is within a range of 0-0.5, if the change amplitude is within the range, the change amplitude is stable, otherwise, the change amplitude is unstable, if the change amplitude is not within the range, the change amplitude is not stable, and if the change amplitude is not within the range, the change amplitude is not stable, the change amplitude is not high, the chip is not processed, meanwhile, the highlight marking is carried out on the chip, defect information is generated, and meanwhile, the defect information is transmitted to a display end;
If any group of data of voltage and current has unstable condition in the time period t, further analysis is needed, the power supply condition in the time period t is judged, the specific power supply condition is represented as the change condition of the voltage and the current when the chip is supplied, if the power supply condition is unstable in the time period t, the whole chip is unstable due to power supply, then the voltage and the current change corresponding to the abnormal chip under the condition that the power supply condition is stable is obtained, if the abnormal chip still has unstable condition in the power supply condition, the abnormal chip is not caused to be unstable due to the power supply condition, the abnormal information is generated, if the abnormal chip has stable condition, the abnormal chip is caused to be unstable due to the power supply condition, the abnormal information is generated, the abnormal chip is marked in the same way, and the abnormal chip is transmitted to the display end.
The edge information analysis end is used for acquiring the transmitted edge position information and analyzing according to the defect characteristics corresponding to the edge position information, and the specific analysis mode is as follows:
Obtaining all defect products in a time period T, meanwhile, comparing the similarity of the defect products, wherein the specific similarity comparison is represented by analyzing the coincidence degree of defect shapes of the defect products, classifying the defect products according to the similarity, for example, classifying the defect products with the similarity of 80%, 70% or 60%, obtaining defect classified products which are marked as i, and the number of the defect products with the dissimilarity is marked as Si, and meanwhile, calculating the corresponding defect occupation ratio according to the number of the defect products, wherein the specific calculation mode is as follows:
marking all packaging machines as n, wherein n=1, 2, … and m, obtaining the number of all packaging products of the marking packaging machine n in a time period T as Sn, calculating the occupation ratio according to the number Si of defective products, sequencing the occupation ratio from large to small, comparing the occupation ratio with a preset value, taking a specific value of the preset value according to the value in actual production, screening the packaging machines with the occupation ratio larger than the preset value, and marking the packaging machines as machines to be analyzed;
and then analyzing the quantity Si of the products with different similarity defects of the machinery to be analyzed, analyzing the distribution situation of the similarity of the products with the similarity defects, carrying out distributed production or centralized production classification on the machinery to be analyzed according to the similarity, generating corresponding distribution information, and transmitting the distribution information to a display end.
Specifically, the distributed production indicates that there is diversity in the similarity of the defect products corresponding to the mechanical production to be analyzed, for example, three defect products with the similarity of 80%, 70% and 60% exist, and for such cases, the distributed production is classified, while the centralized production indicates that there is singleness in the similarity, and only single defect products with the similarity of 80%, 70% or 60% exist.
And the display end is used for displaying the acquired distribution information to an operator.
The invention provides an automatic packaging system based on a leadless packaged chip. Compared with the prior art, the method has the following beneficial effects:
According to the invention, the defects are detected according to the images of the chips, the specific positions of the defects are monitored and positioned for the chips with the defects, and the specific influence of the defects on the whole is analyzed according to the obtained specific positions, so that the follow-up improvement of production is facilitated, the analysis of the packaging mechanical equipment is carried out according to the produced defective chips, the distribution condition of the whole defective products of the packaging machinery is judged by analyzing the similarity of the defective products, and the packaging machinery is regulated in different modes according to the distribution condition of the defective products, so that the probability of defects in the production process is reduced, and the production efficiency is improved.
Drawings
FIG. 1 is a schematic diagram of a system of the present invention;
FIG. 2 is a schematic diagram of defect locations according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1 and 2, the present application provides an automated packaging system based on leadless packaged chips, comprising: the device comprises an encapsulated chip image acquisition end, an image processing end, an edge information analysis end, a central information analysis end and a display end.
Example 1
The image acquisition end of the packaged chip firstly acquires the image of the packaged chip, simultaneously generates image information according to the acquired image in an integrating way, transmits the image information to the image processing end, and the acquired image shoots the whole packaged chip through the high-definition camera.
The image processing end analyzes the acquired image information, judges whether the packaged chip has defects or not by identifying the image, and the specific analysis mode is as follows:
The method comprises the steps of obtaining an encapsulated chip image, carrying out four equal division on the encapsulated chip image, wherein the dividing standard is that the encapsulated chip image is subjected to four equal division in the transverse direction and the longitudinal direction by taking the center of the encapsulated chip as an origin, obtaining four equal division images after equal division, and obtaining a standard image, wherein the standard image represents an encapsulated chip high-definition image without any defect, and carrying out four equal division on the standard image to obtain a standard equal division image;
respectively carrying out label processing on the average image and the standard average image, simultaneously carrying out matching on two groups of images with the same label, for example, carrying out label marking on four average images obtained after the average of the packaged chip images as 1,2, 3 and 4 according to clockwise, carrying out label marking on the picture at the upper left corner as 1, and the like, carrying out the same label processing on the average standard image, then carrying out matching on the average image with the label as 1 and the standard average image, and the like, judging whether two groups of images with the same label have differences, if the two groups of images with the same label do not have differences, indicating that the corresponding area of the packaged chip does not have defects, classifying the average image into normal images, if the two groups of images with the same label have differences, indicating that the corresponding area of the packaged chip has defects, classifying the average image into abnormal images, and simultaneously comparing and screening the four images according to the matching mode.
And classifying the packaged chips by screening the equipartition images, classifying the packaged chips into defective products if abnormal images exist in the four equipartition images, otherwise classifying the packaged chips into normal products if all the four equipartition images are normal images, and not performing any treatment if the packaged chips are normal products.
Acquiring an image of a packaged chip corresponding to a defective product, establishing a rectangular coordinate system by taking a central point as an origin, simultaneously marking all the defective points on the image of the packaged chip, generating a defective area of the defective product by using all the defective points, analyzing the position of the defective area, judging whether the defective area is positioned at the edge position or the central position of the defective product, indicating that the defect is a central defect and generating central position information if the defective area is positioned at the central area of the packaged chip, otherwise, indicating that the defect is an edge defect if the defective area is not positioned at the central area, simultaneously generating edge position information, transmitting the edge position information to an edge information analysis end, and transmitting the central position information to a central information analysis end.
In combination with the actual analysis, for example, as shown in fig. 2, if the defect is located at the periphery of the central area of the overall image, the defect is indicated to be an edge defect, if the defect is located at the central area of the overall image, the defect is indicated to be a center defect, corresponding defect information is further generated, when the chip is packaged, the damage to the chip may be caused by misoperation, similar damage may exist in different positions, and the influence of damage to the whole chip caused by different degrees is different.
For example, defects of a chip, such as a transistor structure, may cause a slow operation speed and a reduced processing capacity, and cannot meet design standards;
defects may cause unstable phenomena of the chip at the time of operation, such as random restarting or jamming, which may affect the user experience and may cause data loss;
if the power supply part of the chip has defects, voltage instability can be caused, and the normal operation of the whole system is affected.
Example two
As a second embodiment of the present invention, there is a difference from the first embodiment in that the center information analysis terminal is configured to analyze the acquired center position information.
The central information analysis end acquires the transmitted central position information and judges whether the current position defect is generated to influence the whole chip or not, and the specific judging mode is as follows:
Obtaining voltage and current corresponding to a defective product in a time period t, judging the change condition of the voltage and current corresponding to the defective product in the time period t, classifying the change condition into a stable condition and an unstable condition, wherein the classification standard is that the change amplitude of the voltage and the current is within a range of 0-0.5, if the change amplitude is within the range, the change amplitude is stable, otherwise, the change amplitude is unstable, if the change amplitude is not within the range, the change amplitude is not stable, and if the change amplitude is not within the range, the change amplitude is not stable, the change amplitude is not high, the chip is not processed, meanwhile, the highlight marking is carried out on the chip, defect information is generated, and meanwhile, the defect information is transmitted to a display end;
If any group of data of voltage and current has unstable condition in the time period t, further analysis is needed, the power supply condition in the time period t is judged, the specific power supply condition is represented as the change condition of the voltage and the current when the chip is supplied, if the power supply condition is unstable in the time period t, the whole chip is unstable due to power supply, then the voltage and the current change corresponding to the abnormal chip under the condition that the power supply condition is stable is obtained, if the abnormal chip still has unstable condition in the power supply condition, the abnormal chip is not caused to be unstable due to the power supply condition, the abnormal information is generated, if the abnormal chip has stable condition, the abnormal chip is caused to be unstable due to the power supply condition, the abnormal information is generated, the abnormal chip is marked in the same way, and the abnormal chip is transmitted to the display end.
In practice, the chip is unstable due to voltage and current factors during use, and if the power supply is insufficient during use, current fluctuation is further caused, and firstly, the power consumption and heat generation of the chip are affected by the current change. When the current demand of the chip changes, voltage disturbances may occur in a small local area of the power plane, which may affect the stability and performance of the chip. If the current is too high, it may cause the chip to overheat, thereby affecting the speed and lifetime of the chip.
Second, the stability of the voltage is critical to the proper operation of the chip. If the power supply voltage is too close to the working voltage, power supply fluctuation noise and external interference can have a large influence on the circuit, and the circuit performance can be reduced. If the voltage is too high, excessive electrical strain may be generated, resulting in chip damage. At the same time, the power supply voltage variation of the chip also affects the speed and performance thereof. For example, after the voltage drops, the chip may slow down; as the voltage increases, the chip will become faster.
The display end is used for acquiring the transmitted power supply abnormality information or defect information and displaying the power supply abnormality information or defect information to an operator.
Example III
As an embodiment three of the present invention, the difference between the embodiment one and the embodiment two is that the edge information analysis end is used for analyzing the obtained edge position information.
The edge information analysis end is used for acquiring the transmitted edge position information and analyzing according to the defect characteristics corresponding to the edge position information, and the specific analysis mode is as follows:
Obtaining all defect products in a time period T, meanwhile, comparing the similarity of the defect products, wherein the specific similarity comparison is represented by analyzing the coincidence degree of defect shapes of the defect products, classifying the defect products according to the similarity, for example, classifying the defect products with the similarity of 80%, 70% or 60%, obtaining defect classified products which are marked as i, and the number of the defect products with the dissimilarity is marked as Si, and meanwhile, calculating the corresponding defect occupation ratio according to the number of the defect products, wherein the specific calculation mode is as follows:
marking all packaging machines as n, wherein n=1, 2, … and m, obtaining the number of all packaging products of the marking packaging machine n in a time period T as Sn, calculating the occupation ratio according to the number Si of defective products, sequencing the occupation ratio from large to small, comparing the occupation ratio with a preset value, taking a specific value of the preset value according to the value in actual production, screening the packaging machines with the occupation ratio larger than the preset value, and marking the packaging machines as machines to be analyzed;
and then analyzing the quantity Si of the products with different similarity defects of the machinery to be analyzed, analyzing the distribution situation of the similarity of the products with the similarity defects, carrying out distributed production or centralized production classification on the machinery to be analyzed according to the similarity, generating corresponding distribution information, and transmitting the distribution information to a display end.
Specifically, the distributed production indicates that there is diversity in the similarity of the defect products corresponding to the mechanical production to be analyzed, for example, three defect products with the similarity of 80%, 70% and 60% exist, and for such cases, the distributed production is classified, while the centralized production indicates that there is singleness in the similarity, and only single defect products with the similarity of 80%, 70% or 60% exist.
And the display end is used for displaying the acquired distribution information to an operator.
In the fourth embodiment, as the fourth embodiment of the present invention, the emphasis is placed on the implementation of the first, second and third embodiments in combination.
Some of the data in the above formulas are numerical calculated by removing their dimensionality, and the contents not described in detail in the present specification are all well known in the prior art.
The above embodiments are only for illustrating the technical method of the present invention and not for limiting the same, and it should be understood by those skilled in the art that the technical method of the present invention may be modified or substituted without departing from the spirit and scope of the technical method of the present invention.
Claims (8)
1. An automated packaging system based on leadless packaged chips, comprising:
the packaged chip image acquisition end is used for acquiring the packaged chip image, generating image information and transmitting the image information to the image processing end;
The image processing end is used for judging the integrity of the packaged chip according to the transmitted image information, equally dividing the image of the packaged chip, matching the equally divided image with the standard image, judging whether the difference exists, classifying the packaged chip as a defective product if the difference exists, classifying the packaged chip as a normal product if the difference does not exist, further carrying out positioning analysis on a defective area aiming at the defective product to generate edge position information or center position information, and transmitting the generated information to the center information analysis end or the edge information analysis end respectively;
The central information analysis end acquires the transmitted central position information, judges whether the defect exists at the central position and affects the whole work according to the voltage and the current of the defect product in the time period t, generates abnormal information or power supply abnormal information, and transmits the abnormal information or power supply abnormal information to the display end;
The edge information analysis end is used for acquiring the transmitted edge position information, classifying according to the similarity of defective products in the time period T, calculating the defect occupation ratio corresponding to the packaging machinery according to the number of the defective products, performing distributed production or centralized production classification on the packaging machinery according to the similarity distribution of the defective products, and transmitting the two to the display end.
2. The automated packaging system based on leadless packaged chips as defined in claim 1, wherein the specific way for the image processing terminal to classify the packaged chips is:
S1: obtaining an image of a packaged chip, equally dividing four equal parts according to the center point of the image as an origin to obtain four equal parts of equal divided images, obtaining a standard image, equally dividing four equal parts to obtain four standard equal divided images, and simultaneously marking the equal divided images;
s2: and carrying out differential matching on the average images with the same labels and the standard average images, classifying the average images into abnormal images if the average images have the differences, classifying the average images into normal images if the average images have the differences, and so on to match all the average images, classifying the packaged chips with the abnormal images into defective products, and classifying the packaged chips without the abnormal images into normal products.
3. The automated packaging system based on leadless packaged chips as defined in claim 1, wherein the specific manner of performing the defect area positioning analysis on the defective product by the image processing terminal is as follows:
Acquiring an image of a packaged chip of a defective product, establishing a rectangular coordinate system by taking the center of the image as an origin, marking all defective points on the image of the packaged chip of the defective product, and then comprehensively and integrally generating a defective area;
When the defect area is located at the periphery of the central area of the packaged chip, edge position information is generated, and when the defect area is located at the central area of the packaged chip, central position information is generated.
4. The automated packaging system based on leadless packaged chips as defined in claim 1, wherein the specific manner in which the central location information terminal analyzes the central location information is:
acquiring voltage and current corresponding to a defective product in a time period t, classifying stable conditions and unstable conditions according to the change conditions of the voltage and the current, if the stable conditions exist in the time period t, not processing, highlighting a chip, generating defect information, and transmitting the defect information to a display end;
If any group of unstable conditions exist in the voltage and the current in the time period t, the voltage and the current are required to be subjected to secondary analysis, so that a power supply condition in the time period t is obtained, a power supply unstable signal is generated when the power supply condition is unstable, and a power supply stable signal is generated when the power supply condition is stable;
if the power supply instability signal is generated, acquiring voltage and current corresponding to the abnormal chip in the stable time period, analyzing the voltage and current change condition of the abnormal chip, generating abnormal information if the voltage and current have an unstable condition, otherwise, generating power supply abnormal information if the voltage and the current are both stable conditions.
5. The automated packaging system based on leadless packaged chips as defined in claim 1, wherein the specific manner of analyzing the obtained edge position information by the edge information analysis terminal is as follows:
Obtaining all defect products in a time period T, classifying according to the similarity of the defect products, marking i as i, i=a, b, c, … and z, and simultaneously obtaining the number of the defect products with the similarity of the corresponding types as Si;
Marking all packaging machines as n, wherein n=1, 2, … and m, obtaining the quantity of all packaging products of the packaging machine n in a time period T as Sn, calculating the quantity ratio of defective products to packaging products, and sequencing the quantity ratio from large to small;
comparing the quantity ratio with a preset value, screening out packaging machines corresponding to the quantity ratio larger than the preset value, and recording the packaging machines as machines to be analyzed.
6. The automated packaging system based on leadless packaged chips as defined by claim 5 wherein the analysis of the machine to be analyzed by the edge information analysis terminal is:
Obtaining the quantity Si of products with different similarity defects of the machinery to be analyzed, and classifying the machinery to be analyzed according to the distribution condition of the products with the similarity defects to obtain production classification information, wherein the specific classification mode is as follows: when the distribution condition is single type similarity, the machinery to be analyzed is centralized production, and when the distribution condition is multi-type similarity, the machinery to be analyzed is decentralized production.
7. The automated packaging system based on leadless packaged chips of claim 1, wherein the display terminal is configured to display the acquired power supply abnormality information, defect information, and production classification information to an operator.
8. The automated packaging system based on leadless packaged chips of claim 1, wherein the packaged chips are electrically connected in one direction between an image acquisition end, an image processing end, an edge information analysis end, a central information analysis end, and a display end.
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| CN201434842Y (en) * | 2009-05-27 | 2010-03-31 | 华南理工大学 | Automatic chip appearance defect detection system |
| CN105335963A (en) * | 2015-09-24 | 2016-02-17 | 凌云光技术集团有限责任公司 | Edge defect detection method and apparatus |
| CN113791084A (en) * | 2021-08-20 | 2021-12-14 | 安徽初代物联科技有限责任公司 | Mini LED wafer appearance defect detection system and method |
| CN116337868A (en) * | 2023-02-28 | 2023-06-27 | 靖江安通电子设备有限公司 | Surface defect detection method and detection system |
| CN117686516A (en) * | 2024-01-29 | 2024-03-12 | 江苏优众微纳半导体科技有限公司 | Automatic chip appearance defect detection system based on machine vision |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201434842Y (en) * | 2009-05-27 | 2010-03-31 | 华南理工大学 | Automatic chip appearance defect detection system |
| CN105335963A (en) * | 2015-09-24 | 2016-02-17 | 凌云光技术集团有限责任公司 | Edge defect detection method and apparatus |
| CN113791084A (en) * | 2021-08-20 | 2021-12-14 | 安徽初代物联科技有限责任公司 | Mini LED wafer appearance defect detection system and method |
| CN116337868A (en) * | 2023-02-28 | 2023-06-27 | 靖江安通电子设备有限公司 | Surface defect detection method and detection system |
| CN117686516A (en) * | 2024-01-29 | 2024-03-12 | 江苏优众微纳半导体科技有限公司 | Automatic chip appearance defect detection system based on machine vision |
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