CN118098334B - Fault testing method of RRAM - Google Patents
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Abstract
The invention belongs to the field of integrated circuits, and discloses a fault test method of RRAM (resistive random access memory), which is used for analyzing fault models of all conventional memories and fault primitives of RRAM specific fault models to obtain a test sequence capable of detecting the fault models; deducing a March-RAWR algorithm which can cover most of conventional memory faults and RRAM specific faults on the basis of the March-C-, march C-1T 1R and other algorithms by using the obtained test sequence; the March-RAWR algorithm is used as a core to construct a built-in self-test MBIST circuit suitable for the RRAM; and injecting faults into the RRAM memory, running an MBIST circuit to perform fault test, and recording the addresses of the fault units. The fault coverage rate of MARCH RAWR algorithm proposed by the method is up to 89.92%. The built-in self-test circuit built by the method has a simple structure and small extra occupied area.
Description
Technical Field
The invention belongs to the field of integrated circuits, and particularly relates to a fault testing method of RRAM.
Background
Resistive Random Access Memory (RRAM) is an emerging memory technology that competes with the mainstream memory technologies Dynamic Random Access Memory (DRAM) and FLASH memory (FLASH). RRAM differs from mainstream memory technology in that data is stored in terms of resistance rather than charge, meaning that RRAM is not subject to scaling limitations associated with charge storage; in addition, the RRAM is a non-volatile memory (NVM), and has advantages of high memory density, low power consumption, and compatibility with back-end-of-line (BEOL) of standard Complementary Metal Oxide Semiconductor (CMOS) process, etc., and is widely used in various fields such as storage technology, memory computing, logic system, etc., so that the RRAM is expected to replace the conventional memory in the future. However, its nanoscale manufacturing process introduces uncertainty, leading to failure and subsequent read errors.
Studies have shown that failures of conventional memories also occur on RRAM, and that RRAM also has special failures that are different from conventional memories. At present, the mainstream algorithm cannot effectively detect the special faults of the RRAM, for example, patent application CN112750486A discloses a fault test method of a resistive random access memory, patent application CN114171100A discloses a test method of a resistive random access memory with high fault coverage rate, simple read-write operation is used for detecting faults of conventional memories such as SA0, SA1, TF0, TF1 and R1D, and the fault coverage rate is not high; patent application CN116343886a discloses a configurable March algorithm based on built-in self test of memory, which designs a configurable March algorithm, although the algorithm can effectively reduce test time, the algorithm is mainly aimed at SRAM and DRAM, and special faults of RRAM are not considered; special faults of RRAM are also difficult to detect.
Disclosure of Invention
In order to solve the technical problems, the invention provides a fault test method of RRAM, which designs an improved test algorithm aiming at the special faults of RRAM, constructs an MBIST circuit suitable for RRAM, can effectively detect the special faults of RRAM, can detect the faults of some conventional memories, and effectively improves the fault coverage rate of RRAM.
The invention relates to a fault test method of RRAM, which comprises the following steps:
Step 1, analyzing fault primitives of RRAM fault models, and deducing a required test sequence according to each fault model;
Step 2, deducing a March-RAWR test algorithm according to a required test sequence;
step3, constructing an MBIST circuit suitable for RRAM according to a March-RAWR algorithm;
and 4, injecting faults into the RRAM, detecting the faults of the RRAM by using an MBIST circuit, and outputting the address information of the fault unit after the test is completed.
Further, the RRAM fault model comprises RRAM special faults and conventional faults, wherein the RRAM special faults comprise Deep faults, USF faults, CFud faults and dCFud faults; the regular faults include static single-unit faults, static double-unit faults, dynamic single-unit faults and dynamic double-unit faults.
Further, the RRAM has five states according to different resistance sizes, namely Deep1, logic 1, USF, logic 0 and Deep0; for the RRAM in an undefined state, setting two resistors R ref1 and R ref0 at the boundary of the USF state to respectively correspond to reference resistors R ref1 and R ref0 for read operation, and R ref0>Rref1 for detecting the USF state of the RRAM; RRAM resistances in Logic 0 and Logic 1 states are R0 and R1, and the reference resistance R r corresponding to R0 and R1 operation is set to be (R 0+R1)/2, so that the 0 state and the 1 state can be effectively distinguished, and the RRAM resistances are used for detecting conventional faults;
For an RRAM cell with USF fault, when the RRAM cell is converted from 0 state to 1 state, the resistance value of the RRAM cell is larger than R ref1 because the fault falls into the USF state; when r ref1 read operations are performed, it can be detected that the RRAM cell is in a non-1 state and is not in accordance with the expected 1 state, thereby detecting that the RRAM fails.
Further, the March-RAWR test algorithm is specifically described as ：{M1↑↓ (w0); M2↑ (rref0 w0 r0n r0 w1 r1 w1 rref1); M3↑ (rref1 w1 r1n r1 w0 r0 w0 rref0); M4↓ (rref0 w0 r0 r0 w1 r1 w1 r1); M5↓ (rref1 w1 r1 r1 w0 r0 w0 r0); M6↑↓ (r0)};
Wherein M1-M6 are elements, +.sup.representing the ascending order of addresses, +.sup.representing the descending order of addresses, +.sup. ∈representing the ascending order of addresses or the descending order of addresses, w0 represents writing 0 data to the selected memory cell, and w1 represents writing 1 data to the selected memory cell; r0 represents a read 0 operation on the selected memory cell, where the expected data value of the memory cell is 0; r1 represents a read 1 operation performed on the selected memory cell, where the expected data value of the memory cell is 1; r0 n represents n consecutive read 0 operations on the selected memory cell; r1 n represents n consecutive read 1 operations on the selected memory cell; r ref1,rref0 represents a read operation for detecting a RRAM special failure.
Further, the MBIST circuit comprises:
a control generator: controlling each module of the whole MBIST circuit to sequentially execute a March-RAWR test algorithm according to the sequence of M1-M6;
an address generator: generating address signals required by a March-RAWR test algorithm;
a data generator: generating a data signal required by a March-RAWR test algorithm;
a comparator: comparing the difference between the actual data and the expected data of the RRAM read by the memory, checking whether the read-write value of the memory is correct, and if so, outputting a signal test_fail to be low, wherein the fault address recorder does not record information; if the error occurs, the output signal test_fail is high, and the fault address recorder records the address of the storage unit with the fault;
Fault address recorder: for recording the address of the faulty memory cell and outputting the specific faulty cell address via the address signal Fail _ ADR.
Further, the RRAM comprises a peripheral circuit, a memristor array, a sense amplifier and a reference resistor;
the peripheral circuit receives the MBIST circuit signal or the external logic signal, is controlled by the MUX selector, receives the external logic signal when the bist_en signal is 0, and receives the MBIST circuit signal when the bist_en signal is 1. The peripheral circuit decodes after receiving the signal and outputs an output signal to the memristor array;
The two input ends of the sense amplifier are connected with the output signals R inx of the memristor array at one end, and x represents the column number of the selected storage unit; the other end is connected with an output signal R ref of the reference resistor; under normal conditions, the sense amplifier only has a reference resistor with a fixed resistance, and in order to detect the specific faults of RRAM, the invention sets three reference resistors with different resistance values, and is connected with the sense amplifier through a data selector MUX with one fourth; the fourth data selector selects a reference resistor with a corresponding size by controlling the enabling end; the reference resistances are R ref0,Rr and R ref1 from large to small, respectively, the R ref0 resistance is selected when the read operation is R ref0, the R ref1 resistance is selected when the read operation is R ref1, and the R r resistance is selected when the read operation is R0 and R1.
Further, the fault detection process is as follows:
Step 4-1, injecting faults into the RRAM memory:
Step 4-2, entering test mode by MBIST circuit, and sequentially executing March-RAWR algorithm {M1↑↓ (w0); M2↑ (rref0 w0 r0n r0 w1 r1 w1 rref1); M3↑ (rref1 w1 r1n r1 w0 r0 w0 rref0); M4↓ (rref0w0 r0 r0 w1 r1 w1 r1); M5↓ (rref1 w1 r1 r1 w0 r0 w0 r0); M6↑↓ (r0)};
And 4-3, when the algorithm performs a reading operation, the sensitive amplifier converts the information stored in the corresponding RRAM storage unit into a digital signal and outputs the digital signal to the comparator, and the comparator compares the actual signal with the expected signal. If the actual result is different from the expected result, indicating that the RRAM memory has faults; after the algorithm execution of step 4-4 is finished, if there is a fault in the RRAM memory, the test_fail signal of the comparator is pulled high, and the fault address recorder records the address of the fault unit.
The beneficial effects of the invention are as follows: according to the method, a March-RAWR algorithm capable of effectively covering most fault models is deduced by analyzing a conventional fault model and a specific fault model of the RRAM, the time complexity of the algorithm is 32N+2nN (N is more than or equal to 1 and less than or equal to 10) (N represents the number of March elements in the algorithm, N represents the number of continuous reading), all static single unit faults, static double unit faults, most dynamic single unit faults, dynamic double unit faults and RRAM special faults can be covered, and the fault coverage rate is up to 89.92%; meanwhile, compared with the conventional built-in self-test circuit, the built-in self-test circuit designed according to the March-RAWR algorithm in the method provided by the invention has the advantages that only one data selector is added to the sense amplifier part, and the required reference resistance can be selected according to algorithm elements, so that the test circuit can be used as a substitute of the conventional built-in self-test circuit, and the additional added area is small.
Drawings
FIG. 1 is a flow chart of the method of the present invention;
FIG. 2 is a RRAM state diagram;
FIG. 3 is a built-in self-test MBIST graph;
Fig. 4 is a schematic diagram of fault injection.
Detailed Description
In order that the invention may be more readily understood, a more particular description of the invention will be rendered by reference to specific embodiments that are illustrated in the appended drawings.
The invention discloses a fault test method of RRAM, as shown in figure 1, comprising the following steps:
and step 1, analyzing fault primitives of a common memory fault model and RRAM special fault models, and deducing a required test sequence according to each fault model.
In this embodiment, by analyzing the fault model of the RRAM, all the considered fault models and the fault primitives thereof are shown in table 1. Table 1 contains static single cell faults, static double cell faults, dynamic single cell faults, dynamic double cell faults, and RRAM special faults. It should be noted that the March-RAWR algorithm proposed by the present invention is to cover as many fault models as possible with a small time complexity, and does not include all memory fault models.
TABLE 1 failure model and failure primitives
Unlike the general memory SRAM, DRAM, RRAM has 5 storage states (0, 1, deep0, deep1, usf) in total, as shown in fig. 2. In fig. 2, R 1 represents the minimum resistance of the RRAM in the 1 state, R 0 represents the maximum resistance of the RRAM in the 0 state, and R ref1 and R ref0 represent the boundary resistance of the USF state, respectively. In table 1, D1 represents Deep1, D0 represents Deep0, and U represents USF. If only r0 and r1 are used, the two read operations can only distinguish between the 0 and 1 states, and the memristor in the USF state cannot be detected; the USF is a fault state to be detected, and the invention designs r ref0 and r ref1 to correspond to the boundary resistance value of the USF state, and can distinguish the USF state from the 0 and 1 states when the two operations are carried out.
In order to detect the fault model of the memory, a sensitization sequence and a detection sequence required by the fault are deduced according to the fault primitive, so that elements in the March-RAWR algorithm need to enable the fault to be detected through the sensitization sequence, and then whether the storage unit has the fault is judged through the detection sequence.
For the special faults of the RRAM, the Deep fault indicates that one RRAM cell is written with 0 or 1 according to stored information on the basis of stored information 0 or 1, so that the RRAM cell is in Deep 0 or Deep 1 fault, and at the moment, a value opposite to the stored value is written into the RRAM cell again, and the state of the RRAM is not changed. The detection can be performed by a conventional read operation, and the faults USF, CFud, dCFud and the like mean that the read-write operation on the RRAM memory cell can cause the RRAM memory cell to enter an undefined state, and the output result can be randomly output between 0 and 1 when the RRAM memory cell is detected by the conventional read operation, so that an additional circuit is required to be designed for detecting the faults.
Because RRAM has five states in total, depending on the resistance size, the Deep state does not require an additional read operation to detect. To detect RRAM in undefined state, two resistors R ref1 and R ref0（Rref0>Rrref1) at the USF state boundary are set corresponding to the reference resistors of R ref0 and R ref1 read operations, respectively, for detecting the USF state of RRAM. For an RRAM cell with USF fault, when it is converted from 0 state to 1 state, because the fault falls into USF state, the resistance value of the RRAM cell is larger than R ref1, and when R ref1 read operation is performed, the RRAM cell at the moment can be detected to be in a non-1 state and not in accordance with the expected 1 state, so that the RRAM is detected to be faulty. And R0 and R1 operate the corresponding reference resistor R r to be (R 0+R1)/2, which can effectively distinguish the 0 state and the 1 state for detecting the conventional faults.
And step 2, deducing a test algorithm March-RAWR according to a required test sequence.
In this embodiment, regarding the RRAM fault model analyzed in step 1, taking Deep fault as an example, writing 0 or 1 into one RRAM cell according to stored information on the basis of already storing 0 or 1, so that the RRAM cell is in Deep 0 or Deep 1 fault, writing a value opposite to the stored value into the RRAM cell again at this time, and not changing the state of the RRAM. To detect this failure, the sensitive operation described above needs to be included in the March element and a determination of whether there is a failure is made by an opposite write operation and read operation. The Fault Primitive (FP) of one Deep fault is <1w1/D1/- > or <0w0/D0/- >, and the corresponding test sequences are "+.sup. ∈ (… w1w0r0 …)", and "+.sup. ∈ (… w0w1r1 …)". The corresponding test sequences of the USF faults are "++.E (… w1r ref1 …)" and "+.E (… w0r ref0 …)". For a dual cell failure, such as Cfud, when a write operation is performed to the donor cell (a-cell), the state of the acceptor cell (v-vell) will change to an undefined state, taking one of the failure primitives <0;0w1/U/-, as an example, the test sequence is related to the address sizes of the acceptor cell and the donor cell, and when the address of the acceptor cell is lower than the donor cell, the test sequence is "∈ (… w1 …) ∈ (… r ref1 w0 …)"; When the acceptor unit is lower than the donor unit, the test sequence is "++.h (… w1 …) +.h (… r ref1 w0 …)". For the dual cell dynamic failure dCFud, when two successive write operations are performed on the donor cell (a-cell), the state of the acceptor cell (v-vell) changes to an undefined state, taking one of the failure primitives <0;0w 1/U/- >, as an example, the test sequence is related to the address sizes of the acceptor cell and the donor cell, and when the address of the acceptor cell is lower than the donor cell, the test sequence is "-type ∈ (… w1 …) ∈ (… r ref1 w0w0 …)"; When the acceptor unit is lower than the donor unit, the test sequence is "++.i (… w1 …) +.i (… r ref1 w0w0 …)". For dynamic faults dRDF n, after performing a write operation on a memory cell, performing a plurality of continuous read operations to cause a jump of a logic value of the memory cell, and reading out an erroneous logic value, wherein one fault primitive is <0w0r0 n/≡1>; at this time, a plurality of continuous read operations are needed, and the test sequence is "++.v. (… w0r0 n r0 …)".
Aiming at the analysis of the memory fault model, a March-RAWR algorithm with higher fault coverage rate is provided, and the detection sequence is that ：{M1↑↓ (w0); M2↑ (rref0 w0 r0n r0 w1 r1 w1 rref1); M3↑ (rref1 w1 r1n r1 w0 r0 w0 rref0); M4↓ (rref0 w0 r0 r0 w1 r1 w1 r1); M5↓ (rref1 w1 r1 r1 w0 r0 w0 r0); M6↑↓ (r0)}.
Wherein "+. #" represents an ascending order of addresses, "+. #" represents a descending order of addresses, "+. #" represents an ascending order of addresses or a descending order of addresses, ".w" represents a writing operation, "r" represents a read operation, "r0 n" represents that n consecutive reads are to be performed, and "r ref0" represents a read operation for detecting a failure specific to the RRAM.
Step 3, designing an MBIST circuit suitable for RRAM according to algorithm elements in March-RAWR
In this embodiment, as shown in fig. 3, the MBIST circuit includes the following units:
a control generator: controlling each module of the whole MBIST circuit to operate a March-RAWR algorithm in sequence;
An address generator: generating address signals required by a test algorithm;
a data generator: generating a data signal required by a test algorithm;
a comparator: comparing the difference between the actual data and the expected data of the RRAM read by the memory, checking whether the read-write value of the memory is correct, and if so, outputting a signal test_fail to be low, wherein the fault address recorder does not record information; if the error occurs, the output signal test_fail is high, and the fault address recorder records the address of the storage unit with the fault;
Fault address recorder: the method comprises the steps of recording a storage unit address with faults and outputting a specific fault unit address through an address signal fail_ADR;
The sense amplifier of the RRAM memory has two input ends, one end of which is connected with the output signal R inx (x represents the column number of the selected memory cell) of the memristor array; one end is connected with the output signal R ref of the reference resistor. Under normal conditions, the sense amplifier only has a reference resistor with a fixed resistance, in order to detect the specific fault of RRAM, the invention sets three reference resistors with different resistance values, and the reference resistors are connected with the sense amplifier through a data selector (MUX), and the circuit structure of the reference resistors is shown in figure 3; the fourth data selector selects a reference resistor with a corresponding size by controlling the enabling ends A0 and A1; the reference resistances are R ref0,Rr and R ref1 from large to small, when the reading operation is R ref0, R ref0 resistance is selected, and at the moment, the enabling signal A0 is 0 and A1 is 1; when the read operation is R ref1, selecting R ref1 resistor, wherein the enable signal A0 is 1 and A1 is 1; when the read operation is R0 and R1, the R r resistor is selected, and the enable signal A0 is 0 or 1, and A1 is 0.
And 4, injecting faults into the RRAM, detecting the faults of the RRAM by using an MBIST circuit, and outputting the address information of the fault unit after the test is completed.
In the present invention, the Device-AWARE TEST (Device perception test) method is used as the fault injection method, and the faults actually occurring in the RRAM operation process are simulated by changing the electrical parameters of the used RRAM model, as shown in fig. 4. The specific operation method is to change parameters in Veriloga models of RRAM, then operate MBIST circuit under the digital-analog mixed simulation environment of Verilog+Virtuoso, and observe simulation waveform outputted by simulation software.
The built-in self-test MBIST circuit is a test circuit outside the conventional function of the RRAM memory, the test signal should be separated from the external logic signal by the one-out-of-two data selector, the one-out-of-two data selector is controlled by the bist_en enable signal, and when the bist_en signal is 1, the RRAM memory enters the test mode, and the MBIST circuit starts to operate.
The testing process comprises the following steps: firstly, injecting faults into RRAM memories, then, entering a test mode by an MBIST circuit, sequentially executing a March-RAWR algorithm {↑↓(w0);↑(rref0 w0 r0n r0 w1 r1 w1 rref1); ↑ (rref1 w1 r1n r1 w0 r0 w0 rref0);↓ (rref0 w0 r0 r0 w1 r1 w1 r1);↓ (rref1 w1 r1 r1 w0 r0 w0 r0);↑↓(r0)},, converting information stored by a corresponding RRAM memory unit into digital signals by a sense amplifier when the algorithm performs reading operation, outputting the digital signals to a comparator, and comparing the actual signals with expected signals by the comparator to check whether the RRAM memories have faults or not. After the algorithm execution is finished, if the RRAM memory has a fault, a test_fail signal of the comparator is pulled high, and meanwhile, the fault address recorder records the address of the fault unit. Table 2 shows the fault coverage comparison using the method of this example with the existing method.
TABLE 2 fault coverage of different March algorithms
As can be seen from table 2, this embodiment can cover all static single-cell faults, static double-cell faults, and most dynamic single-cell faults, dynamic double-cell faults, and RRAM special faults, with a fault coverage of 89.92%. There is very high fault coverage compared to other algorithms.
The foregoing is merely a preferred embodiment of the present invention, and is not intended to limit the present invention, and all equivalent variations using the description and drawings of the present invention are within the scope of the present invention.
Claims (6)
1. A method for testing a fault of an RRAM, comprising the steps of:
Step 1, analyzing fault primitives of RRAM fault models, and deducing a required test sequence according to each fault model;
Step 2, deducing a March-RAWR test algorithm according to a required test sequence;
step3, constructing an MBIST circuit suitable for RRAM according to a March-RAWR algorithm;
step 4, injecting faults into the RRAM, detecting the faults of the RRAM by using an MBIST circuit, and outputting address information of a fault unit after the test is completed;
The RRAM fault model comprises RRAM special faults and conventional faults, and the RRAM has five states according to different resistance sizes, namely Deep1, logic 1, USF, logic 0 and Deep0; for the RRAM in an undefined state, setting two resistors R ref1 and R ref0 at the boundary of the USF state to respectively correspond to reference resistors R ref1 and R ref0 for read operation, and R ref0>Rref1 for detecting the USF state of the RRAM; RRAM resistances in Logic 0 and Logic 1 states are R0 and R1, the magnitude of a reference resistance R r corresponding to R0 and R1 operation is set to be (R 0+R1)/2, and the states of 0 and 1 are distinguished for detecting normal faults;
The March-RAWR test algorithm is specifically described as follows:
{M1↑↓ (w0); M2↑ (rref0 w0 r0n r0 w1 r1 w1 rref1); M3↑ (rref1 w1 r1n r1 w0 r0 w0 rref0); M4↓ (rref0 w0 r0 r0 w1 r1 w1 r1); M5↓ (rref1 w1 r1 r1 w0 r0 w0 r0); M6↑↓ (r0)};
Wherein M1-M6 are elements, +.sup.representing the ascending order of addresses, +.sup.representing the descending order of addresses, +.sup. ∈representing the ascending order of addresses or the descending order of addresses, w0 represents writing 0 data to the selected memory cell, and w1 represents writing 1 data to the selected memory cell; r0 represents a read 0 operation on the selected memory cell, where the expected data value of the memory cell is 0; r1 represents a read 1 operation performed on the selected memory cell, where the expected data value of the memory cell is 1; r0 n represents n consecutive read 0 operations on the selected memory cell; r1 n represents n consecutive read 1 operations on the selected memory cell; r ref1,rref0 represents a read operation for detecting a RRAM-specific failure.
2. The method for testing the failure of the RRAM of claim 1, wherein the special failures of the RRAM include Deep failure, USF failure, CFud failure, and dCFud failure; the regular faults include static single-unit faults, static double-unit faults, dynamic single-unit faults and dynamic double-unit faults.
3. The method for testing a failure of an RRAM of claim 2, wherein,
For an RRAM cell with USF fault, when the RRAM cell is converted from 0 state to 1 state, the resistance value of the RRAM cell is larger than R ref1 because the fault falls into the USF state; when r ref1 read operations are performed, it can be detected that the RRAM cell is in a non-1 state and is not in accordance with the expected 1 state, thereby detecting that the RRAM fails.
4. The method for testing the failure of the RRAM of claim 1, wherein the MBIST circuit includes:
a control generator: controlling each module of the whole MBIST circuit to sequentially execute a March-RAWR test algorithm according to the sequence of M1-M6;
an address generator: generating address signals required by a March-RAWR test algorithm;
a data generator: generating a data signal required by a March-RAWR test algorithm;
A comparator: comparing the difference between the actual data and the expected data of the RRAM read by the memory, and checking whether the read-write value of the memory is correct or not; if the output signal test_fail is correct, the fault address recorder does not record information; if the error occurs, the output signal test_fail is high, and the fault address recorder records the address of the storage unit with the fault;
Fault address recorder: for recording the address of the faulty memory cell and outputting the specific faulty cell address via the address signal Fail _ ADR.
5. The method for testing the fault of the RRAM of claim 4, wherein the RRAM includes a peripheral circuit, a memristor array, a sense amplifier, and a reference resistor;
The peripheral circuit receives an MBIST circuit signal or an external logic signal and is controlled by a MUX selector; when the BIST_EN signal is 0, the peripheral circuit receives an external logic signal; when the BIST_EN signal is 1, the peripheral circuit receives the MBIST circuit signal; the peripheral circuit decodes after receiving the signal and outputs an output signal to the memristor array;
The two input ends of the sense amplifier are connected with the output signals R inx of the memristor array at one end, and x represents the column number of the selected storage unit; the other end is connected with an output signal R ref of the reference resistor and is connected with the sense amplifier through a data selector MUX; the fourth data selector selects a reference resistor with a corresponding size by controlling the enabling end; the reference resistances are R ref0,Rr and R ref1 from large to small, respectively, the R ref0 resistance is selected when the read operation is R ref0, the R ref1 resistance is selected when the read operation is R ref1, and the R r resistance is selected when the read operation is R0 and R1.
6. The method for testing the failure of the RRAM of claim 1, wherein the failure detection process is:
Step 4-1, injecting faults into the RRAM memory:
Step 4-2, entering test mode by MBIST circuit, and sequentially executing March-RAWR algorithm {M1↑↓ (w0); M2↑ (rref0w0 r0n r0 w1 r1 w1 rref1); M3↑ (rref1 w1 r1n r1 w0 r0 w0 rref0); M4↓ (rref0 w0 r0 r0 w1 r1 w1 r1); M5↓ (rref1 w1 r1 r1 w0 r0 w0 r0); M6↑↓ (r0)};
Step 4-3, when the algorithm performs a reading operation, the sensitive amplifier converts the information stored in the corresponding RRAM storage unit into a digital signal and outputs the digital signal to the comparator, and the comparator compares the actual signal with the expected signal; if the actual result is different from the expected result, indicating that the RRAM memory has faults;
after the algorithm execution of step 4-4 is finished, if there is a fault in the RRAM memory, the test_fail signal of the comparator is pulled high, and the fault address recorder records the address of the fault unit.
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