CN118095965A

CN118095965A - Preparation method of semiconductor chip with asymmetric geometric structure

Info

Publication number: CN118095965A
Application number: CN202410492186.0A
Authority: CN
Inventors: 王国宏; 李璟; 郭德博
Original assignee: Nanjing Ajibi Information Technology Co ltd
Current assignee: Nanjing Ajibi Information Technology Co ltd
Priority date: 2024-04-23
Filing date: 2024-04-23
Publication date: 2024-05-28

Abstract

The invention relates to the technical field of semiconductor chips, in particular to a preparation method of a semiconductor chip with an asymmetric geometric structure. Firstly, acquiring chip images under different angles, wherein each chip image is divided into at least two sub-blocks uniformly; combining chip images corresponding to the same chip under different angles to obtain a target image; acquiring a cutter path cutting time and an overheat temperature coefficient corresponding to a chip image; and inputting the chip image, the cutter path cutting time and the overheat temperature coefficient into a trained expert model, and judging the quality of chip arrangement corresponding to the chip image. The preparation method provided by the embodiment of the invention determines the angle and the gesture and the comprehensive arrangement mode by analyzing the surface reflection characteristics of the semiconductor chip, thereby optimizing the arrangement condition of the chip.

Description

Preparation method of semiconductor chip with asymmetric geometric structure

Technical Field

The invention relates to the technical field of semiconductor chips, in particular to a preparation method of a semiconductor chip with an asymmetric geometric structure.

Background

The semiconductor chip is an electronic component, which is composed of a plurality of basic elements such as transistors, capacitors, resistors and the like, and is embedded on a small silicon chip. It is one of the most important basic parts in modern electronic technology, and is widely applied to the fields of computers, communication, medical treatment, military industry and the like. The semiconductor chip has special property for controlling current, and can automatically control the current, thereby realizing various circuit functions. Compared with the traditional discrete components, the semiconductor chip has the advantages of small volume, low power consumption, reliable operation, high production efficiency and the like.

The preparation of the semiconductor chip influences the application of the semiconductor chip, when the semiconductor chip with the asymmetric geometric structure is prepared, the packaging structure is designed into an asymmetric hexahedron so as to form a trapezoid structure, whether the chip arrangement quality problem occurs when the semiconductor chip with the asymmetric geometric structure is prepared or not is difficult to judge, and when the chip arrangement quality problem occurs, the flow and the cost of manufacturing an application product can be reduced.

Disclosure of Invention

In order to solve the technical problem that whether the chip arrangement quality problem occurs or not during the preparation of the semiconductor chip with the asymmetric geometric structure is difficult to judge, the invention aims to provide a preparation method of the semiconductor chip with the asymmetric geometric structure, which adopts the following technical scheme:

Acquiring chip images under different angles, wherein each chip image is divided into at least two sub-blocks uniformly; combining chip images corresponding to the same chip under different angles to obtain a target image;

acquiring a cutter path cutting time and an overheat temperature coefficient corresponding to a chip image; inputting the chip image, the cutter path cutting time and the overheat temperature coefficient into a trained expert model, and judging the quality of chip arrangement corresponding to the chip image;

The training process of the expert model is as follows: constructing an arrangement characteristic descriptor of the chip according to the reflection intensity of each sub-block in the target image; constructing an arrangement posture descriptor of the chip according to the average light quantity reflected by the chip corresponding to the sub-block in each chip image; determining difference constraint values of different sub-chip packages according to differences among arrangement feature descriptors, differences among arrangement gesture descriptors, differences in cutter path cutting time and differences in overheat temperature coefficients in chip arrangement states in different sub-chip packaging processes; based on the difference constraint value, different times of chip packages are clustered, and an expert model is trained according to the clustering result and the corresponding chip images.

Preferably, the merging the chip images corresponding to the same chip under different angles to obtain the target image includes:

And taking the maximum value of RGB components of the pixel points at the same position in different chip images as the pixel value of the pixel points at the same position in the target image, and determining the pixel value of the pixel point at each position in the target image to obtain the target image.

Preferably, the constructing the arrangement feature descriptor of the chip according to the reflection intensity of each sub-block in the target image includes:

taking the sum value of the pixel values of each sub-block in the target image as a characteristic component corresponding to the sub-block; and constructing an arrangement characteristic descriptor of the chip by the characteristic component of each sub-block in the target image.

Preferably, the constructing a chip arrangement posture descriptor according to the average light quantity reflected by the chip corresponding to the sub-block in each chip image includes:

determining a chip circuit area in each sub-block in the chip image;

For each chip image, calculating the pixel value and the ratio of the value in each sub-block to the area of the chip circuit area in the sub-block as the corresponding attitude component of each sub-block; and constructing an arrangement posture descriptor of the chip by the posture component of each sub-block in each chip image.

Preferably, the determining the chip circuit area in each sub-block in the chip image includes:

and acquiring a connected domain of the bright part in each sub-block in the chip image by using an Ojin method as a chip circuit area.

Preferably, the method for obtaining the path cutting time corresponding to the chip image comprises the following steps:

Generating a cutting path according to a preset trapezoid boundary by using LaserGRBL, generating the path in a contour mode, setting the path distance to be 80% of the cutting spot diameter, setting the cutting speed to be 100mm/s, and obtaining the time T required by cutting the cutter path.

Preferably, the method for acquiring the overheat temperature coefficient corresponding to the chip image comprises the following steps:

drawing a heating area based on the radius area, performing Gaussian blur processing on the heating area to enable the color to be closest to 1 at the circle center value, and then outwards gradually changing to 0 to form a Gaussian circular heating area; wherein the heating area is circular;

Setting a heat radiation coefficient alpha, and in the case of setting the cutting speed to 100mm/s, when drawing 20 times per second, each drawing requires multiplying the value of the previous picture by alpha;

When the simulated cutting is started, the temperature of all points is 0, when the simulated cutting passes through each position, the temperature at the position is increased, and then the temperature slowly descends according to an exponential decay mode, so as to simulate the actual heat exchange process;

And sequencing the maximum values in the pictures in the stacking process, and taking top-10% of the maximum values as an overheat temperature coefficient.

Preferably, the determining the difference constraint value of the chip package of different times according to the difference between the arrangement feature descriptors, the difference between the arrangement gesture descriptors, the difference of the path cutting time and the difference of the overheat temperature coefficient in the chip arrangement state in the chip package process of different times includes:

calculating the sum of the difference of the cutter path cutting time and the difference of the overheat temperature coefficient as a constraint adjustment value;

and taking the product of the difference between the arrangement feature descriptors, the difference between the arrangement gesture descriptors and the constraint adjustment value as the difference constraint value of different sub-chip packages.

Preferably, the calculation method of the difference between the arrangement posture descriptors is as follows: calculating cosine similarity between distribution gesture descriptors in different times of chip packaging processes; and taking the difference value between a preset first threshold value and cosine similarity as the difference between the arrangement gesture descriptors of different sub-chip packages.

Preferably, the step of inputting the chip image, the path cutting time and the overheat temperature coefficient into a trained expert model to judge the quality of chip arrangement corresponding to the chip image includes:

Inputting the chip image into a CNN part of a twin network in an expert model, and determining the category of the chip image;

Acquiring the median of the path cutting time of other chip images in the category of the chip image as the longest time Th1;

acquiring the median of the overheat temperature coefficients of other chip images in the category of the chip images as the most serious heat accumulation Th2;

When the cutter path cutting time of the current chip image is smaller than the longest time Th1 and the overheat temperature coefficient is smaller than the worst heat accumulation Th2, judging that the quality of chip arrangement corresponding to the chip image is qualified; otherwise, judging that the quality of the chip arrangement corresponding to the chip image is unqualified.

The embodiment of the invention has at least the following beneficial effects:

The invention relates to the technical field of semiconductor chips. Firstly, acquiring a cutter path cutting time and an overheat temperature coefficient corresponding to a chip image; inputting the chip image, the cutter path cutting time and the overheat temperature coefficient into a trained expert model, and judging the quality of chip arrangement corresponding to the chip image; the method uses the existing laser processing tool path planning tool to plan the tool path cutting path, and considers the efficiency problem caused by certain heat accumulation and tool path idle running. Analyzing the reflection intensity of each sub-block in the target image and the average light quantity reflected by the chip corresponding to the sub-block in each chip image, and determining the difference constraint values of different chip packages; based on the difference constraint value, different times of chip packages are clustered, and an expert model is trained according to the clustering result and the corresponding chip images. The preparation method provided by the embodiment of the invention determines the angle and the gesture and the comprehensive arrangement mode by analyzing the surface reflection characteristics of the semiconductor chip, thereby optimizing the arrangement condition of the chip.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions and advantages of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are only some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flow chart of a method for fabricating an asymmetric geometry semiconductor chip according to one embodiment of the present invention;

FIG. 2 is a schematic diagram of an asymmetric geometry semiconductor chip;

FIG. 3 is a flow chart of the training steps of the expert model.

Detailed Description

In order to further describe the technical means and effects adopted by the invention to achieve the preset aim, the following is a detailed description of a specific implementation, structure, characteristics and effects of the asymmetric geometric structure semiconductor chip manufacturing method according to the invention with reference to the accompanying drawings and the preferred embodiment. In the following description, different "one embodiment" or "another embodiment" means that the embodiments are not necessarily the same. Furthermore, the particular features, structures, or characteristics of one or more embodiments may be combined in any suitable manner.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

The embodiment of the invention provides a specific implementation method of a semiconductor chip preparation method with an asymmetric geometric structure, which is applicable to the scene of semiconductor chip preparation. The packaging structure of the semiconductor chip in the scene is designed into an asymmetric hexahedron structure, so that the front face and the positive and negative poles of the chip can be directly identified, the taping process is avoided, and the process and the cost for manufacturing the application product are obviously reduced. The embodiment of the invention processes the path planned by the laser cutting mechanism, and can flexibly realize the special-shaped packaging structure. In the embodiment of the invention, only a simple steel net or steel plate is needed as the bracket. Firstly, preparing a rectangular chip substrate, and then sending the substrate into a tray for positioning. And then processing the substrate by analyzing the characteristics of the tray and planning a laser path so as to realize the asymmetric shape of the packaging structure. Because a plurality of semiconductors can be processed in batches at one time in the production process, a die is not needed, and the preparation method of the embodiment of the invention can be completed by using the existing laser processing tool path planning tool, but has the problems of certain heat accumulation and efficiency when the tool path runs empty. The preparation method provided by the embodiment of the invention determines the angle and the gesture and the comprehensive arrangement mode by analyzing the surface reflection characteristics of the semiconductor chip, thereby optimizing the distribution of the tray and the laser cutting consumption. According to the embodiment of the invention, based on the circuit distribution mode of the polarized light analysis semiconductor chip, the expert model Q is trained in combination with the evaluation parameters of tool path time and thermal accumulation, so that whether the arrangement mode is required to be re-disordered is judged to shorten the processing time.

The following specifically describes a specific scheme of the preparation method of the semiconductor chip with the asymmetric geometric structure provided by the invention with reference to the accompanying drawings.

Referring to fig. 1, a flowchart illustrating steps of a method for manufacturing a semiconductor chip with an asymmetric geometric structure according to an embodiment of the invention is shown, the method includes the following steps:

Step S100, obtaining chip images under different angles, wherein each chip image is divided into at least two sub-blocks in an equipartition way; and combining chip images corresponding to the same chip under different angles to obtain a target image.

Referring to fig. 2, fig. 2 is a schematic diagram of an asymmetric geometry semiconductor chip; in fig. 2, a is a front surface of an asymmetric geometric structure semiconductor chip, b is a back surface of the asymmetric geometric structure semiconductor chip, c, d, e, f is a side surface of the asymmetric geometric structure semiconductor chip, a is the asymmetric geometric structure semiconductor chip, and B, C is a bonding wire region of the substrate; four sides of the side c, d, e, f of the semiconductor chip with the asymmetric geometric structure form a trapezoid structure; the side surfaces c and d are in parallel structures, and the side surfaces e and f are not parallel.

In order to prepare the semiconductor chip with the asymmetric geometric structure, a rectangular substrate b is firstly required to be prepared, and finally, the whole packaging is completed through colloid such as resin or silica gel. Typical packaging steps include:

and preparing a rectangular substrate b of the semiconductor chip package with the asymmetric geometric structure, wherein the rectangular substrate b is provided with an insulation area and a bonding wire area, the substrate is made of FR4, and a copper foil layer is arranged on the substrate to serve as the insulation area and the bonding wire area. The substrate size is typically varied from 3x5mm to 10x15mm, depending on the size of the package.

The practitioner routes and reserves pads on bond wire area B and bond wire area C, with bond wire widths of approximately 100-300 microns. Electrode patterns are manufactured through screen printing or vapor deposition, and current conduction of the semiconductor chip with the asymmetric geometric structure is guaranteed.

And then the semiconductor chip A with the asymmetric geometric structure is welded on the bonding wire area B and the bonding wire area C of the substrate through conductive glue or solder, a gold wire bonding machine is generally used for welding the positive electrode and the negative electrode of the semiconductor chip with the asymmetric geometric structure on the bonding pad of the substrate for electric connection, and then glue such as resin or silica gel is injected around the semiconductor chip with the asymmetric geometric structure to form a light conversion layer, and the semiconductor chip A with the asymmetric geometric structure is fixed and protected.

After the steps of a typical package structure are given, the embodiment of the invention also provides a preparation method, and the preparation process of the semiconductor chip with the single asymmetric geometric structure is as follows:

The package is loaded into a dicing platform with visual positioning function, and the position of the semiconductor chip with asymmetric geometric structure is determined through image recognition. The now asymmetric geometry semiconductor chip enters the tray with the front side of the chip up or down, exposing the etched macro circuit pattern. Wherein the front side of the chip is in particular a light sensitive, light emitting device or an integrated circuit.

According to the preparation method of the embodiment of the invention, two operations are specifically completed by observing the macroscopic circuit pattern: 1. identifying the arrangement pattern to ensure that the cutting path can be substantially optimised; 2. and carrying out gesture recognition to generate a final cutting path.

And for generating a cutting path, specifically, cutting the side edge of the semiconductor chip with the asymmetric geometric structure by using laser cutting equipment to manufacture an asymmetric packaging body. Furthermore, the embodiment of the invention cuts the side surface of the semiconductor chip with the asymmetric geometric structure according to the preset path by using the laser beam, and the cutting depth can reach the inside of the substrate. The practitioner needs to calibrate the laser power during dicing, and if the power is too high, the asymmetric geometry semiconductor chip will be burned out, and if too low, the dicing will be insufficient. Typically the power is between 5-20W.

Specifically, the semiconductor chip with the asymmetric geometric structure after cutting comprises six faces, and in view of the characteristics of laser cutting and focusing errors, the embodiment of the invention requires that at least one face after cutting is trapezoid, not square or rectangle, at least one face of all faces of the packaging structure is trapezoid, and the shape of the face can be isosceles trapezoid or right trapezoid to form the asymmetric packaging structure. The shape of the finally cut packaging structure is a truncated cuboid, so that the packaging structure is convenient to identify and use.

Then preparing preparation is carried out, specifically, by discharging for a plurality of times and based on a circuit distribution mode of a polarized light analysis chip, and combining with evaluation parameters of cutter path cutting time and thermal accumulation, an expert system is trained to distinguish better conditions from worse conditions in advance, so that the problem that a cutter path is planned by consuming a large amount of calculation time in the formal preparation process or the problem that the cutter path is low in efficiency and accumulated in heat is avoided.

Firstly, image acquisition is carried out, namely chip images under different angles are acquired. Specific:

The practitioner needs to give a surface light source to irradiate the chip tray, and the chip tray can be made of steel mesh or stainless steel. In the embodiment of the invention, a white light LED can be selected as a scattering light source, and the power of the light source is 100W. The light source was placed on the equiaxed side of the tray 1 meter from the center of the tray with an illuminance of about 500lux. Therefore, the surface of the tray is uniformly illuminated by scattered light which does not cause overexposure, an implementer can adjust the light automatically, the chip is ensured to reflect light with different wavelengths at certain angles, namely, the chip is ensured to reflect light with different colors at certain angles, and meanwhile, the tray is prevented from being overexposed.

In the embodiment of the invention, basler acA2500-14uc color (RGB) GigE industrial cameras are used, the cameras are kept at proper distances from the tray, the tray is ensured to completely enter into the view range, and the cameras shoot from right above to below. The embodiment of the invention samples the circular polarizer to analyze the reflection phenomenon caused by the circuit pattern, and can also analyze the reflection phenomenon caused by the circuit pattern by using the circular polarizer, and firstly, the Circular Polarizer (CPL) is arranged at the front end of the camera lens. The CPL can be installed by adopting a C-port thread matched with a camera or other matched fixing modes, so that the CPL can rotate at different angles, and the specific installation process is not repeated here.

The CPL can be rotated to a fixed angle by motor drive. Thus, each time image data of the chip distribution of the tray is acquired, the angle of the polarizer (CPL) needs to be sequentially adjusted, and the rotation is performed at intervals of 15 ° for a total of 24 rotations. After each rotation, the illuminated tray was photographed using an installed industrial camera to take 24 pictures to capture the reflection pattern of the chip as viewed from different angles for further analysis. The chip images at different angles can be obtained. In the embodiment of the invention, one chip corresponds to 24 chip images.

The material properties of the circuit part and the non-circuit part of the chip are different, which makes them also different in their reflective properties for light. Smooth and planar portions such as metal lines may be specularly reflected, while rough portions such as semiconductor substrates may be diffusely reflected. Therefore, the macroscopically visible circuit pattern may have a pattern of uneven brightness and scattering, and the illumination light source has a high or low reflection intensity.

For CPL, it is a filter that can allow light in a specific direction to pass through, so that light in other directions can be filtered out. When CPL is rotated, the direction of light that can pass through is also changed. Therefore, the reflection condition of different parts of the chip under different light rays can be reflected by rotating the CPL and shooting the obtained picture.

The material properties of the circuit portion and the non-circuit portion of the chip are different, such as the metal lines and the semiconductor substrate, and their reflection properties for light are different. The smooth and flat surface portions may be specularly reflected, such as metal lines, while the rough surface portions may be diffusely reflected, such as semiconductor substrates. Thus, the macroscopically observed circuit pattern has a pattern of varying brightness and scattering, and the illumination source has a high and low reflection intensity. And the circuit patterns have a space, and the circuit patterns have large patterns and small patterns, and the line width and the line distance are different. The reflective behavior of circuit patterns of different shapes and arrangements can also form different patterns, depending on the exposure to light. For example, an isolated circuit pattern may be surrounded by surrounding non-circuit portions, the reflection of which may be affected by the surrounding environment. Although the chip surface appears planar, there are actually irregularities at the microscopic level, so that different reflection patterns can be seen from different angles. For the chip images at 24 different angles, each chip image corresponds to a polarization state of a specific angle because the chip images are photographed at different angles of the polarizer (CPL).

After obtaining the chip pictures obtained by reflection at each angle under CPL, the color industrial camera adopted by the embodiment of the invention can capture the reflection modes of different colors, and in order to normalize the intensity of reflection, the embodiment of the invention obtains 24 chip gray-scale pictures by taking the maximum value of RGB components of each pixel point from 24 chip images.

Further, the maximum reflection intensity of each pixel point in the 24 chip gray level images is selected as the pixel value of the corresponding pixel point of the target image, namely, the maximum gray level value corresponding to each pixel point in the 24 chip gray level images is selected as the pixel value of the corresponding pixel point of the target image. The target image is actually a picture combining a plurality of angular reflection intensities, which can better show the shape and position of the circuit pattern.

It may also be understood that, in order to determine the number of chips, the maximum value of RGB components of the pixel point at the same position in the 24 chip images is taken as the pixel value of the pixel point at the same position in the target image, and the pixel value of the pixel point at each position in the target image is determined, so as to obtain the target image.

The target image is divided into 16×16 sub-blocks, resulting in 256 sub-blocks in total. Each chip image is also divided into 16 x 16 sub-blocks, and 256 sub-blocks are obtained in total.

Step S200, obtaining the cutter path cutting time and the overheat temperature coefficient corresponding to the chip image; and inputting the chip image, the cutter path cutting time and the overheat temperature coefficient into a trained expert model, and judging the quality of chip arrangement corresponding to the chip image.

Firstly, the cutting time of the cutter path is evaluated, for the cutting process, the pose of the chip is firstly determined based on a template matching mode, and the calculation time of the process is long, so that the cutter path is used for determining the arrangement advantages and disadvantages in the test process, and the cutter path is not exhaustive in the final batch preparation link, and the advantages and disadvantages can be directly judged through an expert model, and the pose is calculated only for the excellent situation and the cutter path is generated.

Firstly, the pose of the chip is determined based on a template matching mode, and because peripheral circuits of the light reflecting part of the semiconductor chip are different, the pose of the chip can be matched and determined through modes such as edge matching, normalized cross correlation and the like, and the detailed description is omitted.

Based on the pose, the edge to be cut can be determined, so that a cutting knife path is obtained by using a path generation mode. For the generation and time assessment of cutting paths, generally depending on the different ancillary design software, the embodiment of the invention uses LaserGRBL to generate cutting paths according to a predetermined trapezoidal boundary. The paths are generated in a contour manner, and the path pitch is set to 80% of the cutting spot diameter to ensure the continuity of cutting. And finally, carrying out cutter path simulation, wherein the cutting speed is set to be 100mm/s, and obtaining the time T required by cutter path cutting.

Further, the degree of heat accumulation is calculated, namely, the overheat temperature coefficient corresponding to the chip image is obtained. For the knife path, the knife path is firstly regarded as a dynamic video, namely a light spot moving process, and for the process, the vicinity of the light spot can be regarded as a hot area, namely a heating area with a radius of a plurality of cm. In the embodiment of the invention, the radius of the heating area is set to be 1cm, and the heating area is regarded as 15 pixels in the whole simulation area, and the picture size is 2440 x 2440.

Drawing a heating area based on the radius area, performing Gaussian blur processing on the heating area to enable the color to be closest to 1 at the circle center value, and then outwards gradually changing to 0 to form a Gaussian circular heating area; wherein the heating area is circular. Namely, drawing a heating area based on a radius area, specifically a Gaussian circle, specifically performing Gaussian blur processing, enabling the color to be closest to 1 at the center value, then outwards gradually changing to 0, forming the Gaussian circle heating area, updating the position every second according to the position of a cutter path, and drawing the whole picture, wherein the speed is 20 times/second.

The heat radiation coefficient α is set on the basis of the entire screen, that is, on the basis of the entire image, and when 20 times per second of drawing are performed with the cutting speed set to 100mm/s, each drawing requires the value of the previous screen to be multiplied by α, thereby treating as heat radiation. In the embodiment of the invention, the value of the heat dissipation coefficient is 0.99, and in other embodiments, the value is adjusted by an implementer according to the actual situation.

Each pixel in the picture represents the temperature at the location, a layer-by-layer representation of the heat transfer equation in a two-dimensional plane. At the start of the simulated cut, all pixels are at 0 temperature, i.e. ambient temperature, which coincides with the actual physical process. Then, when the light spot passes through each position, the temperature of each position rises and slowly drops in an exponential decay mode in the subsequent process, and the actual heat exchange process is simulated. That is, when the simulated cutting is started, the temperature of all points is 0, and when the simulated cutting passes through each position, the temperature at the position rises, and then slowly falls according to an exponential decay mode, so as to simulate the actual heat exchange process.

For the heat accumulation phenomenon, the embodiment of the invention takes top-10000 of the maximum value in the whole heat accumulation process as the overheat temperature coefficient after 300 times of feeding test, collection and simulation. For the heat accumulation phenomenon in one test, the maximum value in the pictures in the accumulation process is sequenced, and the top-10% of the maximum value is taken as the overheat temperature coefficient R.

So far, the embodiment of the invention can evaluate the quality degree of different cutting paths according to the coefficient R on the aspects of heat distribution and heat accumulation from the thermal perspective.

Inputting the chip image into a CNN part of a twin network in an expert model, and determining the category of the chip image; acquiring the median of the path cutting time of other chip images in the category of the chip image as the longest time Th1; acquiring the median of the overheat temperature coefficients of other chip images in the category of the chip images as the most serious heat accumulation Th2; when the cutter path cutting time of the current chip image is smaller than the longest time Th1 and the overheat temperature coefficient is smaller than the worst heat accumulation Th2, judging that the quality of chip arrangement corresponding to the chip image is qualified; otherwise, judging that the quality of the chip arrangement corresponding to the chip image is unqualified.

Referring to fig. 3, fig. 3 is a flowchart of the training steps of the expert model. Training an expert model, namely:

step S201, constructing an arrangement characteristic descriptor of the chip according to the reflection intensity of each sub-block in the target image.

The target image represents the maximum response of reflection, as many reflections as possible are reserved, different color scattering phenomena can be obtained by the singly filtered chip images collected under 24 angles unlike direct shooting without CPL, and the reflection effect can be unified to the greatest extent through the synthesis of the maximum RGB component and the maximum pixel value. Compared with RGB direct graying, the method can further improve the uniformity of reflection and match the step of continuous rotation of CPL in the acquisition process.

The target image is segmented, and each sub-block corresponds to a unique reflection mode for the original image. This process is similar to viewing the chip from different angles, with each sub-block capturing a macroscopic reflection that differs in intensity and direction.

The method for dividing the sub-blocks is designed according to the reflection characteristic of the chip and the vertical acquisition mode, and the intensity and the direction of the reflection depend on the direction of the incident light according to the characteristic of CPL. For a sub-block that is not at the imaging optical axis, then it is equivalent to taking a picture of the chip from a different angle of the camera optical axis, and the intensity and direction of the macroscopic reflection captured by each sub-block will be different.

For the mode that the pixel value of each of the 24 chip images takes the maximum value, if a chip is arranged beside the position of the sub-block, and the chip is positioned and oriented to have stronger reflection against a specific angle of the optical axis of the camera, the reflection is quite likely to be the most representative pixel value of the sub-block. In the analysis that follows, the sub-blocks and the optical axes are not matched, but for the arrangement of the feature descriptors X, these responses need to be unified, so that the pixels of each sub-block, in which 24 chip images are synthesized into the target image, are one pixel maximum response value.

Taking the sum value of the pixel values of each sub-block in the target image as a characteristic component corresponding to the sub-block; and constructing an arrangement feature descriptor by the feature component of each sub-block in the target image. For each sub-block, the maximum response value of each pixel point in the sub-block can be calculated, and further, the distribution gesture descriptors can be determined through subsequent analysis, so that the intensity and the direction of the reflection mode can be reflected, and an important basis is provided for the subsequent laser cutting step.

Step S202, constructing a chip arrangement posture descriptor according to the average light quantity reflected by the chip corresponding to the sub-block in each chip image.

In addition to obtaining the arrangement feature descriptor X, it is also necessary to obtain the arrangement posture descriptor Y. In order to obtain the arrangement posture descriptor Y, a rough chip area calculation is also required based on 24 chip images.

For a chip image, the embodiment of the invention uses the Ojin method to obtain the connected domain of the bright part in each sub-block in the target image, and the connected domain of the bright part corresponding to each sub-block is used as a chip circuit area, and represents the area of a reflecting object in one sub-block, namely the area of a circuit of the chip. It should be noted that, the acquisition of the bright portion connected domain in the image by the oxford method is a well-known technique of those skilled in the art, and will not be described herein.

Taking the pixel value and the ratio of the pixel value of each chip circuit area to the area of the chip circuit area as the corresponding characteristic component of each chip circuit area; and constructing an arrangement feature descriptor by the feature components of the chip circuit area in each sub-block in the target image.

Based on the corresponding positions of the 256 sub-blocks divided in advance, the reflected light amount per 15 ° of each chip image is calculated for 24 chip images, which can be achieved by calculating the pixel sum under each window. This value will correspond to the total amount of light that can be reflected to the industrial camera.

Because the reflection intensity of the light intensity can be represented by the pixel values in the photo, the value of each pixel point on each chip picture is accumulated, so that the total quantity of the reflected light under the corresponding angle can be obtained, and the total quantity is the sum of the light intensities of all the reflected light rays. For example, in a sub-block, the sum of all pixel values of the picture taken at a CPL angle of 15 ° is 10000, at 30 ° is 10050, and at 45 ° is 10100, and the light intensity of the reflected light at these angles is due to the gradual increase of the reflection intensity caused by the angles of some chips.

Therefore, according to the average brightness of the chip reflection corresponding to the sub-block in each chip image, the arrangement posture descriptor Y of the chip is constructed, and the specific is as follows: for each chip image, calculating the pixel value and the ratio of the value to the area of the chip circuit area in each sub-block of the chip image as the corresponding attitude component of each sub-block; and constructing an arrangement gesture descriptor by gesture components of each sub-block in each chip image.

That is, for one sub-block, the amount of reflected light per 15 °, specifically the sum of pixels under each sub-block, is calculated, corresponding to the total amount of light that the sub-block can reflect to the industrial camera at that angle. Then dividing the sum of the pixels of the sub-block by the area of the chip circuit area to obtain the average light quantity reflected by each chip, thereby obtaining the descriptor Y of the arrangement posture. This descriptor may describe the reflection characteristics of the chip under light in more detail.

For 24 chip images and 256 sub-blocks correspondingly, the gesture descriptor Y is arranged as a 6144-dimensional high-dimensional vector, and all components of the high-dimensional vector are finally ordered from large to small, so that the distribution form of gestures is represented.

The arrangement posture descriptor Y calculates the total quantity of reflected light in all sub-blocks based on the substance characteristics of the chips, the light source, the property of the imaging device and the optical axis characteristics of the sub-blocks, thereby obtaining the average quantity of light reflected by each chip at different sub-block positions at different angles. The arrangement posture descriptor Y reflects the reflection intensity and direction change of the chip under various angles, and the numerical distribution contains the arrangement characteristics of the chip. The arrangement posture descriptor Y is special data of physical characteristics, light characteristics and imaging processes of the chip, and can describe characteristics of arrangement and posture of the chip in a high-dimensional vector mode.

So far, for one feeding operation on the tray, the arrangement characteristic descriptor X and the arrangement posture descriptor Y can be acquired.

For the arrangement characteristic descriptor X and the arrangement posture descriptor Y which are acquired through multiple tests, the descriptors have the arrangement characteristics which are kept as far as possible, but the advantages and disadvantages cannot be distinguished, and the dimensions of all the dimensions are not uniform.

Step S203, determining difference constraint values of different sub-chip packages according to differences among arrangement feature descriptors, differences among arrangement gesture descriptors, differences in path cutting time and differences in overheat temperature coefficients in chip arrangement states in different sub-chip packaging processes.

After the arrangement characteristic descriptor X, the arrangement posture descriptor Y, the cutter path cutting time T and the overheat temperature coefficient R are determined, a measurement function is constructed according to the following relation, so that modes under different arrangement conditions are distinguished. It should be noted that, the difference constraint values of different sub-chip packages can be determined by the constructed metric function.

Firstly, for the arrangement feature descriptor X and the arrangement gesture descriptor Y, the dimension of the arrangement gesture descriptor Y is high, and in the embodiment of the invention, the dimension of the arrangement gesture descriptor Y is 6144 dimension, but the dimension is the same, so that the normalized cosine similarity is used as a measurement function:。

For the arrangement feature descriptors X, the difference between the arrangement feature descriptors in the chip arrangement state in the two chip packaging processes is measured by calculating the Euclidean distance (L2 Norm): ; wherein/> For the difference between arrangement feature descriptors in the chip arrangement state in the two-time chip packaging process,/>The L2 distance of the arrangement feature descriptors between the arrangement feature descriptors in the chip arrangement state in the two chip packaging processes is the Euclidean distance. That is, the difference between the arrangement feature descriptors reflects how much the reflected light intensity pattern is different in the chip arrangement state in the two packaging processes.

Since the arrangement posture descriptor Y is a vector with a higher dimension, the similarity of the chip arrangement state in the two chip packaging processes can be calculated by adopting normalized cosine similarity, and then the corresponding measurement value is obtained by subtracting the cosine similarity from 1.

The calculation formula of the cosine similarity is as follows:

；

Wherein, Cosine similarity of the arrangement posture descriptor Y1 of any secondary chip packaging process and the arrangement posture descriptors Y2 of other secondary chip packaging processes; /(I)The arrangement gesture descriptors are arranged in the chip packaging process for any time; /(I)The arrangement gesture descriptors are used for another chip packaging process; /(I)A function of the dot product operation is performed for both vectors. After the cosine similarity is obtained, the cosine similarity is subjected to subsequent normalization processing, and in the embodiment of the invention, the normalization processing can be performed by using a linear normalization algorithm, and in other embodiments, the normalization processing can be performed by using other normalization algorithms.

Wherein,Representing the distribution similarity between the reflected light intensities under different chip arrangement postures in the two chip packaging processes. And then, the difference value between a preset first threshold value and cosine similarity is used as the difference between the arrangement gesture descriptors of different sub-chip packages. In the embodiment of the present invention, the value of the first threshold is preset to be 1, and in other embodiments, the value is adjusted by the practitioner according to the actual situation. The difference between the distribution gesture descriptors of different sub-chip packages represents the distribution difference degree between the reflected light intensities under the two distribution gestures.

For the cutter path cutting time and the overheat temperature coefficient, the absolute value of the difference value between two test results in the chip arrangement state in the chip packaging process of different times can be directly calculated as the corresponding measurement value.

For the cutter path cutting time under the chip arrangement state in the different times of chip packaging processes, the calculation method of the difference of the cutter path cutting time comprises the following steps: and calculating the absolute value of the difference value of the cutting time of the cutter path in the chip arrangement state in the two chip packaging processes, and taking the absolute value as the difference of the cutting time of the cutter path in the chip arrangement state in the two chip packaging processes. The difference of the cutter path cutting time only needs to be concerned about the size of the time difference, and does not need to be concerned about which chip packaging process has long time.

For the overheat temperature coefficient in the chip arrangement state in the different times of chip packaging, the method for calculating the difference of the overheat temperature coefficients comprises the following steps: and calculating the absolute value of the difference value of the overheat temperature coefficients in the chip arrangement state in the two chip packaging processes, and taking the absolute value as the difference of the overheat temperature coefficients in the chip arrangement state in the two chip packaging processes. The difference of the overheat temperature coefficients only needs to be concerned about how much difference of heat accumulation degree is in the two packaging processes, and does not need to be concerned about which chip packaging process has high heat temperature coefficient.

And determining difference constraint values of different sub-chip packages after the differences among the arrangement feature descriptors, the differences among the arrangement posture descriptors, the differences of cutter path cutting time and the differences of overheat temperature coefficients in the chip arrangement state in the different sub-chip package processes are respectively obtained.

Specifically, calculating the sum of the difference of the cutter path cutting time and the difference of the overheat temperature coefficient as a constraint adjustment value; and taking the product of the difference between the arrangement feature descriptors, the difference between the arrangement gesture descriptors and the constraint adjustment value as the difference constraint value of different sub-chip packages.

The calculation formula of the difference constraint value is as follows:

；

Wherein, Is a difference constraint value; /(I)Differences between descriptors for arrangement features; /(I)Differences between the arrangement gesture descriptors; /(I)The difference of cutting time of the cutter path; /(I)The difference of cutting time of the cutter path; /(I)To constrain the adjustment value.

The difference constraint value reflects the comprehensive difference degree of the test result in the chip arrangement state in the chip packaging process on the four key indexes, when one value is particularly large, the value of the difference constraint value S can be greatly increased, namely if any evaluation index, such as chip arrangement, cutting time or heat accumulation, is greatly different in the two test results, the change can be amplified into the final difference constraint value S, so that the test result in the chip arrangement state in the two chip packaging processes is more different.

Furthermore, in the chip preparation process, the difference of two chip arrangement modes, cutting time and heat accumulation conditions can be measured rapidly according to the obtained difference constraint value S.

And step S204, clustering the chip packages of different times based on the difference constraint value, and training an expert model according to the clustering result and the corresponding chip image.

The embodiment of the invention uses the DBSCAN algorithm to carry out rough marking of the same class and different classes, and can effectively classify various kinds of distribution non-uniformity based on the concept of density reachability.

Taking the process of each chip package as a sample point, and clustering different chip packages based on a difference constraint value: (1) For each sample point P in all test data, the distance of that point to all other points is calculated and compared to a set distance threshold (Eps). It should be noted that, the distances between the different sample points are the difference constraint values calculated in step S500 in the embodiment of the present invention. If the density of the points is maximized as much as possible, i.e., there are at least other MinPts number of points within the Eps neighborhood of the sample point P, then the sample point is marked as a core point. (2) The sample point is marked for access, marked P as accessed. If there are at least a number of MinPts points within the Eps neighborhood of sample point P, a new cluster is created and P is added to this cluster. Then, find all points that are not assigned to any cluster, if there are at least MinPts number of points in the Eps neighborhood of these points, then add these points to this cluster too. (3) When a new cluster is found in step (2), step 2 is repeated until all marginal points of the current cluster are visited, i.e. points within the Eps neighborhood of the cluster core point but not the core point itself are visited. (4) When all points have been accessed, if there are still points that have not been assigned to any cluster, then these points are considered noise. It should be noted that, the clustering method using the DBSCAN algorithm is a well-known technique for those skilled in the art, and will not be described herein.

Through the steps, the DBSCAN algorithm classifies points in the test sample into three types, namely:

core object: a point within radius Eps that exceeds the number of MinPts;

boundary object: the number of points within the radius Eps is less than MinPts, but falls within the radius Eps of the core object;

noise object: i.e. objects that are neither core nor boundary.

By neglecting the noise object, a plurality of clustering results can be obtained, and for the same class of results, the results are marked as different class IDs, namely, the clustering of different sub-chip packages based on the difference constraint value is realized.

Based on the same class ID, randomly rotating the target image M, inputting the target image M into the CNN based on ResNet, adding a full-connection structure to an output layer, outputting a 256-dimensional feature descriptor Z, and using the training twin network H for representing the types of the same class and different classes, namely, classifying the training twin network.

Aiming at the features related to the layout characteristics in the earlier stage, the embodiment of the invention utilizes deep learning to perform pattern recognition.

Specifically, the target image M is randomly rotated by 90 ° so as to be input into a Convolutional Neural Network (CNN) model based on ResNet a structure as different reflection characteristics and two-dimensional spatial arrangement characteristics. When designing a network, a full convolution network structure is added at an output layer on the basis of an original ResNet model, and the output is set to 256 dimensions.

For the CNN network model, the arrangement pose and the dense condition of chips in the target image M can be captured, so that the influences caused by processing time and heat accumulation brought by different arrangement modes are distinguished.

Thus the twin network can identify the features of the X component between different classes, while at the same time the backbone part of the network can separate the features of the arrangement of feature descriptors X and at the end characterize a new feature descriptor Z for distinguishing between different classes.

The chip image acquired at present can be input into the CNN part of the twin network through the trained CNN part of the twin network, and the category of the chip image acquired at present can be determined.

The CNN part of the trained twin network H can better capture the pose characteristics and the distribution characteristics of small targets, based on the CNN part, the added full-connection structure is removed, a new full-connection structure is added, and the output layer is 2 channels for two classification.

Based on the cutter path cutting time T and the overheat temperature coefficient R which are of the same type in the earlier stage evaluation, a new threshold is constructed to evaluate the arrangement effect:

specifically, for all lane cutting times T of the chip images in the same type determined earlier through the twin network H, the median is regarded as the longest time Th1. Likewise, for all the superheat temperature coefficients R of the chip images in the same type, which were previously determined by the twin network H, the median is considered as the most severe heat build-up Th2.

When the cutter path cutting time T is smaller than Th1 and the overheat temperature coefficient R is smaller than Th2, the chip arrangement is considered to be excellent, and the chip arrangement is considered to be of a passing type, namely the quality of the chip arrangement corresponding to the current chip image is considered to be qualified; otherwise, the chip arrangement effect is considered to be poor, and the chip arrangement effect is considered to be of a failed type, namely the quality of the chip arrangement corresponding to the current chip image is considered to be unqualified. And triggering the shaking signal of the material disc, wherein the shaking signal is used as a signal for rearranging chips when the quality is unqualified.

Finally, the weight of the CNN is fixed to train the classifier, and only the full connection layer is trained to obtain the expert model Q. This is because the fixed CNN weights can ensure that the learned features remain unchanged, and the CNN part in the twinning network H can capture the pose features and the distribution features of small targets well, so that chip arrangements with similar properties can be classified together.

The final expert model Q identifies those arrangements that are likely to result in shorter cutting times and more uniform heat distribution, thereby distinguishing whether the characteristics of the arrangement are excellent.

Finally training to obtain an expert model Q, and directly inputting a CPL synthetic diagram by using the expert model Q in the subsequent preparation process, so as to quickly determine whether rearrangement is needed or not, optimize the processing time and avoid the situation that heat accumulation is too serious.

In summary, the embodiments of the present invention relate to the technical field of semiconductor chips. Firstly, acquiring chip images under different angles, wherein each chip image is divided into at least two sub-blocks uniformly; combining chip images corresponding to the same chip under different angles to obtain a target image; acquiring a cutter path cutting time and an overheat temperature coefficient corresponding to a chip image; and inputting the chip image, the cutter path cutting time and the overheat temperature coefficient into a trained expert model, and judging the quality of chip arrangement corresponding to the chip image. The preparation method provided by the embodiment of the invention determines the angle and the gesture and the comprehensive arrangement mode by analyzing the surface reflection characteristics of the semiconductor chip, thereby optimizing the arrangement condition of the chip.

It should be noted that: the sequence of the embodiments of the present invention is only for description, and does not represent the advantages and disadvantages of the embodiments. The processes depicted in the accompanying drawings do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments.

Claims

1. A method for fabricating a semiconductor chip having an asymmetric geometry, the method comprising the steps of:

2. The method for preparing a semiconductor chip with an asymmetric geometric structure according to claim 1, wherein the merging the chip images corresponding to the same chip under different angles to obtain the target image comprises:

3. The method for manufacturing a semiconductor chip with an asymmetric geometric structure according to claim 1, wherein the constructing an arrangement feature descriptor of the chip according to the reflection intensity of each sub-block in the target image comprises:

4. The method for preparing a semiconductor chip with an asymmetric geometric structure according to claim 1, wherein the constructing an arrangement posture descriptor of the chip according to the average light quantity reflected by the chip corresponding to the sub-block in each chip image comprises:

determining a chip circuit area in each sub-block in the chip image;

5. The method of manufacturing an asymmetric geometry semiconductor chip of claim 4, wherein said determining chip circuit area in each sub-block in the chip image comprises:

6. The method for manufacturing a semiconductor chip with an asymmetric geometric structure according to claim 1, wherein the method for obtaining the path cutting time corresponding to the chip image is as follows:

7. The method for manufacturing a semiconductor chip with an asymmetric geometric structure according to claim 1, wherein the method for acquiring the overheat temperature coefficient corresponding to the chip image comprises the steps of:

8. The method for preparing a semiconductor chip with an asymmetric geometric structure according to claim 1, wherein determining the difference constraint value of the chip package of different times according to the difference between the arrangement feature descriptors, the difference between the arrangement posture descriptors, the difference of the path cutting time and the difference of the overheat temperature coefficient in the chip arrangement state in the chip package process of different times comprises:

9. The method for manufacturing an asymmetric geometric semiconductor chip according to claim 1, wherein the method for calculating the difference between the arrangement posture descriptors is as follows: calculating cosine similarity between distribution gesture descriptors in different times of chip packaging processes; and taking the difference value between a preset first threshold value and cosine similarity as the difference between the arrangement gesture descriptors of different sub-chip packages.

10. The method for manufacturing a semiconductor chip with an asymmetric geometric structure according to claim 1, wherein the step of inputting the chip image, the tool path cutting time and the overheat temperature coefficient into a trained expert model to determine the quality of chip arrangement corresponding to the chip image comprises the steps of: