CN118074880B - Vehicle-mounted serial/deserializer and control system and method for recovery of vehicle-mounted serial/deserializer - Google Patents
Vehicle-mounted serial/deserializer and control system and method for recovery of vehicle-mounted serial/deserializer Download PDFInfo
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Abstract
The invention relates to a vehicle-mounted serializer/deserializer and a control system and method for recovering the same. The control system includes: the data delay circuit is used for connecting a reverse low-speed data receiver in the serial/deserializer, receiving a receiving signal received by the reverse low-speed data receiver in real time and outputting a delay signal according to the receiving signal; the sampler is positioned at the downstream of the data delay circuit and outputs a sampling signal according to the received signal and the delay signal; the logic judging circuit is positioned at the downstream of the sampler, judges whether the link is abnormal according to the sampling signal and outputs a control signal; and the controller is connected with the logic judging circuit and controls the link according to the control signal. The invention detects the abnormal condition of the transmission link of the vehicle-mounted serial/deserializer in real time and recovers the communication of the serial/deserializer in real time.
Description
Technical Field
The invention relates to the technical field of data transmission; in particular, the present invention relates to a control system and method for an in-vehicle serializer/deserializer and its recovery.
Background
In the field of automotive communications, asymmetric rate full duplex serializer/deserializer (SerDes) technology is widely applied to scenes such as vehicle-mounted cameras, vehicle-mounted multimedia audio/video transmission, and the like. In order to ensure stability and reliability of the transmission link, the high-speed transmitting end of the SerDes in the application scenario needs to transmit high-speed data and simultaneously receive a low-speed control signal from the receiving end.
However, when an abnormal situation occurs in the transmission link of the SerDes, the signal of the high-speed transmitting port is seriously affected, and thus the low-speed control signal cannot be stably received, which finally results in that the SerDes cannot meet the development requirement of the data transmission technology in the field of automobile communication.
Disclosure of Invention
In view of the above, the present invention provides an on-board serializer/deserializer and a control system and method for its recovery that solve or at least mitigate one or more of the above-identified problems and other problems with the prior art.
To achieve the foregoing object, a first aspect of the present invention provides a control system for recovering a transmission link of an in-vehicle asymmetric rate full duplex serializer/deserializer in real time, wherein the control system includes:
the data delay circuit is used for connecting a reverse low-speed data receiver in the serial/deserializer, receiving a receiving signal received by the reverse low-speed data receiver in real time and outputting a delay signal according to the receiving signal;
The sampler is positioned at the downstream of the data delay circuit and outputs a sampling signal according to the received signal and the delay signal;
The logic judging circuit is positioned at the downstream of the sampler, judges whether the link is abnormal according to the sampling signal and outputs a control signal; and
And the controller is connected with the logic judging circuit and is used for controlling the link according to the control signal.
In the control system as described above, optionally, the received signal includes a first received signal and a second received signal, the delayed signal includes a first delayed signal and a second delayed signal, polarities of the first received signal and the second received signal are opposite, and polarities of the first delayed signal and the second delayed signal are opposite.
In the control system as described above, optionally, the sampler samples the delayed signal by a falling edge of the received signal to obtain the sampled signal or the sampler samples the received signal by a rising edge of the delayed signal to obtain the sampled signal.
In the control system as described above, optionally, the logic determination circuit counts the sampling signals, and clears the count every time M.
In the control system as described above, optionally, the control signals include a first control signal and a second control signal,
When the number of low-level signals in the sampling signals is less than or equal to N, the logic judging circuit judges that the link is in a normal state and outputs the first control signal;
when the number of high-level signals in the sampling signals is larger than N, the logic judging circuit judges that the link is in an abnormal state and outputs the second control signal.
In the control system as described above, optionally,
When the controller receives the first control signal, the controller monitors the link;
when the controller receives the second control signal, the controller restores the link when the abnormal condition is resolved before the controller resets the state of the circuit to the link for communication.
In the control system as described above, optionally, the serializer/deserializer includes:
The transmitting terminal comprises a forward high-speed data transmitter and a forward high-speed data receiver, wherein the forward high-speed data transmitter is used for transmitting forward high-speed data, and the forward high-speed data transmitter is used for receiving the forward high-speed data;
A receiving end including a reverse low-speed data transmitter for transmitting reverse low-speed data to the reverse low-speed data receiver and the reverse low-speed data receiver,
And the forward high-speed data transmitter and the forward high-speed data receiver and the reverse low-speed data transmitter and the reverse low-speed data receiver are connected by a cable or a shielded twisted pair.
To achieve the foregoing object, a second aspect of the present invention provides a method for recovering a transmission link of an on-board asymmetric-rate full duplex serializer/deserializer in real time based on the control system according to any one of the foregoing first aspect, wherein the method steps are as follows:
step A: the data delay circuit receives the received signal in real time and outputs the delay signal;
And (B) step (B): the sampler receives the received signal and the delay signal, and outputs the sampling signal;
Step C: the logic judging circuit receives the sampling signal and outputs the control signal;
step D: and C, the controller controls the link and returns to the step A.
In order to achieve the foregoing object, a third aspect of the present invention provides an on-board asymmetric rate full duplex serializer/deserializer for an automotive communication system, wherein the serializer/deserializer is connected with the control system as in any of the foregoing first aspects.
In the serializer/deserializer as described above, optionally, the serializer/deserializer further includes:
The transmitting end comprises a forward high-speed data transmitter and a reverse low-speed data receiver, wherein the forward high-speed data transmitter is used for transmitting forward high-speed data, and the reverse low-speed data receiver is used for receiving and transmitting the receiving signals;
The receiving end comprises a reverse low-speed data transmitter and a forward high-speed data receiver, wherein the reverse low-speed data transmitter is used for transmitting the receiving signal to the reverse low-speed data receiver, and the forward high-speed data receiver is used for receiving the forward high-speed data.
In the serializer/deserializer described above, the transmitting end and the receiving end are optionally connected by a cable or shielded twisted pair.
The invention provides an on-board serializer/deserializer and a control system and method for recovering the same. The control system of the invention samples the delay signal of the high-speed transmitting end of the vehicle-mounted serial/deserializer by detecting the signal of the high-speed transmitting end of the vehicle-mounted serial/deserializer according to specific logic, further judges the working condition of the transmission link of the vehicle-mounted serial/deserializer according to specific standards, and finally recovers the transmission link in real time by the controller. The control system of the invention effectively detects the abnormal condition of the transmission link of the vehicle-mounted serial/deserializer and restores the work of the transmission link in real time, so that the SerDes meets the development requirement of the data transmission technology in the field of vehicle communication.
Drawings
The present disclosure will become more apparent with reference to the accompanying drawings. It is to be understood that these drawings are solely for purposes of illustration and are not intended as a definition of the limits of the invention. In the figure:
FIG. 1 is a schematic block diagram of one embodiment of a control system for recovering in real time a transmission link of an on-board asymmetric-rate full duplex serializer/deserializer of the present invention;
FIG. 2 is a schematic diagram of the principle of operation of the sampler in the embodiment shown in FIG. 1; and
Fig. 3 is a schematic diagram of an anomaly that may occur in the transmission link of the on-board SerDes.
Detailed Description
With reference to the drawings and the specific embodiments, the structure, composition, features, advantages, etc. of an on-board serializer/deserializer and its recovered control system and method of the present invention will be described below by way of example, but all descriptions should not be used to limit the present invention in any way.
Furthermore, to the extent that any individual feature described or implied in the embodiments set forth herein, or any individual feature shown or implied in the figures, the invention still allows any combination or deletion of such features (or equivalents thereof) without any technical hurdle, and further embodiments according to the invention are considered to be within the scope of the disclosure herein.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature.
FIG. 1 is a schematic block diagram of one embodiment of a control system of the present invention, which may include a data delay circuit, a sampler, a logic determination circuit, and a controller. As can be seen from fig. 1, one side of the data delay circuit of the control system is connected with the reverse low-speed data receiver of the SerDes at the upstream thereof, and the other side is connected with the sampler, the logic judgment circuit and the controller at the downstream thereof in series.
In this embodiment, the reverse low-speed data receiver of the SerDes transmits the received signal sent by the receiving end of the SerDes to the data delay circuit on one hand and to the sampler on the other hand; the data delay circuit receives the received signal in real time and outputs a delay signal to the sampler according to the received signal; the sampler outputs sampling signals to the logic judging circuit according to the delay signals and the receiving signals; the logic judging circuit judges whether the circuit is abnormal according to the sampling signal, and then generates a control signal and transmits the control signal to the controller; finally, the control system controls the circuit through the controller.
Specifically, the received signal is transmitted to the data delay circuit and the sampler through the reverse low-speed data receiver. The data delay circuit generates a delay signal corresponding to the received signal according to the received signal after receiving the received signal, and transmits the delay signal to a sampler at the downstream of the data delay circuit. And after the sampler receives the delay signal and the receiving signal sent by the reverse low-speed data receiver, sampling the delay signal by the falling edge of the receiving signal or sampling the receiving signal by the rising edge of the delay signal, and finally generating a sampling signal.
In this embodiment, the delay time set by the data delay circuit is set according to specific practice and experience resulting from the practice, and in other alternative embodiments, the specific delay time can be set by one skilled in the art according to the minimum pulse width of the received signal.
The received signal includes a first received signal and a second received signal, and the delayed signal includes a first delayed signal and a second delayed signal, where polarities of the first received signal and the second received signal are opposite, and polarities of the first delayed signal and the second delayed signal are opposite.
It is very difficult to determine whether an abnormality occurs in the transmission link of the SerDes by only the reception signal received by the reverse low-speed data receiver, and the data delay circuit effectively solves this problem. The data delay circuit generates a delay signal based on the received signal, so that the control system can further process the received signal and the delay signal to judge whether the transmission link is abnormal or not.
Fig. 2 is a schematic diagram of the working principle of the sampler in the embodiment shown in fig. 1, where fig. 2 (a) is a graph of a received signal, a delayed signal and a sampled signal when no abnormal condition occurs in a transmission link of the SerDes, and fig. 2 (b) is a graph of a received signal, a delayed signal and a sampled signal when an abnormal condition occurs in a transmission link of the SerDes.
As can be seen from fig. 2 (a), when the transmission link of the SerDes operates normally, the minimum signal pulse width of the received signal is a normal value and is greater than the delay time set by the data delay circuit. In this case, when the sampler samples the delayed signal by a falling edge in the received signal or samples the received signal by a rising edge of the delayed signal, the obtained sampled signal must be a high level signal.
When an abnormal condition occurs in the transmission link of the SerDes, the received signal received by the reverse low-speed data receiver is subject to crosstalk of the high-speed data transmitted by the forward high-speed transmitter of the SerDes, the frequency of the received signal is increased, and the minimum signal pulse width of the received signal is smaller than the minimum signal pulse width in normal operation under the condition that the duty ratio is unchanged.
As can be seen from fig. 2 (b), when an abnormal situation occurs in the transmission link of the SerDes, the minimum signal pulse width of the received signal in fig. 2 (b) is smaller and smaller than the delay time set by the data delay circuit, compared with the received signal in fig. 2 (a). In this case, when the sampler samples the delayed signal by a falling edge in the received signal or samples the received signal by a rising edge of the delayed signal, a low-level signal appears in the obtained sampled signal.
Therefore, whether the transmission link of the SerDes works normally or not or whether the transmission link of the SerDes is abnormal or not, the control system can convert normal and abnormal received signals into sampling signals corresponding to the normal and abnormal received signals, and accordingly the control system can judge whether the transmission link of the SerDes is abnormal or not through the sampling signals.
The setting of delay time in the data delay circuit has a certain subjectivity, and partial tiny errors can be generated when the delay time is compared with the minimum signal pulse width of the received signal, and the working state of the transmission link cannot be judged through single judgment in the sampler, so that the control system provided by the invention is provided with a logic judgment circuit.
As can be seen from fig. 1, the sampling signal generated by the sampler is transmitted to the logic judgment circuit, the logic judgment circuit receives the sampling signal and counts, and the logic judgment circuit clears the count every time M. The logic judgment circuit can judge whether the transmission link works normally or not through the following logic:
When the number of low-level signals in the sampling signals is less than or equal to N, the logic judging circuit judges that the link is in a normal state and outputs a first control signal;
when the number of low-level signals in the sampling signals is larger than N, the logic judging circuit judges that the link is in an abnormal state and outputs a second control signal.
It should be noted here that, in this embodiment, the time M may be any time from 0.1 microsecond to 10 microseconds, for example, 1 microsecond, and the number N may be any value from 1 to 20, for example, 4. In alternative embodiments, the time M and the number N may take other suitable values.
In addition, in this embodiment, in order to achieve the above object, the logic determination circuit may employ a saturation type counter, and the saturation type counter may measure a fixed number within a certain period of time, so as to meet the working requirement of the logic determination circuit in the present invention. In alternative embodiments, the logic determination circuit may be other devices or circuits having a determination function and a control signal output function.
The controller receives the control signal output from the logic judgment circuit and controls the transmission link according to the control signal. Specifically, the control signal comprises a first control signal and a second control signal, when the link is in a normal working state, the logic judgment circuit continuously outputs the first control signal to the controller, and the controller monitors the transmission link; when the controller receives the second control signal, the link is in an abnormal state, and the controller resets the state of the circuit in real time until the serializer and the deserializer communicate with each other. When the abnormal situation is solved, the controller restores the link in real time, the serializer and the deserializer re-handshake, and the controller receives the first control signal again and is in a state of monitoring the transmission link again. Therefore, the control system provided by the invention can quickly recover the transmission link in real time on the basis of detecting the fault of the transmission link of the SerDes, thereby ensuring the normal operation of the asymmetric rate full duplex SerDes.
The invention also provides a method for the control system to quickly recover the transmission link of the asymmetric rate full duplex serial/deserializer in real time, which comprises the following steps:
step A: the data delay circuit receives the received signal in real time and outputs a delay signal;
and (B) step (B): the sampler receives the received signal and the delay signal and outputs a sampling signal;
step C: the logic judging circuit receives the sampling signal and outputs a control signal;
step D: and C, the controller controls the link and returns to the step A.
Next, each step will be described in detail.
And step A is used for acquiring the received signal and generating a corresponding delay signal. The received signal received by the reverse low-speed data receiver is a key physical quantity for judging whether the transmission link of the SerDes fails, so in the step A, the reverse low-speed data receiver transmits the received signal to the data delay circuit and the sampler, and the data delay circuit generates a delay signal based on the received signal;
step B generates a corresponding sampling signal based on the received signal. In the step B, a sampler receives the received signal and the delay signal and generates a sampling signal through a certain sampling logic;
And C, judging the link state based on the sampling signal and generating a control signal. In the step C, a logic judgment circuit receives a sampling signal, judges the link state through certain judgment logic and generates a corresponding control signal;
step D is used for fast real-time recovery of the link. In step D, the controller receives the control signal and controls the transmission link according to the type of the control signal.
Fig. 3 is a schematic diagram of an abnormal situation that may occur in the transmission link of the vehicle-mounted SerDes, where fig. 3 (a) is a schematic diagram of an abnormal situation that may occur in the vehicle-mounted SerDes in the single-ended operation mode, and fig. 3 (b) is a schematic diagram of an abnormal situation that may occur in the vehicle-mounted SerDes in the differential operation mode. As can be seen from fig. 3, the transmission link of the SerDes includes a transmitting end and a receiving end, where the transmitting end includes a forward high-speed data transmitter and a reverse low-speed data receiver, the forward high-speed data transmitter is used for transmitting forward high-speed data, and the reverse low-speed data receiver is used for receiving and transmitting a receiving signal; the receiving end comprises a reverse low-speed data transmitter and a forward high-speed data receiver, wherein the reverse low-speed data transmitter is used for transmitting a receiving signal to the reverse low-speed data receiver, and the forward high-speed data receiver is used for receiving forward high-speed data. And the forward high-speed data transmitter and the forward high-speed data receiver and the reverse low-speed data transmitter and the reverse low-speed data receiver are connected by a cable or a shielded twisted pair.
When the position a and the position c in the diagram (a) of fig. 3 are disconnected, no signal exists in the transmission link, and the existing technical scheme based on the amplitude detection of the decoupling signal can distinguish the abnormal condition from the normal working condition; however, when only a is broken in fig. 3 (a) or only d is broken in fig. 3 (b), the conventional solution based on the detection of the amplitude of the decoupling signal cannot distinguish the abnormal situation from the normal working situation because the signal still exists in the transmission link, and because the influence of the near-end disconnection and the far-end disconnection of the high-speed transmitting end of the SerDes transmission link on the port signal is different, it is difficult to identify all the abnormal situations by the conventional detection technology. However, wherever the diagrams (a) and (b) of fig. 3 are broken, the received signal of the reverse low-speed data receiver at the transmitting end of the SerDes will be subjected to crosstalk of the forward high-speed signal, so that the present invention can effectively monitor the transmission link with respect to the received signal of the reverse low-speed data receiver.
The invention also provides a vehicle-mounted asymmetric rate full-duplex serializer/deserializer for an automobile communication system, wherein the serializer/deserializer is connected with a control system, and the serializer/deserializer further comprises:
The transmitting end comprises a forward high-speed data transmitter and a reverse low-speed data receiver, wherein the forward high-speed data transmitter is used for transmitting forward high-speed data, and the reverse low-speed data receiver is used for receiving and transmitting the receiving signals;
The receiving end comprises a reverse low-speed data transmitter and a forward high-speed data receiver, wherein the reverse low-speed data transmitter is used for transmitting the receiving signal to the reverse low-speed data receiver, and the forward high-speed data receiver is used for receiving the forward high-speed data.
In addition, the transmitting end and the receiving end may be connected by a cable or a shielded twisted pair. Specifically, as shown in the figure, the forward high-speed data transmitter and the forward high-speed data receiver and the reverse low-speed data transmitter and the reverse low-speed data receiver are connected by a cable or a shielded twisted pair.
In summary, the present invention provides an on-vehicle serializer/deserializer and a control system and method for recovering the same. The control system of the invention samples the delay signal of the high-speed transmitting end of the vehicle-mounted serial/deserializer by detecting the signal of the high-speed transmitting end of the vehicle-mounted serial/deserializer according to specific logic, further judges the working condition of the transmission link of the vehicle-mounted serial/deserializer according to specific standards, and finally recovers the transmission link in real time by the controller. The control system of the invention effectively detects the abnormal condition of the transmission link of the vehicle-mounted serial/deserializer and restores the work of the transmission link in real time, so that the SerDes meets the development requirement of the data transmission technology in the field of vehicle communication.
The technical scope of the present invention is not limited to the above description, and those skilled in the art may make various changes and modifications to the above-described embodiments without departing from the technical spirit of the present invention, and these changes and modifications should be included in the scope of the present invention.
Claims (10)
1. A control system for recovering in real time a transmission link of an on-board asymmetric rate full duplex serializer/deserializer, the control system comprising:
the data delay circuit is used for connecting a reverse low-speed data receiver in the serial/deserializer, receiving a receiving signal received by the reverse low-speed data receiver in real time and outputting a delay signal according to the receiving signal;
The sampler is positioned at the downstream of the data delay circuit and outputs a sampling signal according to the received signal and the delay signal;
The logic judging circuit is positioned at the downstream of the sampler, judges whether the link is abnormal according to the sampling signal and outputs a control signal; and
And the controller is connected with the logic judging circuit and is used for controlling the link according to the control signal.
2. The control system of claim 1, wherein the received signal comprises a first received signal and a second received signal, the delayed signal comprises a first delayed signal and a second delayed signal, the first received signal is of opposite polarity to the second received signal, and the first delayed signal and the second delayed signal are of opposite polarity.
3. The control system of claim 1, wherein the sampler samples the delayed signal by a falling edge of the received signal to obtain the sampled signal or the sampler samples the received signal by a rising edge of the delayed signal to obtain the sampled signal.
4. The control system of claim 1 wherein said logic determination circuit counts said sampled signals, said logic determination circuit clears the count every time M.
5. The control system of claim 1, wherein the control signals comprise a first control signal and a second control signal,
When the number of low-level signals in the sampling signals is less than or equal to N, the logic judging circuit judges that the link is in a normal state and outputs the first control signal;
when the number of high-level signals in the sampling signals is larger than N, the logic judging circuit judges that the link is in an abnormal state and outputs the second control signal.
6. The control system of claim 5, wherein,
When the controller receives the first control signal, the controller monitors the link;
When the controller receives the second control signal, the controller restores the link when the abnormal condition is resolved before resetting the state of the circuit to the link for communication.
7. The control system of claim 1, wherein the serializer/deserializer comprises:
The transmitting end comprises a forward high-speed data transmitter and a reverse low-speed data receiver, wherein the forward high-speed data transmitter is used for transmitting forward high-speed data, and the reverse low-speed data receiver is used for receiving and transmitting the receiving signals;
A receiving end including a reverse low-speed data transmitter for transmitting the reception signal to the reverse low-speed data receiver and a forward high-speed data receiver for receiving the forward high-speed data,
And the forward high-speed data transmitter and the forward high-speed data receiver and the reverse low-speed data transmitter and the reverse low-speed data receiver are connected by a cable or a shielded twisted pair.
8. Method for recovering in real time the transmission link of an on-board asymmetric rate full duplex serializer/deserializer based on the control system according to any of the previous claims 1 to 7, characterized by the following steps:
step A: the data delay circuit receives the received signal in real time and outputs the delay signal;
And (B) step (B): the sampler receives the received signal and the delay signal, and outputs the sampling signal;
Step C: the logic judging circuit receives the sampling signal and outputs the control signal;
step D: and C, the controller controls the link and returns to the step A.
9. An on-board asymmetric rate full duplex serializer/deserializer for an automotive communication system, wherein the serializer/deserializer is connected with a control system as in any of claims 1-7.
10. The serializer/deserializer of claim 9, wherein the serializer/deserializer further comprises:
The transmitting end comprises a forward high-speed data transmitter and a reverse low-speed data receiver, wherein the forward high-speed data transmitter is used for transmitting forward high-speed data, and the reverse low-speed data receiver is used for receiving and transmitting the receiving signals;
A receiving end including a reverse low-speed data transmitter for transmitting the reception signal to the reverse low-speed data receiver and a forward high-speed data receiver for receiving the forward high-speed data,
The transmitting end and the receiving end are connected through a cable or a shielded twisted pair.
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| US10447506B1 (en) * | 2016-04-01 | 2019-10-15 | Aquantia Corp. | Dual-duplex link with independent transmit and receive phase adjustment |
| CN112084137B (en) * | 2020-08-20 | 2023-05-09 | 南京航空航天大学 | SerDes high-robustness transceiver circuit |
| CN115878536A (en) * | 2022-11-11 | 2023-03-31 | 珠海天威技术开发有限公司 | Communication method of serial bus, data signal sampling circuit of serial bus and sampling method |
| CN117744583A (en) * | 2023-12-22 | 2024-03-22 | 成都海光集成电路设计有限公司 | Chip under test for improving parallel test channel rate, method, electronic device and storage medium |
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| A 13-Gb/s Single-Ended NRZ Receiver With 1-Sample per 2-UI Using Data Edge Sampling for Memory Interfaces;Hyoshin Kang et.al;《IEEE Transactions on Circuits and Systems II: Express Briefs ( Early Access )》;20240206;全文 * |
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