CN118072784A - Method and circuit for adaptively generating column select line signals - Google Patents

Abstract

The invention provides a method and a circuit for adaptively generating a column selection line signal. The method comprises the following steps. Generating a second signal from a selected candidate signal of a plurality of candidate signals including a first candidate signal and a second candidate signal, wherein in response to the first signal being set to an active state, the first candidate signal is set to an active state when a configurable time interval associated with a parameter from a register set has elapsed; when a certain time interval elapses, the second candidate signal is set to an active state; and after the first signal is set to an active state, the selected candidate signal is set to an active state prior to the remaining portion of the plurality of candidate signals. A column select line signal is generated from the first signal and the second signal.

Description

Method and circuit for adaptively generating column select line signals

Technical Field

The present invention relates to a method and a circuit for adaptively generating a column select line signal, and more particularly, to a method and a circuit for adaptively generating a column select line signal for a memory device.

Background

Referring to FIG. 1, a bit line sense amplifier architecture for a Dynamic Random Access Memory (DRAM) is shown. In fig. 1, a sense amplifier SA is used for a read or write operation of a DRAM. The sense amplifier SA has terminals connected to a pair of bit lines designated BL and BL, and has terminals electrically coupled to a pair of data lines designated DL and DL through switches (e.g., transistors) controlled by column-select line (CSL) signals.

Referring to FIG. 2, the operation of the DRAM of FIG. 1 in relation to Column Select Line (CSL) signals is shown in a timing diagram, wherein signal names above the dash-dot line, such as signal CK_t, command (e.g., write (WR) or Read (RD)), LDQS_t, DQ [0:7 represents an external signal (e.g., originating from an external device such as a host), and a signal name below the dash-dot line, such as BL, CSL, DL, etc., represents an internal signal (e.g., originating from the internal operation of the DRAM control circuit). Referring to fig. 1 and 2, when a read command is executed in the DRAM, the CSL signal is set to be active (asserted) (e.g., in a high state) for a certain period of time (i.e., an access period) so that the plurality of switches are turned on and data read from the memory cells (not shown) to reach the plurality of bit lines can be applied to the plurality of data lines through the plurality of switches. When a write command is executed in the DRAM, the CSL signal is set to be active for a certain period of time (i.e., an access period) so that the plurality of switches are turned on and data to be written to memory cells (not shown) on the plurality of data lines can be applied to the plurality of bit lines through the plurality of switches. As shown in FIG. 2, after an access cycle, the CSL signal is set to an inactive state (de-asserted) (e.g., in a low state).

Referring to FIG. 2, for a write command (e.g., denoted as WR) operation, the memory specifications require corresponding data line signals (e.g., denoted as DL and) Reset during the precharge period after the access period has elapsed to gradually reach the respective appropriate voltage level. For write or read commands, the corresponding data line signals (e.g., denoted as DL and/>) Cannot be reset to reach the respective appropriate voltage level, and subsequent write or read commands to the DRAM device may fail.

Disclosure of Invention

It is an object of the present invention to propose a method and a device for adaptively generating a column select line signal for a memory device to adaptively control the column select line signal, thereby contributing to the stability of an access operation of the memory device.

To achieve at least the above object, the present invention proposes a method of adaptively generating a column select line signal for a memory device, the method comprising the following steps. A first signal is generated in response to a memory access command. Generating a second signal from a selected candidate signal of a plurality of candidate signals including a first candidate signal and a second candidate signal, wherein in response to the first signal being set to an active state, the first candidate signal is set to an active state when a configurable time interval associated with a parameter from a register set has elapsed; when a certain time interval elapses, the second candidate signal is set to an active state; and after the first signal is set to an active state, the selected candidate signal is set to an active state prior to the remaining portion of the plurality of candidate signals. A column select line signal is generated from the first signal and the second signal.

In some embodiments, the step of generating the second signal comprises the following steps. The selected candidate signal is determined from the plurality of candidate signals, wherein after the first signal is set to an active state, the selected candidate signal is set to an active state prior to the remaining portion of the plurality of candidate signals. Outputting the selected candidate signal as the second signal.

In some embodiments, the step of generating the second signal further comprises the following steps. After the first signal is set to an active state, the first candidate signal is generated according to the configurable time interval associated with the parameter from the register set. The second candidate signal is generated according to the specific time interval after the first signal is set to an active state.

In some embodiments, the step of generating the column select line signal includes the following steps. The first signal and the second signal are received to generate the column select line signal. After the first signal is set to an active state, the column select line signal is set to an active state. After the second signal is set to an active state, the column select line signal is set to an inactive state.

To achieve at least the above object, the present invention proposes a circuit for adaptively generating a column select line signal for a memory device, the circuit comprising: an initial signal generating circuit, a column selection line signal control circuit, and a column selection line signal output circuit. The initial signal generation circuit is configured to generate a first signal in response to a memory access command. The column selection line signal control circuit is coupled to the initial signal generation circuit and configured to generate a second signal according to a candidate signal selected from a plurality of candidate signals including a first candidate signal and a second candidate signal, wherein after the first signal is set to an active state, the first candidate signal is set to an active state when a configurable time interval associated with a parameter from a register set has elapsed; when a certain time interval elapses, the second candidate signal is set to an active state; and after the first signal is set to an active state, the selected candidate signal is set to an active state prior to the remaining portion of the plurality of candidate signals. The column select line signal output circuit is coupled to the column select line signal control circuit and configured to generate a column select line signal based on the first signal and the second signal.

In some embodiments, the column select line signal control circuit includes a control circuit configured to determine the selected candidate signal from the plurality of candidate signals, wherein after the first signal is set to an active state, the selected candidate signal is set to an active state prior to the remaining portion of the plurality of candidate signals, and the control circuit is configured to output the selected candidate signal as the second signal.

In some embodiments, the column select line signal control circuit also includes a first candidate signal generation circuit and a second candidate signal generation circuit. The first candidate signal generation circuitry is configured to generate the first candidate signal in accordance with the configurable time interval associated with the parameter from the register set after the first signal is set to an active state. The second candidate signal generation circuit is configured to generate the second candidate signal according to the specific time interval after the first signal is set to an active state.

In some embodiments, the column select line signal output circuit includes a first signal input, a second signal input, a column select line signal output, and output logic. The first signal input end is used for receiving the first signal. The second signal input end is used for receiving the second signal. The column selection line signal output terminal is used for outputting the column selection line signal. The output logic circuit is configured to generate the column select line signal, wherein the output logic circuit is configured to set the column select line signal to an active state after the first signal is set to an active state, and the output logic circuit is configured to set the column select line signal to an inactive state after the second signal is set to an active state.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that need to be used in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 (Prior Art) is a schematic diagram of the architecture of a bit line sense amplifier for a Dynamic Random Access Memory (DRAM).

FIG. 2 (Prior Art) is a timing diagram showing the operation of the DRAM of FIG. 1 in relation to Column Select Line (CSL) signals.

FIG. 3 is a timing diagram for illustrating the problem of insufficient precharge period of a Column Select Line (CSL) signal.

FIG. 4 is a timing diagram illustrating another problem of having a longer access time than designed for Column Select Line (CSL) signals due to process variations.

FIG. 5 is a flow chart illustrating a method of adaptively generating a column select line signal according to one embodiment of the invention.

Fig. 6 is a timing diagram showing generation of Column Select Line (CSL) signals of a DRAM according to a first signal (CAI) and a second signal (CAD) according to an embodiment of the present invention.

Fig. 7 is a timing diagram showing one example of generating a Column Select Line (CSL) signal using a second signal (CAD) generated from a plurality of candidate signals and based on the embodiment of fig. 5.

Fig. 8 is a timing diagram showing another example of generating a Column Select Line (CSL) signal using a second signal (CAD) generated from a plurality of candidate signals and based on the embodiment of fig. 5.

Fig. 9 is a block diagram showing an architecture of a circuit for generating a Column Select Line (CSL) signal from a first signal (CAI) and a second signal (CAD) according to an embodiment of the invention.

FIG. 10 is a block diagram illustrating one embodiment of the Column Select Line (CSL) signal control circuit of FIG. 9.

FIG. 11 is a block diagram illustrating one embodiment of a control circuit to generate a second signal (CAD) from a plurality of candidate signals.

FIG. 12 is a block diagram illustrating one embodiment of a control circuit to generate a second signal (CAD) from a plurality of candidate signals.

FIG. 13 is a block diagram illustrating one embodiment of a control circuit to generate a second signal (CAD) from a plurality of candidate signals.

Fig. 14 is a timing diagram showing one example of using the control circuit of fig. 13 to generate a second signal (CAD) from a plurality of candidate signals.

FIG. 15 is a block diagram illustrating one embodiment of a candidate signal generation circuit.

Fig. 16 is a schematic circuit diagram illustrating one embodiment of the delay chain circuit of fig. 15.

Fig. 17 is a timing chart showing an example of generating a candidate signal (cad_ck) using the control circuits of fig. 15 and 16.

Fig. 18 is a block diagram showing an architecture according to a memory device, in which a circuit for adaptively generating a Column Select Line (CSL) signal according to a first signal (CAI) and a second signal (CAD) according to an embodiment of the present invention is applied.

Reference numerals illustrate:

1. Circuit for adaptively generating column select line signals

10. Initial signal generating circuit

20. 20A CSL signal control circuit

21. 21A, 21B, 21C control circuit

23. 23A, 25 candidate signal generating circuit

30 CSL signal output circuit

90. Mode register set

211. 213 Switch

215. 217 Logic circuit

225. 227 Switch controller

231. 231A delay chain circuit

233. Multi-path selector

237. Pulse generator

500. Memory device

510. Command input interface

520. Row command decoder

530. Column command decoder

535 CSL signal control circuit

540. Column control circuit

550. Row control circuit

560. Memory cell array

570. Data input/output interface

580. Data control circuit

590. Mode register set

BL、Bit line

DL、Data line

SA sense amplifier

Ck_t clock signal

TCK clock period

WR write command

RD read command

LDQS_t and DQ signals

CSL column select line

TWTR_L write to read command delay

Long delay between tccd_l commands

VCC supply voltage

CAI first signal

CAD second signal

CAD_CK, CAD_DE candidate signal

CS1, CS2 control signal

EN_CK and EN_DE control signals

DL 11-DL 20 delay cell

Input terminal of D delay unit

Output terminal of Q delay unit

DCK clock signal

Inverted version of clock signal DCK

Delay signals of CAD_CK00, CAD_CK05-CAD_CK40

WL write latency

BANK [0], BANK [1] to BANK [ n ] memory BANKs

S10 to S30 steps

Detailed Description

The method and circuit for adaptively generating column select line signals according to the embodiments of the present invention will be further described with reference to the accompanying drawings.

Before providing various embodiments in accordance with the present invention in various aspects, the inventors' observations and studies of generating column-select line (CSL) signals during operation of DRAM devices will be described.

In one example, a control circuit of a DRAM device is configured to generate a Column Select Line (CSL) signal having an access period of a particular number of clock cycles, represented by k tCK, according to a configurable parameter k, where k is a configurable parameter representing a particular number of clock cycles. For example, parameter k is stored or programmed in, for example, a register set, e.g., a mode register that meets memory specifications such as DDR2, DDR3, DDR4, etc. (referred to as the DDR family). Depending on the DDR series memory specification employed by the DRAM device, the appropriate value of parameter k can be provided or programmed in the control circuitry of the DRAM device, and parameter k can be set to one of the provided values in response to a setting made by the control circuitry of the DRAM device or a computer system using the DRAM device. However, in some cases, as observed by the inventors, the value of parameter k may be set to an inappropriate value such that the Column Select Line (CSL) signal has an insufficient precharge period. Referring to fig. 3, a timing diagram is shown for the problem of insufficient precharge period of the Column Select Line (CSL) signal. In the example shown in fig. 3, the value of the parameter k is 4, so that the access period of the Column Select Line (CSL) signal is 4 clock cycles (e.g., 4 tck), and the precharge period is 2 clock cycles (e.g., 2 tck). In the worst case, as shown in FIG. 3, for an operation of a write command with a delay (e.g., denoted by tWTR_L or referred to as write-to-read command delay) from an internal write transaction (write transaction) to an internal read command for the same bank group, the corresponding data line signals (e.g., by DL and DLIndicated) cannot be reset to their respective appropriate voltage levels (e.g., higher voltage levels in the case of DL, such as supply voltage VCC; just/>For example, a lower voltage level) is due to the precharge period having only two clock cycles (i.e., 2 tck). Thus, after the write command is completed, the DRAM device cannot execute a read command with CAS_n-CAS_n command latency (e.g., represented by tCCD_L or referred to as long latency between commands) for the same bank group because of the data line signals DL and/>Are not reset to their respective appropriate voltage levels during a previous write command, where CAS stands for column-address-strobe. In addition, as shown in fig. 3, the read command with tccd_l is executed within 4 clock cycles, but the access period of the Column Select Line (CSL) signal is 4 clock cycles (e.g., 4 tck) with a delay, which also results in the operation failure of the read command.

In another example, a control circuit of a DRAM device is configured to generate a Column Select Line (CSL) signal having an access period of a particular time interval. The specific time interval is defined to be a value conforming to the DDR series memory specification by using a dedicated signal generating circuit in the control circuit, for example. The signal generation circuit may be designed by internal circuit components to generate a Column Select Line (CSL) signal as desired, depending on the DDR family of memory specifications employed by the DRAM device. However, in some cases, as observed by the inventors, the signal generation circuit may suffer from process, voltage and temperature (process, voltage and temperature, PVT) variations such that the Column Select Line (CSL) signal has an insufficient precharge period. Referring to fig. 4, a timing diagram illustrating a problem of a Column Select Line (CSL) signal having an access time (e.g., 3.5ns or more) longer than a specified time interval (e.g., 2.5 ns) due to process variations (such as PVT) of a DRAM device is shown. As shown in the example of fig. 4, the thick arrow indicates that the falling edge indicated by the solid line, which is designed for the access time of the Column Select Line (CSL) signal, is extended to the falling edge indicated by the broken line, resulting in a smaller precharge period. This can lead to potential risks for subsequent operation of the DRAM device. In the worst case, the precharge period may be so insufficient that the corresponding data line signals (e.g., denoted as DL and) Failing to be reset to the respective appropriate voltage level causes a write or read failure in the DRAM device.

With respect to the above-mentioned problems observed and studied by the inventors, the following techniques for adaptively generating Column Select Line (CSL) signals are presented in accordance with various embodiments of the present invention in various aspects.

Referring to fig. 5, a flow chart illustrating a method of adaptively generating a column select line signal according to one embodiment of the present invention may represent various embodiments based on the embodiment of fig. 5. As shown in fig. 5, the method for adaptively generating the column select line signal includes steps S10 to S30.

In step S10, a first signal (e.g., denoted as CAI) is generated in response to the memory access command.

In step S20, a second signal (e.g., denoted as CAD) is generated based on a selected candidate signal of the plurality of candidate signals, wherein after the first signal is set to an active state, the selected candidate signal is set to an active state prior to the remaining unselected candidate signals of the plurality of candidate signals. The plurality of candidate signals may include at least two or more candidate signals.

In step S30, a Column Select Line (CSL) signal is generated from the first signal (CAI) and the second signal (CAD).

By the method shown in fig. 5, since the second signal (CAD) can be generated from a selected candidate signal among a plurality of candidate signals, the Column Selection Line (CSL) signal can be adaptively generated from the first signal (CAI) and the second signal (CAD). The plurality of candidate signals may be implemented to be set to an active state at a different time sequence after the first signal is set to an active state. Thus, the method shown in FIG. 5 may be implemented to adaptively control a Column Select Line (CSL) signal.

With respect to the "active state" (asserting) of a signal (or an alternative form thereof, such as "asserted" or "asserted"), it means that the signal is set to its enabled state (ACTIVE STATE) (or an enabled voltage level), which may be set to a high or low level. With respect to the "inactive state" (de-asserting) of the signal (or an alternative form thereof, such as "de-asserted" or "de-assertion"), it is meant that the signal is set to its inactive state (INACTIVE STATE) (or inactive voltage level), which may be set to a high or low level. If the signal is in the active-low state, then making the signal in the active state means that the signal is set to the low level, and making the signal in the inactive state means that the signal is set to the high level. If the signal is in the active-high state, then making the signal in the active state means that the signal is set to the high level, and making the signal in the inactive state means that the signal is set to the low level.

Referring to fig. 6, a timing diagram illustrating the generation of Column Select Line (CSL) signals of a DRAM according to a first signal (CAI) and a second signal (CAD) according to one embodiment of the method shown in fig. 3 is shown. As shown in fig. 6, when a write or read command (e.g., denoted as "WR" or "RD", respectively) is issued in a DRAM device conforming to a memory specification such as DDR2, DDR3, DDR4, or other, a first signal (e.g., denoted as CAI) is set to an active state (e.g., set to an active state as a pulse for a period of time) after a time interval of a certain number of clock cycles required according to the memory specification has elapsed, to indicate an initiation (or start) of an access cycle of the Column Select Line (CSL) signal. For example, when a write command is issued in a DRAM device, after a time interval equal to the write latency plus an additional number of clock cycles has elapsed, the first signal (CAI) is set to an active state, wherein the write latency (WRITE LATENCY, WL) is equal to the sum of the CAS Write Latency (CWL) and the additive latency (ADDITIVE LATENCY, AL). In one example, the Write Latency (WL) is set to 20 (clock period), with cwl=20 and al=0. As shown in fig. 6, in response to a write command issued during the T0 period of the clock signal ck_t, after a time interval of 24 clock cycles (e.g., wl=20 plus an additional 4 clock cycles) has elapsed, the first signal (CAI) is set to an active state as a pulse (e.g., the T24 period of the clock signal ck_t). As shown in fig. 6, after the Column Select Line (CSL) signal is set to an active state, a second signal (e.g., denoted as CAD) is set to an active state (e.g., set to an active state for a period of time as a pulse) to indicate an end of an access period of the Column Select Line (CSL) signal or to indicate an initiation (or start) of a precharge period of the Column Select Line (CSL) signal. As will be exemplified below, the second signal (CAD) is set to an active state in accordance with a candidate signal selected from a plurality of candidate signals. Of course, implementation of the present invention is not limited to the above examples. In some examples, in a DRAM device conforming to the DDR4 memory specification, the first signal (CAI) is set to active after a time interval equal to the write latency (wl=50 (clock cycles), where cwl=30 and al=20) plus an additional number of 2 or 4 clock cycles has elapsed to implement the method based on fig. 5.

Referring to fig. 7, a timing diagram of one example of generating a Column Select Line (CSL) signal using a second signal (CAD) generated from a plurality of candidate signals and based on the embodiment of fig. 5 is shown. In fig. 7, the plurality of candidate signals includes a candidate signal cad_ck and a candidate signal cad_de. After the first signal (CAI) is set to the active state, the candidate signal cad_ck is set to the active state when a configurable clock period of k×tck (e.g., k=4) has elapsed, and the candidate signal cad_de is set to the active state when a specific clock period (e.g., 2.5 ns) has elapsed. In this case, the candidate signal cad_ck is set to the active state before the candidate signal cad_de is set to the active state, so that the second signal (CAD) is determined based on the candidate signal cad_ck, thereby giving the Column Selection Line (CSL) signal an access period of 4×tck. In this way, the Column Select Line (CSL) signal will have a sufficient precharge period for a write command with a write to read command delay (tWTR_L) or a read command with a long delay between commands (tCCD_L), where tCCD_L is set to 8, for example, as in a mode register.

Referring to fig. 8, a timing diagram of another example of generating a Column Select Line (CSL) signal using a second signal (CAD) generated from a plurality of candidate signals and based on the embodiment of fig. 5 is shown. In contrast, the clock frequency shown in the example of fig. 8 is less than the clock frequency of fig. 7. Thus, the time of the clock cycle (e.g., tCK) is greater than the time of the clock cycle of fig. 7 in the example of fig. 8. In fig. 8, after the first signal (CAI) is set to the active state, when a configurable clock period of k×tck (e.g., k=4) elapses, the candidate signal cad_ck is set to the active state, and when a specific clock period (e.g., 2.5 ns) elapses, the candidate signal cad_de is set to the active state. In this case, the candidate signal cad_ck is set to the active state before the candidate signal cad_de is set to the active state, so that the second signal (CAD) is determined based on the candidate signal cad_ck, thereby giving the Column Selection Line (CSL) signal an access period of 2.5 ns. In this way, the Column Select Line (CSL) signal will have a sufficient precharge period for either a write command with tWTR_L or a read command with tCCD_L, where tCCD_L is set to 8, for example.

In some embodiments, the step of generating the second signal (CAD) (step S20) comprises the following steps. The selected candidate signal is determined from the plurality of candidate signals, wherein after the first signal is set to an active state, the selected candidate signal is set to an active state prior to the remaining portion of the plurality of candidate signals (or other candidate signals). The selected candidate signal is thus output as the second signal (CAD).

In some embodiments, the step of generating the second signal (CAD) (step S20) further comprises the following steps. After the first signal is set to an active state, a first candidate signal (e.g., cad_ck) is generated according to a configurable time interval associated with a parameter from a register set (e.g., including one or more registers). After the first signal is set to active, a second candidate signal (e.g., cad_de) is generated according to a specific time interval. For example, the mode register is a mode register that meets memory specifications such as DDR2, DDR3, DDR4, etc. (referred to as DDR family). For example, the configurable time interval may be equal to the parameter (e.g., k) times a clock cycle time (tCK), where k may be a value of not less than 2 and tCK may be about 2.5ns, 1.25ns, 0.625ns, or others. For example, as shown in fig. 7 and 8, the first signal (e.g., CAI), the plurality of candidate signals (e.g., cad_ck, cad_de), and the second signal (e.g., CAD) are set to active states as pulse signals, respectively, and the pulse widths of the plurality of pulse signals are smaller than the Column Select Line (CSL) signal. Of course, implementation of the present invention is not limited to the above examples.

In some embodiments, the step of generating the Column Select Line (CSL) signal (step S30) includes the following steps. The first signal (CAI) and the second signal (CAD) are received to generate the Column Select Line (CSL) signal. After the first signal (CAI) is set to an active state, the Column Select Line (CSL) signal is set to an active state. After the second signal (CAD) is set to active state, the Column Select Line (CSL) signal is set to inactive state (de-asserted).

Referring to fig. 9, a block diagram of an architecture of a circuit for generating a Column Select Line (CSL) signal from a first signal (CAI) and a second signal (CAD) according to one embodiment of the invention is shown. In fig. 9, the circuit 1 for adaptively generating a column selection line signal includes an initial signal generation circuit 10, a CSL signal control circuit 20, and a CSL signal output circuit 30. The initial signal generating circuit 10 is configured to generate a first signal (CAI) in response to a memory access command. The CSL signal control circuit 20 is coupled to the initial signal generating circuit 10 and configured to generate a second signal (CAD) according to a selected candidate signal of the plurality of candidate signals, wherein after the first signal is set to the active state, the selected candidate signal is set to the active state before the rest of the plurality of candidate signals (or other candidate signals). The CSL signal output circuit 30 is coupled to the CSL signal control circuit 20 and configured to generate a Column Select Line (CSL) signal according to the first signal (CAI) and the second signal (CAD). As such, the circuitry that adaptively generates the column select line signals can be used to implement the method of fig. 5 or based on the embodiment of fig. 5.

In some embodiments, the initial signal generation circuit 10 is configured to generate a first signal (CAI) in response to a memory access command (e.g., a write or read command issued in a DRAM device), as described above or other examples with respect to fig. 6-8 or other figures to set the first signal to an active state. For example, the initial signal generating circuit 10 is configured to set the first signal (CAI) to an active state after a time interval (e.g., T0 to T24 cycles) equal to the Write Latency (WL) plus an additional number of clock cycles elapses in response to a write command issued in the DRAM device. The initial signal generation circuit 10 may be configured to obtain one or more parameters associated with a Write Latency (WL) of a DRAM device, for example, from a set of mode registers that conform to a memory specification. The initial signal generation circuit 10 may be implemented by utilizing logic circuitry or other suitable digital or analog circuitry, such as digital delay circuitry, which is capable of being digitally controlled in response to memory access commands. Furthermore, the initial signal generating circuit 10 may be configured to set the subsequent first signal (CAI) to an active state in response to a read command issued after the write command, as shown in fig. 6.

In some embodiments, the CSL signal control circuit 20 is configured to determine the selected candidate signal from the plurality of candidate signals (e.g., cad_ck and cad_de), wherein after the first signal is set to an active state, the selected candidate signal is set to an active state prior to the remaining portion of the plurality of candidate signals (or other candidate signals), and the CSL signal control circuit 20 is configured to output the selected candidate signal as the second signal (CAD). For example, the CSL signal control circuit 20 includes a control circuit configured to determine the selected candidate signal from the plurality of candidate signals (e.g., cad_ck and cad_de), and the control circuit is configured to output the selected candidate signal as the second signal (CAD).

Please refer to fig. 10, which is a block diagram illustrating an embodiment of the CSL signal control circuit of fig. 9. In fig. 10, the CSL signal control circuit 20A is one embodiment of the CSL signal control circuit 20 and is configured to generate a second signal (CAD) from the first signal (CAI). The CSL signal control circuit 20A includes a control circuit 21 and a plurality of candidate signal generating circuits 23 and 25.

Referring to fig. 11, a block diagram of one embodiment of a control circuit for generating a second signal (CAD) from a plurality of candidate signals is shown. In fig. 11, the control circuit 21A has a plurality of inputs for receiving a plurality of candidate signals (e.g., cad_ck and cad_de) and an output for outputting a second signal (CAD). The control circuit 21A includes a plurality of signal paths, each of which is connected to a corresponding one of the plurality of input terminals, a corresponding switch, and the output terminal. For example, in fig. 11, the first signal path includes an input to receive the candidate signal cad_ck, a corresponding switch 211, and the output; and the second signal path comprises a further input to receive the candidate signal cad_de, a corresponding switch 213 and said output. In addition, the switches (e.g., switches 211, 213) of the plurality of signal paths are controlled by respective control signals (e.g., denoted as CS1, CS 2).

By using the control signal, the control circuit 21A may be configured to determine a candidate signal selected from the plurality of candidate signals (e.g., cad_ck and cad_de) and output the selected candidate signal as the second signal (CAD), wherein after the first signal is set to the active state, the selected candidate signal is set to the active state prior to the remaining portion (or other candidate signals) of the plurality of candidate signals. For example, initially, after the first signal is set to an active state, switches (e.g., 211, 213) in the plurality of signal paths are turned on by an active state (asserted) of the plurality of control signals (e.g., denoted as CS1, CS 2). In one case, when the candidate signal cad_ck is set to the active state before the candidate signal cad_de is set to the active state (as shown in fig. 7), the control signal CS1 is maintained in the active state and the control signal CS2 is changed to the inactive state, so that the switch 211 is still turned on and the switch 213 is turned off, and thus the candidate signal cad_ck becomes the selected candidate signal. In another case, when the candidate signal cad_de is set to the active state before the candidate signal cad_ck is set to the active state (as shown in fig. 8), the control signal CS2 is maintained in the active state and the control signal CS1 is changed to the inactive state, so that the switch 213 is still turned on and the switch 211 is turned off, and thus the candidate signal cad_de becomes the selected candidate signal. In this way, the control circuit 21A selects only one candidate signal from the plurality of candidate signals, transmits the selected candidate signal through its corresponding signal path, and outputs the selected candidate signal as the second signal (CAD). Any embodiment of the control circuit 21A shown in fig. 11 or based thereon may be used to implement the circuitry of step S20 of the method shown in fig. 5, such as a CSL signal control circuit (e.g., 20A) or control circuit 21. Furthermore, according to the above example, the control circuit 21A may be further implemented for more candidate signals.

Referring to fig. 12, a block diagram of one embodiment of a control circuit for generating a second signal (CAD) from a plurality of candidate signals is shown. The control circuit 21B shown in fig. 12 is an architecture based on the embodiment shown in fig. 11. The control circuit 21B further includes a logic circuit 215 and a logic circuit 217 as compared with the control circuit 21A of fig. 11. The logic circuit 215 outputs a control signal CS1 according to the first signal (CAI) and the candidate signal cad_de to control the switch 211 in the signal path for the candidate signal cad_ck. The logic circuit 217 outputs a control signal CS2 according to the first signal (CAI) and the candidate signal cad_ck to control the switch 213 in the signal path for the candidate signal cad_de. Logic circuits 215 and 217 can operate in a similar manner in respective signal paths for a plurality of candidate signals. The operation of the control circuit 21B using the control signals CS1, CS2 is similar to the corresponding operation of the control circuit 21A.

Referring to fig. 13, a block diagram of one embodiment of a control circuit for generating a second signal (CAD) from a plurality of candidate signals is shown. The control circuit 21C shown in fig. 13 is an architecture based on the embodiment shown in fig. 11 or fig. 12. In comparison with the control circuit 21B of fig. 12, the control circuit 21C includes an output circuit 220, a switch controller 225, and a switch controller 227.

The output circuit 220 outputs a second signal (CAD) based on the plurality of candidate signals cad_ck and cad_de. Output circuit 220 may be considered a circuit implementation of switches 211 and 213. The output circuit 220 is also controlled in accordance with the respective control signals (denoted as en_ck, en_de) as compared with the control signals CS1, CS2 of the control circuit 21A or 21B. As shown in fig. 13, the output circuit 220 may be implemented by a logic circuit including a plurality of logic gates, such as NAND (NAND) gates. In other examples, output circuit 220 may be implemented by any suitable logic gates and/or suitable circuit components, among others.

The switch controller 225 is configured to generate a control signal en_ck according to the first signal (CAI) and the candidate signal cad_de to control the output circuit 220 in the signal path for the candidate signal cad_ck. The switch controller 227 is configured to generate a control signal en_de according to the first signal (CAI) and the candidate signal cad_ck to control the output circuit 220 in the signal path for the candidate signal cad_de.

As shown in fig. 13, the switch controller 225 or 227 may be implemented by a logic circuit including a plurality of logic gates, such as NAND (NAND) gates, NOT (NOT) gates, or other logic gates, and/or digital circuit components, among others. The switch controller 225 or 227 is a trigger-based, such as a reset-set (RS) trigger.

Referring to fig. 14, a timing diagram illustrating one example of using the control circuit of fig. 13 to generate a second signal (CAD) from a plurality of candidate signals is shown.

Please refer to fig. 13 and 14, which are used to explain the circuit operation using the control signal. Initially, in response to the active state of the first signal (CAI), the logic circuits 225 and 227 (or 215 and 217 of fig. 12) can set the control signals en_ck and en_de (or CS1, CS2 of fig. 12) to the active state in order to turn on the output circuit 220 (or switches 211, 213 of fig. 12) in the signal path. After the first signal (CAI) is set to the active state, the plurality of candidate signals cad_ck and cad_de are individually set to the active state after the respective delay times. In response to one of the candidate signals (e.g., cad_de) being first set to an active state, the logic circuit 225 (or 215 of fig. 12) for the other candidate signal (e.g., cad_ck) sets the corresponding control signal en_ck (or CS1 of fig. 12) to an inactive state such that the signal path of the other candidate signal (e.g., cad_ck) is turned off in the output circuit 220 (or corresponding switch 211 of fig. 12). At the same time, the logic circuit 227 (or 217 of fig. 12) for the candidate signal (e.g., cad_de) that is first set to the active state holds the corresponding control signal en_de (e.g., CS 2) in the active state such that the signal path of the candidate signal (e.g., cad_de) that is first set to the active state in the output circuit 220 (or the corresponding switch 213 of fig. 12) is still open and the candidate signal (e.g., cad_de) that is first set to the active state is conducted. Then, when the candidate signal (e.g., cad_ck) is set to the active state, the corresponding control signal en_de (e.g., CS 2) is set to the inactive state for the logic circuit 227 (or 217 of fig. 12) of the candidate signal (e.g., cad_de) that was first set to the active state. The logic circuits 225, 227 can operate in a similar manner in respective signal paths for a plurality of candidate signals. The operation of the control circuit 21C using the control signals en_ck, en_de is similar to that of the control circuit 21A or 21B, and will not be described in detail for brevity.

Some embodiments regarding generating a plurality of candidate signals are presented below.

For example, as shown in fig. 10, the candidate signal generating circuit 23 has an input to receive the first signal (CAI) and an output to output a candidate signal (e.g., cad_ck), and may be implemented to include a circuit that generates the candidate signal (e.g., cad_ck) according to a configurable time interval associated with the parameter k from a register set (e.g., mode register) after the first signal is set to an active state. The candidate signal generation circuit 23 may be implemented by using a logic circuit, a read circuit configured to read a register set storing a value of a mode register defined by the DDR specification, and/or a pulse generator or other suitable circuit, such as a logic circuit, a timer, a delay circuit, an amplifier, and the like. The candidate signal generating circuit 23 may be implemented so as to be configured such that the candidate signal cad_ck generated after the first signal (CAI) is set to the active state has one pulse after a delay of k clock cycles (e.g., k×tck).

For example, the candidate signal generation circuit 25 has an input to receive the first signal (CAI) and an output to output a candidate signal (e.g., cad_de), and may be implemented to include a circuit that generates the candidate signal (e.g., cad_de) according to a specific time interval after the first signal is set to an active state. The candidate signal generation circuitry 25 may be implemented by utilizing logic circuitry, and/or a pulse generator or other suitable circuitry, such as logic circuitry, timers, delay circuits, amplifiers, etc. The candidate signal generating circuit 23 may be implemented such that the candidate signal cad_de generated after the first signal (CAI) is set to the active state has one pulse after the delay of the specific time interval.

Table 1 shows a plurality of examples of setting of the mode register set of the DDR series specifications. The user may select one of the values in the first column of table 1 and set the selected value in a register set, such as a mode register defined by the DDR specification and implemented in the memory device. The second column of table 1 may be used to implement the candidate signal generation circuit 23 to generate the candidate signal cad_ck, where the parameter k may be set to 2, 2.5, 3, 3.5, or 4. The third column of table 1 may be used to implement the candidate signal generation circuit 25 to generate the candidate signal cad_de.

TABLE 1

Referring to fig. 15, a block diagram of one embodiment of a candidate signal generation circuit is shown. In fig. 15, the candidate signal generating circuit 23A is an embodiment of the candidate signal generating circuit 23, which is configured to generate a candidate signal (e.g., cad_ck) according to a configurable time interval associated with a parameter k from a register set (e.g., the mode register set 90) after the first signal (CAI) is set to an active state. As shown in fig. 15, the candidate signal generation circuit 23A includes a delay chain circuit 231, a multiplexer 233, and a pulse generator 237. The delay chain circuit 231 receives the first signal (CAI) and a clock signal (e.g., DCK) and outputs a plurality of delay signals having different delay times for the first signal (CAI). The multiplexer 233 is configured to select and output one of the plurality of delay signals according to a selection signal, wherein the selection signal is based on one or more corresponding parameters from the mode register set 90. The pulse generator 237 generates pulses in response to the output signal of the multiplexer 233 to generate the candidate signal cad_ck.

For example, as shown in the second column of Table 1, the mode register set MR6 has a specific register for storing a setting (having a value of 4, 5, 6, 7 or 8) of tCCD_L.min corresponding to the parameter k (e.g., set to 2, 2.5, 3, 3.5 or 4, respectively). Thus, the delay chain 231 is capable of generating a plurality of delay signals having respective delay times of 2×tck, 2.5×tck, 3×tck, 3.5×tck, or 4×tck. Further, the multiplexer 233 may be implemented to select and output one of the plurality of delay signals according to a selection signal based on a set value from the mode register set MR 6. For example, the multiplexer 233 may be configured to select a delayed signal having a delay time of 2 tck according to a selection signal representing 4, and so on.

Referring to fig. 16, a schematic circuit diagram of one embodiment of the delay chain circuit of fig. 15 is shown. As shown in fig. 16, the delay chain circuit 231A includes a plurality of delay cells, e.g., D-latches, coupled in series or in a chained manner, denoted as DL11-DL20. The delay unit DL11 has an input (denoted D) and an output (denoted Q) for receiving the first signal (CAI), wherein the delay unit DL11 is configured to receive the first signal (CAI) by an inverted version of the clock signal DCK (denoted Q) And is clocked. The delay unit DL12 has an input (D) for receiving an output of the delay unit DL11 and an output (Q) for outputting a delay signal (e.g., denoted as cad_ck 00), wherein the delay unit DL12 is clocked by the clock signal DCK. Similarly, delay cells DL 13-DL 20 are connected in series or in a chain to produce the plurality of delayed signals (e.g., denoted cad_ck05, cad_ck10, … …, cad_ck 40). For example, the plurality of delay signals cad_ck20, cad_ck25, cad_ck30, cad_ck35, and cad_ck40 are output to the multiplexer 233.

Referring to fig. 17, a timing diagram of an example of generating a candidate signal (cad_ck) using the control circuits of fig. 15 and 16 is shown. As shown in fig. 17, in response to the write command (WR), the first signal (CAI) is set to an active state as a pulse after the Write Latency (WL) is added to a time interval of an additional number of clock cycles (e.g., wl+4 in total). The active state of the first signal (CAI) enables the delay chain circuit 231A so that the plurality of delay signals cad_ck00 to cad_ck40 are sequentially generated in a pulse manner. In one example, the multiplexer 233 outputs the delay signal cad_ck40 in response to a select signal associated with tccd_l.min being 8 or parameter k being 4. Thus, in response to the active state of the delay signal cad_ck40, the pulse generator 237 generates a pulse wave as the candidate signal cad_ck.

In some embodiments, as shown in fig. 9, the CSL signal output circuit 30 includes: the first signal input end, the second signal input end, the output end and the output logic circuit. The first signal input is configured to receive the first signal (CAI). The second signal input is configured to receive the second signal (CAD). The output terminal is used for outputting the Column Selection Line (CSL) signal. The output logic circuit is configured to generate the Column Select Line (CSL) signal, wherein the output logic circuit is configured to set the Column Select Line (CSL) signal to an active state after the first signal (CAI) is set to an active state; and the output logic is configured to set the Column Select Line (CSL) signal to an inactive state after the second signal (CAD) is set to an active state, as shown in fig. 6, 7, or 8.

Referring to fig. 18, a block diagram of an architecture according to a memory device is shown, in which a circuit for adaptively generating a Column Select Line (CSL) signal according to a first signal (CAI) and a second signal (CAD) according to one embodiment of the invention is applied. In fig. 18, the memory device 500 includes a command input interface 510, a row command decoder 520, a column command decoder 530, a Column Select Line (CSL) signal control circuit 535, a column control circuit 540, a row control circuit 550, a memory cell array 560, a data input output interface 570, and a data control circuit 580. The command input interface 510 is configured to receive external signals such as ck_t, ck_c, CKE, cs_n, act_n, ras_n, cas_n, we_n, BG0, BG1, BA0, BA1, A0-a13, which are specified by the DDR series memory specifications, and to output commands or control signals to subsequent circuits, such as row command decoder 520 and column command decoder 530, respectively. The data input output interface 570 is configured to receive or transmit signals, such as signals DQ0-DQ7, LDQS_t, LDQS_c, DQ8-DQ15, UDQS, t_UDQS_c, as specified by the DDR series memory Specification. The memory cell array 560 may be implemented to include a plurality of memory BANKs (BANKs), such as BANK [0], BANK [1] to BANK [ n ].

The circuit 1 shown in fig. 9 (or its associated embodiment based on fig. 5 or 9) that adaptively generates a column select line signal may be implemented in a memory device 500. Referring to fig. 9 and 15, in one embodiment, the initial signal generating circuit 10, the CSL signal control circuit 20 and the CSL signal output circuit 30 may be implemented in the column command decoder 530, the Column Select Line (CSL) signal control circuit 535 and the column control circuit 540, respectively.

In some embodiments, the initial signal generation circuit 10 may be implemented in the column command decoder 530, the CSL signal control circuit 20 and the CSL signal output circuit 30 may be implemented in the column control circuit 540, such that the Column Select Line (CSL) signal control circuit 535 may be embedded in the column control circuit 540. Furthermore, a set of mode registers 590 may be provided to and coupled to the CSL signal control circuit 535 as specified by the memory specification (e.g., DDR family). For example, the CSL signal control circuitry 535 may be configured to generate a first candidate signal according to a configurable time interval associated with a parameter retrieved from the mode register set 590 and to generate a second candidate signal according to a particular time interval. Of course, implementation of the present invention is not limited to the above examples. In some embodiments, the mode register set 590 may be implemented in one or more circuit elements (such as 510, 520, 530, 540, or 550 of fig. 18), as appropriate.

Accordingly, various embodiments of methods and circuits for adaptively generating column select line signals for memory devices have been provided above to adaptively control column select line signals to facilitate stability of access operations of the memory devices.

Furthermore, in embodiments associated with circuitry for adaptively generating column select line signals (e.g., fig. 9 and 10), at least one of the circuitry, or a combination thereof, may be implemented by one or more circuits such as a microprocessor, processor, or digital signal processor. Or the above-described circuits may be designed based on technology using a Hardware Description Language (HDL) such as Verilog language or any other design method of digital circuits familiar to those skilled in the art, and may be implemented based on one or more of circuits using a field programmable gate array (field programmable GATE ARRAY, FPGA), or an application-specific integrated circuit (ASIC), or Complex Programmable Logic Device (CPLD), or may be implemented using dedicated circuits or modules. However, the implementation of the present invention is not limited to the above examples. Further, steps S10 to S30 in fig. 5 may be implemented by logic circuits or other suitable digital or analog circuits.

The foregoing is merely exemplary of the present invention and is not intended to limit the scope of the present invention.

Claims (11)

1. A method of adaptively generating a column select line signal for a memory device, the method comprising the steps of:

Generating a first signal in response to a memory access command;

Generating a second signal from a selected candidate signal of a plurality of candidate signals including a first candidate signal and a second candidate signal, wherein in response to the first signal being set to an active state, the first candidate signal is set to an active state when a configurable time interval associated with a parameter from a register set has elapsed; when a certain time interval elapses, the second candidate signal is set to an active state; and after the first signal is set to an active state, the selected candidate signal is set to an active state prior to the remaining portion of the plurality of candidate signals; and

A column select line signal is generated from the first signal and the second signal.

2. The method of claim 1, wherein the step of generating the second signal comprises:

Determining the selected candidate signal from the plurality of candidate signals, wherein after the first signal is set to an active state, the selected candidate signal is set to an active state prior to the remaining portion of the plurality of candidate signals; and

Outputting the selected candidate signal as the second signal.

3. The method of claim 2, wherein the step of generating the second signal further comprises:

Generating the first candidate signal according to the configurable time interval associated with the parameter from the register set after the first signal is set to an active state;

The second candidate signal is generated according to the specific time interval after the first signal is set to an active state.

4. The method of claim 1, wherein the step of generating the column select line signal comprises:

Receiving the first signal and the second signal to generate the column select line signal;

Setting the column select line signal to an active state after the first signal is set to an active state; and

After the second signal is set to an active state, the column select line signal is set to an inactive state.

5. A circuit for adaptively generating a column select line signal for a memory device, the circuit comprising:

an initial signal generation circuit configured to generate a first signal in response to a memory access command;

A column select line signal control circuit coupled to the initial signal generation circuit and configured to generate a second signal based on a candidate signal selected from a plurality of candidate signals including a first candidate signal and a second candidate signal, wherein after the first signal is set to an active state, the first candidate signal is set to an active state when a configurable time interval associated with a parameter from a register set has elapsed; when a certain time interval elapses, the second candidate signal is set to an active state; and after the first signal is set to an active state, the selected candidate signal is set to an active state prior to the remaining portion of the plurality of candidate signals; and

A column select line signal output circuit coupled to the column select line signal control circuit and configured to generate a column select line signal based on the first signal and the second signal.

6. The circuit of claim 5, wherein the column select line signal control circuit comprises:

A control circuit configured to determine the selected candidate signal from the plurality of candidate signals, wherein after the first signal is set to an active state, the selected candidate signal is set to an active state prior to the remaining portion of the plurality of candidate signals, and the control circuit is configured to output the selected candidate signal as the second signal.

7. The circuit of claim 6, wherein the column select line signal control circuit further comprises:

a first candidate signal generation circuit configured to generate the first candidate signal according to the configurable time interval related to the parameter from the register set after the first signal is set to an active state; and

A second candidate signal generating circuit configured to generate the second candidate signal according to the specific time interval after the first signal is set to an active state.

8. The circuit of claim 5, wherein the column select line signal output circuit comprises:

A first signal input for receiving the first signal;

the second signal input end is used for receiving the second signal;

A column selection line signal output terminal for outputting the column selection line signal; and

And an output logic circuit configured to generate the column select line signal, wherein the output logic circuit is configured to set the column select line signal to an active state after the first signal is set to an active state, and the output logic circuit is configured to set the column select line signal to an inactive state after the second signal is set to an active state.

9. The circuit of claim 5, wherein the column select line signal control circuit is coupled between a column command decoder and a column control circuit of the memory device.

10. The circuit of claim 5, wherein the initial signal generation circuit is disposed in a column command decoder of the memory device.

11. The circuit of claim 5, wherein the column select line signal output circuit is disposed in a column control circuit of the memory device.