CN118068165A - BMC chip testing method and system - Google Patents
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Abstract
The invention discloses a BMC chip testing method and system, the testing system of the BMC chip testing system provided by the invention comprises a connecting slot, wherein the connecting slot is provided with a transmitting interface, the BMC chip to be tested is provided with a receiving interface, when the BMC chip is embedded into the connecting slot, the transmitting interface and the receiving interface are correspondingly connected one by one, and the interface serial numbers of the transmitting interface and the interface serial numbers of the receiving interface which are correspondingly connected are consistent; when a test is started, the upper computer generates a plurality of configuration information, and at least 1 sensor serial numbers with different interface serial numbers exist in any 2 configuration information; each piece of configuration information corresponds to an interface configuration type of a server in practical application, and the method can respectively conduct one-time pertinence test on each piece of configuration information; and repeating the test for a plurality of times so as to perform corresponding tests on all the configuration information, thereby improving the test efficiency.
Description
Technical Field
The invention relates to the technical field of BMC chips, in particular to a BMC chip testing method and system.
Background
BMC (BaseBoard Management Controller), chinese name is baseboard management system, which is independent of other hardware on server system, and can monitor and manage power supply, temperature, etc. of the whole server system.
The BMC chip needs to be subjected to functional test before leaving the factory, and the test of the BMC chip is mainly carried out by manual or detection instrument to carry out auxiliary test at present; the BMC chip may be mounted on different types of servers in actual application, and when the different types of servers are in communication connection with the BMC chip, the service function signals of the servers are not identical to the connection modes between pins of the BMC chip; when the existing BMC chip is tested, the servers of different types are required to be tested respectively, so that the test time period is long, and the test efficiency is low.
Disclosure of Invention
The invention mainly aims to provide a BMC chip testing method and system, and aims to solve the problem that when a BMC chip is tested at present, different types of servers need to be tested respectively, so that the testing time period is long.
The technical scheme provided by the invention is as follows:
a BMC chip test method is applied to a BMC chip test system; the system comprises a test main board and an upper computer; the test main board is provided with a processor, a connecting slot and a sensor group; the sensor group comprises a plurality of sensors, and each sensor is correspondingly provided with a unique sensor number; the connecting slot is used for embedding the BMC chip to be tested; the upper computer is connected with the test main board in a communication way; the connecting slot comprises a plurality of transmitting interfaces; the BMC chip comprises a plurality of receiving interfaces; each transmitting interface is correspondingly provided with a different interface serial number, and each receiving interface is correspondingly provided with a different interface serial number; when the BMC chip is embedded into the connecting slot, the sending interfaces and the receiving interfaces are connected in one-to-one correspondence, and the interface serial numbers of the sending interfaces and the interface serial numbers of the receiving interfaces which are connected in a corresponding manner are consistent; the method comprises the following steps:
The upper computer generates a plurality of configuration information, wherein the configuration information comprises a sensor number and an interface serial number corresponding to the sensor number;
The upper computer randomly selects 1 configuration information which is not marked as finishing information, marks the configuration information as target information and sends the target information to the processor;
the processor respectively acquires the acquired data of each sensor for 1 time, establishes a corresponding relation between the acquired data and a transmitting interface corresponding to an interface serial number corresponding to a sensor number of the corresponding sensor based on target information, and transmits the acquired data to the BMC chip through the corresponding transmitting interface;
The BMC chip packs the received acquired data and an interface serial number of a receiving interface for receiving the acquired data to form feedback information, and sends the feedback information to the upper computer through the connecting slot;
the upper computer generates test result information based on the feedback information and marks the target information as completion information based on the test result information.
Preferably, the upper computer generates test result information based on the feedback information, marks the target information as the completion information based on the test result information, and includes:
after the upper computer receives the first feedback information, marking the time of receiving the first feedback information as the starting time;
The upper computer judges whether a first preset number of feedback information is received within a first preset time from the starting moment, wherein the first preset number is consistent with the number of the sensors;
If yes, the upper computer judges whether the sensor number and the interface serial number corresponding to the sensor for collecting data in the same feedback information accord with the corresponding relation between the sensor number and the interface serial number in the target information;
If yes, the upper computer generates test result information for expressing that the test passes;
If the test result information does not accord with the test result information, the upper computer generates the test result information for expressing that the test fails;
If not, the upper computer generates test result information for expressing that the test fails;
after the test result information is generated, the upper computer marks the target information as the completion information, and removes the mark of the target information of the completion information.
Preferably, the processor acquires the acquired data of each sensor 1 time, establishes a corresponding relationship between the acquired data and a transmitting interface corresponding to an interface serial number corresponding to a sensor number of a corresponding sensor based on the target information, and transmits the acquired data to the BMC chip through the corresponding transmitting interface, and then further includes:
The processor packages the acquired data and the sensor numbers of the corresponding sensors to form comparison information, and sends the comparison information to the upper computer;
The upper computer judges whether the sensor number and the interface serial number of the sensor for collecting data in the same feedback information accord with the corresponding relation between the sensor number and the interface serial number in the target information or not, and then the method further comprises the following steps:
if yes, the upper computer packs and stores the sensor number corresponding to the interface serial number in the feedback information into the feedback information based on the target information;
The upper computer establishes a corresponding relation between feedback information and comparison information which are contained and have consistent sensor numbers, and judges whether acquired data in the feedback information and the comparison information which correspond to each other are consistent or not;
If the test result information is consistent with the test result information, the upper computer generates the test result information for expressing the passing of the test;
if the test result information is inconsistent, the bit machine generates test result information for expressing that the test fails.
Preferably, the upper computer randomly selects 1 configuration information which is not marked as the completion information, marks the configuration information as the target information, and sends the target information to the processor, and then the method further comprises the steps of:
The processor acquires the acquired data sent by the sensor once every second preset time length, marks the source sensor with the acquired data reaching the second preset number as the target sensor when the number of the acquired data received by the processor from the same sensor reaches the second preset number, and stops receiving the acquired data from the target sensor;
the processor sends the second preset number to the upper computer;
the processor establishes a corresponding relation between each acquired data and a transmitting interface corresponding to the interface serial number corresponding to the corresponding sensor serial number based on the target information, and transmits the acquired data to the BMC chip through the corresponding transmitting interface;
The BMC chip packs the received acquired data and an interface serial number of a receiving interface for receiving the acquired data to form feedback information, and sends the feedback information to the upper computer through the connecting slot;
The upper computer generates test result information based on the feedback information and the second preset quantity, marks the target information as finish information based on the test result information, removes the mark of the target information of the finish information, then executes the steps of randomly selecting 1 configuration information which is not marked as the finish information by the upper computer, marks the configuration information as the target information, and sends the target information to the processor.
Preferably, the upper computer generates test result information based on the feedback information and the second preset number, marks the target information as completion information based on the test result information, and removes the mark of the target information of the completion information, including:
After the upper computer receives the first feedback information, marking the time of receiving the first feedback information as the initial time;
The upper computer judges whether a third preset number of feedback information is received within a third preset time from the initial moment, wherein the third preset number is the product of the second preset number and the number of the sensors;
If yes, the upper computer judges whether the sensor number and the interface serial number of the sensor corresponding to the acquired data in the same feedback information accord with the corresponding relation between the sensor number and the interface serial number in the target information;
If yes, the upper computer generates test result information for expressing that the test passes;
If the test result information does not accord with the test result information, the upper computer generates the test result information for expressing that the test fails;
If not, the upper computer determines a receiving interface with a fault based on the feedback information and the second preset number, and generates test result information for expressing that the test fails, wherein the test result information comprises an interface serial number of the receiving interface with the fault;
after the test result information is generated, the upper computer marks the target information as the completion information, and removes the mark of the target information of the completion information.
Preferably, the upper computer determines a receiving interface with a fault based on the feedback information and a second preset number, and generates test result information for expressing that the test fails, including:
The upper computer classifies the feedback information with the same interface serial number into the same feedback information group;
The upper computer marks the feedback information groups with the quantity of the feedback information being less than the second preset quantity as target groups, and determines the receiving interfaces corresponding to the interface serial numbers in the feedback information in the target groups as the receiving interfaces with faults.
Preferably, the test motherboard includes a plurality of connection slots; the number of the sending interfaces of each connecting slot is consistent, and the interface serial numbers of the sending interfaces at the same position of each connecting slot are consistent; the upper computer randomly selects 1 configuration information which is not marked as finishing information, marks the configuration information as target information, and sends the target information to the processor, and then the method further comprises the following steps:
the processor acquires the acquired data of each sensor for 1 time respectively, and establishes a corresponding relation between each acquired data and a transmitting interface corresponding to an interface serial number corresponding to a sensor serial number of a corresponding sensor in sequence based on target information;
the processor sequentially sends all the acquired data to all the BMC chips through corresponding sending interfaces;
each BMC chip packs the received acquired data and the interface serial numbers of the receiving interfaces for receiving the acquired data to form feedback information, and sends the feedback information to the upper computer through the connecting slot;
After the upper computer receives the first feedback information, marking the moment of receiving the first feedback information as a starting moment;
The upper computer judges whether a fourth preset number of feedback information is received within a first preset time from the starting point moment, wherein the fourth preset number is the product of the number of the sensors and the number of the connecting slots in the test main board;
If yes, executing the upper computer to judge whether the sensor number and the interface serial number corresponding to the sensor for collecting data in the same feedback information accord with the corresponding relation between the sensor number and the interface serial number in the target information or not, and then, executing the following steps;
If not, the upper computer generates test result information for expressing that the test fails;
after the test result information is generated, the upper computer marks the target information as the completion information, and removes the mark of the target information of the completion information;
and executing the steps that the upper computer randomly selects 1 configuration information which is not marked as the completion information and marks the configuration information as target information, and sending the target information to the processor.
Preferably, the upper computer comprises a display module; the upper computer randomly selects 1 configuration information which is not marked as finishing information, marks the configuration information as target information, and sends the target information to the processor, and then the method further comprises the following steps:
The processor acquires the acquired data of each sensor in real time and sends the acquired data of each sensor to the upper computer;
The display module displays the acquired data of each sensor in real time.
Preferably, the system further comprises a test box; the test box body is internally provided with a temperature adjusting module, and the test main board is arranged in the test box body; the upper computer is in communication connection with the temperature adjusting module and is used for controlling the temperature in the test box body; the sensor group comprises a temperature sensor; the method further comprises the steps of:
the upper computer adjusts the temperature in the test box body to a first preset temperature value through the temperature adjusting module and keeps a fourth preset time length;
the upper computer adjusts the temperature in the test box body to a second preset temperature value through the temperature adjusting module and keeps a fourth preset time period, wherein the second preset temperature value is higher than the first preset temperature value.
The invention also provides a BMC chip test system, and a BMC chip test method is applied; the system comprises a test main board and an upper computer; the test main board is provided with a processor, a connecting slot and a sensor group; the sensor group comprises a plurality of sensors, and each sensor is correspondingly provided with a unique sensor number; the connecting slot is used for embedding the BMC chip to be tested; the upper computer is connected with the test main board in a communication way; the connecting slot comprises a plurality of transmitting interfaces; the BMC chip comprises a plurality of receiving interfaces; each transmitting interface is correspondingly provided with a different interface serial number, and each receiving interface is correspondingly provided with a different interface serial number; when the BMC chip is embedded into the connecting slot, the sending interfaces and the receiving interfaces are connected in one-to-one correspondence, and the interface serial numbers of the sending interfaces and the interface serial numbers of the receiving interfaces which are connected in a corresponding manner are consistent.
Through the technical scheme, the following beneficial effects can be realized:
The BMC chip testing method provided by the invention can shorten the testing period and improve the testing efficiency; the test system of the BMC chip test system comprises a connecting slot, wherein the connecting slot is provided with a transmitting interface, the BMC chip to be tested is provided with a receiving interface, when the BMC chip is embedded into the connecting slot, the transmitting interface and the receiving interface are connected in one-to-one correspondence, and the interface serial numbers of the transmitting interface and the receiving interface which are connected in correspondence are consistent; when a test is started, the upper computer generates a plurality of configuration information, and at least 1 sensor serial numbers with different interface serial numbers exist in any 2 configuration information; each piece of configuration information corresponds to an interface configuration type of a server in practical application, and the method carries out one-time pertinence test on each piece of configuration information, and comprises the following specific processes: the processor acquires the acquired data of each sensor, establishes a corresponding relation between the acquired data and a transmitting interface corresponding to an interface serial number corresponding to a sensor number of a corresponding sensor based on target information, and then transmits the acquired data to the BMC chip through the corresponding transmitting interface, wherein the interface type corresponding to the communication transmission process simulates the server interface configuration type corresponding to the target information; after receiving the acquired data, the BMC chip packs the received acquired data and an interface serial number of a receiving interface for receiving the acquired data to form feedback information, and sends the feedback information to the upper computer; the upper computer judges whether the BMC chip passes the test or not based on the feedback information; the operation is repeated for a plurality of times so as to perform corresponding tests on all configuration information, thereby realizing that a plurality of different types of server adaptation tests are performed on the BMC chips on the same test main board, and the BMC chips are not required to be respectively inserted into different server main boards for testing, thereby greatly shortening the test period and improving the test efficiency.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a first embodiment of a BMC chip testing method according to the present invention.
Detailed Description
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The invention provides a BMC chip testing method and system.
As shown in fig. 1, in a first embodiment of a BMC chip testing method provided by the present invention, the method is applied to a BMC chip testing system; the system comprises a test main board and an upper computer; the test main board is provided with a processor, a connecting slot (for example, a Socket slot, namely a pin type processor slot) and a sensor group; the sensor group comprises a plurality of sensors (such as a temperature sensor, a voltage sensor, a current sensor and the like), and each sensor is correspondingly provided with a unique sensor number (such as a sensor number 1 corresponding to the temperature sensor, a sensor number 2 corresponding to the voltage sensor and a sensor number 3 corresponding to the current sensor); the connecting slot is used for embedding the BMC chip to be tested; the upper computer is connected with the test main board in a communication way; the connection slot includes a plurality of transmitting interfaces (for example, GPIO interfaces (General-purpose input/output), and the number of transmitting interfaces is 32 in this embodiment); the BMC chip includes a plurality of receiving interfaces (for example, GPIO interfaces, and the number of transmitting interfaces in this embodiment is 32); each transmitting interface is correspondingly provided with a different interface serial number (for example, from 1 to 32), and each receiving interface is correspondingly provided with a different interface serial number (for example, from 1 to 32); when the BMC chip is embedded into the connecting slot, the sending interfaces and the receiving interfaces are connected in one-to-one correspondence, and the interface serial numbers of the sending interfaces and the interface serial numbers of the receiving interfaces which are connected in a corresponding manner are consistent; the embodiment comprises the following steps:
Step S110: the upper computer generates a plurality of configuration information, wherein the configuration information comprises sensor numbers and interface serial numbers corresponding to the sensor numbers, the interface serial numbers corresponding to the sensor numbers in the same configuration information are different, and at least 1 sensor number with different interface serial numbers exists in any 2 configuration information.
In this embodiment, the range of the interface serial number is 1 to 32. For example, in the 1 st configuration information: the interface serial number corresponding to the sensor serial number 1 is 2, the interface serial number corresponding to the sensor serial number 2 is 3, and the interface serial number corresponding to the sensor serial number 3 is 5; configuration information 2: the interface serial number corresponding to the sensor serial number 1 is 10, the interface serial number corresponding to the sensor serial number 2 is 12, and the interface serial number corresponding to the sensor serial number 3 is 15.
Specifically, different configuration information corresponds to different interface configuration schemes of the server in actual application respectively, and by setting a plurality of different configuration information, the interface configuration schemes of the server in actual application can be reflected.
Step S120: the upper computer randomly selects 1 configuration information which is not marked as finishing information, marks the configuration information as target information and sends the target information to the processor.
Specifically, the target information in this embodiment adopts the 1 st configuration information as the target information.
Step S130: the processor respectively acquires the acquired data of each sensor for 1 time, establishes a corresponding relation between the acquired data and a transmitting interface corresponding to the interface serial number corresponding to the sensor serial number of the corresponding sensor based on the target information, and transmits the acquired data to the BMC chip through the corresponding transmitting interface.
Specifically, the collected data is corresponding data collected by a sensor, such as temperature data collected by a temperature sensor and voltage data collected by a voltage sensor. After the processor receives the acquired data, establishing a corresponding relation between the acquired data and a transmitting interface corresponding to the interface serial number corresponding to the sensor serial number of the corresponding sensor, so that the acquired data can be conveniently transmitted subsequently; and then the acquired data are sent to the BMC chip through the corresponding sending interface.
In this embodiment, the following steps are: the method comprises the steps of sending acquired data with a corresponding sensor number of 1 to a BMC chip through a sending interface with an interface number of 2, sending the acquired data with the corresponding sensor number of 2 to the BMC chip through a sending interface with an interface number of 3, and sending the acquired data with the corresponding sensor number of 3 to the BMC chip through a sending interface with an interface number of 5. I.e. the acquisition data is transmitted via the transmission interfaces with interface serial numbers 2,3 and 5, respectively.
Step S140: and the BMC chip packages the received acquired data and the interface serial numbers of the receiving interfaces for receiving the acquired data to form feedback information, and sends the feedback information to the upper computer through the connecting slot.
Specifically, the feedback information includes collected data and an interface serial number corresponding to a receiving interface for receiving the collected data, so as to facilitate subsequent test result judgment. Under the condition that the BMC chip normally communicates, the sensor number and the interface serial number corresponding to the acquired data in the same feedback information should accord with the corresponding relation in the target information, so that the upper computer can judge whether the BMC chip passes the test or not based on the feedback information.
Step S150: the upper computer generates test result information based on the feedback information and marks the target information as completion information based on the test result information, and then performs the step S110 and the following steps again.
The BMC chip testing method provided by the invention can shorten the testing period and improve the testing efficiency; the test system of the BMC chip test system comprises a connecting slot, wherein the connecting slot is provided with a transmitting interface, the BMC chip to be tested is provided with a receiving interface, when the BMC chip is embedded into the connecting slot, the transmitting interface and the receiving interface are connected in one-to-one correspondence, and the interface serial numbers of the transmitting interface and the receiving interface which are connected in correspondence are consistent; when a test is started, the upper computer generates a plurality of configuration information, and at least 1 sensor serial numbers with different interface serial numbers exist in any 2 configuration information; each piece of configuration information corresponds to an interface configuration type of a server in practical application, and the method carries out one-time pertinence test on each piece of configuration information, and comprises the following specific processes: the processor acquires the acquired data of each sensor, establishes a corresponding relation between the acquired data and a transmitting interface corresponding to an interface serial number corresponding to a sensor number of a corresponding sensor based on target information, and then transmits the acquired data to the BMC chip through the corresponding transmitting interface, wherein the interface type corresponding to the communication transmission process simulates the server interface configuration type corresponding to the target information; after receiving the acquired data, the BMC chip packs the received acquired data and an interface serial number of a receiving interface for receiving the acquired data to form feedback information, and sends the feedback information to the upper computer; the upper computer judges whether the BMC chip passes the test or not based on the feedback information; the operation is repeated for a plurality of times so as to perform corresponding tests on all configuration information, thereby realizing that a plurality of different types of server adaptation tests are performed on the BMC chips on the same test main board, and the BMC chips are not required to be respectively inserted into different server main boards for testing, thereby greatly shortening the test period and improving the test efficiency.
In a second embodiment of the method for testing a BMC chip according to the present invention, based on the first embodiment, step S150 includes the following steps:
step S210: after the upper computer receives the first feedback information, the time when the first feedback information is received is marked as the starting time.
Step S220: the upper computer judges whether a first preset number (for example, 3) of feedback information is received in a first preset time period from a starting time (the first preset time period is a sufficient time period that the BMC chip can receive all the acquired data and generate feedback information to send to the upper computer, for example, 5 seconds), wherein the first preset number is consistent with the number of the sensors.
Specifically, if the upper computer receives the first preset number of feedback information, the BMC chip is indicated to receive all the test information from the processor and smoothly send the test information to the upper computer, and communication between the BMC chip and the processor is indicated to be smooth.
If yes, step S230 is executed: the upper computer judges whether the corresponding sensor number and interface serial number of the sensor for collecting data in the same feedback information accord with the corresponding relation between the sensor number and the interface serial number in the target information.
Specifically, if so, it is necessary to further determine whether the communication between the BMC chip and the processor is normal (i.e., whether the receiving interface is normal); when the sensor number and the interface serial number corresponding to the sensor for collecting data in the same feedback information accord with the corresponding relation between the sensor number and the interface serial number in the target information, the BMC is proved to receive the test information through the correct receiving interface, and the interface communication between the BMC chip and the processor is proved to be correct and smooth.
Step S240: if so, the upper computer generates test result information for expressing the passing of the test.
Step S250: if the test result information does not accord with the test result information, the upper computer generates the test result information for expressing that the test fails.
If not, go to step S260: the upper computer generates test result information for expressing that the test fails.
Specifically, if not, it is indicated that communication between the BMC chip and the processor is not smooth, so that test result information indicating that the test fails is directly generated.
Step S270: after the test result information is generated, the upper computer marks the target information as the completion information, and removes the mark of the target information of the completion information.
Specifically, after the test of the present round is completed, the upper computer marks the target information as the completion information, and removes the mark of the target information of the completion information, so that when the next test cycle is repeated, the upper computer can be ensured not to select the configuration information after the test is completed.
In a third embodiment of the method for testing a BMC chip according to the present invention, based on the second embodiment, step S130 further includes the following steps:
Step S310: and the processor packages the acquired data and the sensor numbers of the corresponding sensors to form comparison information, and sends the comparison information to the upper computer.
Step S230, further comprising the following steps:
step S320: and if the information is in accordance with the interface serial number, the upper computer packages and stores the sensor serial number corresponding to the interface serial number in the feedback information into the feedback information based on the target information.
Step S330: the upper computer establishes a corresponding relation between the feedback information and the comparison information which are contained and have the same sensor numbers, and judges whether the acquired data in the feedback information and the comparison information which correspond to each other are consistent or not.
Specifically, whether the collected data are lost in the process of transmitting the collected data to the BMC chip is judged by judging whether the collected data in the feedback information and the comparison information which correspond to each other are consistent or not, so that whether the performance of the BMC chip is qualified or not is further judged.
Step S340: if the test result information is consistent with the test result information, the upper computer generates the test result information for expressing the passing of the test.
Step S350: if the test result information is inconsistent, the bit machine generates test result information for expressing that the test fails.
In a fourth embodiment of the method for testing a BMC chip according to the present invention, based on the first embodiment, step S120 further includes the following steps:
Step S410: the processor acquires the acquired data sent by the sensor once every a second preset time period (for example, 0.1 second), and when the number of the acquired data received by the processor from the same sensor reaches a second preset number (for example, 10), the source sensors with the acquired data reaching the second preset number are marked as target sensors, and the acquisition of the acquired data from the target sensors is stopped.
Specifically, each sensor sends 10 acquisitions of data to the processor.
Step S420: the processor sends the second preset number to the upper computer.
Step S430: the processor establishes a corresponding relation between each acquired data and a transmitting interface corresponding to the interface serial number corresponding to the corresponding sensor serial number based on the target information, and transmits the acquired data to the BMC chip through the corresponding transmitting interface.
Step S440: and the BMC chip packages the received acquired data and the interface serial numbers of the receiving interfaces for receiving the acquired data to form feedback information, and sends the feedback information to the upper computer through the connecting slot.
Step S450: the upper computer generates test result information based on the feedback information and the second preset number, marks the target information as completion information based on the test result information, removes the mark of the target information of the completion information, and then performs the step S120 and the subsequent steps again.
Specifically, the upper computer judges whether the BMC chip passes the test or not by judging the feedback information and the second preset quantity, and generates test result information; that is, the embodiment provides a scheme of how to test the BMC chip when the processor receives the multiple collection data sent by the single sensor.
In a fifth embodiment of the method for testing a BMC chip according to the present invention, based on the fourth embodiment, step S450 includes the following steps:
step S510: after the upper computer receives the first feedback information, the time when the first feedback information is received is marked as the initial time.
Step S520: the upper computer judges whether a third preset number of feedback information is received within a third preset time period (for example, 10 seconds) from the initial time, wherein the third preset number is the product of the second preset number and the number of the sensors.
Specifically, the third preset number in this embodiment is the product of 10 and 3, i.e., 30. If the upper computer receives the third preset number of feedback information, the BMC chip is indicated to receive all the acquired data from the processor and smoothly send the acquired data to the upper computer, and communication between the BMC chip and the processor is indicated to be smooth.
If yes, step S530 is executed: the upper computer judges whether the sensor number and the interface serial number of the sensor corresponding to the acquired data in the same feedback information accord with the corresponding relation between the sensor number and the interface serial number in the target information.
Specifically, when the sensor number and the interface serial number of the sensor corresponding to the acquired data in the same feedback information conform to the corresponding relation between the sensor number and the interface serial number in the target information, the BMC is proved to receive the test information through the correct receiving interface, and the interface communication between the BMC chip and the processor is proved to be correct and smooth.
Step S540: if so, the upper computer generates test result information for expressing the passing of the test.
Step S550: if the test result information does not accord with the test result information, the upper computer generates the test result information for expressing that the test fails.
If not, go to step S560: the upper computer determines a receiving interface with a fault based on the feedback information and the second preset number, and generates test result information for expressing that the test fails, wherein the test result information comprises an interface serial number of the receiving interface with the fault.
Specifically, if not, it is indicated that the interface between the BMC chip and the processor is correctly and smoothly communicated, and at this time, the upper computer needs to determine which receiving interface of the BMC chip has a fault based on the second preset number.
Step S570: after the test result information is generated, the upper computer marks the target information as the completion information, and removes the mark of the target information of the completion information.
In a sixth embodiment of the method for testing a BMC chip according to the present invention, based on the fifth embodiment, step S560 includes the following steps:
step S610: the upper computer classifies the feedback information with the same interface serial number into the same feedback information group.
Step S620: the upper computer marks the feedback information groups with the quantity of the feedback information being less than the second preset quantity as target groups, and determines the receiving interfaces corresponding to the interface serial numbers in the feedback information in the target groups as the receiving interfaces with faults.
Specifically, under normal conditions, the number of feedback information in each feedback information group should be equal to the second preset number, if the number of feedback information is less than the second preset number, it is indicated that the test information is lost in the transmission process, so that the feedback information group with the number of feedback information less than the second preset number is directly marked as a target group, and the receiving interface corresponding to the interface serial number in the feedback information in the target group is determined as the receiving interface with the fault.
In a seventh embodiment of a method for testing a BMC chip according to the present invention, based on the second embodiment, a test motherboard includes a plurality of connection slots (e.g., 4 connection slots); the number of the sending interfaces of each connecting slot is consistent, and the interface serial numbers of the sending interfaces at the same position of each connecting slot are consistent; step S120, further comprising the following steps:
step S710: the processor acquires the acquired data of each sensor for 1 time respectively, and establishes a corresponding relation between each acquired data and a transmitting interface corresponding to the interface serial number corresponding to the sensor serial number of the corresponding sensor in sequence based on the target information.
Step S720: and the processor sequentially transmits the acquired data to each BMC chip through the corresponding transmitting interface.
Step S730: and each BMC chip packages the received acquired data and the interface serial numbers of the receiving interfaces for receiving the acquired data to form feedback information, and sends the feedback information to the upper computer through the connecting slot.
Step S740: after the upper computer receives the first feedback information, the time when the first feedback information is received is marked as the starting point time.
Step S750: the upper computer judges whether a fourth preset number of feedback information is received within a first preset time period (for example, 5 seconds) from the starting point moment, wherein the fourth preset number is the product of the number of the sensors and the number of the connecting slots in the test main board.
In particular, the fourth preset number here is the product of 4 and 3, i.e. 12. If the upper computer receives the fourth preset number of feedback information, the BMC chip is indicated to receive all the acquired data from the processor and smoothly send the acquired data to the upper computer, and the communication between all the BMC chips and the processor is indicated to be smooth.
If yes, go to step S230 and the following steps.
Specifically, after the upper computer receives all feedback information, it needs to further determine whether the communication between each BMC chip to be tested and the processor is normal (i.e. whether the interface is normal); when the sensor number and the interface serial number corresponding to the sensor for collecting data in the same feedback information accord with the corresponding relation between the sensor number and the interface serial number in the target information, the BMC is proved to be really used for receiving the collected data through a correct receiving interface, and the interface communication between the BMC chip and the processor is proved to be correct and smooth.
If not, go to step S760: the upper computer generates test result information for expressing that the test fails.
Specifically, if not, it is indicated that the communication between each BMC chip and the processor is not smooth, so that test result information indicating that the test fails is directly generated.
Step S770: after the test result information is generated, the upper computer marks the target information as the completion information, and removes the mark of the target information of the completion information.
Step S120 and the following steps are performed.
Specifically, the embodiment can connect a plurality of BMC chips to the same test motherboard for testing, i.e. can test the plurality of BMC chips at the same time, thereby further improving the testing efficiency.
In an eighth embodiment of a method for testing a BMC chip according to the present invention, based on the first embodiment, the upper computer includes a display module (for example, a display screen); step S120, further comprising the following steps:
Step S810: the processor acquires the acquired data of each sensor in real time and sends the acquired data of each sensor to the upper computer.
Step S820: the display module displays the acquired data of each sensor in real time.
Specifically, the embodiment can send the collected data (such as the temperature value of the test motherboard, the voltage value of the test motherboard, and the current value of the test motherboard) collected by the sensor to the upper computer in real time for display.
In a ninth embodiment of the method for testing a BMC chip provided by the invention, based on the first embodiment, the system further comprises a test box body; a temperature adjusting module (comprising a refrigerating module and a heating module) is arranged in the test box body, and the test main board is arranged in the test box body; the upper computer is in communication connection with the temperature adjusting module and is used for controlling the temperature in the test box body; the sensor group comprises a temperature sensor; the embodiment further comprises the following steps:
Step S910: the upper computer adjusts the temperature in the test box body to a first preset temperature value through the temperature adjusting module and keeps a fourth preset time period (for example, 10 minutes).
Step S920: the upper computer adjusts the temperature in the test box body to a second preset temperature value through the temperature adjusting module and keeps a fourth preset time period, wherein the second preset temperature value is higher than the first preset temperature value.
Specifically, the temperature of the test box body is regulated through the upper computer, so that different environment temperatures of the BMC chip in practical application are simulated, and the test accuracy is improved.
In a tenth embodiment of the BMC chip testing method provided by the present invention, based on the first embodiment, the system further includes a power supply module and a voltage adjustment module; the power supply module is used for supplying power to the test main board; the voltage regulating module is electrically connected with the power supply module; the upper computer is in communication connection with the voltage regulating module and is used for controlling the power supply voltage of the test main board; the sensor group also comprises a voltage sensor; the embodiment further comprises the following steps:
Step S110: the upper computer adjusts the power supply voltage of the test main board to a first preset voltage value through the voltage adjusting module and keeps a fifth preset time period (for example, 3 minutes).
Step S110: the upper computer adjusts the power supply voltage of the test main board to a second preset voltage value through the voltage adjusting module and keeps a fifth preset time period, wherein the second preset voltage value is higher than the first preset voltage value.
Specifically, the upper computer is used for adjusting the power supply voltage of the test main board, so that different power supply conditions of the BMC chip in practical application are simulated, and the test accuracy is improved.
The invention also provides a BMC chip test system, and a BMC chip test method is applied; the system comprises a test main board and an upper computer; the test main board is provided with a processor, a connecting slot and a sensor group; the sensor group comprises a plurality of sensors, and each sensor is correspondingly provided with a unique sensor number; the connecting slot is used for embedding the BMC chip to be tested; the upper computer is connected with the test main board in a communication way; the connecting slot comprises a plurality of transmitting interfaces; the BMC chip comprises a plurality of receiving interfaces; each transmitting interface is correspondingly provided with a different interface serial number, and each receiving interface is correspondingly provided with a different interface serial number; when the BMC chip is embedded into the connecting slot, the sending interfaces and the receiving interfaces are connected in one-to-one correspondence, and the interface serial numbers of the sending interfaces and the interface serial numbers of the receiving interfaces which are connected in a corresponding manner are consistent.
The foregoing embodiment numbers of the present invention are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.
From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and including several instructions for causing a terminal (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to perform the method according to the embodiments of the present invention.
The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present invention and the scope of the claims, which are to be protected by the present invention.
Claims (10)
1. The BMC chip testing method is characterized by being applied to a BMC chip testing system; the system comprises a test main board and an upper computer; the test main board is provided with a processor, a connecting slot and a sensor group; the sensor group comprises a plurality of sensors, and each sensor is correspondingly provided with a unique sensor number; the connecting slot is used for embedding the BMC chip to be tested; the upper computer is connected with the test main board in a communication way; the connecting slot comprises a plurality of transmitting interfaces; the BMC chip comprises a plurality of receiving interfaces; each transmitting interface is correspondingly provided with a different interface serial number, and each receiving interface is correspondingly provided with a different interface serial number; when the BMC chip is embedded into the connecting slot, the sending interfaces and the receiving interfaces are connected in one-to-one correspondence, and the interface serial numbers of the sending interfaces and the interface serial numbers of the receiving interfaces which are connected in a corresponding manner are consistent; the method comprises the following steps:
The upper computer generates a plurality of configuration information, wherein the configuration information comprises a sensor number and an interface serial number corresponding to the sensor number;
The upper computer randomly selects 1 configuration information which is not marked as finishing information, marks the configuration information as target information and sends the target information to the processor;
the processor respectively acquires the acquired data of each sensor for 1 time, establishes a corresponding relation between the acquired data and a transmitting interface corresponding to an interface serial number corresponding to a sensor number of the corresponding sensor based on target information, and transmits the acquired data to the BMC chip through the corresponding transmitting interface;
The BMC chip packs the received acquired data and an interface serial number of a receiving interface for receiving the acquired data to form feedback information, and sends the feedback information to the upper computer through the connecting slot;
the upper computer generates test result information based on the feedback information and marks the target information as completion information based on the test result information.
2. The method of claim 1, wherein the host computer generates test result information based on the feedback information, and marks the target information as the completion information based on the test result information, comprising:
after the upper computer receives the first feedback information, marking the time of receiving the first feedback information as the starting time;
The upper computer judges whether a first preset number of feedback information is received within a first preset time from the starting moment, wherein the first preset number is consistent with the number of the sensors;
If yes, the upper computer judges whether the sensor number and the interface serial number corresponding to the sensor for collecting data in the same feedback information accord with the corresponding relation between the sensor number and the interface serial number in the target information;
If yes, the upper computer generates test result information for expressing that the test passes;
If the test result information does not accord with the test result information, the upper computer generates the test result information for expressing that the test fails;
If not, the upper computer generates test result information for expressing that the test fails;
after the test result information is generated, the upper computer marks the target information as the completion information, and removes the mark of the target information of the completion information.
3. The method for testing a BMC chip according to claim 2, wherein the processor obtains the collected data of each sensor 1 time, establishes a correspondence between the collected data and a transmission interface corresponding to an interface serial number corresponding to a sensor serial number of a corresponding sensor based on the target information, and transmits the collected data to the BMC chip through the corresponding transmission interface, and further comprises:
The processor packages the acquired data and the sensor numbers of the corresponding sensors to form comparison information, and sends the comparison information to the upper computer;
The upper computer judges whether the sensor number and the interface serial number of the sensor for collecting data in the same feedback information accord with the corresponding relation between the sensor number and the interface serial number in the target information or not, and then the method further comprises the following steps:
if yes, the upper computer packs and stores the sensor number corresponding to the interface serial number in the feedback information into the feedback information based on the target information;
The upper computer establishes a corresponding relation between feedback information and comparison information which are contained and have consistent sensor numbers, and judges whether acquired data in the feedback information and the comparison information which correspond to each other are consistent or not;
If the test result information is consistent with the test result information, the upper computer generates the test result information for expressing the passing of the test;
if the test result information is inconsistent, the bit machine generates test result information for expressing that the test fails.
4. The method for testing a BMC chip according to claim 1, wherein the host computer randomly selects 1 configuration information which is not marked as completion information, marks the configuration information as target information, and sends the target information to the processor, and further comprises:
The processor acquires the acquired data sent by the sensor once every second preset time length, marks the source sensor with the acquired data reaching the second preset number as the target sensor when the number of the acquired data received by the processor from the same sensor reaches the second preset number, and stops receiving the acquired data from the target sensor;
the processor sends the second preset number to the upper computer;
the processor establishes a corresponding relation between each acquired data and a transmitting interface corresponding to the interface serial number corresponding to the corresponding sensor serial number based on the target information, and transmits the acquired data to the BMC chip through the corresponding transmitting interface;
The BMC chip packs the received acquired data and an interface serial number of a receiving interface for receiving the acquired data to form feedback information, and sends the feedback information to the upper computer through the connecting slot;
The upper computer generates test result information based on the feedback information and the second preset quantity, marks the target information as finish information based on the test result information, removes the mark of the target information of the finish information, then executes the steps of randomly selecting 1 configuration information which is not marked as the finish information by the upper computer, marks the configuration information as the target information, and sends the target information to the processor.
5. The method of claim 4, wherein the host computer generates test result information based on the feedback information and the second preset number, marks the target information as completion information based on the test result information, and removes the mark of the target information of the completion information, and the method comprises:
After the upper computer receives the first feedback information, marking the time of receiving the first feedback information as the initial time;
The upper computer judges whether a third preset number of feedback information is received within a third preset time from the initial moment, wherein the third preset number is the product of the second preset number and the number of the sensors;
If yes, the upper computer judges whether the sensor number and the interface serial number of the sensor corresponding to the acquired data in the same feedback information accord with the corresponding relation between the sensor number and the interface serial number in the target information;
If yes, the upper computer generates test result information for expressing that the test passes;
If the test result information does not accord with the test result information, the upper computer generates the test result information for expressing that the test fails;
If not, the upper computer determines a receiving interface with a fault based on the feedback information and the second preset number, and generates test result information for expressing that the test fails, wherein the test result information comprises an interface serial number of the receiving interface with the fault;
after the test result information is generated, the upper computer marks the target information as the completion information, and removes the mark of the target information of the completion information.
6. The method for testing a BMC chip according to claim 5, wherein the host computer determines a failed receiving interface based on the feedback information and the second preset number, and generates test result information for indicating that the test fails, comprising:
The upper computer classifies the feedback information with the same interface serial number into the same feedback information group;
The upper computer marks the feedback information groups with the quantity of the feedback information being less than the second preset quantity as target groups, and determines the receiving interfaces corresponding to the interface serial numbers in the feedback information in the target groups as the receiving interfaces with faults.
7. The method for testing a BMC chip according to claim 2, wherein the test motherboard comprises a plurality of connection slots; the number of the sending interfaces of each connecting slot is consistent, and the interface serial numbers of the sending interfaces at the same position of each connecting slot are consistent; the upper computer randomly selects 1 configuration information which is not marked as finishing information, marks the configuration information as target information, and sends the target information to the processor, and then the method further comprises the following steps:
the processor acquires the acquired data of each sensor for 1 time respectively, and establishes a corresponding relation between each acquired data and a transmitting interface corresponding to an interface serial number corresponding to a sensor serial number of a corresponding sensor in sequence based on target information;
the processor sequentially sends all the acquired data to all the BMC chips through corresponding sending interfaces;
each BMC chip packs the received acquired data and the interface serial numbers of the receiving interfaces for receiving the acquired data to form feedback information, and sends the feedback information to the upper computer through the connecting slot;
After the upper computer receives the first feedback information, marking the moment of receiving the first feedback information as a starting moment;
The upper computer judges whether a fourth preset number of feedback information is received within a first preset time from the starting point moment, wherein the fourth preset number is the product of the number of the sensors and the number of the connecting slots in the test main board;
If yes, executing the upper computer to judge whether the sensor number and the interface serial number corresponding to the sensor for collecting data in the same feedback information accord with the corresponding relation between the sensor number and the interface serial number in the target information or not, and then, executing the following steps;
If not, the upper computer generates test result information for expressing that the test fails;
after the test result information is generated, the upper computer marks the target information as the completion information, and removes the mark of the target information of the completion information;
and executing the steps that the upper computer randomly selects 1 configuration information which is not marked as the completion information and marks the configuration information as target information, and sending the target information to the processor.
8. The method for testing a BMC chip according to claim 1, wherein the host computer comprises a display module; the upper computer randomly selects 1 configuration information which is not marked as finishing information, marks the configuration information as target information, and sends the target information to the processor, and then the method further comprises the following steps:
The processor acquires the acquired data of each sensor in real time and sends the acquired data of each sensor to the upper computer;
The display module displays the acquired data of each sensor in real time.
9. The method of claim 1, wherein the system further comprises a test box; the test box body is internally provided with a temperature adjusting module, and the test main board is arranged in the test box body; the upper computer is in communication connection with the temperature adjusting module and is used for controlling the temperature in the test box body; the sensor group comprises a temperature sensor; the method further comprises the steps of:
the upper computer adjusts the temperature in the test box body to a first preset temperature value through the temperature adjusting module and keeps a fourth preset time length;
the upper computer adjusts the temperature in the test box body to a second preset temperature value through the temperature adjusting module and keeps a fourth preset time period, wherein the second preset temperature value is higher than the first preset temperature value.
10. A BMC chip test system, wherein the BMC chip test method according to any one of claims 1 to 9 is applied; the system comprises a test main board and an upper computer; the test main board is provided with a processor, a connecting slot and a sensor group; the sensor group comprises a plurality of sensors, and each sensor is correspondingly provided with a unique sensor number; the connecting slot is used for embedding the BMC chip to be tested; the upper computer is connected with the test main board in a communication way; the connecting slot comprises a plurality of transmitting interfaces; the BMC chip comprises a plurality of receiving interfaces; each transmitting interface is correspondingly provided with a different interface serial number, and each receiving interface is correspondingly provided with a different interface serial number; when the BMC chip is embedded into the connecting slot, the sending interfaces and the receiving interfaces are connected in one-to-one correspondence, and the interface serial numbers of the sending interfaces and the interface serial numbers of the receiving interfaces which are connected in a corresponding manner are consistent.
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