CN118051089A - Bidirectional current low-dropout linear voltage regulator - Google Patents

Bidirectional current low-dropout linear voltage regulator Download PDF

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CN118051089A
CN118051089A CN202410442690.XA CN202410442690A CN118051089A CN 118051089 A CN118051089 A CN 118051089A CN 202410442690 A CN202410442690 A CN 202410442690A CN 118051089 A CN118051089 A CN 118051089A
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transistor
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power
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resistor
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CN118051089B (en
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胡欢
黄善飞
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Beijing Zhongtian Star Control Technology Development Co ltd Chengdu Branch
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Beijing Zhongtian Star Control Technology Development Co ltd Chengdu Branch
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Abstract

The invention discloses a bidirectional current low-dropout linear voltage regulator, which relates to the technical field of low-dropout voltage regulators and comprises the following components: the operational amplifier OPA1 outputs a signal V 1 and a signal V 2, the signal V 1 and the signal V 2 are used for driving the second power adjustment circuit, the signal V 1 and the signal V 2 are also used for driving the operational amplifier OPA2 and the operational amplifier OPA3, the negative input ends of the operational amplifier OPA2 and the operational amplifier OPA3 are respectively connected with a first level shift circuit and a second level shift circuit, the signal V 1 and the signal V 2 are amplified and level shifted to obtain a signal V 3 and a signal V 4, and the signal V 3 and the signal V 4 are used for driving the first power adjustment circuit. The voltage source VDD provides an external power source and the final signal is output through the signal output terminal V OUT. The voltage stabilizer not only can provide bidirectional conduction current for a load, but also can maintain extremely low static power consumption of the bidirectional current low-dropout voltage stabilizer under the condition of light load or no load.

Description

Bidirectional current low-dropout linear voltage regulator
Technical Field
The invention relates to the technical field of low dropout regulators, in particular to a bidirectional current low dropout linear regulator.
Background
The electronic device needs to provide a stable voltage which does not change with power supply fluctuation and load for the internal chip, and the most common mode is to use a low dropout linear regulator (LDO), and the traditional LDO is composed of a power switch tube, an error amplifier and a voltage dividing resistor. However, in the application scenarios of motor driving, semiconductor refrigerator controller and the like, which require bidirectional current, the conventional LDO can only provide unidirectional current due to the limitation of circuit topology structure, and the application is limited, so that the low dropout voltage regulator with bidirectional current regulation is derived.
Prior art 1: publication number CN114442717a, entitled low dropout voltage regulator with bidirectional current regulation, includes a voltage divider circuit, an operational amplifier, a regulating circuit, and an output circuit. The voltage dividing circuit divides a power voltage to generate a preset voltage. The operational amplifier generates a bias voltage according to the preset voltage and an output voltage of the output end, the regulating circuit generates a first regulating voltage and a second regulating voltage according to the bias voltage, and the output circuit regulates a difference value between a first current and a second current according to the first regulating voltage and the second regulating voltage so as to regulate the output voltage.
The low dropout voltage regulator in prior art 1 can perform bidirectional current adjustment on the output terminal to adjust the output voltage, so as to support a larger power supply voltage range or a more stable output voltage, but the scheme still has the problem of higher static power consumption under the condition of no load or light load.
Therefore, a bi-directional current low dropout linear voltage regulator is needed to solve the problem that the static power consumption of the existing voltage regulator is high under no-load or light-load conditions.
Disclosure of Invention
In order to solve the problem that the static power consumption of the existing bidirectional current low dropout voltage regulator is higher under the condition of no load or light load, the invention provides a bidirectional current low dropout linear voltage regulator, which comprises: a voltage source VDD, an operational amplifier OPA1, an operational amplifier OPA2, an operational amplifier OPA3, a first level shift circuit, a second level shift circuit, a first power adjustment circuit, and a second power adjustment circuit;
The operational amplifier OPA1 is configured to: the positive input end is connected with the reference voltage V REF, the negative input end is connected with the input voltage V B, and the two output ends respectively output a signal V 1 and a signal V 2;
Wherein the signal V 1 and the signal V 2 are connected and drive the second power adjustment circuit;
The operational amplifier OPA2 is configured to: the positive input end is connected with the signal V 1, the negative input end is connected with the output end through the first level shift circuit, and the output end is connected with the first power adjustment circuit and outputs a signal V 3;
The operational amplifier OPA3 is configured to: the positive input end is connected with the signal V 2, the negative input end is connected with the output end through the second level shift circuit, and the output end is connected with the first power adjustment circuit and outputs a signal V 4;
wherein the signal V 3 and the signal V 4 are connected and drive the first power adjustment circuit;
one end of the first power adjusting circuit and one end of the second power adjusting circuit are connected with the voltage source VDD, the other end of the first power adjusting circuit and the other end of the second power adjusting circuit are grounded, and the first power adjusting circuit and the second power adjusting circuit are connected with the signal output end V OUT.
The invention is realized by the following technical scheme: the input V B is connected with a fixed potential and is input from the negative end of the operational amplifier OPA1, the reference voltage V REF is input from the positive end of the operational amplifier OPA1, the difference of signals of the positive end and the negative end of the operational amplifier OPA1 is amplified by the operational amplifier OPA1, the signals V 1 and V 2 are respectively output through two output ends, and the signals V 1 and V 2 are used for driving the second power adjusting circuit; meanwhile, the signals V 1 and V 2 are respectively connected to the operational amplifier OPA2 and the operational amplifier OPA3, meanwhile, the negative terminals of the operational amplifier OPA2 and the operational amplifier OPA3 are respectively connected with the first level shift circuit and the second level shift circuit, the output signal of the amplified and added with the shift level V 1 is the output signal of the amplified and added with the shift level V 3,V2, the output signal of the amplified and added with the shift level V 4, the signals V 3 and V 4 are used for driving the first power adjusting circuit, the voltage source VDD plays a role of providing an external power supply, and the signals are output through the signal output end V OUT after being adjusted by the first power adjusting circuit and the second power adjusting circuit.
The bidirectional current LDO is usually composed of an operational amplifier, a power tube MP, a power tube MN and a voltage dividing resistor, but the sizes of the power tubes MP and MN are larger, so that the static power consumption of the existing current LDO is extremely high under the condition of no load. The first power adjusting circuit is driven by signals output by the power amplifiers OPA2 and OPA3, and the signals output by the operational amplifiers OPA2 and OPA3 are shifted by the first level shifting circuit and the second level shifting circuit to control the voltage of the grid electrode of the transistor in the first power adjusting circuit, so that the effect of lower static power consumption of the first power circuit is finally realized. Through the arrangement of the structure, the problem that the static power consumption of the existing bidirectional current low-dropout voltage regulator is higher under the condition of no load or light load is solved.
Further, the first power adjustment circuit includes a transistor MP1 and a power tube MN1, where a gate of the power tube MP1 is connected to an output end of the operational amplifier OPA2, a source of the power tube MP1 is connected to the voltage source VDD, a gate of the power tube MN1 is connected to an output end of the operational amplifier OPA3, a source of the power tube MN1 is grounded, and a drain of the power tube MP1 and a drain of the power tube MN1 are both connected to the signal output end V OUT.
The amplified signals of the operational amplifiers OPA2 and OPA3 are output to the gates of the transistors MP1 and MN1, and the amplified signals (currents) can control the turn-on voltage of the transistors, and by controlling the output signals of the operational amplifiers OPA2 and OPA3, the static power consumption of the power transistors MP1 and MN1 is finally reduced.
Further, the second power adjustment circuit includes a power tube MP5 and a power tube MN5, where a gate of the power tube MP5 is connected to the first output end of the operational amplifier OPA1, a source of the power tube MP5 is connected to the voltage source VDD, a gate of the power tube MN5 is connected to the second output end of the operational amplifier OPA1, a source of the power tube MN5 is grounded, and a drain of the power tube MP5 and a drain of the power tube MN5 are both connected to the signal output end V OUT.
The power tubes MP5 and MN5 can ensure that the output power tube keeps low-power-consumption conduction under the condition of no load or light load of the voltage stabilizer, thereby ensuring that the whole negative feedback loop normally works under the condition of light load or heavy load.
Further, the area of the power tube MP1 and the area of the power tube MN1 are both N 1, and the area of the power tube MP5 and the area of the power tube MN5 are both the ratio of N 2,N1 to N 2, which is greater than a preset constant.
For the existing bidirectional current LDO, the conventional bidirectional current LDO is usually composed of an operational amplifier, a power switch tube MP, a power switch tube MN and two voltage dividing resistors, but the sizes of the power switch tube MP and the power switch tube MN are far larger than those of other MOS tubes, so that the bidirectional current LDO has extremely high static power consumption under the condition of no load, therefore, the embodiment provides the same-direction driving signal by designing the operational amplifier OPA1, simultaneously divides the power switch tube MP into MP1 and MP5, divides the power switch tube MN into MN1 and MN5, and satisfies that the ratio of the areas of MP1 and MP5 (MN 1 and MN 5) is larger than a preset constant, namely the area of limiting MP5 and MN5 is far smaller than that of MP1 and MN1. The power tubes MP5 and MN5 are driven by the operational amplifier OPA1, and the areas of the MP5 and MN5 are far smaller than those of the MP and MN, so that the static power consumption is smaller; the power tubes MP1 and MN1 are driven by the operational amplifiers OPA2 and OPA3, and the level shift circuit shifts the level of the signals output by the operational amplifiers OPA2 and OPA3, so that the static power consumption of the power tubes MP1 and MN1 is far smaller than that of MP and MN.
Further, the output stage structure of the operational amplifier OPA1 includes: transistor MP2, transistor MP3, transistor MP4, transistor MN2, transistor MN3, transistor MN4, current source I B1, current source 2αi B1, current source I B2, and current source 2αi B2;
The source of the transistor MP4 is connected to the signal V IN1, the drain of the transistor MP4 is connected to the signal V IN2, the gate of the transistor MP4 is connected to the gate and the drain of the transistor MP3, the drain of the transistor MP3 is connected to the positive terminal of the current source I B1, the negative terminal of the current source I B1 is grounded, the source of the transistor MP3 is connected to the gate and the drain of the transistor MP2, the source of the transistor MP2 is connected to the voltage source VDD, the positive terminal of the current source 2αi B1 is connected to the voltage source VDD, the negative terminal of the current source 2αi B1 is connected to the source of the transistor MP4, the source of the transistor MP4 is connected to the gate of the power transistor MP5, the source of the power transistor MP5 is connected to the voltage source VDD, and the drain of the power transistor MP5 is connected to the signal output terminal V OUT;
The drain of the transistor MN4 is connected to the signal V IN1, the source of the transistor MN4 is connected to the signal V IN2, the gate of the transistor MN4 is connected to the gate and the drain of the transistor MN3, the drain of the transistor MN3 is connected to the negative terminal of the current source I B2, the positive terminal of the current source I B2 is connected to the voltage source VDD, the source of the transistor MN3 is connected to the drain and the gate of the transistor MN2, the source of the transistor MN2 is grounded, the positive terminal of the current source 2αi B2 is connected to the source of the transistor MN4, the negative terminal of the current source 2αi B2 is grounded, the gate of the power transistor MN5 is connected to the source of the transistor MN4, the source of the power transistor MN5 is grounded, and the drain of the power transistor MN5 is connected to the signal output terminal V OUT;
The signal V IN1 and the signal V IN2 are two co-directional signals transferred from the intermediate stage of the OPA1 op-amp.
The transistors MP2, MP3, MP4, MN2, MN3, MN4 and four current sources form an output stage structure of the operational amplifier OPA1, the signals V IN1 and V IN2 are two homodromous signals transmitted by the intermediate stage of the operational amplifier OPA1, the transistors MP2, MP3, MP4 and the power transistor MP5 form a linear transconductance loop, that is, the gate-source voltage of the power transistor MP5 plus the gate-source voltage of the transistor MP4 is equal to the gate-source voltage of the transistor MP2 plus the gate-source voltage of the transistor MP3, and the static gate-source voltage of the transistor MP2, the static gate-source voltage of the transistor MP3 and the static gate-source voltage of the transistor MP4 can be determined by designing the size of the current source I B1, so that the static gate-source voltage of the transistor MP5, that is, the static direct current value of the voltage V IN1 is, the transconductance linear loop MP2, MP3, MP4 and MP5 play a role in determining the static current of the power transistor MP 5; similarly, the transconductance linear loops MN2, MN3, MN4, and MN5 function to determine the quiescent current of the power tube MN 5.
Further, the first level shift circuit includes a current source I D, a resistor R D1, and a resistor R D2, one end of the resistor R D1 is connected to an external voltage source, the other end of the resistor R D1, a positive end of the current source I D, and one end of the resistor R D2 are all connected to the negative input end of the operational amplifier OPA2, the negative end of the current source I D is grounded, and the other end of the resistor R D2 is connected to the output end of the operational amplifier OPA 2.
The signal V 1 is amplified and level-shifted to obtain the signal V 3, and by setting the values of the current source I D, the resistor R D1 and the resistor R D2, the signal V 3 is greater than the signal V 1, and the value of V 3 is greater than the value of the power transistor MP1, which is close to being turned off, but the signal V 3 is greater than the signal V 1, because for the PMOS transistor, the larger the gate voltage, the smaller the gate-source voltage, the smaller the current of the power transistor MP1, and the smaller the power consumption.
Further, the second level shift circuit includes a current source I D1, a resistor R D3, and a resistor R D4, where a positive end of the current source I D1 is connected to an external voltage source, a negative end of the current source I D1, one end of the resistor R D3, and one end of the resistor R D4 are all connected to a negative input end of the operational amplifier OPA3, another end of the resistor R D3 is grounded, and another end of the resistor R D4 is connected to an output end of the operational amplifier OPA 3.
The signal V 2 is amplified and level-shifted to obtain the signal V 4, and by setting the values of the current source ID 1, the resistor R D3 and the resistor R D4, the signal V 4 is smaller than the signal V 2, and the value of V 4 may be as small as the power transistor MN1 is close to off, and the signal V 4 is smaller than the signal V 2 because for the NMOS transistor, the smaller the gate voltage, the smaller the gate-source voltage, the smaller the current of the power transistor MN1, and thus the smaller the power consumption.
Further, the voltage stabilizer further includes a resistor R 1 and a resistor R 2, one end of the resistor R 1 is connected to the voltage V REF, the other end of the resistor R 1 and one end of the resistor R 2 are both connected to the positive input end of the operational amplifier OPA1, and the other end of the resistor R 2 is connected to the signal output end V OUT.
The output voltage is collected through a resistor R 1 and a resistor R 2, and a collected voltage signal is input to the positive input end of the operational amplifier OPA1 to form negative feedback regulation.
Further, the voltage stabilizer further comprises a resistor R L and a voltage source V L, one end of the resistor R L is connected with the signal output end V OUT, and the other end of the resistor R L is connected with the voltage source V L.
The resistor R L and the voltage source V L form a load circuit, and the load circuit plays a role in simulating a load.
The one or more technical schemes provided by the invention have at least the following technical effects or advantages:
The invention divides the power adjusting circuit into the first power adjusting circuit and the second power adjusting circuit, drives the second power adjusting circuit through the operational amplifier OPA1, drives the first power adjusting circuit through the operational amplifiers OPA2 and OPA3, and simultaneously carries out level shift on output signals by accessing a level shift circuit into the negative inputs of the operational amplifiers OPA2 and OPA3, thereby solving the problem that the static power consumption of the existing bidirectional current low-dropout voltage regulator is higher under the condition of no load or light load.
Drawings
The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention;
FIG. 1 is a schematic circuit diagram of a bi-directional current LDO;
FIG. 2 is a schematic diagram of an output stage structure of a bi-directional current LDO;
FIG. 3 is a schematic diagram of a bi-directional current low dropout linear voltage regulator of the present invention;
FIG. 4 is a graph showing the variation of the signals V1, V2, V3 and V4 with the output voltage according to the present invention;
Fig. 5 is a schematic diagram showing the connection between the output stage structure of the operational amplifier OPA1 and the power transistors MP5 and MN5 in the present invention.
Detailed Description
In order that the above-recited objects, features and advantages of the present invention will be more clearly understood, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description. In addition, the embodiments of the present invention and the features in the embodiments may be combined with each other without collision.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than within the scope of the description, and therefore the scope of the invention is not limited to the specific embodiments disclosed below.
Referring to fig. 1 and 2, fig. 1 is a schematic circuit diagram of a conventional bi-directional current LDO, fig. 2 is a schematic structure diagram of an output stage of the bi-directional current LDO, and based on fig. 1, fig. 2 and fig. 3, a problem of high static power consumption of the conventional bi-directional current LDO under a no-load condition is specifically analyzed, and a specific implementation manner of the embodiment of the invention for solving the problem of high static power consumption is provided.
As shown in fig. 1, the bi-directional current LDO is composed of a dual-ended output operational amplifier OPA1, a power tube MP, a power tube MN, and voltage dividing resistors R 1 and R 2, wherein the dual-ended output operational amplifier OPA1 is a class AB output operational amplifier for providing a drive signal in the same direction, the output stage structure is as shown in fig. 2, and the transistors MP, MP2, MP3, MP4, MN2, MN3, and MN4 form a linear transconductance loop, and the dimensions thereof satisfy the relation:
wherein, : Ratio of gate widths of power tubes and other tubes; /(I): Hole mobility of the PMOS tube; /(I): Hole mobility of the NMOS tube; c OXP: grid capacitance of unit area of the PMOS tube; c OXN: grid capacitance of unit area of the PMOS tube; w MP: the unit area gate width of the PMOS tube; w MN: the unit area gate width of the NMOS tube; l MP: the unit area gate length of the PMOS tube; l MN: the unit area gate length of the NMOS tube.
Then the currents I push and I pull of the power tube MP and the power tube MN satisfy the following relationship:
In the absence of load, I push=Ipull, the static values of currents I push and I pull are:
The minimum value of currents I push and I pull is:
Since the power switching transistors MP and MN need to supply a large current under heavy load, the maximum value of the MP and MN gate-source voltages cannot be too small, so that there is a sufficient gap between the value of α and 4. (if α=4, the sum of the currents flowing through MN4 and MP4 is 8 times that flowing through MP2, MP3, MN2 and MN3, and a sufficient voltage drop is required on the current source 2αi B1, which results in that any one of the MN4 and MP4 cannot flow through too much current, and thus the minimum gate-source voltages of MN4 and MP4 are limited, and the maximum value of the MP and MN gate-source voltages are limited), and at the same time, in order to obtain low on-resistance, the sizes of the power transistors MP and MN are far greater than those of the other MOS transistors, i.e., β is far greater than 1, which results in high static power consumption of the bidirectional current LDO under no load or light load.
In order to solve the above-mentioned problems, please refer to fig. 3, fig. 3 is a schematic diagram of a bidirectional current low dropout linear voltage regulator according to the present invention, the voltage regulator comprises: a voltage source VDD, an operational amplifier OPA1, an operational amplifier OPA2, an operational amplifier OPA3, a first level shift circuit, a second level shift circuit, a first power adjustment circuit, and a second power adjustment circuit;
The operational amplifier OPA1 is configured to: the positive input end is connected with the reference voltage V REF, the negative input end is connected with the input voltage V B, and the two output ends respectively output a signal V 1 and a signal V 2;
Wherein the signal V 1 and the signal V 2 are connected and drive the second power adjustment circuit;
The operational amplifier OPA2 is configured to: the positive input end is connected with the signal V 1, the negative input end is connected with the output end through the first level shift circuit, and the output end is connected with the first power adjustment circuit and outputs a signal V 3;
The operational amplifier OPA3 is configured to: the positive input end is connected with the signal V 2, the negative input end is connected with the output end through the second level shift circuit, and the output end is connected with the first power adjustment circuit and outputs a signal V 4;
wherein the signal V 3 and the signal V 4 are connected and drive the first power adjustment circuit;
one end of the first power adjusting circuit and one end of the second power adjusting circuit are connected with the voltage source VDD, the other end of the first power adjusting circuit and the other end of the second power adjusting circuit are grounded, and the first power adjusting circuit and the second power adjusting circuit are connected with the signal output end V OUT.
Referring to fig. 4, fig. 4 is a schematic diagram showing the change of signals V1, V2, V3 and V4 along with the output voltage in the present invention. Firstly, the power tube MP and the power tube MN in fig. 2 are respectively divided into two power tubes MP1, MP5, MN1 and MN5, the areas of the power tube MP1 and the power tube MN1 are N 1, and the areas of the power tube MP5 and the power tube MN5 are N 2, N1: the ratio of N2 is greater than a preset constant, N 1 is defined to be far greater than N 2, that is, the multiple of N 1 and N 2 is at least 1000 times, two input ends of the operational amplifier OPA1 are respectively used for inputting signals V REF and V B, and two output ends of the operational amplifier OPA1 output signals V 1 and V 2 for driving the power tube MP5 and the power tube MN5, and because the areas of the power tubes MP5 and MN5 are far smaller than those of the power tubes MP and MN, the static power consumption of the power tubes MP5 and MN5 is far smaller than those of the power tubes MP and MN. Meanwhile, output signals V 1 and V 2 of the operational amplifier OPA1 are also used for being connected with the positive end of the operational amplifier OPA2 and the positive end of the operational amplifier OPA3, the output of the operational amplifier OPA2 and the output of the operational amplifier OPA3 are respectively connected back to the negative ends of the operational amplifier OPA2 and the operational amplifier OPA3 through voltage dividing resistors, meanwhile, the negative ends of the operational amplifier OPA2 and the operational amplifier OPA3 are both connected with a current source, the effect of the current source enables output signals V 3 and V 4 of the operational amplifier OPA2 and the operational amplifier OPA3 to generate level shift, the value of the current source and the voltage dividing resistor is set to enable V 4＜V2,V3＞V1, the value of V 4 is small enough to enable a power tube MN1 to be close, and the value of V 3 is large to enable the power tube MP1 to be close to be closed. For NOMS tubes, the smaller the gate voltage, the smaller the gate-source voltage, and finally the smaller the quiescent current of MN 1; for the PMOS tube, the larger the gate voltage is, the smaller the gate-source voltage is, and the smaller the static current of the final MP1 is. Therefore, the static power consumption of the power tube MP1 and the power tube MN1 is also much smaller than those of the power tubes MP and MN in the no-load condition. According to the analysis, the embodiment of the invention can effectively solve the problem that the static power consumption of the bidirectional current LDO is too high under the condition of no load or light load.
The first power adjustment circuit comprises a transistor MP1 and a power tube MN1, wherein a grid electrode of the power tube MP1 is connected with an output end of the operational amplifier OPA2, a source electrode of the power tube MP1 is connected with the voltage source VDD, a grid electrode of the power tube MN1 is connected with an output end of the operational amplifier OPA3, a source electrode of the power tube MN1 is grounded, and a drain electrode of the power tube MP1 and a drain electrode of the power tube MN1 are both connected with the signal output end V OUT.
The second power adjustment circuit comprises a power tube MP5 and a power tube MN5, wherein a grid electrode of the power tube MP5 is connected with a first output end of the operational amplifier OPA1, a source electrode of the power tube MP5 is connected with the voltage source VDD, a grid electrode of the power tube MN5 is connected with a second output end of the operational amplifier OPA1, a source electrode of the power tube MN5 is grounded, and a drain electrode of the power tube MP5 and a drain electrode of the power tube MN5 are both connected with the signal output end V OUT.
The area of the power tube MP1 and the area of the power tube MN1 are N 1, and the area of the power tube MP5 and the area of the power tube MN5 are the ratio of N 2,N1 to N 2 which is larger than a preset constant.
The first power adjusting circuit comprises power tubes MP1 and MN1, the second power adjusting circuit comprises power tubes MP5 and MN5, the power tubes MP in the common bidirectional current LDO are divided into power tubes MP1 and MP5, the power tubes MN are divided into power tubes MN1 and MN5, the areas of the power tubes MP1 and MN1 are N 1, the areas of the power tubes MP5 and MN5 are N 2, and N 1 is far larger than N 2. Therefore, the areas of the power tubes MP5 and MN5 are far smaller than those of the power tubes MP and MN, the static power consumption of the power tubes MP and MN is also far smaller than that of the power tubes MP and MN, and meanwhile, the power tubes MP5 and MN5 can ensure that the output power tube keeps low-power conduction under the condition of no load or light load, so that the whole negative feedback loop can work normally under the condition of light load or heavy load. The areas of the power tubes MP1 and MN1 in the first power adjustment circuit are larger, but the power tubes MP1 and MN1 are driven by the operational amplifiers OPA2 and OPA3, and the operational amplifiers OPA2 and OPA3 are level shifted by the level shift circuit, so that the quiescent current of the final power tubes MP1 and MN1 is far smaller than the quiescent current in the power tubes MP and MN, i.e. the quiescent power consumption of the power tubes MP1 and MN1 is also far smaller than the quiescent power consumption of the power tubes MP and MN.
Referring to fig. 5, fig. 5 is a schematic diagram showing the connection between an output stage structure of an operational amplifier OPA1 and power transistors MP5 and MN5, wherein the output stage structure of the operational amplifier OPA1 includes: transistor MP2, transistor MP3, transistor MP4, transistor MN2, transistor MN3, transistor MN4, current source I B1, current source 2αi B1, current source I B2, and current source 2αi B2;
The source of the transistor MP4 is connected to the signal V IN1, the drain of the transistor MP4 is connected to the signal V IN2, the gate of the transistor MP4 is connected to the gate and the drain of the transistor MP3, the drain of the transistor MP3 is connected to the positive terminal of the current source I B1, the negative terminal of the current source I B1 is grounded, the source of the transistor MP3 is connected to the gate and the drain of the transistor MP2, the source of the transistor MP2 is connected to the voltage source VDD, the positive terminal of the current source 2αi B1 is connected to the voltage source VDD, the negative terminal of the current source 2αi B1 is connected to the source of the transistor MP4, the source of the transistor MP4 is connected to the gate of the power transistor MP5, the source of the power transistor MP5 is connected to the voltage source VDD, and the drain of the power transistor MP5 is connected to the signal output terminal V OUT;
The drain of the transistor MN4 is connected to the signal V IN1, the source of the transistor MN4 is connected to the signal V IN2, the gate of the transistor MN4 is connected to the gate and the drain of the transistor MN3, the drain of the transistor MN3 is connected to the negative terminal of the current source I B2, the positive terminal of the current source I B2 is connected to the voltage source VDD, the source of the transistor MN3 is connected to the drain and the gate of the transistor MN2, the source of the transistor MN2 is grounded, the positive terminal of the current source 2αi B2 is connected to the source of the transistor MN4, the negative terminal of the current source 2αi B2 is grounded, the gate of the power transistor MN5 is connected to the source of the transistor MN4, the source of the power transistor MN5 is grounded, and the drain of the power transistor MN5 is connected to the signal output terminal VOUT;
The signal V IN1 and the signal V IN2 are two co-directional signals transferred from the intermediate stage of the OPA1 op-amp.
The transistors MP2, MP3, MP4, MN2, MN3 and MN4, the current sources I B1、2αIB1、IB2 and 2αi B2 together form an output stage structure of the operational amplifier OPA1, the transistors MP2, MP3, MP4 and the power tube MP5 form a linear transconductance loop, that is, the gate-source voltage of MP5 plus the gate-source voltage of MP4 is equal to the gate-source voltage of MP2 plus the gate-source voltage of MP3, and the static gate-source voltage of MP2, the static gate-source voltage of MP3 and the static gate-source voltage of MP4 can be determined by designing the size of the current source I B1, thereby determining the static gate-source voltage of MP5, and therefore, the transconductance linear loops MP2, MP3, MP4 and MP5 play a role in determining the static current of the power tube MP 5. The transconductance linear loops MN2, MN3, MN4, and MN5 function to determine the quiescent current of the power tube MN 5.
The first level shift circuit includes a current source I D, a resistor R D1, and a resistor R D2, one end of the resistor R D1 is connected to an external voltage source, the other end of the resistor R D1, the positive end of the current source I D, and one end of the resistor R D2 are all connected to the negative input end of the operational amplifier OPA2, the negative end of the current source I D is grounded, and the other end of the resistor R D2 is connected to the output end of the operational amplifier OPA 2.
Signal V 1 is processed by OPA2 to obtain signal V 3, signal V 3 is level shifted by the first level shift circuit, and finally signal V 3 and signal V 1 satisfy the following relation:
By adjusting the values of the current source I D, the resistor R D1 and the resistor R D2, V 3 can be larger than V 1, and the value of V 3 is larger than that of the power tube MP1 and close to closing, so that the effect of reducing the static power consumption of the power tube MP1 is finally achieved.
The second level shift circuit includes a current source I D1, a resistor R D3, and a resistor R D4, where a positive end of the current source I D1 is connected to an external voltage source, a negative end of the current source I D1, one end of the resistor R D3, and one end of the resistor R D4 are all connected to a negative input end of the operational amplifier OPA3, another end of the resistor R D3 is grounded, and another end of the resistor R D4 is connected to an output end of the operational amplifier OPA 3.
Signal V 2 is processed by OPA3 to obtain signal V 4, signal V 4 is level shifted by a second level shifting circuit, and finally signal V 4 and signal V 2 satisfy the following relation:
By adjusting the values of the current source I D1, the resistor R D3 and the resistor R D4, V 4 can be smaller than V 2, and the value of V 4 is small enough that the power tube MN1 is close to be closed, and finally the effect of reducing the static power consumption of the power tube MN1 is achieved.
The voltage stabilizer further comprises a resistor R 1 and a resistor R 2, one end of the resistor R 1 is connected with the voltage V REF, the other end of the resistor R 1 and one end of the resistor R 2 are both connected with the positive input end of the operational amplifier OPA1, and the other end of the resistor R 2 is connected with the signal output end V OUT.
Output voltage is acquired through a resistor R 1 and a resistor R 2, and an acquired voltage signal is input to the positive input end of the operational amplifier OPA1 to form negative feedback regulation.
The voltage stabilizer further comprises a resistor R L and a voltage source V L, one end of the resistor R L is connected with the signal output end V OUT, and the other end of the resistor R L is connected with the voltage source V L.
The resistor R L and the voltage source V L form a load circuit to play a role in simulating a load.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims (9)

1. A bi-directional current low dropout linear voltage regulator, the voltage regulator comprising: a voltage source VDD, an operational amplifier OPA1, an operational amplifier OPA2, an operational amplifier OPA3, a first level shift circuit, a second level shift circuit, a first power adjustment circuit, and a second power adjustment circuit;
The operational amplifier OPA1 is configured to: the positive input end is connected with the reference voltage V REF, the negative input end is connected with the input voltage V B, and the two output ends respectively output a signal V 1 and a signal V 2;
Wherein the signal V 1 and the signal V 2 are connected and drive the second power adjustment circuit;
The operational amplifier OPA2 is configured to: the positive input end is connected with the signal V 1, the negative input end is connected with the output end through the first level shift circuit, and the output end is connected with the first power adjustment circuit and outputs a signal V 3;
The operational amplifier OPA3 is configured to: the positive input end is connected with the signal V 2, the negative input end is connected with the output end through the second level shift circuit, and the output end is connected with the first power adjustment circuit and outputs a signal V 4;
wherein the signal V 3 and the signal V 4 are connected and drive the first power adjustment circuit;
one end of the first power adjusting circuit and one end of the second power adjusting circuit are connected with the voltage source VDD, the other end of the first power adjusting circuit and the other end of the second power adjusting circuit are grounded, and the first power adjusting circuit and the second power adjusting circuit are connected with the signal output end V OUT.
2. The bidirectional current low dropout linear regulator according to claim 1, wherein the first power adjustment circuit comprises a power tube MP1 and a power tube MN1, a gate of the power tube MP1 is connected to the output terminal of the operational amplifier OPA2, a source of the power tube MP1 is connected to the voltage source VDD, a gate of the power tube MN1 is connected to the output terminal of the operational amplifier OPA3, a source of the power tube MN1 is grounded, and a drain of the power tube MP1 and a drain of the power tube MN1 are both connected to the signal output terminal V OUT.
3. The bidirectional current low dropout linear regulator according to claim 2, wherein the second power adjustment circuit comprises a power tube MP5 and a power tube MN5, wherein a gate of the power tube MP5 is connected to the first output terminal of the operational amplifier OPA1, a source of the power tube MP5 is connected to the voltage source VDD, a gate of the power tube MN5 is connected to the second output terminal of the operational amplifier OPA1, a source of the power tube MN5 is grounded, and a drain of the power tube MP5 and a drain of the power tube MN5 are both connected to the signal output terminal V OUT.
4. The bi-directional current low dropout linear regulator according to claim 3, wherein the area of said power tube MP1 and the area of said power tube MN1 are N 1, and the area of said power tube MP5 and the area of said power tube MN5 are N 2,N1 and N 2, respectively, and the ratio of said power tube MP1 to said power tube MN5 is greater than a predetermined constant.
5. A bi-directional current low dropout linear regulator according to claim 3, wherein said output stage structure of operational amplifier OPA1 comprises: transistor MP2, transistor MP3, transistor MP4, transistor MN2, transistor MN3, transistor MN4, current source I B1, current source 2αi B1, current source I B2, and current source 2αi B2;
The source of the transistor MP4 is connected to the signal V IN1, the drain of the transistor MP4 is connected to the signal V IN2, the gate of the transistor MP4 is connected to the gate and the drain of the transistor MP3, the drain of the transistor MP3 is connected to the positive terminal of the current source I B1, the negative terminal of the current source I B1 is grounded, the source of the transistor MP3 is connected to the gate and the drain of the transistor MP2, the source of the transistor MP2 is connected to the voltage source VDD, the positive terminal of the current source 2αi B1 is connected to the voltage source VDD, the negative terminal of the current source 2αi B1 is connected to the source of the transistor MP4, the source of the transistor MP4 is connected to the gate of the power transistor MP5, the source of the power transistor MP5 is connected to the voltage source VDD, and the drain of the power transistor MP5 is connected to the signal output terminal V OUT;
The drain of the transistor MN4 is connected to the signal V IN1, the source of the transistor MN4 is connected to the signal V IN2, the gate of the transistor MN4 is connected to the gate and the drain of the transistor MN3, the drain of the transistor MN3 is connected to the negative terminal of the current source I B2, the positive terminal of the current source I B2 is connected to the voltage source VDD, the source of the transistor MN3 is connected to the drain and the gate of the transistor MN2, the source of the transistor MN2 is grounded, the positive terminal of the current source 2αi B2 is connected to the source of the transistor MN4, the negative terminal of the current source 2αi B2 is grounded, the gate of the power transistor MN5 is connected to the source of the transistor MN4, the source of the power transistor MN5 is grounded, and the drain of the power transistor MN5 is connected to the signal output terminal VOUT;
The signal V IN1 and the signal V IN2 are two co-directional signals transferred from the intermediate stage of the OPA1 op-amp.
6. The bi-directional current low dropout linear regulator according to claim 1, wherein said first level shift circuit comprises a current source I D, a resistor R D1, and a resistor R D2, wherein one end of said resistor R D1 is connected to an external voltage source, the other end of said resistor R D1, the positive end of said current source I D, and one end of said resistor R D2 are all connected to the negative input of said operational amplifier OPA2, the negative end of said current source I D is grounded, and the other end of said resistor R D2 is connected to the output of said operational amplifier OPA 2.
7. The bi-directional current low dropout linear regulator according to claim 1, wherein said second level shifting circuit comprises a current source I D1, a resistor R D3, and a resistor R D4, wherein a positive terminal of said current source I D1 is connected to an external voltage source, wherein a negative terminal of said current source I D1, one terminal of said resistor R D3, and one terminal of said resistor R D4 are all connected to a negative input terminal of said operational amplifier OPA3, and wherein the other terminal of said resistor R D3 is grounded, and wherein the other terminal of said resistor R D4 is connected to an output terminal of said operational amplifier OPA 3.
8. The bi-directional current low dropout linear regulator according to claim 1, further comprising a resistor R 1 and a resistor R 2, wherein one end of said resistor R 1 is connected to said voltage V REF, the other end of said resistor R 1 and one end of said resistor R 2 are both connected to the positive input terminal of said operational amplifier OPA1, and the other end of said resistor R 2 is connected to said signal output terminal V OUT.
9. The bi-directional current low dropout linear regulator according to claim 1, further comprising a resistor R L and a voltage source V L, wherein one end of said resistor R L is connected to said signal output terminal V OUT, and the other end of said resistor R L is connected to said voltage source V L.
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