CN118043966A - 交叉场效应晶体管库单元架构设计 - Google Patents

交叉场效应晶体管库单元架构设计 Download PDF

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CN118043966A
CN118043966A CN202280066199.0A CN202280066199A CN118043966A CN 118043966 A CN118043966 A CN 118043966A CN 202280066199 A CN202280066199 A CN 202280066199A CN 118043966 A CN118043966 A CN 118043966A
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transistors
pair
transistor
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gate
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理查德·T·舒尔茨
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Abstract

描述了用于有效地创建存储位单元布局的***和方法。在各种实施方式中，库中的单元使用交叉场效应晶体管(FET)，该交叉场效应晶体管(FET)包括具有导电沟道的垂直堆叠的全环绕栅极(GAA)晶体管，该导电沟道在这些晶体管之间以正交方向排列。该垂直堆叠的晶体管的沟道使用相反的掺杂极性。第一类单元包括器件，其中特定垂直堆叠中的两个器件中的每个器件接收相同输入信号。第二类单元包括器件，其中特定垂直堆叠中的两个器件接收不同输入信号。该第二类单元的高度尺寸大于该第一类单元。

Description

交叉场效应晶体管库单元架构设计
背景技术
相关技术的描述
随着半导体制造工艺的进步和裸片几何尺寸的减小，半导体芯片提供更多的功能和性能，同时占用更少的空间。虽然已经取得了许多进步，但现代技术在处理和集成电路设计中仍然出现设计问题，这限制了潜在的益处。例如，电容耦合、电迁移、诸如至少漏电流之类的短沟道效应和制程产量是一些影响半导体芯片的整个裸片的器件放置和信号路由的问题。这些问题有可能延迟设计的完成，并影响上市时间。
为了缩短半导体芯片的设计周期，在可能的情况下，手动全定制设计被自动化替代。在一些情况下，手动创建标准单元布局。在其他情况下，调整布局布线工具所使用的规则，从而自动化单元创建。但是，自动化过程有时不满足针对性能、功耗、信号完整性、制程产量、本地和外部信号路由两者(包括内部交叉耦合连接)、引脚访问等的每个规则。因此，设计人员手动地创建这些单元以实现多个特性的更好结果或者重写用于布局布线工具的规则。但是，许多时候，布局工具和规则仍无法在不消耗大量功率和占用大量裸片面积的情况下实现最终电路所必需的性能。
鉴于上述情况，需要用于创建标准单元布局的有效方法和***。
附图说明
图1是利用交叉场效应晶体管(FET)的标准单元布局的俯视图的概括图。
图2是利用交叉FET的标准单元布局的俯视图的概括图。
图3是利用交叉FET的标准单元布局的俯视图的概括图。
图4是利用交叉FET的标准单元布局的俯视图的概括图。
图5是利用交叉FET的标准单元布局的俯视图的概括图。
图6是布尔逻辑门原理图的概括图。
图7是利用交叉FET的布尔逻辑门的布局的俯视图的概括图。
图8是利用交叉FET的布尔逻辑门的布局的俯视图的概括图。
图9是利用交叉FET的布尔逻辑门的布局的俯视图的概括图。
图10是利用交叉FET的布尔逻辑门的布局的俯视图的概括图。
图11是多路复用器门的原理图的概括图。
图12是利用交叉FET的多路复用器门的布局的俯视图的概括图。
图13是利用交叉FET的多路复用器门的布局的俯视图的概括图。
图14是利用交叉FET的多路复用器门的布局的俯视图的概括图。
图15是用于有效地创建利用交叉FET的标准单元布局的方法的一个实施方案的概括图。
图16是具有使用利用交叉FET的标准单元的集成电路的计算***的概括图。
虽然本发明可以有各种修改和另选形式，但具体实施方案在附图中通过举例的方式示出并且在本文进行详细描述。然而，应当理解，附图和对其的详细描述并不旨在将本发明限制为所公开的特定形式，而是相反，本发明是涵盖落入由所附权利要求书限定的本发明范围内的所有修改、等效物和替代方案。
具体实施方式
在以下描述中，阐述了许多具体细节以提供对本发明的透彻理解。然而，本领域普通技术人员应认识到，可以在没有这些具体细节的情况下实践本发明。在一些情况下，未详细示出众所周知的电路、结构和技术，以避免模糊本发明。此外，应当理解，为了简单和清楚说明，图中所示的元件不一定按比例绘制。例如，一些元件的尺寸相对于其他元件被放大。
考虑了用于有效地创建存储位单元布局的***和方法。在各种实施方式中，一个或多个标准单元包括交叉场效应晶体管(FET)。如本文所用，“交叉FET”也称为“XFET”。另外，如本文所使用，“晶体管”也称为“半导体器件”或“器件”。在一些实施方式中，交叉FET是垂直堆叠的全环绕栅极(GAA)晶体管，例如顶部垂直GAA晶体管(或GAA晶体管)垂直地形成在底部GAA晶体管的顶部，两个GAA晶体管之间至少有隔离氧化物层。此外，顶部GAA晶体管具有一个或多个导电沟道，该一个或多个导电沟道的位置与底部GAA晶体管的一个或多个导电沟道正交。因此，顶部GAA晶体管通过一个或多个顶部沟道的电流流动方向与底部GAA晶体管的一个或多个底部沟道的电流流动方向正交。
顶部GAA晶体管的一个或多个顶部沟道的掺杂极性与底部GAA晶体管的一个或多个底部沟道的掺杂极性相反。例如，在实施方式中，顶部GAA晶体管包括一个或多个p型沟道，而底部GAA晶体管包括一个或多个n型沟道。在另一实施方式中，p型和n型极性在顶部GAA晶体管和底部GAA晶体管的一个或多个沟道之间相反。利用顶部GAA晶体管和底部GAA晶体管之间的正交方位，基于它们的方位，顶部和底部GAA晶体管两者都具有各自载流子的最大迁移率。
标准单元库包括至少两个不同高度的标准单元(或单元)。例如，第一单元包括具有不同掺杂极性的沟道的一对晶体管，该对晶体管接收两个不同输入信号。该对中第一掺杂极性的晶体管的栅极区长度大于该对中第二掺杂极性的晶体管的栅极区长度。在一个示例中，多路复用器的选择控制信号相对于n型器件的n型金属栅极沿垂直方向路由，致使n型金属栅极延伸，从而在多路复用器内创建必要连接。在该n型器件上方(或下方)形成的p型器件不接收选择控制信号。因此，在垂直堆叠的交叉FET内，两个器件接收不同输入信号。该单元的高度尺寸的增长大于不具有这种垂直堆叠器件的单元的高度。当特定垂直堆叠的交叉FET中的p型器件和n型器件中的每一者接收相同输入信号时，不必增加器件中任一者的栅极区长度。因此，单元库具有两个一般类别的单元。第一类单元包括器件，其中特定垂直堆叠中的两个器件中的每个器件接收相同输入信号。第二类单元包括器件，其中特定垂直堆叠中的两个器件接收不同输入信号。该第二类单元的高度尺寸大于该第一类单元。
现在转到图1，示出了使用交叉FET的标准单元布局100的俯视图的概括框图。标准单元布局100用于使用交叉FET的逆变器。但是，在其他实施方式中，用于标准单元布局100的特性和技术用于各种其他类型的布尔门和复合门。布局100附有p型和n型交叉FET的三维(3-D)图示。如图所示，p型器件垂直堆叠在n型器件上。n型器件至少包括在n型沟道104周围形成的n型栅极102。类似地，在p型沟道108周围形成p型栅极106。因此，p型沟道108的掺杂极性与底部n型器件的n型沟道104的极性相反。虽然示出了单个n型沟道104和单个p型沟道108，但在其他实施方式中，半导体器件包括其他数量的沟道。在一些实施方式中，沟道是横向纳米线。在其他实施方式中，沟道是纳米片。
n型沟道104和n型栅极102朝向p型沟道108和p型栅极106的正交方向。换句话说，n型沟道104和n型栅极102朝向与p型沟道108和p型栅极106的方向呈90度的方向。因此，底部n型器件通过n型沟道104的电流流动方向与顶部p型器件的p型沟道108的电流流动方向正交。利用顶部p型器件和底部n型器件之间的正交方位，基于它们的方位，该器件两者都具有各自载流子的最大迁移率。另外，顶部p型器件和底部n型器件的正交方位允许垂直堆叠的器件之间的连接使用单个过孔层。
在标准单元布局100中，金属零层(M0或Metal0)130是最顶层。栅极触点是下一垂直最高层，但为了便于说明，未示出栅极触点。p型栅极106是下一个垂直最高层，其次是p型纳米片108，其创建了p型沟道。绝缘层位于顶部p型器件和底部n型器件之间，绝缘层中的器件之间形成栅极触点。在标准单元布局100(或布局100)提供的空中俯视图中未示出该栅极触点。后续将提供标准单元布局的横截面图。垂直堆叠器件之间的栅极触点直接连接到p型金属栅极106和n型金属栅极102，无需穿过任何金属层。
p型器件的过孔(或触点)122将p型器件的漏极区连接到p型器件的局部互连件112。n型器件的过孔(或触点)120将n型器件的漏极区连接到n型器件的局部互连件110。布局100的垂直堆叠器件占用较少裸片上面积。单个过孔层的使用降低了电路的电阻和电容。与鳍式FET相比，全环绕栅极(GAA)纳米线或纳米片的使用降低了阈值电压，加快了开关时间，减少了漏电流，并进一步减少短沟道效应。除漏电流之外其他短沟道效应的示例有闩锁效应、漏致势垒降低效应(DIBL)、穿孔、性能对温度的依赖性、冲击电离以及与硅衬底和用于源极和漏极区的阱之间的寄生电容。
布局100中交叉FET的正交方位的一个优点包括单个过孔层。相反，互补FET(CFET)使用多个金属层和多个过孔层来在垂直堆叠器件之间进行连接。与CFET相比，访问交叉FET的底部器件的源极和漏极区更容易。布局100中交叉FET的正交位的另一优点是使用垂直堆叠器件中每个器件中的每个载流子的最大迁移率。
现在转到图2，示出了标准单元布局200的俯视图的概括框图。标准单元布局200用于使用交叉FET的2输入布尔NAND门。布局200附有p型和n型交叉FET的三维(3-D)图示。先前描述的触点(或过孔)、材料和结构编号相同。如图所示，n型器件垂直堆叠在p型器件上。类似于布局100，在其他实施方式中，布局200中交叉FET使用多个n型沟道104和多个p型沟道108。类似于布局100，布局200在n型沟道104与p型沟道108之间采用正交方位，并且使用单个过孔层在垂直堆叠器件之间创建连接。
与鳍式场效应晶体管(鳍式FET)相比，其中掺杂硅的鳍与硅衬底有物理接触，垂直GAA器件的沟道与硅衬底没有物理接触。通常，与鳍式FET相比时，GAA晶体管降低了阈值电压，加快了开关时间，减少了漏电流，并进一步减少短沟道效应。在一些实施方式中，GAA晶体管的掺杂硅的沟道是纳米线。在其他实施方式中，GAA晶体管的掺杂硅的沟道是纳米片。纳米片是掺杂硅的片，而不是掺杂硅的线。换句话说，纳米片是比横向纳米线更宽和更粗的线。纳米片还可以被认为是鳍，其被旋转并被放置在其垂直位于硅衬底上方的侧面上，使得纳米片不与硅衬底物理接触。相反，在纳米片和硅衬底之间形成金属栅极。但是，这种想象中没有描述用于形成纳米片的实际制造步骤。
在底部GAA晶体管的顶部垂直堆叠顶部GAA晶体管进一步提高了性能，降低了功耗，减小了由GAA晶体管占用的裸片面积，并进一步减少了短沟道效应。互补FET(CFET)包括垂直堆叠在底部GAA晶体管顶部的顶部GAA晶体管，两者之间至少具有氧化物层用于隔离。但是，CFET使用顶部GAA晶体管，该晶体管的一个或多个沟道与底部GAA晶体管的一个或多个沟道在相同方向对齐。然而，如前所示，交叉FET在顶部GAA晶体管的一个或多个沟道和底部GAA晶体管的一个或多个沟道之间具有正交方位。与互补FET相比，交叉FET对于顶部GAA晶体管和底部GAA晶体管中的每一者具有更好的迁移率，因此性能更高。互补FET使用两个金属层和三个过孔层在顶部GAA晶体管和底部GAA晶体管之间创建连接。相反，交叉FET利用单个金属层和单个过孔层连接顶部和底部GAA晶体管。交叉FET使用传统半导体制造步骤在第一晶圆中形成底部GAA晶体管，在第二晶圆中形成顶部GAA晶体管。第一晶圆和第二晶圆通过混合接合工艺彼此连接，这提高了产量。
在下面的描述中，图3至图5中示出了用于形成逆变器的布局技术。这些技术还用于形成六晶体管(6T)随机存取数据存储的存储位单元，该存储位单元在硅衬底上方占用了四个晶体管的平面面积。如图6所示，这种使用交叉FET的存储位单元被用于内存库中。图7至图15中示出了用于形成6T随机存取数据存储的存储位单元的布局技术。
现在转到图3，示出了标准单元布局300的俯视图的概括框图。右侧示出了布局300的俯视图，并且左侧示出了横截面图。对于该逆变器，p型器件垂直堆叠在n型器件上。但是，在其他实施方式中，可能会并且考虑到将n型器件垂直堆叠在p型器件上。逆变器的每个器件使用全环绕栅极(GAA)金属，该金属以360度方式包裹栅极区中的一个或多个纳米片。在第一晶圆上制造底部n型器件。在单独的第二晶圆上制造顶部p型器件，然后将第二晶圆接合到第一晶圆，如后文所述。
这里，在布局300中，在硅衬底302上沉积绝缘体上硅(SOI)氧化物层304。在各种实施方式中，SOI氧化物层304是二氧化硅(SiO2)层。半导体器件制造工艺构建局部绝缘体上硅(SOI)，使器件的主体与硅衬底302绝缘。在一个实施方式中，所形成的SOI氧化物层304较厚。在SOI氧化物层304上形成沟道堆叠。在一个实施方式中，沟道堆叠是n型纳米片306。沉积栅极金属材料308，随后通过CMP步骤抛光栅极金属308。在各种实施方式中，氮化钛(TiN)用于栅极金属308。栅极金属308以360度方式设置在n型纳米片306的周围。在栅极区周围沉积层间介质(ILD)氧化物层310。
形成n型源极和漏极区314。在一个实施方式中，n型源极和漏极区314是掺杂磷的外延生长硅。之后，形成n型局部互连件312。在一些实施方式中，n型局部互连件312包括钨、钴、钌或钼。在初始ILD氧化物310层上形成氮化硅层316和附加ILD氧化物310。例如，在ILD氧化物层310上沉积氮化硅(SiNx)层316。无定形氢化氮化硅(SiNx)的化学和电学性质使得这种材料成为集成电路中绝缘层的良好候选材料。蚀刻氮化物层316和ILD氧化物层310中的每一者，以便为栅极触点318创造空间。类似的，蚀刻氮化物层316和ILD氧化物层310中的每一者，以便为漏极触点320创造空间。在所创造的空间中沉积栅极触点318和漏极触点320。
参考图4，示出了标准单元布局400的俯视图的概括框图。先前描述的触点(或过孔)、材料和其他布局元素编号相同。右侧的标准单元布局400(或布局400)是在使用交叉FET的逆变器的布局300上执行的半导体处理步骤的延续。布局400也附有布局400中使用的半导体层的横截面图，并且在左侧示出该图。在ILD氧化物层310中的n型栅极触点318上方形成沟道堆叠。在一个实施方式中，沟道堆叠是p型纳米片402。在一些实施方式中，单独晶圆上生长了交替层，例如硅锗半导体外延生长层与硅半导体外延生长层交替。将具有交替层的单独晶圆接合到(图3)布局300的ILD氧化物层310的顶部。在其他实施方式中，交替层生长在布局300的ILD氧化物层310的顶部，随后采用先前提到的工艺之一将层蚀刻成p型纳米片402的大小。先前提到的工艺是针对形成n型纳米片306描述的。
现在转到图5，示出了标准单元布局500的俯视图的概括框图。先前描述的触点(或过孔)、材料和其他布局元素编号相同。右侧的标准单元布局500(或布局500)是在创建使用交叉FET的逆变器的布局400上执行的半导体处理步骤的延续。布局500也附有布局500中使用的半导体层的横截面图，并且在左侧示出该图。蚀刻ILD氧化物层310为p型栅极502创造空间，该栅极放置在p型纳米片402周围。类似地，蚀刻ILD氧化物层310，以便为漏极触点504创造空间。在所创造的空间中沉积栅极触点318和漏极触点504。此处，沉积金属零层(或metal0或Metal0或M0)506，为逆变器创建更多连接。注意，金属零层506也被称为不同的名称，以保持将金属零层用作水平层(例如在下一层中)的惯例。
转到图6，示出了布尔NAND逻辑门600的原理图的一个实施方式的概括框图。在所示的实施方式中，布尔NAND逻辑门600(或逻辑门600)接收指示为A 610和B 612的两个输入信号，并且产生指示为Out 620的输出信号。逻辑门600使用以并联配置连接的两个p型器件P1 602和P2 604。逻辑门600还使用以串联配置连接的两个n型器件N1 606和N2 608。逻辑门600是使用交叉FET的类型单元的晶体管原理图的示例，其中垂直堆叠器件接收相同输入信号。例如，p型器件P1 602和n型器件N1 606中的每一者接收输入信号A 610。类似地，p型器件P2 604和n型器件N2 608中的每一者接收输入信号B 612。
逻辑门600的半导体制造电路包括在同一垂直堆叠中的p型器件P1 602和n型器件N1 606。逻辑门600的半导体制造电路还包括在同一垂直堆叠中的p型器件P2 604和n型器件N2 608。对于每个垂直堆叠，相应的器件接收相同输入信号。因此，器件不必延伸栅极区来完成逻辑门600的制造电路的内部连接。逆变器和逻辑门600是这种类型的单元的几个示例中的两个示例。
如本文所用，布尔逻辑高电平也被称为逻辑高电平。相似地，布尔逻辑低电平也被称为逻辑低电平。在各种实施方式中，逻辑高电平等于电源参考电压电平，并且逻辑低电平等于接地参考电压电平。如本文所用，当电路节点或线存储电压电平，该电压电平启用接收到该电压电平的晶体管或该电压电平指示操作被启用时，该节点或线被“断言”。例如，当N型晶体管在其栅极端子上接收到正非零电压电平，该正非零电压电平是高于其源极端子上的电压电平的至少阈值电压时，N型晶体管被启用。
如本文所用，当电路节点或线存储电压电平，该电压电平禁用接收到该电压电平的晶体管时，该节点或线被“否定”。当n型晶体管在其栅极端子上接收到电压电平，该电压电平在其源极端子上的电压电平的阈值电压内时，n型晶体管被禁用。相似地，当p型晶体管在其栅极端子上接收到电压电平，该电压电平是低于其源极端子上的电压电平的至少阈值电压时，p型晶体管被启用。当p型晶体管在其栅极端子上接收到电压电平，该电压电平在其源极端子上的电压电平的阈值电压内时，p型晶体管被否定。另外，操作是基于对应的控制信号被断言或被否定来启用和禁用的。
当输入信号A 610和B 612中的任一者具有逻辑低电平时，启用p型器件P1 602和P2 604中的对应一者，并且为输出信号Out 620生成逻辑高电平。否则，当输入信号A 610和B 612两者均具有逻辑高电平时，n型器件N1 606和N2 608中的每一者被启用，并且为输出信号Out 620生成逻辑低电平。
在以下描述中，(图7)布局700描述了用于形成逻辑门600的n型器件的布局的步骤，而(图8至图10)布局800至布局1000描述了用于形成逻辑门600的p型器件的布局的步骤。先前描述的触点(或过孔)、材料和其他布局元素在图7至图10编号相同。现在转到图7，示出了逻辑门600的布局700的俯视图的概括框图。对于该布局，p型器件垂直堆叠在n型器件上。但是，在其他实施方式中，可能会并且考虑到将n型器件垂直堆叠在p型器件上。逆变器的每个器件使用全环绕栅极(GAA)金属，该金属以360度方式包裹栅极区中的一个或多个纳米片。在第一晶圆上制造底部n型器件。在单独的第二晶圆上制造顶部p型器件，然后将第二晶圆接合到第一晶圆，如后文所述。
这里，在图7的布局700中，针对(图6)逻辑门600的布局，以类似于前面针对逆变器描述的方式形成n型纳米片堆叠702、金属栅极704、n型局部互连件312和漏极触点320。在图8的布局800中，在n型栅极触点318上形成沟道堆叠，即p型纳米片402。在图9的布局900中，沉积p型栅极金属材料902。p型栅极金属902以360度方式设置在p型纳米片402的周围。在栅极区周围沉积层间介质(ILD)氧化物层310。
之后，形成p型局部互连件508。蚀刻氧化物层，并且在p型金属栅极902上方形成栅极触点318，在p型局部互连件508上方形成p型触点504。在图10的布局1000中，沉积金属零层(M0)506，用于为逻辑门600的布局创建进一步连接。随后制造该布局，并且逻辑门600为整个集成电路的一部分。注意，布局1000的金属栅极尚未被延伸以创建连接。但是，对于其他单元，这种延伸是必要的。
参考图11，示出了多路复用器门1100的原理图的一个实施方式的概括框图。在所示的实施方式中，多路复用器门1100(或mux门1100)接收指示为A 1150、B 1152和S1154的三个输入信号，并且产生指示为Z 1160的输出信号。mux门1100使用P5 1130和N5 1132作为逆变器，从接收的信号S1154产生信号SB 1156。mux门1100使用器件P6 1140和N6 1142作为逆变器，从接收的信号ZB 1160产生信号Z 1102。
P3 1114和N1 1120接收输入信号A 1150，器件P4 1116和N2 1122接收输入信号B1152，并且器件P1 1110和N4 1126接收输入信号S1154。另外，器件P2 1112和N3 1124接收内部产生的信号SB 1156。器件1110至器件1126以提供复用器功能的配置来连接。举例来说，当选择输入信号S1154被断言时，mux门1100在输出信号Z 1160上产生等同于输入信号B1152的当前逻辑电平的逻辑电平。当选择输入信号S1154被否定时，mux门1100在输出信号Z 1160上产生等同于输入信号A 1150的当前逻辑电平的逻辑电平。
mux门1100是使用交叉FET的类型单元的晶体管原理图的示例，其中垂直堆叠器件接收不同输入信号。举例来说，mux门1100的半导体制造电路包括在同一垂直堆叠中的p型器件P1 1110和n型器件N1 1120。如图所示，p型器件P1 1110接收信号S1154，而n型器件N11120接收不同的信号，例如信号A 1150。类似地，包括一对器件P2 1112和N2 1122的垂直堆叠接收不同输入信号。
同样地，包括一对器件P3 1114和N3 1124的垂直堆叠中的每一者接收不同信号，并且包括P4 1116和N4 1126的垂直堆叠接收不同信号。这种单元具有接收不同输入信号的器件的至少一个垂直堆叠，具有至少一个延伸的栅极区以完成所制造的电路的内部连接。因此，单元的高度尺寸增加到大于包括垂直堆叠的单元的高度，该堆叠中相应的器件接收相同输入信号。例如，mux门1100制造单元的高度大于逻辑门600制造单元的高度。
在以下描述中，(图12)布局1200提供用于形成(图11)mux门1100的n型器件的布局的技术，而(图13至图14)布局1300至布局1400提供用于形成mux门1100的p型器件的布局的技术。先前描述的触点(或过孔)、材料和其他布局元素在图12至图14编号相同。现在转到图12，示出了mux门1100的布局1200的俯视图的概括框图。对于该布局，p型器件垂直堆叠在n型器件上。但是，在其他实施方式中，可能会并且考虑到将n型器件垂直堆叠在p型器件上。
这里，在图12的布局1200中，针对(图11)mux门1100的布局，以类似于前面针对逆变器和逻辑门600描述的方式形成n型纳米片堆叠702、金属栅极704、n型局部互连件312、栅极触点318和漏极触点320。此处示出了用于n型器件的mux门1100中所使用的信号名称和器件名称，以帮助描述布局的形成。注意，器件N3 1124和N4 1126具有延伸的栅极区以完成mux门1100的制造电路的后续内部连接。
在图13的布局1300中，如上所述，形成p型纳米片402，沉积p型栅极金属材料902，并且形成p型局部互连件508。此处示出了用于p型器件的mux门1100中所使用的信号名称和器件名称，以帮助描述布局的形成。注意，一对器件N3 1124和P1 1110接收不同的输入，例如n型器件N3 1124的输入SB 1156和p型器件P1 1110的输入S1154。n型器件N3 1124的栅极区被延伸以完成mux门1100的制造电路的后续内部连接。还应注意，一对器件N4 1126和P21112接收不同的输入，例如n型器件N4 1126的输入S1154和p型器件P2 1112的输入SB1156。n型器件N4 1126的栅极区被延伸以完成mux门1100的制造电路的后续内部连接。在图14的布局1400中，沉积金属零层(M0)506和金属一层(M1)1402，用于为mux门1100的布局创建进一步连接。随后制造该布局，并且mux门1100为整个集成电路的一部分。
现在参考图15，示出了用于有效地创建利用交叉FET的标准单元布局的方法1500的一个实施方案。出于论述的目的，以顺序的次序示出此实施方案中的步骤。然而，在其他实施方案中，一些步骤以与所示不同的顺序发生，一些步骤同时执行，一些步骤与其他步骤组合，并且一些步骤不存在。
半导体制造工艺形成使用交叉FET的第一类型的单元，其中垂直堆叠的器件接收相同输入信号(框1502)。半导体制造工艺(或过程)形成使用交叉FET的第二类型的单元，其中至少一个垂直堆叠的器件接收不同输入信号(框1504)。该过程将第一类型和第二类型的单元放置在集成电路中(框1506)。如果未向集成电路的输入节点施加电位(条件框1508的“否”分支)，则集成电路等待上电(框1510)。但是，如果向集成电路的输入节点施加电位(条件框1510的“是”分支)，则集成电路将电流从输入节点经由两种类型的单元中的一者传送到输出节点(框1512)。
参考图16，示出了计算***1600的一个实施方案。计算***1600包括处理器1610和存储器1630。为了便于说明，未示出诸如存储器控制器、总线或通信织构、一个或多个锁相环(PLL)和其他时钟生成电路、功率管理单元等的接口。应当理解，在其他实施方式中，计算***1600包括与处理器1610相同类型或不同类型的其他处理器、一个或多个***设备、网络接口、一个或多个其他存储器设备等中的一者或多者。在一些实施方式中，计算***1600的功能结合在片上***(SoC)上。在其他实施方式中，计算***1600的功能结合在***母板中的***卡上。计算***1600用于多种计算设备诸如台式计算机、平板计算机、膝上型电脑、智能电话、智能手表、游戏控制台、个人助理设备等中的任一种计算设备中。
处理器1610包括硬件诸如电路。例如，处理器1610包括至少一个集成电路1620，该集成电路利用交叉FET来实现标准单元。例如，集成电路至少包括第一类单元1622，其中特定垂直堆叠中的两个器件中的每个器件接收相同输入信号。另一类单元1624包括特定垂直堆叠中的至少一对器件，其中该对中的每个器件接收不同输入信号。单元1624的高度尺寸大于单元1622，这是因为这对器件中晶体管的栅极区具有延伸栅极区，以完成对应单元内的内部连接。这些单元使用先前描述的布局技术。
在各种实施方式中，处理器1610包括一个或多个处理单元。在一些实施方式中，处理单元中的每个处理单元包括能够进行通用数据处理的一个或多个处理器内核以及相关联高速缓冲存储器子***。在这种实施方式中，处理器1610是中央处理单元(CPU)。在另一实施方式中，处理内核是计算单元，每个计算单元具有高度并行的数据微架构，该数据微架构具有多个并行执行道和相关联数据存储缓冲器。在这种实施方式中，处理器1610是图形处理单元(GPU)、数字信号处理器(DSP)或其他者。
在一些实施方式中，存储器1630包括硬盘驱动器、固态盘、其他类型的闪存、便携式固态驱动器、磁带驱动器等中的一者或多者。存储器1630存储操作***(OS)1632、由代码1634表示的一个或多个应用和至少源数据1636。存储器1630还能够存储由处理器1610在执行代码1634的特定应用时生成的中间结果数据和最终结果数据。尽管示出了单个操作***1632和代码1634和源数据1636的单个实例，但在其他实施方式中，在存储器1630中存储另一数量的这些软件组件。操作***1632包括用于发起处理器1610的启动、向硬件电路分配任务、管理计算***1600的资源以及托管一个或多个虚拟环境的指令。
处理器1610和存储器1630中的每一者包括用于彼此通信的接口单元以及包括在计算***1600中的任何其他硬件组件。接口单元包括用于为内存请求和内存响应提供服务的队列和用于基于特定通信协议彼此通信的控制电路。通信协议确定各种参数，例如电源电压电平、确定操作电源电压和操作时钟频率的功率性能状态、数据速率、一个或多个突发模式等。
应注意，上述实施方案中的一者或多者包括软件。在此类实施方案中，实施方法和/或机制的程序指令被输送或存储在计算机可读介质上。被配置为存储程序指令的许多类型的介质可用并且包括硬盘、软盘、CD-ROM、DVD、闪存、可编程ROM(PROM)、随机存取存储器(RAM)和各种其他形式的易失性或非易失性存储装置。一般而言，计算机可访问存储介质包括在使用期间能够由计算机访问以向计算机提供指令和/或数据的任何存储介质。例如，计算机可访问存储介质包括诸如磁性或光学介质，例如磁盘(固定或可移除)、磁带、CD-ROM或DVD-ROM、CD-R、CD-RW、DVD-R、DVD-RW或蓝光等存储介质。存储介质还包括易失性或非易失性存储介质，诸如RAM(例如，同步动态RAM(SDRAM)、双数据速率(DDR、DDR2、DDR3等)SDRAM、低功率DDR(LPDDR2等)SDRAM、Rambus DRAM(RDRAM)、静态RAM(SRAM)等)、能够经由***设备接口(诸如通用串行总线(USB)接口等)访问的ROM、闪存存储器、非易失性存储器(例如，闪存)。存储介质包括微电子机械***(MEMS)，以及能够经由诸如网络和/或无线链路的通信介质访问的存储介质。
另外，在各种实施方案中，程序指令包括在高级编程语言(诸如C)或设计语言(HDL)(诸如Verilog、VHDL或数据库格式(诸如GDS II流格式(GDSII))中的硬件功能的行为级描述或寄存器传输级(RTL)描述。在一些情况下，描述由合成工具读取，该合成工具合成描述以产生包括来自合成库的门列表的网表。网表包括门集，其也表示包括***的硬件的功能。然后将网表放置并穿设以产生描述待施加到掩码的几何形状的数据集。然后将掩码用于各种半导体制造步骤中以产生与***相对应的半导体电路或电路。另选地，计算机可访问存储介质上的指令是如所期望的网表(具有或不具有合成库)或数据集。另外地，该指令用于由如和Mentor/>的此类供应商的基于硬件的类型仿真器进行仿真的目的。
尽管已经相当详细地描述了以上实施方案，但是一旦完全了解上述公开内容，许多变型和修改对于本领域技术人员将变得显而易见。旨在将以下权利要求书解释为涵盖所有此类变型和修改。

Claims (20)

1.一种集成电路，包括：
第一单元，所述第一单元包括：
第一对晶体管，所述第一对晶体管具有不同掺杂极性的沟道，所述第一对晶体管被配置为通过所述第一对晶体管中的每个晶体管接收第一输入信号；和
第二对晶体管，所述第二对晶体管具有不同掺杂极性的沟道，所述第二对晶体管被配置为接收两个不同输入信号，其中所述第二对晶体管中的第一掺杂极性的晶体管的栅极区长度大于所述第一对晶体管中的第二掺杂极性的晶体管的栅极区长度；
其中响应于对所述集成电路的输入节点施加电位，电流通过所述第一单元从所述输入节点传送到所述集成电路的输出节点。
2.根据权利要求1所述的集成电路，其中所述第一对晶体管和所述第二对晶体管中不同于所述第一掺杂极性的第二掺杂极性的晶体管具有彼此物理连接的栅极区。
3.根据权利要求1所述的集成电路，其中所述第一对晶体管和所述第二对晶体管中的每一者占用单个晶体管在硅衬底上的面积。
4.根据权利要求3所述的集成电路，其中所述第一对晶体管包括：
第一晶体管，所述第一晶体管包括朝向第一方向的第一沟道；
氧化物层，所述氧化物层与所述第一晶体管相邻；和
第二晶体管，所述第二晶体管与所述氧化物层相邻，其中所述第二晶体管包括第二沟道，所述第二沟道朝向与所述第一方向正交的方向。
5.根据权利要求4所述的集成电路，其中：
沟道包括纳米片；并且
所述第一晶体管和所述第二晶体管中的每一者是垂直全环绕栅极(GAA)器件。
6.根据权利要求1所述的集成电路，还包括第二单元，所述第二单元包括：
第三对晶体管，所述第三对晶体管具有不同掺杂极性的沟道，所述第三对晶体管被配置为通过所述第三对晶体管中的每个晶体管接收第二输入信号；和
第四对晶体管，所述第四对晶体管具有不同掺杂极性的沟道，所述第四对晶体管被配置为通过所述第四对晶体管中的每个晶体管接收第三输入信号，其中所述第三对晶体管和所述第四对晶体管中的每个晶体管的栅极区长度相同。
7.根据权利要求6所述的集成电路，其中所述第一单元的高度大于所述第二单元的高度。
8.一种方法，包括：
在集成电路的第一单元中形成第一对晶体管，所述第一对晶体管具有不同掺杂极性的沟道，所述第一对晶体管被配置为通过所述第一对晶体管中的每个晶体管接收第一输入信号；
在所述第一单元中形成第二对晶体管，所述第二对晶体管具有不同掺杂极性的沟道，所述第二对晶体管被配置为接收两个不同输入信号，其中所述第二对晶体管中的第一掺杂极性的晶体管的栅极区长度大于所述第一对晶体管中的所述第二掺杂极性的晶体管的栅极区长度；
响应于对所述集成电路的输入节点施加电位，电流通过所述第一单元从所述输入节点传送到所述集成电路的输出节点。
9.根据权利要求8所述的方法，形成所述第一对晶体管和所述第二对晶体管中不同于所述第一掺杂极性的第二掺杂极性的晶体管，所述晶体管具有彼此物理连接的栅极区。
10.根据权利要求8所述的方法，还包括：形成所述第一对晶体管和所述第二对晶体管中的每一者，其具有单个晶体管在硅衬底上的面积。
11.根据权利要求10所述的方法，还包括：
在所述第一对晶体管中放置第一晶体管和第二晶体管；
形成所述第一晶体管，所述第一晶体管具有朝向第一方向的第一沟道；
形成氧化物层，所述氧化物层与所述第一晶体管相邻；以及
形成所述第二晶体管，所述第二晶体管与所述氧化物层相邻，其中所述第二晶体管包括第二沟道，所述第二沟道朝向与所述第一方向正交的方向。
12.根据权利要求11所述的方法，其中：
沟道包括纳米片；并且
所述第一晶体管和所述第二晶体管中的每一者是垂直全环绕栅极(GAA)器件。
13.根据权利要求8所述的方法，还包括：在所述集成电路的第二单元中形成：
第三对晶体管，所述第三对晶体管具有不同掺杂极性的沟道，所述第三对晶体管被配置为通过所述第三对晶体管中的每个晶体管接收第二输入信号；和
第四对晶体管，所述第四对晶体管具有不同掺杂极性的沟道，所述第四对晶体管被配置为通过所述第四对晶体管中的每个晶体管接收第三输入信号，其中所述第三对晶体管和所述第四对晶体管中的每个晶体管的栅极区长度相同。
14.根据权利要求13所述的方法，还包括：形成高度大于所述第二单元的高度的所述第一单元。
15.一种计算***，包括：
存储器，所述存储器被配置为存储一个或多个任务的指令和所述一个或多个任务要处理的源数据；
集成电路，所述集成电路被配置为使用所述源数据执行所述指令，其中所述集成电路包括：
第一单元，所述第一单元包括：
第一对晶体管，所述第一对晶体管具有不同掺杂极性的沟道，所述第一对晶体管被配置为通过所述第一对晶体管中的每个晶体管接收第一输入信号；和
第二对晶体管，所述第二对晶体管具有不同掺杂极性的沟道，所述第二对晶体管被配置为接收两个不同输入信号，其中所述第二对晶体管中的第一掺杂极性的晶体管的栅极区长度大于所述第一对晶体管中的第二掺杂极性的晶体管的栅极区长度；
其中响应于对所述集成电路的输入节点施加电位，电流通过所述第一单元从所述输入节点传送到所述集成电路的输出节点。
16.根据权利要求15所述的计算***，其中所述第一对晶体管和所述第二对晶体管中不同于所述第一掺杂极性的第二掺杂极性的晶体管具有彼此物理连接的栅极区。
17.根据权利要求16所述的计算***，其中所述第一对晶体管和所述第二对晶体管中的每一者占用单个晶体管在硅衬底上的面积。
18.根据权利要求17所述的计算***，其中所述第一对晶体管包括：
第一晶体管，所述第一晶体管包括朝向第一方向的第一沟道；
氧化物层，所述氧化物层与所述第一晶体管相邻；和
第二晶体管，所述第二晶体管与所述氧化物层相邻，其中所述第二晶体管包括第二沟道，所述第二沟道朝向与所述第一方向正交的方向。
19.根据权利要求18所述的计算***，其中：
沟道包括纳米片；并且
所述第一晶体管和所述第二晶体管中的每一者是垂直全环绕栅极(GAA)器件。
20.根据权利要求15所述的计算***，还包括第二单元，所述第二单元包括：
第三对晶体管，所述第三对晶体管具有不同掺杂极性的沟道，所述第三对晶体管被配置为通过所述第三对晶体管中的每个晶体管接收第二输入信号；和
第四对晶体管，所述第四对晶体管具有不同掺杂极性的沟道，所述第四对晶体管被配置为通过所述第四对晶体管中的每个晶体管接收第三输入信号，其中所述第三对晶体管和所述第四对晶体管中的每个晶体管的栅极区长度相同。
CN202280066199.0A 2021-09-29 2022-09-09 交叉场效应晶体管库单元架构设计 Pending CN118043966A (zh)

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