CN118041307A - Pulse generating circuit with temperature compensation function and adjustable pulse width - Google Patents
Pulse generating circuit with temperature compensation function and adjustable pulse width Download PDFInfo
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Abstract
The invention discloses a pulse generating circuit with temperature compensation function and adjustable pulse width, which belongs to the field of pulse generating circuits in digital-analog hybrid integrated circuits, and comprises a positive temperature coefficient reference current generating circuit and a negative temperature coefficient reference current generating circuit, wherein the output of the positive temperature coefficient reference current generating circuit and the output of the negative temperature coefficient reference current generating circuit are connected with the drain electrode of an MOS tube Q6 of a charge-discharge control switch circuit, and the output of an input control logic signal decoding circuit is respectively connected with the grid electrodes of an MOS tube Q2, an MOS tube Q3, an MOS tube Q4 and an MOS tube Q5 in a variable charge capacitor circuit; the input positive electrode of a comparator U1 in the comparator circuit is connected with the source electrode of the MOS tube Q6; the input end of the nor gate in the output nor gate logic circuit is connected with the output end of the comparator U1. The circuit counteracts the temperature coefficient of the capacitor by utilizing the temperature characteristic of the charging current, realizes the temperature compensation of the capacitor during charging, and simultaneously realizes the adjustment of pulse width by utilizing the programmable design of the charging capacitance value.
Description
Technical Field
The invention relates to the field of pulse generating circuits in digital-analog hybrid integrated circuits, in particular to a pulse generating circuit with a temperature compensation function and adjustable pulse width.
Background
In the digital-analog hybrid integrated circuit, a pulse generating circuit is required in circuits such as an asynchronous successive approximation type analog-digital converter, a time data converter, a pulse width modulation power supply controller, a full-bridge driving dead zone control time and the like, and the pulse width is expected to be unchanged in a wide temperature range, and the pulse width is adjustable according to different applications, so that the pulse generating circuit presents a serious challenge.
The pulse generation circuit commonly used at present is mainly divided into gate delay and trigger generation based on high-speed clock counting control. By adjusting the delay time of the input signal, the time when the trigger receives the pulse trigger is controlled, and finally, a pulse signal with a specific width can be obtained on the output of the trigger. In terms of pulse conditioning, the width of the output pulse can be adjusted by varying the duration of the input signal or the manner in which the delay is triggered. In digital circuits, the required time delay may be achieved by a delay chain, e.g. cascading a plurality of gates or using special delay devices.
The principle of the pulse generating circuit using high-speed clock counting is to generate a pulse signal using a high-frequency clock signal and a counter, count an input clock by the counter, and generate the pulse signal at a specific count value, thereby controlling the width of the pulse. The circuits are generally capable of providing higher accuracy and stability because they take advantage of the high-speed clock signal and the accurate counting capability of the counter. The preset value of the counter is adjusted to flexibly realize pulse output with different widths. But such circuits require high stability and accuracy of the clock signal. Any clock signal variations or instabilities may have an impact on the generation of the pulses. Meanwhile, if the phase of the clock signal is shifted or disturbed during counting, the time when the counter reaches the preset count value may deviate, and the accuracy of the pulse width may be affected.
The traditional pulse width generation circuit is generally realized by adopting a delay based on a digital gate circuit, and the generated pulse width has larger change along with temperature due to the temperature characteristic of the delay of the gate circuit; another pulse width generation circuit scheme based on high-speed clock counting requires a high-precision high-speed clock generation circuit, resulting in a large increase in the power consumption area of the system.
Disclosure of Invention
For the problems in the prior art, the invention adopts a scheme based on capacitor charge and discharge and a voltage comparator to realize a pulse generating circuit, and the temperature compensation and width adjustability of the pulse width are realized by the temperature compensation circuit and the variable capacitance circuit, so that the technical requirements of various application occasions are met at lower cost.
In order to achieve the above purpose, the present invention provides the following technical solutions:
the pulse generating circuit with the temperature compensation function and the pulse width adjustment comprises a positive temperature coefficient reference current generating circuit, a negative temperature coefficient reference current generating circuit, a variable charging capacitor circuit, an input control logic signal decoding circuit, a charge-discharge control switch circuit, a comparator circuit and an output NOR gate logic circuit;
the output end of the positive temperature coefficient reference current generating circuit outputs a signal Ierf _p;
the output end of the negative temperature coefficient reference current generating circuit outputs a signal Ierf _C;
The charge-discharge control switch circuit comprises a MOS tube Q1 and a MOS tube Q6;
The signal Ierf _p output by the positive temperature coefficient reference current generation circuit and the signal Ierf _c output by the negative temperature coefficient reference current generation circuit are connected with the drain electrode of the MOS transistor Q6 at the same time;
the grid electrode of the MOS tube Q6 is connected with the drain electrode of the MOS tube Q1, and the grid electrode of the MOS tube Q1 is connected with a pulse signal;
The variable charging capacitor circuit comprises a MOS tube Q2, a MOS tube Q3, a MOS tube Q4, a MOS tube Q5, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4 and a capacitor C5;
the source electrode of the MOS tube Q1 in the charge-discharge control switch circuit is connected with the source electrode of the MOS tube Q2, the source electrode of the MOS tube Q3, the source electrode of the MOS tube Q4 and the source electrode of the MOS tube Q5 at the same time;
the drain electrode of the MOS tube Q2 is connected with one end of a capacitor C1, and the other end of the capacitor C1 is connected with the source electrode of the MOS tube Q6 in the charge-discharge control switch circuit;
The drain electrode of the MOS tube Q3 is connected with one end of a capacitor C2, and the other end of the capacitor C2 is connected with the source electrode of the MOS tube Q6;
the drain electrode of the MOS tube Q4 is connected with one end of a capacitor C3, and the other end of the capacitor C3 is connected with the source electrode of the MOS tube Q6;
the drain electrode of the MOS tube Q5 is connected with one end of a capacitor C4, and the other end of the capacitor C4 is connected with the source electrode of the MOS tube Q6;
one end of a capacitor C5 is connected with the source electrode of the MOS tube Q6 in the charge-discharge control switch circuit, and the other end of the capacitor C5 is connected with the source electrode of the MOS tube Q1 in the charge-discharge control switch circuit;
The input control logic signal decoding circuit is a 2-4 decoder, the input of the input control logic signal decoding circuit is connected with 2 control bits, and the output of the input control logic signal decoding circuit is respectively connected with the grid electrode of the MOS tube Q2, the grid electrode of the MOS tube Q3, the grid electrode of the MOS tube Q4 and the grid electrode of the MOS tube Q5 in the variable charging capacitor circuit;
the comparator circuit comprises a resistor R1, a capacitor C6 and a comparator U1;
The input positive electrode of the comparator U1 is connected with the source electrode of the MOS tube Q6 in the charge-discharge control switch circuit;
The input cathode of the comparator U1 is connected with one end of a resistor R1, and the other end of the resistor R1 is connected with a reference voltage;
The output NOR gate logic circuit comprises a NOR gate, one input end of the NOR gate is connected with the output end of a comparator U1 in the comparator circuit, and the other input end of the NOR gate is connected with the grid electrode of a MOS tube Q6 in the charge-discharge control switch circuit; and outputting a required pulse signal by the NOR gate.
As a further scheme of the invention: the input negative electrode of the comparator U1 is connected with one end of a capacitor C6 at one end of a resistor R1, and the other end of the capacitor C6 is grounded.
As a further scheme of the invention: the positive temperature coefficient reference current generation circuit comprises a MOS tube Q7, a MOS tube Q8, a MOS tube Q9, a MOS tube Q10, a MOS tube Q11, a MOS tube Q12, a MOS tube Q13, a MOS tube Q14 and a resistor R2;
The source electrode and the grid electrode of the MOS tube Q7 are simultaneously connected with a reference voltage VDD;
the source electrode and the grid electrode of the MOS tube Q8 are simultaneously connected with the drain electrode of the MOS tube Q7, and the drain electrode of the MOS tube Q8 is grounded;
The grid electrode of the MOS tube Q9 is connected with the grid electrode of the MOS tube Q7, and the grid electrode of the MOS tube Q10 is connected with the grid electrode of the MOS tube Q8;
The source electrode of the MOS tube Q9 is connected with the drain electrode of the MOS tube Q10; the source of the MOS transistor Q10 is grounded.
As a further scheme of the invention: the drain electrode of the MOS tube Q9 is connected with one end of the resistor R2 and the grid electrode of the MOS tube Q12 at the same time;
The other end of the resistor R2 is connected with the source electrode of the MOS tube Q12 and the grid electrode of the MOS tube Q11 at the same time;
The drain electrode of the MOS tube Q12 is connected with the source electrode of the MOS tube Q11; the drain electrode of the MOS tube Q11 is connected with the source electrode of the MOS tube Q13; the drain electrode of the MOS tube Q13 is connected with the source electrode of the MOS tube Q14;
the grid electrode of the MOS tube Q13 is connected with the grid electrode of the MOS tube Q11; the grid electrode of the MOS tube Q14 is connected with the grid electrode of the MOS tube Q12;
the drain of MOS transistor Q14 outputs signal Ierf _p.
As a further scheme of the invention: the negative temperature coefficient reference current generation circuit comprises a MOS tube Q15, a MOS tube Q16, a MOS tube Q17, a MOS tube Q18, a MOS tube Q19, a resistor R3, a resistor R4, a resistor R5, an operational amplifier U2 and a capacitor C7;
one end of a resistor R3 is connected with a reference voltage source, and the other end of the resistor R3 is connected with the input anode of the operational amplifier U2;
The input cathode of the operational amplifier U2 is connected with one end of a resistor R5, and the other end of the resistor R5 is grounded;
the output end of the operational amplifier U2 is connected with the grid electrode of the MOS tube Q15, and the source electrode of the MOS tube Q15 is connected with the input cathode of the operational amplifier U2.
As a further scheme of the invention: the drain electrode of the MOS tube Q15 is connected with one end of the resistor R4 and the grid electrode of the MOS tube Q17 at the same time;
The other end of the resistor R4 is connected with the source electrode of the MOS tube Q17 and the grid electrode of the MOS tube Q16 at the same time;
The drain electrode of the MOS tube Q17 is connected with the source electrode of the MOS tube Q16; the drain electrode of the MOS tube Q16 is connected with the source electrode of the MOS tube Q18; the drain electrode of the MOS tube Q18 is connected with the source electrode of the MOS tube Q19;
The grid electrode of the MOS tube Q18 is connected with the grid electrode of the MOS tube Q16; the grid electrode of the MOS tube Q19 is connected with the grid electrode of the MOS tube Q17;
drain output Ierf _c of MOS transistor Q19.
As a further scheme of the invention: the input positive electrode of the operational amplifier U2 is connected with one end of a capacitor C7, and the other end of the capacitor C7 is grounded.
As a further scheme of the invention: the positive temperature coefficient reference voltage VDD input by the positive temperature coefficient reference current generating circuit is generated by a band gap reference circuit, the band gap reference circuit has a temperature coefficient, and the generated reference voltage can change along with the temperature change.
As a further scheme of the invention: the reference voltage source input by the negative temperature coefficient reference current generating circuit is from the feedback voltage of the band gap reference circuit or the system circuit, and the voltage source is input into the positive input end of the operational amplifier after passing through the filter circuit, wherein the resistor is a positive temperature coefficient resistor.
Compared with the prior art, the invention has the beneficial effects that:
The key technology of the invention is to counteract the temperature coefficient of the capacitor by utilizing the temperature characteristic of the charging current, and the function consists of a positive temperature coefficient reference current generating circuit and a negative temperature coefficient reference current generating circuit. The temperature coefficient of the capacitance causes the capacitance value to change with temperature. When the capacitance changes with temperature, the current generated by the positive temperature coefficient reference current source through the current mirror also changes, the two cancel each other, and the pulse width is expected to remain unchanged in a wide temperature range.
The circuit adopts a reference current source with adjustable temperature coefficient to charge the capacitor, the temperature coefficient of the capacitor is offset by utilizing the temperature characteristic of charging current, the temperature compensation of the capacitor is realized during charging, and the pulse width is adjustable by utilizing the programmable design of the charging capacitance value.
Drawings
Fig. 1 is a schematic circuit diagram of a pulse generating circuit with temperature compensation and pulse width adjustment according to an embodiment of the present disclosure.
Fig. 2 is a schematic circuit diagram of a positive temperature coefficient reference current generating circuit in a pulse generating circuit with temperature compensation and pulse width adjustment according to an embodiment of the present disclosure.
Fig. 3 is a schematic circuit diagram of a negative temperature coefficient reference current generating circuit in a pulse generating circuit with temperature compensation and pulse width adjustment according to an embodiment of the present disclosure.
The reference numerals in the drawings are: 1. a positive temperature coefficient reference current generation circuit; 2. a negative temperature coefficient reference current generation circuit; 3. a variable charge capacitance circuit; 4. an input control logic signal decoding circuit; 5. a charge-discharge control switch circuit; 6. a comparator circuit; 7. and an output nor gate logic circuit.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention; it will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be noted that, unless explicitly stated and limited otherwise, the terms "mounted," "provided," "connected," and "connected" are to be construed broadly; for example, the connection may be fixed connection, detachable connection, or integral connection, mechanical connection, electrical connection, direct connection, indirect connection via an intermediate medium, or communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
The invention discloses a pulse generating circuit with temperature compensation function and adjustable pulse width, which comprises a positive temperature coefficient reference current source generating circuit, a negative temperature coefficient reference current source generating circuit, a variable charging capacitor circuit, an input control logic signal decoding circuit, a charge-discharge control switch circuit, a comparator circuit, an output NOR gate circuit and the like. According to the invention, the reference current source with the adjustable temperature coefficient is used for charging the capacitor, the temperature coefficient of the capacitor is offset by utilizing the temperature characteristic of the charging current, the temperature compensation of the charging time is realized, and the pulse width is adjustable by utilizing the programmable design of the charging capacitor value. The pulse generating circuit with temperature compensation and adjustable pulse width, which is designed and realized by the invention, can be widely applied to chips such as an analog-to-digital converter, a time data converter, a power supply control pulse width modulation circuit, a full-bridge driving dead time control and the like.
According to the invention, the reference current source with the adjustable temperature coefficient is used for charging the capacitor, the temperature coefficient of the capacitor is offset by utilizing the temperature characteristic of the charging current, the temperature compensation of the charging time is realized, and the pulse width is adjustable by utilizing the programmable design of the charging capacitor value.
The invention aims to provide a pulse generating circuit with a temperature compensation function and adjustable pulse width, which can provide the characteristics of adjustable pulse width and stable pulse width in a full temperature range.
Referring to fig. 1-3, a pulse generating circuit with temperature compensation and pulse width adjustment includes a positive temperature coefficient reference current generating circuit 1, a negative temperature coefficient reference current generating circuit 2, a variable charge capacitor circuit 3, an input control logic signal decoding circuit 4, a charge/discharge control switch circuit 5, a comparator circuit 6 and an output nor gate logic circuit 7;
The positive temperature coefficient reference current generation circuit 1 comprises a MOS tube Q7, a MOS tube Q8, a MOS tube Q9, a MOS tube Q10, a MOS tube Q11, a MOS tube Q12, a MOS tube Q13, a MOS tube Q14 and a resistor R2;
the source electrode and the grid electrode of the MOS tube Q7 are simultaneously connected with a power supply VDD; the power supply VDD supplies power for the whole circuit, so that the circuit is convenient to use.
The source electrode and the grid electrode of the MOS tube Q8 are simultaneously connected with the drain electrode of the MOS tube Q7, and the drain electrode of the MOS tube Q8 is grounded;
The grid electrode of the MOS tube Q9 is connected with the grid electrode of the MOS tube Q7, and the grid electrode of the MOS tube Q10 is connected with the grid electrode of the MOS tube Q8;
The source electrode of the MOS tube Q9 is connected with the drain electrode of the MOS tube Q10; the source electrode of the MOS tube Q10 is grounded;
the drain electrode of the MOS tube Q9 is connected with one end of the resistor R2 and the grid electrode of the MOS tube Q12 at the same time;
The other end of the resistor R2 is connected with the source electrode of the MOS tube Q12 and the grid electrode of the MOS tube Q11 at the same time;
The drain electrode of the MOS tube Q12 is connected with the source electrode of the MOS tube Q11; the drain electrode of the MOS tube Q11 is connected with the source electrode of the MOS tube Q13; the drain electrode of the MOS tube Q13 is connected with the source electrode of the MOS tube Q14;
the grid electrode of the MOS tube Q13 is connected with the grid electrode of the MOS tube Q11; the grid electrode of the MOS tube Q14 is connected with the grid electrode of the MOS tube Q12;
the drain electrode of the MOS transistor Q14 is connected with the signal Ierf _p;
The negative temperature coefficient reference current generation circuit 2 comprises a MOS tube Q15, a MOS tube Q16, a MOS tube Q17, a MOS tube Q18, a MOS tube Q19, a resistor R3, a resistor R4, a resistor R5, an operational amplifier U2 and a capacitor C7;
one end of a resistor R3 is connected with a reference voltage source, and the other end of the resistor R3 is connected with the input anode of the operational amplifier U2;
one end of the capacitor C7 is connected with the input positive electrode of the operational amplifier U2, and the other end of the capacitor C7 is grounded;
The input cathode of the operational amplifier U2 is connected with one end of a resistor R5, and the other end of the resistor R5 is grounded;
the output end of the operational amplifier U2 is connected with the grid electrode of the MOS tube Q15, and the source electrode of the MOS tube Q15 is connected with the input cathode of the operational amplifier U2;
the drain electrode of the MOS tube Q15 is connected with one end of the resistor R4 and the grid electrode of the MOS tube Q17 at the same time;
The other end of the resistor R4 is connected with the source electrode of the MOS tube Q17 and the grid electrode of the MOS tube Q16 at the same time;
The drain electrode of the MOS tube Q17 is connected with the source electrode of the MOS tube Q16; the drain electrode of the MOS tube Q16 is connected with the source electrode of the MOS tube Q18; the drain electrode of the MOS tube Q18 is connected with the source electrode of the MOS tube Q19;
The grid electrode of the MOS tube Q18 is connected with the grid electrode of the MOS tube Q16; the grid electrode of the MOS tube Q19 is connected with the grid electrode of the MOS tube Q17;
the drain electrode of the MOS tube Q19 is connected with the signal Ierf _C;
the charge-discharge control switch circuit 5 comprises a MOS tube Q1 and a MOS tube Q6;
The signal Ierf _p output by the positive temperature coefficient reference current generating circuit 1 and the signal Ierf _c output by the negative temperature coefficient reference current generating circuit 2 are simultaneously connected with the drain electrode of the MOS transistor Q6,
The grid electrode of the MOS tube Q6 is connected with the drain electrode of the MOS tube Q1, and the grid electrode of the MOS tube Q1 is connected with a pulse signal;
the variable charging capacitor circuit 3 comprises a MOS tube Q2, a MOS tube Q3, a MOS tube Q4, a MOS tube Q5, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4 and a capacitor C5;
The source electrode of the MOS tube Q1 in the charge-discharge control switch circuit 5 is connected with the source electrode of the MOS tube Q2, the source electrode of the MOS tube Q3, the source electrode of the MOS tube Q4 and the source electrode of the MOS tube Q5,
The drain electrode of the MOS tube Q2 is connected with one end of a capacitor C1, and the other end of the capacitor C1 is connected with the source electrode of the MOS tube Q6 in the charge-discharge control switch circuit 5;
The drain electrode of the MOS tube Q3 is connected with one end of a capacitor C2, and the other end of the capacitor C2 is connected with the source electrode of the MOS tube Q6;
the drain electrode of the MOS tube Q4 is connected with one end of a capacitor C3, and the other end of the capacitor C3 is connected with the source electrode of the MOS tube Q6;
the drain electrode of the MOS tube Q5 is connected with one end of a capacitor C4, and the other end of the capacitor C4 is connected with the source electrode of the MOS tube Q6;
one end of a capacitor C5 is connected with the source electrode of the MOS tube Q6 in the charge-discharge control switch circuit 5, the other end of the capacitor C5 is connected with the source electrode of the MOS tube Q1 in the charge-discharge control switch circuit 5,
The input control logic signal decoding circuit 4 is a 2-4 decoder, the input of the input control logic signal decoding circuit 4 is connected with 2 control bits, and the output of the input control logic signal decoding circuit 4 is respectively connected with the grid electrode of the MOS tube Q2, the grid electrode of the MOS tube Q3, the grid electrode of the MOS tube Q4 and the grid electrode of the MOS tube Q5 in the variable charging capacitor circuit 3;
the comparator circuit 6 includes a resistor R1, a capacitor C6, and a comparator U1;
the input positive electrode of the comparator U1 is connected with the source electrode of the MOS tube Q6 in the charge-discharge control switch circuit 5;
The input cathode of the comparator U1 is connected with one end of a resistor R1 and one end of a capacitor C6 at the same time, the other end of the resistor R1 is connected with a reference voltage, and the other end of the capacitor C6 is grounded;
The output NOR gate logic circuit 7 comprises a NOR gate, one input end of the NOR gate is connected with the output end of the comparator U1 in the comparator circuit 6, and the other input end of the NOR gate is connected with the grid electrode of the MOS tube Q6 in the charge-discharge control switch circuit 5; and outputting a required pulse signal by the NOR gate.
The positive temperature coefficient reference current source input by the positive temperature coefficient reference current generating circuit 1 is generated by a band gap reference circuit. The bandgap reference circuit itself has a certain temperature coefficient, and the generated reference voltage will vary with temperature. The reference voltage generated by the band gap reference circuit is applied to a certain resistor to generate current, so that when the temperature rises, the current of the resistor increases, and a positive temperature coefficient current source is realized. The circuit implements a positive temperature coefficient reference current source of a desired magnitude for a portion of the charging current of the capacitor through a current mirror circuit.
The reference voltage source input by the negative temperature coefficient reference current generating circuit 2 can be from a feedback voltage of a band gap reference circuit or a system circuit, and the voltage source is input to a positive input end of an operational amplifier after passing through a filter circuit, wherein the resistor is a positive temperature coefficient resistor.
The variable charge capacitance circuit 3 is composed of a fixed capacitance and a variable capacitance section, and uses digital signal input to select capacitors of different capacitance values or change the working state of the capacitors so as to realize the programming of capacitance values. Wherein the capacitance has a positive temperature coefficient.
The input control logic signal decoding circuit 4 generates a plurality of control signals to control the switch of the capacitor through the input digital logic control signals, so that the circuit has different capacitance values under different signal inputs, and the adjustable output pulse width is realized.
The charge-discharge control switch circuit 5 is used for controlling the charge-discharge on and off of the capacitor, when the mos transistor is turned on, the input current can charge the capacitor of the variable capacitance region, and the time is the starting time of the output pulse width.
The comparator circuit 6 is configured to compare the capacitor charging voltage with an externally input reference voltage, and generate a closing time of the pulse width when the capacitor charging voltage is higher than the externally input voltage and the comparator output is high.
The nor gate logic 7 is used for logically combining the output of the comparator with an enable signal to generate the required pulse signal.
Temperature variations in the temperature compensation function can affect the performance of electronic components, particularly resistors, capacitors, and transistors. In the pulse generating circuit, if temperature variation is not considered, the pulse width may be affected by temperature fluctuation, resulting in unstable results.
By means of circuit design, the working parameters can be automatically adjusted to cope with temperature change, for example, a feedback mechanism or an automatic calibration function is adopted to realize automatic compensation.
The decoding circuit is used for converting the input code signals into corresponding output signals, and can map different input codes to specific outputs, and provides conversion and control functions for the digital circuit.
The key technology of the invention is to counteract the temperature coefficient of the capacitor by utilizing the temperature characteristic of the charging current, and the function consists of a positive temperature coefficient reference current generating circuit and a negative temperature coefficient reference current generating circuit. The temperature coefficient of the capacitance causes the capacitance value to change with temperature. When the capacitance changes with temperature, the current generated by the positive temperature coefficient reference current source through the current mirror also changes, the two cancel each other, and the pulse width is expected to remain unchanged in a wide temperature range.
Compared with the existing pulse generating circuit, the pulse generating circuit has the following advantages:
the circuit adopts a reference current source with adjustable temperature coefficient to charge the capacitor, the temperature coefficient of the capacitor is offset by utilizing the temperature characteristic of charging current, the temperature compensation of the capacitor is realized during charging, and the pulse width is adjustable by utilizing the programmable design of the charging capacitance value.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Accordingly, the embodiments are to be considered in all respects as illustrative and not restrictive. The scope of the invention is indicated by the appended claims rather than by the foregoing description, and all changes that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to the embodiments described in detail below, and that the embodiments described in the examples may be combined as appropriate to form other embodiments that will be apparent to those skilled in the art.
Claims (9)
1. The pulse generating circuit with the temperature compensation function and the adjustable pulse width is characterized by comprising a positive temperature coefficient reference current generating circuit (1), a negative temperature coefficient reference current generating circuit (2), a variable charging capacitor circuit (3), an input control logic signal decoding circuit (4), a charging and discharging control switch circuit (5), a comparator circuit (6) and an output NOR gate logic circuit (7);
The output end of the positive temperature coefficient reference current generating circuit (1) outputs a signal Ierf _p;
the output end of the negative temperature coefficient reference current generating circuit (2) outputs a signal Ierf _C;
The charge-discharge control switch circuit (5) comprises a MOS tube Q1 and a MOS tube Q6;
The signal Ierf _p output by the positive temperature coefficient reference current generation circuit (1) and the signal Ierf _c output by the negative temperature coefficient reference current generation circuit (2) are connected with the drain electrode of the MOS tube Q6 at the same time;
the grid electrode of the MOS tube Q6 is connected with the drain electrode of the MOS tube Q1, and the grid electrode of the MOS tube Q1 is connected with a pulse signal;
the variable charging capacitor circuit (3) comprises a MOS tube Q2, a MOS tube Q3, a MOS tube Q4, a MOS tube Q5, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4 and a capacitor C5;
the source electrode of the MOS tube Q1 in the charge-discharge control switch circuit (5) is connected with the source electrode of the MOS tube Q2, the source electrode of the MOS tube Q3, the source electrode of the MOS tube Q4 and the source electrode of the MOS tube Q5 at the same time;
The drain electrode of the MOS tube Q2 is connected with one end of a capacitor C1, and the other end of the capacitor C1 is connected with the source electrode of the MOS tube Q6 in the charge-discharge control switch circuit (5);
The drain electrode of the MOS tube Q3 is connected with one end of a capacitor C2, and the other end of the capacitor C2 is connected with the source electrode of the MOS tube Q6;
the drain electrode of the MOS tube Q4 is connected with one end of a capacitor C3, and the other end of the capacitor C3 is connected with the source electrode of the MOS tube Q6;
the drain electrode of the MOS tube Q5 is connected with one end of a capacitor C4, and the other end of the capacitor C4 is connected with the source electrode of the MOS tube Q6;
One end of a capacitor C5 is connected with the source electrode of the MOS tube Q6 in the charge-discharge control switch circuit (5), and the other end of the capacitor C5 is connected with the source electrode of the MOS tube Q1 in the charge-discharge control switch circuit (5);
The input control logic signal decoding circuit (4) is a 2-4 decoder, the input of the input control logic signal decoding circuit (4) is connected with 2 control bits, and the output of the input control logic signal decoding circuit (4) is respectively connected with the grid electrode of the MOS tube Q2, the grid electrode of the MOS tube Q3, the grid electrode of the MOS tube Q4 and the grid electrode of the MOS tube Q5 in the variable charging capacitor circuit (3);
the comparator circuit (6) comprises a resistor R1, a capacitor C6 and a comparator U1;
The input positive electrode of the comparator U1 is connected with the source electrode of the MOS tube Q6 in the charge-discharge control switch circuit (5);
The input cathode of the comparator U1 is connected with one end of a resistor R1, and the other end of the resistor R1 is connected with a reference voltage;
The output NOR gate logic circuit (7) comprises a NOR gate, one input end of the NOR gate is connected with the output end of the comparator U1 in the comparator circuit (6), and the other input end of the NOR gate is connected with the grid electrode of the MOS tube Q6 in the charge-discharge control switch circuit (5); and outputting a required pulse signal by the NOR gate.
2. The pulse generating circuit with temperature compensation and pulse width adjustment according to claim 1, wherein the input cathode of the comparator U1 is connected to one end of a capacitor C6 at one end of a resistor R1, and the other end of the capacitor C6 is grounded.
3. The pulse generating circuit with the temperature compensation function and the adjustable pulse width according to claim 2, wherein the positive temperature coefficient reference current generating circuit (1) comprises a MOS tube Q7, a MOS tube Q8, a MOS tube Q9, a MOS tube Q10, a MOS tube Q11, a MOS tube Q12, a MOS tube Q13, a MOS tube Q14 and a resistor R2;
The source electrode and the grid electrode of the MOS tube Q7 are simultaneously connected with a reference voltage VDD;
the source electrode and the grid electrode of the MOS tube Q8 are simultaneously connected with the drain electrode of the MOS tube Q7, and the drain electrode of the MOS tube Q8 is grounded;
The grid electrode of the MOS tube Q9 is connected with the grid electrode of the MOS tube Q7, and the grid electrode of the MOS tube Q10 is connected with the grid electrode of the MOS tube Q8;
The source electrode of the MOS tube Q9 is connected with the drain electrode of the MOS tube Q10; the source of the MOS transistor Q10 is grounded.
4. The pulse generating circuit with temperature compensation function and adjustable pulse width as claimed in claim 3, wherein the drain electrode of the MOS transistor Q9 is connected with one end of the resistor R2 and the gate electrode of the MOS transistor Q12 at the same time;
The other end of the resistor R2 is connected with the source electrode of the MOS tube Q12 and the grid electrode of the MOS tube Q11 at the same time;
The drain electrode of the MOS tube Q12 is connected with the source electrode of the MOS tube Q11; the drain electrode of the MOS tube Q11 is connected with the source electrode of the MOS tube Q13; the drain electrode of the MOS tube Q13 is connected with the source electrode of the MOS tube Q14;
the grid electrode of the MOS tube Q13 is connected with the grid electrode of the MOS tube Q11; the grid electrode of the MOS tube Q14 is connected with the grid electrode of the MOS tube Q12;
the drain of MOS transistor Q14 outputs signal Ierf _p.
5. The pulse generating circuit with the temperature compensation function and the adjustable pulse width according to claim 4, wherein the negative temperature coefficient reference current generating circuit (2) comprises a MOS tube Q15, a MOS tube Q16, a MOS tube Q17, a MOS tube Q18, a MOS tube Q19, a resistor R3, a resistor R4, a resistor R5, an operational amplifier U2 and a capacitor C7;
one end of a resistor R3 is connected with a reference voltage source, and the other end of the resistor R3 is connected with the input anode of the operational amplifier U2;
The input cathode of the operational amplifier U2 is connected with one end of a resistor R5, and the other end of the resistor R5 is grounded;
the output end of the operational amplifier U2 is connected with the grid electrode of the MOS tube Q15, and the source electrode of the MOS tube Q15 is connected with the input cathode of the operational amplifier U2.
6. The pulse generating circuit with temperature compensation function and adjustable pulse width according to claim 5, wherein the drain electrode of the MOS transistor Q15 is connected with one end of a resistor R4 and the gate electrode of the MOS transistor Q17 at the same time;
The other end of the resistor R4 is connected with the source electrode of the MOS tube Q17 and the grid electrode of the MOS tube Q16 at the same time;
The drain electrode of the MOS tube Q17 is connected with the source electrode of the MOS tube Q16; the drain electrode of the MOS tube Q16 is connected with the source electrode of the MOS tube Q18; the drain electrode of the MOS tube Q18 is connected with the source electrode of the MOS tube Q19;
The grid electrode of the MOS tube Q18 is connected with the grid electrode of the MOS tube Q16; the grid electrode of the MOS tube Q19 is connected with the grid electrode of the MOS tube Q17;
The drain of MOS transistor Q19 outputs signal Ierf _C.
7. The pulse generating circuit with temperature compensation and pulse width adjustment according to claim 6, wherein the input positive electrode of the operational amplifier U2 is connected with one end of a capacitor C7, and the other end of the capacitor C7 is grounded.
8. The pulse generating circuit with temperature compensation function and adjustable pulse width according to claim 7, wherein the reference voltage VDD input by the positive temperature coefficient reference current generating circuit (1) is generated by a band gap reference circuit, the band gap reference circuit has a temperature coefficient, and the generated reference voltage changes along with the temperature change.
9. The pulse generating circuit with temperature compensation function and adjustable pulse width according to claim 8, wherein the reference voltage source input by the negative temperature coefficient reference current generating circuit (2) is from the feedback voltage of the band gap reference circuit or the system circuit, and the voltage source is input to the positive input end of the operational amplifier after passing through the filter circuit, wherein the resistor is a positive temperature coefficient resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410228935.9A CN118041307A (en) | 2024-02-29 | 2024-02-29 | Pulse generating circuit with temperature compensation function and adjustable pulse width |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410228935.9A CN118041307A (en) | 2024-02-29 | 2024-02-29 | Pulse generating circuit with temperature compensation function and adjustable pulse width |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN118041307A true CN118041307A (en) | 2024-05-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410228935.9A Pending CN118041307A (en) | 2024-02-29 | 2024-02-29 | Pulse generating circuit with temperature compensation function and adjustable pulse width |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118041307A (en) |
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2024
- 2024-02-29 CN CN202410228935.9A patent/CN118041307A/en active Pending
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