CN118039678A

CN118039678A - Semiconductor device and method of forming the same

Info

Publication number: CN118039678A
Application number: CN202410082958.3A
Authority: CN
Inventors: 林政明; 温伟源; 廖思雅
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2023-01-26
Filing date: 2024-01-19
Publication date: 2024-05-14

Abstract

A dipole layer is formed over the semiconductor channel region. A doped gate dielectric layer is formed over the dipole layer. The doped gate dielectric layer comprises an amorphous material. By means of an annealing process, the amorphous material of the doped gate dielectric layer is converted into a material having at least a partial crystalline phase. After the doped gate dielectric layer is converted to a layer having a partial crystalline phase, a metal-containing gate electrode is formed over the doped gate dielectric layer. Embodiments relate to a semiconductor device and a method of forming the same.

Description

Semiconductor device and method of forming the same

Technical Field

Embodiments of the present application relate to semiconductor devices and methods of forming the same.

Background

The semiconductor Integrated Circuit (IC) industry has experienced an exponential growth. Technological advances in IC materials and design have resulted in multi-generation ICs, where each generation has smaller and more complex circuitry than the previous generation. During the development of ICs, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. Such scaled down processes generally provide benefits by improving production efficiency and reducing associated costs. This shrinking also increases the complexity of processing and manufacturing ICs. For example, high temperature processes during the formation of certain IC components may cause damage to other IC components. Thus, device performance may not be optimal.

Thus, while conventional methods of fabricating semiconductor devices have generally been adequate, they have not been satisfactory in all respects.

Disclosure of Invention

Some embodiments of the present application provide a semiconductor device including: an active region; a dipole layer disposed over the active region; a doped gate dielectric layer disposed over the dipole layer; and a metal-containing gate electrode disposed over the doped gate dielectric layer.

Further embodiments of the present application provide a semiconductor device including: a top-level transistor comprising a first gate structure, wherein the first gate structure comprises a first dipole layer and a first gate dielectric layer disposed over the first dipole layer, wherein the first gate dielectric layer is doped; and a bottom layer transistor vertically bonded to the top layer transistor, wherein the bottom layer transistor comprises a second gate structure, wherein the second gate structure comprises a second gate dielectric layer and a second dipole layer disposed over the second gate dielectric layer, and wherein the first dipole layer and the second dipole layer have different material compositions.

Still further embodiments of the present application provide a method of forming a semiconductor device, comprising: forming a dipole layer over the semiconductor channel region; forming a doped gate dielectric layer over the dipole layer, wherein the doped gate dielectric layer comprises an amorphous material; converting the amorphous material into a material having at least a partial crystalline phase by an annealing process; and forming a metal-containing gate electrode over the doped gate dielectric layer after the converting.

Drawings

The disclosed embodiments are best understood from the following detailed description when read with the accompanying drawing figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A is a perspective view of an IC device in the form of a FinFET in accordance with aspects of an embodiment of the present disclosure.

Fig. 1B is a top plan view of an IC device in the form of a FinFET in accordance with aspects of an embodiment of the present disclosure.

Fig. 1C is a perspective view of an IC device in the form of a GAA device in accordance with aspects of embodiments of the present disclosure.

Fig. 2-6 are cross-sectional side views illustrating a first dipole method of forming a gate structure according to aspects of embodiments of the present disclosure.

Fig. 7A-7B are graphs illustrating dipole distributions based on locations within a gate structure according to aspects of embodiments of the present disclosure.

Fig. 8-18 are cross-sectional side views illustrating a process flow of forming a CFET device according to aspects of embodiments of the present disclosure.

Fig. 19 is a block diagram of a manufacturing system in accordance with aspects of an embodiment of the present disclosure.

Fig. 20 is a flowchart illustrating a method of manufacturing a semiconductor device according to aspects of an embodiment of the present disclosure.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure embodiments. These are, of course, merely examples and are not intended to limit the disclosed embodiments. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Furthermore, in the embodiments of the present disclosure below, forming a component on another component, forming a component connected to and/or coupled to another component may include embodiments in which the components are formed in direct contact, and may also include embodiments in which additional components may be formed between the components such that the components may not be in direct contact. Further, spatially relative terms such as "lower," "upper," "horizontal," "vertical," "above …," "above …," "below …," "below …," "upward," "downward," "top," "bottom," and the like, and derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.) are used to facilitate understanding of the relationship of one component to another in embodiments of the disclosure. Spatially relative terms are intended to encompass different orientations of the device comprising the component. Furthermore, when values or ranges of values are described using "about," "approximately," etc., the term is intended to encompass values within a reasonable range including values, such as within +/-10% of the described value or other values as would be understood by one of skill in the art. For example, the term "about 5nm" encompasses a size range from 4.5nm to 5.5 nm.

Embodiments of the present disclosure relate generally to semiconductor devices and, more particularly, to Field Effect Transistors (FETs), such as three-dimensional fin-FET (FinFET) or full-gate-all-around (GAA) devices. In this regard, the FinFET device is a fin field effect transistor device and the GAA device is a multi-channel field effect transistor device. Recently, both FinFET devices and GAA devices have become increasingly popular in the semiconductor industry because they offer several advantages over conventional Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices (e.g., a "planar" transistor device). These advantages may include better chip area efficiency, improved carrier mobility, and fabrication processes compatible with those of planar devices. Thus, it may be desirable to design an Integrated Circuit (IC) chip using FinFET devices or GAA devices for a portion of the IC chip or the entire IC chip. For example, a Complementary Field Effect Transistor (CFET) may bond together the top layer device and the bottom layer device, wherein the top layer device and/or the bottom layer device may be implemented as GAA devices or FinFET devices.

However, while advantages are provided by FinFET devices and/or GAA devices, certain challenges may still exist in IC applications implementing FinFET or GAA devices, including in CFET devices. For example, conventional threshold voltage (Vt) adjustment may be accomplished by a dipole-driving method that is implemented using relatively high temperatures (e.g., greater than about 700 degrees Celsius) to provide a sufficient Vt adjustment range. However, temperatures above about 500 degrees celsius are typically not allowed for top-level device fabrication in a sequential CFET architecture, as this may affect the electrical performance (e.g., vt drift, ion degradation, etc.) of the underlying devices. Furthermore, in existing CFET schemes, the high-k (HK) material is predominantly amorphous. Amorphous high-k materials may not achieve a sufficiently high dielectric constant. Therefore, device performance is not optimized.

To address the problems discussed above, embodiments of the present disclosure implement a dipole material by a first dipole approach, which eliminates the need for a later-implemented high temperature (e.g., at about 700 degrees celsius or greater than about 700 degrees celsius) dipole driving process. In some embodiments, the dipole material may include yttrium oxide (Y ₂O₃). In other embodiments, the dipole material may include scandium oxide (Sc ₂O₃). As will be discussed in more detail below, the first dipole scheme forms a dipole material prior to the high-k gate dielectric layer. Because the high Wen Ouji drive-in process need not be performed, the potential adverse impact on the underlying devices of the CFET is reduced. Furthermore, embodiments of the present disclosure form a doped high-k gate dielectric layer (e.g., an yttrium doped high-k gate dielectric layer) over the dipole layer. The doped high-k gate dielectric layer may at least partially achieve a crystalline phase (e.g., cubic or tetragonal phase) in response to the annealing process. The crystalline phase provides a greater value of dielectric constant for the high-k gate dielectric layer of the presently disclosed embodiments as compared to the amorphous gate dielectric layer in conventional implementations. The increased dielectric constant values herein result in improved device performance.

Fig. 1A-1C will describe the basic structure of an exemplary FinFET and GAA device. Referring now to fig. 1A and 1B, a three-dimensional perspective view and a top view, respectively, of a portion of an Integrated Circuit (IC) device 90 are shown. IC device 90 may be an intermediate device or portion thereof fabricated during processing of the IC that may include Static Random Access Memory (SRAM) and/or other logic circuitry, passive components such as resistors, capacitors, and inductors, and active components such as p-type FETs (PFETs), n-type FETs (NFETs), finfets, metal Oxide Semiconductor Field Effect Transistors (MOSFETs), complementary Metal Oxide Semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, and/or other memory cells. Embodiments of the present disclosure are not limited to any particular number of devices or device regions or to any particular device configuration unless otherwise stated. For example, while IC device 90 is shown as a three-dimensional FinFET device, the concepts of the embodiments of the present disclosure may also be applied to planar FET devices or GAA devices.

Referring to fig. 1a, an ic device 90 includes a substrate 110. The substrate 110 may include: elemental (single-element) semiconductors such as silicon, germanium, and/or other suitable materials; compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonide, and/or other suitable materials; alloy semiconductors such as SiGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP, gaInAsP and/or other suitable materials. The substrate 110 may be a single layer of material having a uniform composition. Alternatively, the substrate 110 may include multiple material layers having similar or different compositions suitable for IC device fabrication. In one example, the substrate 110 may be a silicon-on-insulator (SOI) substrate having a semiconductor silicon layer formed on a silicon oxide layer. In another example, the substrate 110 may include a conductive layer, a semiconductor layer, a dielectric layer, other layers, or a combination thereof. Various doped regions, such as source/drain regions, may be formed in or on the substrate 110. The doped regions may be doped with an n-type dopant (such as phosphorus or arsenic) and/or a p-type dopant (such as boron), depending on design requirements. The doped regions may be formed directly on the substrate 110 in a p-well structure, an n-well structure, a double-well structure, or using a raised structure. The doped regions may be formed by implantation of dopant atoms, in-situ doped epitaxial growth, and/or other suitable techniques.

A three-dimensional active area 120 is formed on a substrate 110. Active region 120 is an elongated fin structure that protrudes upward beyond substrate 110. Accordingly, the active region 120 may be interchangeably referred to hereinafter as the fin structure 120. Fin structure 120 may be fabricated using suitable processes including photolithography and etching processes. The photolithographic process may include: forming a photoresist layer over the substrate 110; exposing the photoresist to a pattern; performing a post-exposure baking process; and developing the photoresist to form a masking element (not shown) comprising a resist. A recess is then etched into the substrate 110 using the masking element, leaving a fin structure 120 on the substrate 110. The etching process may include dry etching, wet etching, reactive Ion Etching (RIE), and/or other suitable processes. In some embodiments, fin structure 120 may be formed by a double patterning or multiple patterning process. Typically, double patterning or multiple patterning processes combine photolithography and self-aligned processes, allowing creation of patterns with, for example, smaller pitches than are obtainable using single, direct photolithography processes. As an example, a layer may be formed over a substrate and patterned using a photolithographic process. Spacers are formed alongside the patterned layer using a self-aligned process. This layer is then removed and then the remaining spacers or mandrels can be used to pattern fin structure 120.

IC device 90 also includes source/drain features 122 formed over fin structure 120. Source/drain features 122 may include an epitaxial layer epitaxially grown on fin structure 120. IC device 90 also includes an isolation structure 130 formed over substrate 110. Isolation structures 130 electrically separate the various components of IC device 90. Isolation structures 130 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine doped silicate glass (FSG), low-k dielectric materials, and/or other suitable materials. In some embodiments, the isolation structure 130 may include Shallow Trench Isolation (STI) features. In one embodiment, isolation structures 130 are formed by etching trenches into substrate 110 during formation of fin structures 120. The trenches may then be filled with the isolation material described above, followed by a Chemical Mechanical Planarization (CMP) process. Other isolation structures such as field oxide, local oxidation of silicon (LOCOS), and/or other suitable structures may also be implemented as isolation structure 130. Alternatively, the isolation structure 130 may comprise a multi-layer structure, for example, with one or more thermal oxide liner layers.

The IC device 90 also includes a gate structure 140 formed on three sides in the channel region of each fin 120 and engaging the fin structure 120 on three sides in the channel region of each fin 120. Gate structures 140 may be dummy gate structures (e.g., comprising an oxide gate dielectric and a polysilicon gate electrode), or they may be HKMG structures comprising a high-k gate dielectric and a metal gate electrode, wherein HKMG structures are formed by replacing dummy gate structures. Although not depicted herein, gate structure 140 may include additional layers of material, such as an interfacial layer, a capping layer, other suitable layers, or a combination thereof, over fin structure 120.

Referring to fig. 1B, the plurality of fin structures 120 are longitudinally oriented in the X-direction and the plurality of gate structures 140 are longitudinally oriented in the Y-direction, i.e., generally perpendicular to the fin structures 120. In many embodiments, IC device 90 includes additional components such as gate spacers disposed along sidewalls of gate structure 140, a hard mask layer disposed over gate structure 140, and many other components.

It should also be appreciated that aspects of the embodiments of the present disclosure discussed below may be applicable to multi-channel devices, such as full-gate-all-around (GAA) devices. Fig. 1C shows a three-dimensional perspective view of an exemplary GAA device 150. For consistency and clarity reasons, similar components in fig. 1C and 1A-1B will be labeled the same. For example, an active region such as fin structure 120 protrudes vertically upward in the Z-direction out of substrate 110. The isolation structures 130 provide electrical separation between the fin structures 120. Gate structure 140 is located over fin structure 120 and over isolation structure 130. Mask 155 is located over gate structure 140 and gate spacers 160 are located on sidewalls of gate structure 140. A capping layer 165 is formed over fin structure 120 to protect fin structure 120 from oxidation during formation of isolation structure 130.

A plurality of nanostructures 170 are disposed over each of the fin structures 120. The nanostructures 170 may comprise nanoplates, nanotubes or nanowires, or some other type of nanostructure that extends horizontally in the X-direction. The portion of the nanostructure 170 that underlies the gate structure 140 may serve as a channel for the GAA device 150. Dielectric internal spacers 175 may be disposed between nanostructures 170. Furthermore, although not shown for simplicity reasons, each of the nanostructures 170 may be circumferentially surrounded by a gate dielectric as well as a gate electrode. In the illustrated embodiment, the portion of the nanostructure 170 that is located outside of the gate structure 140 may be used as source/drain features of the GAA device 150. In some embodiments, however, continuous source/drain features may be epitaxially grown over portions of fin structure 120 that are outside of gate structure 140. Regardless, conductive source/drain contacts 180 may be formed over the source/drain features to provide electrical connection to the source/drain features. An interlayer dielectric (ILD) 185 is formed over the isolation structure 130 and around the gate structure 140 and the source/drain contacts 180.

Whether the transistors of the IC are implemented as finfets of fig. 1A-1B or GAA devices of fig. 1C, it should be understood that they may benefit from the concepts of the embodiments of the present disclosure, as discussed in more detail below.

Fig. 2-6 are a series of schematic partial cross-sectional side views illustrating an exemplary process flow for fabricating exemplary gate structures 200A and 200B in accordance with an embodiment of the present disclosure. As a non-limiting example, gate structure 200A corresponds to an N-type transistor having a high threshold voltage (Vt), while gate structure 200B corresponds to an N-type transistor having a low threshold voltage. In other words, gate structure 200A is associated with a higher threshold voltage than gate structure 200B. Thus, gate structure 200A may belong to an H-NVt (high threshold voltage NFET) device, while gate structure 200B may belong to an L-NVt (low threshold voltage NFET) device. In some embodiments, the H-NVt device and the L-NVt device may be formed on the same wafer. For example, they may be formed as different circuit components on the same IC. In other embodiments, the H-NVt device and the L-NVt device may be formed on different wafers, e.g., as circuit components of different ICs.

Referring now to fig. 2, gate structures 200A and 200B are formed over active regions 120A and 120B, respectively. Active regions 120A and 120B may be embodiments of active region 120 discussed above with reference to fig. 1C. For example, the active regions 120A and 120B may include vertically protruding fin structures of FinFET or GAA devices. In some embodiments, active regions 120A and 120B may include portions corresponding to channel regions of transistors. In some embodiments, the channel region may include a III-V compound. In this regard, the group III-V compounds include elements from group III of the periodic Table and elements from group V of the periodic Table.

An Interface Layer (IL) 210A and an interface layer 210B are formed over active regions 120A and 120B, respectively. In some embodiments, interface layers 210A and 210B include III-V based oxides.

Dipole layer 220A and dipole layer 220B are formed over interface layers 210A and 210B, respectively. In the illustrated embodiment, dipole layers 220A and 220B function as dipole sources for threshold voltage drift. Conventionally, lanthanum-containing materials (such as lanthanum oxide) can be used as dipole sources for threshold voltage drift. Lanthanum oxide has relatively strong threshold voltage drift characteristics, which may be well suited for conventional dipole layer designs, because conventional dipole layers are formed over high-k gate dielectric layers in a "back dipole" approach. In other words, the high-k gate dielectric layer (and the interfacial layer, if implemented) separates the conventional dipole layer from the active region (where the active region is located below the high-k gate dielectric layer), and the strong threshold voltage drift characteristics of lanthanum oxide can compensate for the distance corresponding to the thickness of the high-k gate dielectric layer.

However, according to the process flow of embodiments of the present disclosure, dipole layers 220A and 220B are formed prior to forming the gate dielectric layer. In other words, the dipole layer is formed "first" in a "first dipole" process flow. This means that the dipole layers 220A and 220B herein are closer to the underlying active regions 120A and 120B because they are separated from the active regions 120A and 120B by the interface layers 210A and 210B rather than by the high-k gate dielectric layers. Thus, if lanthanum oxide is still used to implement dipole layers 220A and 220B, the threshold voltage shift will be greater than the desired threshold voltage shift. Accordingly, the embodiments of the present disclosure implement the dipole layers 220A and 220B using a material having a weaker threshold voltage drift characteristic than lanthanum oxide. In some embodiments, dipole layers 220A and 220B are implemented using yttrium oxide (Y ₂O₃). In other embodiments, the dipole layers 220A and 220B are implemented using scandium oxide (Sc ₂O₃).

The dipole layers 220A and 220B may be formed by a suitable deposition process, such as Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or combinations thereof. The deposition process is performed such that dipole layer 220A has a thickness 230A and dipole layer 220B has a thickness 230B. Thicknesses 230A and 230B are each in a range between about 0.1 nanometers (nm) and about 1 nm. But as shown in fig. 2, thickness 230B is greater than thickness 230A. The reason why the thickness 230B is configured to be greater than the thickness 230A is to take into account the fact that the threshold voltage for the gate structure 200B is lower than the threshold voltage for the gate structure 200A.

Referring now to fig. 3, one or more deposition processes 240 are performed to form a gate dielectric layer 250A and a gate dielectric layer 250B over dipole layers 220A and 220B, respectively. In various embodiments, the deposition process may include CVD or ALD. The deposition process 240 is performed such that the gate dielectric layer 250A has a thickness 260A and the gate dielectric layer 250B has a thickness 260B. In some embodiments, thicknesses 260A and 260B are each thicker than respective thicknesses 230A and 230B of dipole layers 220A and 220B. For example, thicknesses 260A and 260B may be in a range between about 1nm and about 5 nm.

The gate dielectric layers 250A and 250B comprise a high-k dielectric material that is a dielectric material having a dielectric constant greater than that of silicon dioxide. In some embodiments, gate dielectric layers 250A and 250B comprise hafnium oxide. In other embodiments, gate dielectric layers 250A and 250B comprise zirconium oxide.

In some embodiments, gate dielectric layers 250A and 250B are also doped with dopants. For example, the gate dielectric layers 250A and 250B may be doped with yttrium. The implementation of the dopant material in the gate dielectric layers 250A and 250B may be accomplished by tuning the deposition process 240. For example, referring now to fig. 4, deposition process 240 may utilize multiple deposition cycles to form gate dielectric layers 250A and/or 250B. In more detail, the deposition process 240 may include M number of repeated cycles, wherein each cycle of the M number of cycles includes the following cycles:

N number of sub-layers of undoped high-k dielectric material 252 are deposited using N number of cycles; and

A1 cycle is used to deposit a dopant-containing material 254, such as yttria, over the uppermost undoped high-k dielectric material 252.

As a simplified example, assume that the value N has a value of 10. In this case, 10 deposition process cycles (e.g., CVD or ALD) are performed to form 10 sub-layers of high-k dielectric material 252, which may be undoped initially. As discussed above, in some embodiments, the high-k dielectric material 252 may comprise hafnium oxide, or in some other embodiments, zirconium oxide. After depositing the 10 th layer of undoped high-k dielectric material 252, another deposition process (e.g., CVD or ALD) is performed to deposit a sub-layer of dopant-containing material 254 (e.g., yttrium-containing material such as yttrium oxide) on the 10 th sub-layer of undoped high-k dielectric material 252. At this time, a structure including 10 sub-layers of undoped high-k dielectric material 252 and 1 sub-layer of dopant-containing material 254 is formed by a single cycle of M number of cycles.

The above process may be repeated M number of times to form a composite structure comprising M number of repeating stacks, wherein each of the repeating stacks comprises 10 sub-layers of high-k dielectric material 252 and 1 sub-layer of dopant-containing material 254. In this manner, the resulting gate dielectric layer 250A/250B includes a high-k dielectric material 252 and a dopant-containing material 254.

It should be appreciated that the values of M and N may be flexibly configured in various embodiments to accommodate design requirements and/or manufacturing requirements. For example, the greater the value of N, the lower the dopant concentration in the final gate dielectric layer 250A/250B. This is because as N increases, gate dielectric layer 250A/250B will contain more sub-layers of high-k dielectric material while dopant-containing material 254 remains constant (because 1 sub-layer of dopant-containing material 254 is deposited for every N number of sub-layers of high-k dielectric material 252). In other words, the value of N may be configured to adjust the concentration level of dopants (e.g., yttria) in the gate dielectric layers 250A/250B. Meanwhile, the total thickness of the gate dielectric layer 250A/250B (e.g., thickness 260A/260B in FIG. 3) is determined by the value of M. For example, as the value of M increases, the gate dielectric layer 250A/250B will become thicker and vice versa.

It should also be appreciated that there may not be a clear line of demarcation between the high-k dielectric material 252 and the dopant-containing material 254 in the final structure of the gate dielectric layer 250A/250B. For example, dopants (e.g., yttria) from the dopant-containing material 254 can diffuse into one or more sub-layers of the underlying high-k dielectric material 252. For simplicity reasons, this diffusion is not specifically shown herein.

During this fabrication stage, gate dielectric layers 250A and 250B are amorphous, which results in a lower than optimal dielectric constant value. To increase the value of the dielectric constant, an annealing process will be performed to at least partially convert the amorphous material to a material having a crystalline phase, such that the gate dielectric layers 250A and 250B may achieve a higher value of the dielectric constant. This is shown in fig. 5, wherein an annealing process 280 is performed to at least partially convert the amorphous material of gate dielectric layers 250A and 250B to a crystalline material. In such a conversion process, the dopant-containing material 254 (e.g., yttria) will help stabilize the crystalline phase of the high-k dielectric material 252 (e.g., hafnium oxide or zirconium oxide) in the gate dielectric layers 250A and 250B.

In embodiments where gate dielectric layers 250A and 250B include hafnium oxide, annealing process 280 converts at least a portion of the amorphous hafnium oxide material into a crystalline hafnium oxide material having a cubic phase. In embodiments where the gate dielectric layers 250A and 250B include zirconia, the annealing process 280 converts at least a portion of the amorphous zirconia material to a crystalline zirconia material having a tetragonal phase.

Regardless of the material composition and/or crystalline phase of the gate dielectric layers 250A and 250B (after the annealing process 280 has been performed), it should be appreciated that one benefit of the crystalline phase of the gate dielectric layers 250A and 250B is that they produce a greater dielectric constant (compared to the amorphous material of the gate dielectric layers 250A and 250B). The larger dielectric constant of gate dielectric layers 250A and 250B translates into improved performance, e.g., ease of scaling of Equivalent Oxide Thickness (EOT).

In some embodiments, the annealing process 280 is performed with a temperature less than 500 degrees celsius, for example, in a range between about 400 degrees celsius and about 500 degrees celsius. Such a temperature range is specifically configured to minimize damage to the underlying devices of the CFET. In more detail, the annealing process 280 herein is performed on the gate structures 200A and 200B, the gate structures 200A and 200B being the top-level devices of the CFET. At this stage of fabrication, the underlying device (which is bonded to the top device) includes transistors that have been substantially formed. If the temperature of the annealing process 280 is too high (e.g., greater than about 500 degrees celsius), such high temperatures may cause damage to transistor components of the underlying device. Here, by ensuring that the temperature of the annealing process 280 is below 500 degrees celsius, potential damage to the underlying device is prevented or at least minimized.

It should be noted that the relative arrangement between gate dielectric layer 250A and dipole layer 220A (and likewise, between gate dielectric layer 250B and dipole layer 220B) is one of the unique physical characteristics of the devices of the embodiments of the present disclosure, as well as the inherent result of the unique manufacturing process flow of the embodiments of the present disclosure as practiced herein. For example, the unique first dipole approach of the embodiments of the present disclosure inherently results in the formation of dipole layer 220A/220B under gate dielectric layer 250A/250B. In contrast, conventional devices have an opposite relative arrangement between their dipole layer and gate dielectric layer: their dipole layer is located above the gate dielectric layer because conventional devices utilize the back dipole approach. Thus, if a device is detected as having its dipole layer implemented under its gate dielectric layer, it can be demonstrated that such a device is fabricated using the unique first dipole process flow of the embodiments of the present disclosure.

Referring now to fig. 6, a plurality of deposition processes 290 are performed to form a metal-containing gate electrode 300A over a gate dielectric layer 250A and a metal-containing gate electrode 300B over a gate dielectric layer 250B. In some embodiments, the metal-containing gate electrodes 300A and 300B may include a work function metal layer and a filler metal layer. The work function metal layer may help to adjust the threshold voltage of the corresponding transistor, and the filler metal layer may serve as the main conductive portion of the gate electrode. In some embodiments, metal-containing gate electrodes 300A and 300B comprise a pure metal, such as titanium (Ti), aluminum (Al), tungsten (W), tantalum (Ta), and the like. In some other embodiments, metal-containing gate electrodes 300A and 300B comprise a metal compound, such as tantalum nitride (TaN), titanium nitride (TiN), titanium aluminum (TiAl), tungsten nitride (WN), and the like.

Fig. 7A to 7B show a graph 350A and a graph 350B, respectively. Graphs 350A and 350B plot the variation of yttrium concentrations 360A and 360B throughout gate structures 200A and 200B, respectively. For example, graphs 350A and 350B each include an X-axis and a Y-axis. The X-axis of fig. 7A-7B represents vertical position (or depth) within the gate structures 200A-200B. In other words, the X-axis of fig. 7A to 7B corresponds to the vertical direction in fig. 2 to 6. Meanwhile, the Y-axis of FIGS. 7A-7B represents the yttrium concentration in the gate structures 200A-200B.

As shown in graph 350A, yttrium concentration 360A begins at a relatively low level 370A and remains relatively flat across active region 120A and most of interface layer 210A from right to left on the X-axis (i.e., representing a deeper depth to a shallower depth within gate structure 200A). The yttrium concentration 360A begins to rise rapidly near the interface between the interface layer 210A and the dipole layer 220A, reaches a peak 375A near a midpoint within the dipole layer 220A, and then begins to fall until another plateau 380A is reached in the gate dielectric layer 250A. Yttrium concentration 360A remains at or near mesa 380A in a majority of gate dielectric layer 250A and then it begins to rapidly descend past the interface between gate dielectric layer 250A and metal-containing gate electrode 300A. The yttrium concentration 360A reaches another plateau 385A within the metal-containing gate electrode 300A.

The behavior of yttrium concentration 360A shown in fig. 7A is intuitively meaningful because in the illustrated embodiment, dipole layer 220A (where peak 375A is located) is made of yttrium oxide and thus contains the maximum level of yttrium. The fact that gate dielectric layer 250A has a second large yttrium concentration level (i.e., a yttrium concentration level that is lower than that of dipole layer 220A, but higher than that of metal-containing gate electrode 300A) is due to the fact that gate dielectric layer 250A is doped with yttrium, but still consists essentially of a high-k dielectric material (e.g., hafnium oxide or zirconium oxide). The metal-containing gate electrode 300A and the active region 120A contain low levels of yttrium because they are not made of yttrium nor are they directly doped with yttrium. The amount of yttrium in the metal-containing gate electrode 300A and the active region 120A is due to diffusion, wherein yttrium diffuses into these layers from the dipole layer 220A and/or from the doped gate dielectric layer 250A.

The yttrium concentration 360B shown in fig. 7B varies in a manner similar to the yttrium concentration 360A shown in fig. 7A. For example, yttrium concentration 360B also begins at a relatively low level 370B, peaks 375B within dipole layer 220B, drops to a lower plateau 380A within gate dielectric layer 250B, and drops and stabilizes to an even lower plateau 385B within metal-containing gate electrode 300B. One difference between the yttrium concentration 360A of fig. 7A and the yttrium concentration 360A of fig. 7B is that there is a wider band around peak 375B than around peak 375A. This is because the dipole layer 220B is thicker than the dipole layer 220A.

In some embodiments, the ratio between yttrium concentration levels corresponding to peak 375A and plateau level 380A is in a range between about 2% and about 10%, and the ratio between yttrium concentration levels corresponding to plateau level 380A and plateau level 385A is in a range between about 0% and about 2%. Similar ratio ranges may be applicable for peak 375B, plateau level 380A, and plateau level 385B of fig. 7B.

It should be appreciated that the yttrium concentration profiles shown in fig. 7A-7B (including the ratio ranges described above) are actual physical characteristics of devices fabricated according to the process flow of embodiments of the present disclosure, and may be detectable. For example, they may be detected using machines such as Energy Dispersive Spectroscopy (EDS) tools, electron Energy Loss Spectroscopy (EELS) tools, secondary Ion Mass Spectrometry (SIMS) tools, and the like. These detectable yttrium concentration profiles are an inherent result of the unique first-dipole process flow of the embodiments of the present disclosure. For example, the early dipole scheme utilized by the embodiments of the present disclosure inherently produces a peak concentration of yttrium at or near the region between gate dielectric layer 250A/250B and interface layer 210A/B, which region corresponds to the location of dipole layer 220A/220B in the illustrated embodiment. In contrast, the distribution of dipole material (which may be a lanthanum-containing material) in conventional devices will occur at or near the interface between the gate dielectric layer and the metal-containing gate electrode. Furthermore, the fact that the gate dielectric layers 250A/250B are doped with yttrium means that the yttrium levels corresponding to the locations of these layers are higher than the metal-containing gate electrodes 300A/300B, the interface layers 210A/210B, or the active regions 120A/120B, but not as high as the dipole layers 220A/220B. Thus, devices exhibiting the yttrium concentration profiles shown in fig. 7A-7B may be used as evidence that those devices were fabricated using the process flow of embodiments of the present disclosure.

It should also be understood that while yttrium is used herein to describe the dipole distribution of the exemplary device of the disclosed embodiments, this is not intended to be limiting. In other embodiments, scandium oxide (instead of yttrium oxide) may be used to implement the dipole layer 220A/220B. In these embodiments, the distributions shown in fig. 7A-7B may still be present and may be detectable, but the concentration levels will be those of scandium instead of yttrium.

It should be appreciated that while the examples herein correspond to N-type transistors, the same concepts may also be applied to P-type transistors. For example, the first dipole method discussed above may also be used to form a P dipole layer over the active region of a P-type transistor, then a doped gate dielectric layer may be formed over the P dipole layer, followed by an annealing process to at least partially convert the amorphous material of the doped gate dielectric layer to a material having a crystalline phase, and then a metal-containing gate electrode may be formed over the gate dielectric layer. The same benefits can be realized whether the concepts of the embodiments of the present disclosure are used to form N-type transistors or P-type transistors. For example, damage to underlying devices may be avoided and device performance may be improved by increasing the value of the dielectric constant (e.g., by converting amorphous material to crystalline material).

Fig. 8-19 are a series of schematic partial cross-sectional side views illustrating an exemplary process flow of fabricating a sequential CFET 400 according to embodiments of the present disclosure. Referring to fig. 8, cfet 400 includes a substrate 410, which may be an embodiment of substrate 110 discussed above. In some embodiments, the substrate 410 may be a silicon substrate. A plurality of alternating semiconductor layers 430 and 431 are formed over the substrate 410. In some embodiments, semiconductor layer 430 comprises silicon germanium (SiGe) and semiconductor layer 431 comprises silicon (Si). It should be noted that while fig. 8 shows two semiconductor layers 430 and two semiconductor layers 431, any other number (e.g., three or more) of semiconductor layers 430 and 431 may be implemented in other embodiments.

Referring to fig. 9, other processes may be implemented to continue fabrication of the CFET 400, such as fin structure patterning, shallow Trench Isolation (STI) formation, gate patterning, spacer deposition, source/drain etching, internal spacer formation, bottom source/drain epitaxial formation, contact Etch Stop Layer (CESL) formation, and interlayer dielectric (ILD 0) formation, among others. Due to these fabrication processes, portions of the semiconductor layer 431 are patterned into nanostructured channels 431, e.g., such as nanoplates, nanotubes, nanowires, etc. A dummy gate structure 440 is formed over the uppermost one of the nanostructure channels 431. In some embodiments, dummy gate structure 440 may include a polysilicon dummy gate electrode. Each dummy gate structure 440 may be patterned by one or more hard mask layers 450, and the hard mask layers 450 may include one or more dielectric materials. Gate spacers 460 are formed on sidewalls of the dummy gate structure 440. The gate spacer 460 may also comprise a suitable dielectric material. In some embodiments, each of the gate spacers 460 may include multiple gate spacer layers, but for simplicity reasons this is not specifically shown herein.

Source/drain regions 480 are also formed (e.g., by epitaxial growth) by these fabrication processes. As used herein, source/drain regions 480 or "S/D regions" may refer to the source or drain of a transistor device. It may also refer to a region that provides a source and/or drain for multiple transistor devices. An internal spacer 490 is formed between the source/drain region 480 and the semiconductor layer 430. The inner spacer 490 may also include a suitable dielectric material. ILD0 500 is also formed over source/drain regions 480 and between dummy gate structures 440. ILD0 500 comprises a suitable dielectric material to provide electrical isolation between the various microelectronic components of CFET 400. ILD0 500 may be planarized by a Chemical Mechanical Polishing (CMP) process to have its upper surface level.

Referring now to fig. 10, the dummy gate structure 440 is removed. Semiconductor layer 430 (e.g., comprising SiGe) is also removed. Gate dielectric structure 530 and gate electrode 540 are formed to replace removed semiconductor layer 430 and removed dummy gate structure 440. In some embodiments, the gate dielectric structure 530 may be formed by a back dipole method. Details of one of the gate dielectric structures 530 are also shown in the enlarged cross-sectional side view in fig. 10. For example, the gate dielectric structure 530 may include an interface layer 531, a high-k dielectric layer 532 formed over the interface layer 531, and a dipole layer 533 formed over the high-k dielectric layer 532. In some embodiments, the high-k dielectric layer 532 includes hafnium oxide, zirconium oxide, or another suitable dielectric material having a dielectric constant greater than that of silicon dioxide. In some embodiments, dipole layer 533 comprises a lanthanum-containing material, such as lanthanum oxide.

While the post-dipole method is used to form the gate dielectric structure 530 in the illustrated embodiment, it should be understood that in other embodiments the pre-dipole method discussed above in connection with fig. 2-6 may alternatively be used to implement the gate dielectric structure 530. In these alternative embodiments, the gate dielectric structure 530 would include a dipole layer (e.g., yttria or scandia) located below the high-k dielectric layer.

Whichever method is used to form gate dielectric structure 530, gate electrode 540 is formed over gate dielectric structure 530. The gate electrode 540 may include a metal material, for example, a work function metal material and a filler metal material. In other words, gate electrode 540 may be similar to gate electrodes 300A-300B discussed above. A self-aligned contact (SAC) 550 may also be formed over the uppermost surface of the gate electrode 540. Source/drain contacts 560 are formed over source/drain regions 480 to provide electrical connection to source/drain regions 480.

It should be appreciated that the microelectronic assembly discussed above with reference to fig. 8-10 is an assembly of the underlying device 400A of the CFET. Referring now to fig. 11, a bonding process 580 is performed to bond the top layer device 400B of the CFET to the bottom layer device 400A. In more detail, the top-level device 400B includes a substrate 610, which may be an embodiment of the substrate 210 discussed above. In some embodiments, substrate 610 may be similar to substrate 410. For example, both substrates 410 and 610 may be silicon substrates.

The top-level device 400B also includes a plurality of alternating semiconductor layers 630 and 631 formed over the substrate 610. In some embodiments, semiconductor layer 430 comprises silicon germanium (SiGe) and semiconductor layer 431 comprises silicon (Si). It should be noted that although fig. 11 shows three semiconductor layers 630 and two semiconductor layers 631, any other number (e.g., four or more) of semiconductor layers 630 and 631 may be implemented in other embodiments.

Before the bonding process 580 is performed, a bonding layer 640 and a bonding layer 650 are formed over the topmost surfaces of the top-layer device 400B and the bottom-layer device 400A, respectively. Then, the bonding process 580 bonds the top layer device 400B to the bottom layer device 400A through the bonding layers 640 and 650. In other words, the exposed surface of the bonding layer 640 is bonded to the exposed surface of the bonding layer 650. It should be noted that the top device 400B may be vertically "flipped" after bonding to the bottom device 400A, as shown in fig. 12.

Referring now to fig. 13, a thinning process 660 is performed to remove the substrate 610 of the top-level device 400B. In some embodiments, the thinning process 660 may include an etching process, a mechanical grinding process, or a combination thereof. The thinning process 660 may be performed until the topmost semiconductor layer 630 is exposed.

Referring now to fig. 14, an etching process 670 is performed to remove the uppermost one of the semiconductor layers 630. The semiconductor layer 631 serves as an etch stop layer such that the etching process 670 stops when reaching the upper surface of the semiconductor layer 631.

Referring now to fig. 15, a number of processes may be implemented to continue to fabricate the top-level device 400B of the CFET 400. Source/drain regions 680 are also formed, for example, by epitaxial growth. As used herein, source/drain regions 680 or "S/D regions" may refer to the source or drain of a transistor device. It may also refer to a region that provides a source and/or drain for multiple transistor devices. An internal spacer 690 is formed between the source/drain region 680 and the semiconductor layer 630. The inner spacer 690 may also include a suitable dielectric material. In some embodiments, the locations of the source/drain regions 680 of the top layer device 400B are vertically aligned with the locations of the source/drain regions 480 of the bottom layer device 400A, respectively.

A dummy gate structure 700 is formed over the uppermost one of the nanostructure channels 631. In some embodiments, the dummy gate structure 700 may include a polysilicon dummy gate electrode. Each dummy gate structure 700 may be patterned by one or more hard mask layers 710, and the hard mask layers 710 may include one or more dielectric materials. Gate spacers 720 are formed on sidewalls of each of the dummy gate structures 700. The gate spacer 720 may also include a suitable dielectric material. In some embodiments, each of the gate spacers 720 may include multiple gate spacer layers, but for simplicity reasons this is not specifically shown herein.

ILD1 730 is also formed over source/drain regions 680 and between dummy gate structures 700. ILD1 730 comprises a suitable dielectric material to provide electrical isolation between the individual microelectronic components of the top-level device 400B of CFET 400. ILD1 730 may be planarized by a Chemical Mechanical Polishing (CMP) process to have its upper surface level.

Referring now to fig. 16, one or more processes 750 may be performed to remove the dummy gate structure 700 and the semiconductor layer 630 from the top-level device 400B of the CFET 400. For example, the one or more processes 750 may include an etching process. The etching process may be configured to have an etch selectivity between the semiconductor layer 630 and the semiconductor layer 631 such that the semiconductor layer 631 is substantially unaffected when the semiconductor layer 630 is removed. The remaining portion of the semiconductor layer 631 forms nanostructure channels 631, such as, for example, nanoplates, nanotubes, nanowires, and the like. Portions of the gate spacers 720 and ILD1 730 remain. As can be seen in fig. 16, the removal of the semiconductor layer 630 and the dummy gate structure 700 forms openings 770 and 780 in the top-level device 400B.

Referring now to fig. 17, a gate formation process 800 is performed to form a metal-containing gate structure to fill openings 770 and 780. For example, the metal-containing gate structures may each include a gate dielectric structure 830 and a metal-containing gate electrode 840 formed over the gate dielectric structure 830. In accordance with aspects of embodiments of the present disclosure, the gate dielectric structure 830 is formed using the processes discussed above with reference to fig. 2-6. For example, gate dielectric structure 830 may include an interfacial layer (e.g., embodiments of interfacial layer 210A/210B), a dipole layer formed over the interfacial layer (e.g., embodiments of dipole layer 220A/220B), and a doped high-k gate dielectric layer formed over the dipole layer (e.g., embodiments of gate dielectric layer 250A/250B). In other words, the dipole layer of the gate dielectric structure 830 is formed using the prior dipole method discussed above. These different layers of the gate dielectric structure 830 are not separately shown in fig. 17 for simplicity.

In any event, it should be appreciated that the dipole layer of gate dielectric structure 830 comprises a dipole material having weaker threshold voltage adjustment characteristics than lanthanum oxide. For example, the dipole material of the gate dielectric structure 830 may include yttria or scandia. These materials are more suitable herein for adjusting the threshold voltage for the top-level device 400B because the first dipole approach means that the dipole layer is located closer to the nanostructure channel 631 of the top-level device 400B. Furthermore, the dipole-first approach means that the high Wen Ouji drive-in process does not need to be implemented. The process temperature of the annealing process (e.g., performed to convert the amorphous material of the high-k gate dielectric to a crystalline phase material) is sufficiently low (e.g., at about 500 degrees celsius or below about 500 degrees celsius) to prevent or at least reduce potential damage to the microelectronic components of the underlying device 400A. Converting the amorphous material into a crystalline phase material (e.g., hafnium oxide with a cubic phase or zirconium oxide with a tetragonal phase) also helps to increase the dielectric constant of the high-k gate dielectric layer. Thus, the device performance and/or ease of EOT scaling of the top-level device 400B may be improved.

The gate electrode 840 may include a metal material, for example, a work function metal material and a filler metal material. In other words, gate electrode 840 may be similar to gate electrodes 300A-300B discussed above. A self-aligned contact (SAC) 850 may also be formed over the uppermost surface of the gate electrode 840.

Referring now to fig. 18, portions of ILD1 730 formed over source/drain regions 680 are removed. Source/drain contacts 860 are formed over the source/drain regions 680 to provide electrical connection to the source/drain regions 680. It should be appreciated that additional processes may be implemented to continue the fabrication of CFET 400. For example, conductive gate contacts may be formed to provide electrical connection to the gate electrode 840. The encapsulation process may also be implemented to continue the encapsulation of CFET 400.

Fig. 19 illustrates an integrated circuit manufacturing system 900 that may be used to manufacture CFET 400 in accordance with an embodiment of the present disclosure. The manufacturing system 900 includes a plurality of entities 902, 904, 906, 908, 910, 912, 914, 916 … N connected by a communication network 918. The network 918 may be a single network or may be a variety of different networks, such as an intranet and the internet, and may include both wired and wireless communication channels.

In an embodiment, entity 902 represents a service system for manufacturing collaboration; entity 904 represents a user, such as a product engineer monitoring a product of interest; entity 906 represents an engineer, such as a process engineer controlling a process and related recipes, or an equipment engineer monitoring or adjusting the conditions and settings of a process tool; entity 908 represents a metrology tool for IC testing and measurement; entity 910 represents a semiconductor processing tool, such as an EUV tool for performing a photolithography process to define gate spacers of an SRAM device; entity 912 represents a virtual metrology module associated with the processing tool 910; entity 914 represents a high-level process control module associated with process tool 910 and, additionally, other process tools; and entity 916 represents a sampling module associated with processing tool 910.

Each entity may interact with other entities and may provide integrated circuit manufacturing, process control, and/or computing capabilities to other entities and/or receive such capabilities from other entities. Each entity may also include one or more computer systems for performing computations and performing automation. For example, the high-level processing control module of entity 914 can comprise a plurality of computer hardware with software instructions encoded therein. Computer hardware may include hard drives, flash drives, CD-ROMs, RAM memories, display devices (e.g., monitor), input/output devices (e.g., mouse and keyboard). The software instructions may be written in any suitable programming language and may be designed to perform specific tasks.

The integrated circuit manufacturing system 900 enables interactions between entities for purposes of Integrated Circuit (IC) manufacturing, and advanced process control for IC manufacturing. In an embodiment, advanced process control includes adjusting process conditions, settings, and/or recipes for one process tool for an associated wafer based on metrology results.

In another embodiment, metrology results are measured from a subset of processed wafers according to an optimal sampling rate determined based upon process quality and/or product quality. In yet another embodiment, measurements are measured from selected fields and points of a subset of the processed wafers according to an optimal sampling field/point determined based on various characteristics of process quality and/or product quality.

One of the capabilities provided by the IC fabrication system 900 may enable collaboration and information access in areas such as design, engineering, and process, metrology, and advanced process control. Another capability provided by the IC fabrication system 900 may integrate systems between facilities, such as between metrology tools and processing tools. This integration enables facilities to coordinate their activities. For example, integrating the metrology tool and the processing tool may enable more efficient incorporation of manufacturing information into a manufacturing process or APC module, and may enable wafer data to be obtained from in-line or in-situ measurements using the metrology tool integrated into the relevant processing tool.

Fig. 20 is a flow chart of a method 1000 of fabricating a semiconductor device in accordance with aspects of an embodiment of the present disclosure. The method 1000 includes a step 1010 for forming a dipole layer over a semiconductor channel region. In some embodiments, the step 1010 of forming a dipole layer includes depositing a layer of yttria or scandia as the dipole layer.

The method 1000 includes a step 1020 for forming a doped gate dielectric layer over the dipole layer. The doped gate dielectric layer comprises an amorphous material. In some embodiments, the step 1020 of forming a doped gate dielectric layer includes forming an yttrium doped gate dielectric layer. In some embodiments, the step 1020 of forming a doped gate dielectric layer includes performing a first number of deposition cycles. Each cycle of the first number of deposition cycles includes: depositing a sub-layer of undoped gate dielectric material, wherein the undoped gate dielectric material has a dielectric constant greater than that of silicon dioxide; repeating the depositing of the sub-layer a second number of times; and depositing a yttria layer over an uppermost one of the sub-layers of undoped gate dielectric material.

The method 1000 includes a step 1030 for converting the amorphous material of the doped gate dielectric layer into a material having a partial crystalline phase by an annealing process. In some embodiments, the step 1020 of forming a doped gate dielectric layer includes forming a doped hafnium oxide layer, and the step 1030 of converting includes converting the doped hafnium oxide layer into a layer having at least partially a cubic crystalline phase. In other embodiments, the step 1020 of forming a doped gate dielectric layer includes forming a doped zirconia layer, and the step 1030 of converting includes converting the doped zirconia layer into a layer having at least partially a tetragonal phase. In some embodiments, the annealing process is performed using a process temperature of less than about 500 degrees celsius.

The method 1000 includes step 1040 to form a metal-containing gate electrode over the doped gate dielectric layer.

It should be appreciated that the method 1000 may include further steps performed before, during, or after steps 1010-1040. For example, prior to performing steps 1010-1040, the method may include a process performed to form a bottom device of the CFET, and steps to form certain components of a top device of the CFET and bond the top device to the bottom device. Steps 1010-1040 are implemented as part of the formation of the gate structure of the top device of the CFET. For simplicity reasons, other additional steps are not discussed in detail herein.

In summary, embodiments of the present disclosure relate to gate dielectrics for top-level devices that use a first dipole approach to fabricate CFETs. In more detail, the disclosed embodiments do not form a dipole layer over a high-k dielectric layer, but rather form a dipole layer over an interface layer, and then form a doped amorphous high-k gate dielectric layer over the dipole layer. An annealing process is performed to convert at least a portion of the amorphous high-k gate dielectric to a material having a crystalline phase. A metal-containing gate is then formed over the high-k gate dielectric.

Embodiments of the present disclosure provide advantages over conventional CFET devices. It should be understood that other embodiments may provide additional advantages, and that not all advantages need be disclosed herein, and that no particular advantage is necessarily required for all embodiments. One advantage is that device damage is prevented and/or reduced. In more detail, conventional CFET fabrication involves performing a dipole-driving process in fabricating a top-level device. Such dipole driving processes are typically performed with relatively high temperatures, for example, temperatures greater than about 500 degrees celsius. However, by the time this high Wen Ouji drive-in process is performed, microelectronic components of the underlying devices of the CFET have been formed, which are susceptible to damage from high temperatures. In other words, conventional fabrication methods for fabricating the top layer device of the CFET may inadvertently damage the bottom layer device. Here, the unique pre-dipole process flow means that the high Wen Ouji drive-in process is not required. The temperatures associated with the annealing processes performed herein (e.g., at 500 degrees celsius or below 500 degrees celsius) are still low enough to make the microelectronic components of the underlying devices less likely to be damaged. Another advantage of an embodiment of the present disclosure is improved device performance. For example, by at least partially converting the amorphous material of the high-k dielectric layer into a crystalline material, the dielectric constant of the resulting high-k dielectric layer is increased, which results in improved device performance of the gate structure. Other advantages include compatibility with existing manufacturing processes, ease of implementation, and low cost.

One aspect of the disclosed embodiments relates to a device. The device includes an active region. The device includes a dipole layer disposed over the active region. The device includes a doped gate dielectric layer disposed over the dipole layer. The device includes a metal-containing gate electrode disposed over a doped gate dielectric layer.

Another aspect of the disclosed embodiments relates to a device. The device includes a top-level transistor including a first gate structure. The first gate structure includes a first dipole layer and a first gate dielectric layer disposed over the first dipole layer. The first gate dielectric layer is doped with a dopant. The device includes a bottom layer transistor vertically bonded to a top layer transistor. The underlying transistor includes a second gate structure. The second gate structure includes a second gate dielectric layer and a second dipole layer disposed over the second gate dielectric layer. The first dipole layer and the second dipole layer have different material compositions.

Another aspect of the disclosed embodiments relates to a method. A dipole layer is formed over the semiconductor channel region. A doped gate dielectric layer is formed over the dipole layer. The doped gate dielectric layer comprises an amorphous material. By means of an annealing process, the amorphous material of the doped gate dielectric layer is converted into a material having at least a partial crystalline phase. After the doped gate dielectric layer is converted to a layer having a partial crystalline phase, a metal-containing gate electrode is formed over the doped gate dielectric layer.

Some embodiments of the present application provide a semiconductor device including: an active region; a dipole layer disposed over the active region; a doped gate dielectric layer disposed over the dipole layer; and a metal-containing gate electrode disposed over the doped gate dielectric layer. In some embodiments, the dipole layer comprises yttria or scandia. In some embodiments, the doped gate dielectric layer comprises a dielectric material having a dielectric constant greater than that of silicon oxide, and wherein the dielectric material has at least in part a crystalline phase. In some embodiments, the dielectric material comprises hafnium oxide having a cubic crystalline phase; or the dielectric material comprises zirconia having a tetragonal phase. In some embodiments, the dipole layer has a first concentration level of yttrium; the doped gate dielectric layer is doped with yttrium and has a second concentration level of yttrium; the metal-containing gate electrode having a third concentration level of yttrium; the second concentration level is less than the first concentration level; and the third concentration level is less than the second concentration level. In some embodiments, the active region is a first active region, the dipole layer is a first dipole layer, the doped gate dielectric layer is a first doped gate dielectric layer, the metal-containing gate electrode is a first metal-containing gate electrode, and wherein the device further comprises: a second active region; a second dipole layer disposed over the second active region, wherein the second dipole layer and the first dipole layer have different thicknesses; a second doped gate dielectric layer disposed over the second dipole layer; and a second metal-containing gate electrode disposed over the second doped gate dielectric layer. In some embodiments, the first active region, the first dipole layer, the first doped gate dielectric layer, and the first metal-containing gate electrode are part of a first transistor; the second active region, the second dipole layer, the second doped gate dielectric layer, and the second metal-containing gate electrode are part of a second transistor; the first transistor is associated with a first threshold voltage; the second transistor is associated with a second threshold voltage that is lower than the first threshold voltage; and the second dipole layer is thicker than the first dipole layer. In some embodiments, the active region, the dipole layer, the doped gate dielectric layer, and the metal-containing gate electrode are components of a first gate structure of a top-level device of a Complementary Field Effect Transistor (CFET); the complementary field effect transistor further includes a bottom layer device bonded to the top layer device; the underlying device includes a second gate structure; and the second gate structure and the first gate structure include different types of dipole layers. In some embodiments, the dipole layer is a first dipole layer and comprises yttrium and scandium; the second gate structure includes a second gate dielectric layer and a second dipole layer disposed over the second gate dielectric layer; and the second dipole layer comprises lanthanum.

Further embodiments of the present application provide a semiconductor device including: a top-level transistor comprising a first gate structure, wherein the first gate structure comprises a first dipole layer and a first gate dielectric layer disposed over the first dipole layer, wherein the first gate dielectric layer is doped; and a bottom layer transistor vertically bonded to the top layer transistor, wherein the bottom layer transistor comprises a second gate structure, wherein the second gate structure comprises a second gate dielectric layer and a second dipole layer disposed over the second gate dielectric layer, and wherein the first dipole layer and the second dipole layer have different material compositions. In some embodiments, the first dipole layer comprises yttrium or scandium; the first gate dielectric layer is doped with yttrium; and the second dipole layer comprises lanthanum. In some embodiments, the first gate dielectric layer comprises hafnium oxide having a cubic phase or zirconium oxide having a tetragonal phase.

Still further embodiments of the present application provide a method of forming a semiconductor device, comprising: forming a dipole layer over the semiconductor channel region; forming a doped gate dielectric layer over the dipole layer, wherein the doped gate dielectric layer comprises an amorphous material; converting the amorphous material into a material having at least a partial crystalline phase by an annealing process; and forming a metal-containing gate electrode over the doped gate dielectric layer after the converting. In some embodiments, forming the dipole layer includes depositing a layer of yttria or scandia as the dipole layer. In some embodiments, forming the doped gate dielectric layer includes forming an yttrium doped gate dielectric layer. In some embodiments, forming the doped gate dielectric layer includes performing a first number of deposition cycles, wherein each cycle of the first number of deposition cycles includes: depositing a sub-layer of undoped gate dielectric material, wherein the undoped gate dielectric material has a dielectric constant greater than that of silicon dioxide; repeating the depositing of the sub-layer a second number of times; and depositing a yttria layer over an uppermost one of the sub-layers of the undoped gate dielectric material. In some embodiments, forming the doped gate dielectric layer includes forming a doped hafnium oxide layer; and said converting comprises converting said doped hafnium oxide layer into a layer having at least partially a cubic crystalline phase. In some embodiments, forming the doped gate dielectric layer includes forming a doped zirconia layer; and said converting comprises converting said doped zirconia layer into a layer having at least partially a tetragonal phase. In some embodiments, the annealing process is performed with a process temperature of less than about 500 degrees celsius. In some embodiments, the dipole layer, the doped gate dielectric layer, and the metal-containing gate electrode are formed as part of a gate of a top device of a Complementary Field Effect Transistor (CFET), wherein the method further comprises: the top device is bonded to the bottom device of the complementary field effect transistor prior to forming the dipole layer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the embodiments of the present disclosure. Those skilled in the art will appreciate that they may readily use the presently disclosed embodiments as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those of ordinary skill in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the embodiments of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A semiconductor device, comprising:

An active region;

a dipole layer disposed over the active region;

a doped gate dielectric layer disposed over the dipole layer; and

A metal-containing gate electrode disposed over the doped gate dielectric layer.

2. The semiconductor device of claim 1, wherein the dipole layer comprises yttria or scandia.

3. The semiconductor device of claim 1, wherein the doped gate dielectric layer comprises a dielectric material having a dielectric constant greater than a dielectric constant of silicon oxide, and wherein the dielectric material has at least in part a crystalline phase.

4. The semiconductor device of claim 3, wherein:

the dielectric material comprises hafnium oxide having a cubic phase; or alternatively

The dielectric material comprises zirconia having a tetragonal phase.

5. The semiconductor device of claim 1, wherein:

the dipole layer having a first concentration level of yttrium;

the doped gate dielectric layer is doped with yttrium and has a second concentration level of yttrium;

The metal-containing gate electrode having a third concentration level of yttrium;

The second concentration level is less than the first concentration level; and

The third concentration level is less than the second concentration level.

6. The semiconductor device of claim 1, wherein the active region is a first active region, the dipole layer is a first dipole layer, the doped gate dielectric layer is a first doped gate dielectric layer, the metal-containing gate electrode is a first metal-containing gate electrode, and wherein the device further comprises:

a second active region;

a second dipole layer disposed over the second active region, wherein the second dipole layer and the first dipole layer have different thicknesses;

A second doped gate dielectric layer disposed over the second dipole layer; and

A second metal-containing gate electrode disposed over the second doped gate dielectric layer.

7. The semiconductor device of claim 6, wherein:

The first active region, the first dipole layer, the first doped gate dielectric layer, and the first metal-containing gate electrode are part of a first transistor;

the second active region, the second dipole layer, the second doped gate dielectric layer, and the second metal-containing gate electrode are part of a second transistor;

The first transistor is associated with a first threshold voltage;

the second transistor is associated with a second threshold voltage that is lower than the first threshold voltage; and

The second dipole layer is thicker than the first dipole layer.

8. The semiconductor device of claim 1, wherein:

The active region, the dipole layer, the doped gate dielectric layer, and the metal-containing gate electrode are components of a first gate structure of a top-level device of a Complementary Field Effect Transistor (CFET);

The complementary field effect transistor further includes a bottom layer device bonded to the top layer device;

The underlying device includes a second gate structure; and

The second gate structure and the first gate structure include different types of dipole layers.

9. A semiconductor device, comprising:

A top-level transistor comprising a first gate structure, wherein the first gate structure comprises a first dipole layer and a first gate dielectric layer disposed over the first dipole layer, wherein the first gate dielectric layer is doped; and

A bottom layer transistor vertically bonded to the top layer transistor, wherein the bottom layer transistor comprises a second gate structure, wherein the second gate structure comprises a second gate dielectric layer and a second dipole layer disposed over the second gate dielectric layer, and wherein the first dipole layer and the second dipole layer have different material compositions.

10. A method of forming a semiconductor device, comprising:

forming a dipole layer over the semiconductor channel region;

Forming a doped gate dielectric layer over the dipole layer, wherein the doped gate dielectric layer comprises an amorphous material;

converting the amorphous material into a material having at least a partial crystalline phase by an annealing process; and

After the converting, a metal-containing gate electrode is formed over the doped gate dielectric layer.