CN118038949A - Device and method for saving energy consumption in memory refreshing process - Google Patents
Device and method for saving energy consumption in memory refreshing process Download PDFInfo
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Abstract
The invention provides a device and a method for saving energy consumption in a memory refreshing process. The word line control signal is processed by the direct signal generating circuit to generate a direct signal, the direct signal is input into the selection signal input path to generate a selection signal, the time for keeping high potential of the selection signal is shortened compared with that of the direct signal, the starting time of overdrive voltage can be shortened, and the energy consumption in the refreshing process is reduced; the turn-on time of the voltage comparator is controlled through the overdrive voltage control signal, when the overdrive voltage starts to supply power to the sense amplifier, the overdrive voltage charging signal is turned off, the overdrive voltage slowly drops, and when the power supply is completed, the overdrive voltage is replaced by the drive voltage with lower potential to supply power, so that the overdrive voltage is prevented from keeping high potential to work for a long time, and the purpose of effectively reducing power consumption is achieved.
Description
Technical Field
The present application relates to the field of semiconductor integrated circuits, and more particularly, to an apparatus and method for saving energy during a memory refresh process.
Background
Dynamic random access memory (Dynamic Random Access Memory, DRAM) is a common type of computer memory for temporarily storing data and instructions. DRAM has a higher storage density and lower cost than Static Random Access Memory (SRAM), but has a slower read and write speed and requires periodic refreshing to retain data.
The DRAM stores data by storing charge through a capacitor. Each memory cell consists of a capacitor and an access transistor, and when there is charge in the capacitor, it means that a1 is stored, and when there is no charge, it means that a 0 is stored. Since the capacitor leaks out naturally, the capacitor needs to be refreshed periodically to prevent data loss.
Since DRAM is a volatile memory, data is lost after power failure, it is typically used as main memory (memory) for temporarily storing programs and data in operation. In modern computer systems, DRAM is typically inserted onto the motherboard in the form of a module and communicates with the processor through a memory controller.
In the dynamic random access memory, a sense amplifier senses and amplifies data of a memory cell, and the sense amplifier uses two power supply potentials which are respectively marked as a driving voltage and an overdrive voltage, wherein the overdrive voltage potential is higher than the driving voltage potential; after the word line is turned on, the bit line and the capacitor of the memory cell share charge, and the sense amplifier can compare the tiny voltage variation on the bit line with the original voltage (balance voltage) and amplify the voltage to a voltage extremum of logic 1 or 0, and then restore the amplified voltage value to the memory cell through the bit line so as to maintain the integrity of data.
The sense amplifier is turned on to more quickly amplify the data on the bit line to reduce the time (tRCD, RAS to CAS time) from the word line on to the column select signal on, and is typically powered by a higher overdrive voltage level and then continuously powered by the drive voltage level. The data in the dynamic random access memory needs to be refreshed at intervals, so that the correctness of the data is maintained, otherwise, the data is damaged due to the loss of charges in the capacitor. The time of the refresh process can affect the performance and power consumption of the corresponding dynamic random access memory. When the refresh operation is performed, the dynamic random access memory cannot perform the read-write operation. The activation command is used for activating one row of one memory module, so that the data of the row can be read or written by amplifying the data of the bit line through the sense amplifier; after the activation command is executed, the read-write operation can be performed on the dynamic random access memory.
In a common dram, the refresh command and the activate command use the same overdrive voltage level control signal, so that power consumption is greater in the refresh process. In performing an activation operation, it is necessary to use an overdrive voltage at the time of turning on the word line to satisfy the guarantee that the data is accurately amplified at a smaller tRCD. However, during the refresh operation, since the read/write operation is not performed, it is unnecessary to rapidly amplify the data, and the overdrive voltage is used to supply power to the sense amplifier during the and active operation at this time, which may instead result in greater power consumption.
In order to reduce the time for reading data from the memory array, in the design, the sense amplifier uses overdrive voltage with higher potential as a power supply after being started, and the overdrive voltage and the ground voltage supply power for the sense amplifier, so that the overdrive voltage has higher potential and higher speed, and can amplify the voltage change on the bit line more quickly; when the potential is close to the driving voltage, the overdrive voltage stops supplying power and is converted into the driving voltage to start supplying power, and the power consumption is lower because the potential of the driving voltage is lower, and then the driving voltage with slightly lower voltage is used as a power supply to save the power consumption.
In practical use, the power supply duration of the overdrive voltage to the sense amplifier is controlled by a delay circuit in the dynamic random access memory, and the delay time of the delay circuit is greatly influenced by the manufacturing process, the working voltage and the working temperature. When the delay time of the delay circuit becomes large, the time for which the sense amplifier uses the overdrive voltage is greatly lengthened, resulting in an increase in power consumption of the sense amplifier when in use.
Disclosure of Invention
The application provides a device and a method for saving energy consumption in a memory refreshing process, wherein a word line control signal is processed by a direct signal generating circuit to generate a direct signal, the direct signal is input into a selection signal input path to generate a selection signal, and the time of the selection signal for keeping high potential is shortened compared with that of the direct signal, so that the time for starting overdrive voltage is shortened, and the energy consumption in the refreshing process is reduced.
The application controls the turn-on time of the voltage comparator through the overdrive voltage control signal, when the overdrive voltage starts to supply power to the sensing amplifier, the overdrive voltage charging signal is turned off, the overdrive voltage slowly drops, and after the overdrive voltage finishes supplying power to the sensing amplifier, the overdrive voltage is changed into the drive voltage with lower potential to supply power to the sensing amplifier, so that the overdrive voltage can be prevented from keeping high-potential work for a long time, and the purpose of effectively reducing power consumption is achieved.
To achieve one or a part or all of the above or other objects, the present invention provides an apparatus and method for saving energy during a memory refresh process.
An apparatus for saving energy during a memory refresh, comprising:
a word line control signal input, a direct signal generation circuit, a control signal input, and a selector; the control signal input end comprises a direct signal input path, a selection signal input path and a latch signal input path;
the word line control signal input end is connected with the input end of the direct signal generating circuit, the word line control signal is processed by the direct signal generating circuit to generate a direct signal, and the direct signal is input to the direct signal input path and the selection signal input path;
the direct signal input path outputs a direct signal;
The selector controls the selection signal input path to output a direct signal or a selection signal as an overdrive voltage control signal according to the output signal of the latch signal input path.
The selection signal input path comprises a selection circuit, the selection circuit comprises an AND gate circuit, one input end of the AND gate circuit is connected with the direct signal input path, and the output end of the AND gate circuit outputs a selection signal.
The selection circuit is a delay device, an NOT circuit and an AND circuit which are sequentially connected, and the input end of the AND circuit is respectively connected with the direct signal input path and the output end of the NOT circuit.
The selection signal is generated in such a manner that the direct signal is processed by the delay device to generate a delay signal, the not gate circuit inverts the delay signal, and the delay signal after signal inversion and the direct signal are processed by the and gate circuit to generate the selection signal.
The direct signal generation circuit includes:
the delay device, the NOT circuit and the AND circuit are sequentially connected with the word line control signal input end in sequence, and the AND circuit input end is respectively connected with the word line control signal input end and the NOT circuit output end;
The direct signal is generated in such a way that the word line control signal is processed by a delay device to generate signal delay, and then enters an NOT gate to perform signal inversion after generating the signal delay, and the signal after signal inversion and the word line control signal are processed by an AND gate to generate the direct signal.
The delay means is arranged as a delay or delay circuit.
When an activation command is performed, an activation enabling signal generates a high potential signal, a refresh enabling signal keeps a low potential state, a latch generates a high potential output signal, and the selector selects the direct signal as an overdrive voltage control signal according to the high potential output signal of the latch signal input path.
When a refresh command is performed, the refresh enable signal generates a high potential signal, the activation enable signal maintains a low potential state, the latch generates a low potential output signal, and the selector selects the selection signal as an overdrive voltage control signal according to the low potential output signal of the latch signal input path.
The device also comprises a voltage module, a sense amplifier and a storage unit which are sequentially connected;
the voltage module includes an overdrive voltage supply circuit including: the voltage comparator, the overdrive voltage controller, the overdrive voltage circuit and the drive voltage circuit are connected with the sense amplifier;
The input end of the voltage comparator is respectively input with an overdrive voltage reference voltage and an overdrive voltage, the output end of the voltage comparator is connected to the input end of the overdrive voltage controller, and the output end of the overdrive voltage controller is connected with the overdrive voltage circuit;
The voltage comparator controls the overdrive voltage controller to supply power to the sense amplifier through the overdrive voltage charging signal.
The overdrive voltage controller comprises a power supply voltage which is higher than the overdrive voltage, and the output end of the voltage comparator is connected to the switching device so as to control the power supply voltage to supply power for the drive voltage;
the switching device is a MOS transistor, the output end of the voltage comparator is connected to the grid electrode of the MOS transistor, and the switching device is arranged on a circuit with the power supply voltage connected with the overdrive voltage.
The circuit also comprises a signal control circuit, wherein the signal control circuit comprises a word line control signal input;
the word line control signal and the overdrive voltage charging signal are processed by an AND gate circuit to generate the drive voltage control signal;
The word line control signal input end is connected with a ground voltage power supply signal, the ground voltage power supply signal and the word line control signal are input to a row address decoder input end, and the row address decoder output end is connected to each word line of the memory unit.
A method for saving energy consumption in the process of refreshing a memory, which uses the device, comprises the following steps:
the word line control signal input end is input to the direct signal generation circuit, and the word line control signal is processed by the direct signal generation circuit to generate a direct signal;
the direct signal input path, the selection signal input path and the latch signal input path are input to the selector;
The word line control signal is processed by a delay device to generate signal delay, the signal delay is generated and enters an NOT gate to perform signal inversion, and the signal after signal inversion and the word line control signal are processed by an AND gate to generate the direct signal; the direct signal is input to the direct signal input path and the selection signal input path;
The selection signal input path comprises a selection circuit, the direct signal enters the selection circuit, signal delay is generated through a delayer, signal inversion is performed through an NOT gate, and the inverted signal and the direct signal are processed through an AND gate circuit to generate a selection signal;
When an activation command is performed, the latch generates a high-potential output signal, and the selector selects a direct signal as an overdrive voltage control signal; the latch generates a low potential output signal when a refresh command is performed, and the selector selects the selection signal as an overdrive voltage control signal;
the overdrive voltage control signal is processed by the NOT circuit to generate the overdrive voltage charging signal.
After the activation command is input, when the sense amplifier is started, the overdrive voltage charging signal controls the voltage comparator to start working, and outputs a signal to the switching device to control the power supply voltage to charge the overdrive voltage to the reference voltage potential;
when the driving voltage is the working of the sensing amplifier, the overdrive voltage charging signal turns off the output, and the overdrive voltage potential slowly drops;
the word line control signal is connected with the ground voltage power supply signal and is input to the row address decoder, and the row address decoder outputs the word line control signal to each word line of the memory unit.
Compared with the prior art, the invention has the beneficial effects that:
The invention provides a device and a method for saving energy consumption in a memory refreshing process, wherein a word line control signal is processed by a direct signal generating circuit to generate a direct signal, the direct signal is input into a selection signal input path to generate a selection signal, and the time for keeping high potential of the selection signal is shortened compared with that of the direct signal, so that the time for starting overdrive voltage can be shortened, and the energy consumption in the refreshing process is reduced.
The application controls the turn-on time of the voltage comparator through the overdrive voltage control signal, when the overdrive voltage starts to supply power to the sensing amplifier, the overdrive voltage charging signal is turned off, the overdrive voltage slowly drops, and after the overdrive voltage finishes supplying power to the sensing amplifier, the overdrive voltage is changed into the drive voltage with lower potential to supply power to the sensing amplifier, so that the overdrive voltage can be prevented from keeping high-potential work for a long time, and the purpose of effectively reducing power consumption is achieved.
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments, as illustrated in the accompanying drawings.
Drawings
In order to more clearly illustrate the technical solutions of specific embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort to a person of ordinary skill in the art.
Fig. 1 is a schematic structural diagram 1 of an apparatus for saving energy consumption in a memory refresh process according to an embodiment of the present application.
Fig. 2 is a schematic structural diagram 2 of an apparatus for saving energy in a memory refresh process according to an embodiment of the present application.
Fig. 3 is a schematic structural diagram 3 of an apparatus for saving energy in a memory refresh process according to an embodiment of the present application.
Fig. 4 is a partial circuit diagram of an apparatus for saving energy during a memory refresh according to an embodiment of the present application.
Fig. 5 is an overall circuit diagram of an apparatus for saving energy during a memory refresh according to an embodiment of the present application.
FIG. 6 is a graph showing the voltage variation of a sense amplifier of an apparatus for saving power consumption during a memory refresh process according to an embodiment of the present application.
Fig. 7 is a waveform diagram of signal control under an activation command according to an embodiment of the present application.
Fig. 8 is a circuit diagram of another signal control circuit according to an embodiment of the present application.
Fig. 9 is a schematic diagram of pulse widths of waveforms of signals in the circuit diagram of fig. 8.
Fig. 10 is a waveform diagram of signal control under a refresh command according to an embodiment of the present application.
Detailed Description
The foregoing and other features, aspects, and advantages of the present invention will become more apparent from the following detailed description of a preferred embodiment, which proceeds with reference to the accompanying drawings. The directional terms mentioned in the following embodiments are, for example: upper, lower, left, right, front or rear, etc., are merely references to the directions of the attached drawings. Thus, the directional terminology is used for purposes of illustration and is not intended to be limiting of the invention.
The application provides a device and a method for saving energy consumption in a memory refreshing process, wherein a word line control signal is processed by a direct signal generating circuit to generate a direct signal, the direct signal is input into a selection signal input path to generate a selection signal, and the time for keeping high potential of the selection signal is shortened compared with that of the direct signal, so that the time for starting overdrive voltage can be shortened, and the energy consumption in the refreshing process is reduced; the application controls the turn-on time of the voltage comparator through the overdrive voltage control signal, when the overdrive voltage starts to supply power to the sensing amplifier, the overdrive voltage charging signal is turned off, the overdrive voltage slowly drops, and after the overdrive voltage finishes supplying power to the sensing amplifier, the overdrive voltage is changed into the drive voltage with lower potential to supply power to the sensing amplifier, so that the overdrive voltage can be prevented from keeping high-potential work for a long time, and the purpose of effectively reducing power consumption is achieved.
Embodiments of the present application will be described in detail below with reference to the attached drawings. However, it will be understood by those of ordinary skill in the art that in various embodiments of the present application, numerous specific details are set forth in order to provide a thorough understanding of the present application. The claimed application may be practiced without these specific details and with various changes and modifications based on the following embodiments.
Fig. 1 is a schematic structural diagram 1 of a device for saving energy consumption in a memory refresh process according to an embodiment of the present application. Comprising the following steps: the word line control signal input end, the logic circuit, the voltage module, the sense amplifier and the storage unit are sequentially connected;
as shown in fig. 1, the word line control signal is processed by the logic circuit to generate an overdrive voltage charging signal, an overdrive voltage control signal and a drive voltage control signal, and the overdrive voltage charging signal, the overdrive voltage control signal and the drive voltage control signal enter the voltage module;
after the activation command is input, the word line control signal is processed by the logic circuit to generate an overdrive voltage control signal, so that the original overdrive voltage starting time is maintained, and the speed of the memory in the activation command is ensured not to be influenced.
After the refresh command is input, the word line control signal is processed by the logic circuit to generate an overdrive voltage control signal with shorter opening time, so that the overdrive voltage can be closed in advance, and the effect of reducing the energy consumption of the memory in the refresh process is achieved.
Fig. 2 is a schematic structural diagram 2 of an apparatus for saving energy in a memory refresh process according to an embodiment of the present application.
As shown in fig. 2, the voltage module includes an overdrive voltage supply circuit including: a voltage comparator, an overdrive voltage controller, and an overdrive voltage and a drive voltage connected with the sense amplifier;
The input end of the voltage comparator is respectively connected with the overdrive voltage reference voltage and the overdrive voltage, the output end of the voltage comparator is connected with the input end of the overdrive voltage controller, and the output end of the overdrive voltage controller is connected with the overdrive voltage circuit;
the voltage comparator controls the overdrive voltage controller to supply power to the sensing amplifier through the overdrive voltage charging signal, and when the overdrive voltage is used for too long, the power supply voltage of the overdrive voltage is reduced, so that the effect of reducing energy consumption is achieved.
Fig. 3 is a schematic structural diagram of an apparatus for saving energy in a memory refresh process according to an embodiment of the present application.
As shown in fig. 3, the logic circuit includes a direct signal generating circuit, a control signal input terminal, and a selector;
the control signal input terminal includes: a direct signal input path, a select signal input path, and a latch signal input path;
The word line control signal input terminal is connected with the input terminal of the direct signal generating circuit, the word line control signal is processed by the direct signal generating circuit to generate a direct signal, and the direct signal is input into the direct signal input path and the selection signal input path.
The overdrive voltage controller comprises a power supply voltage which is higher than the overdrive voltage, and the output end of the voltage comparator is connected to the switching device so as to control the power supply voltage to supply power for the drive voltage; the switching device is an NMOS transistor triggered by high level, the output end of the voltage comparator is connected to the grid electrode of the NMOS transistor, and the switching device is arranged on a circuit with the power supply voltage connected with the overdrive voltage.
Fig. 4 is a partial circuit diagram of an apparatus for saving energy in a memory refresh process according to an embodiment of the present application.
As shown in fig. 4, the control signal input terminal includes: a direct signal input path, a select signal input path, and a latch signal input path;
The selection signal input path comprises a selection circuit, wherein the selection circuit is a delay device, an NOT circuit and an AND circuit which are sequentially connected, and the input end of the AND circuit is respectively connected with the direct signal input path and the output end of the NOT circuit.
The selection signal is generated by processing the direct signal by the delay device to generate a delay signal, inverting the delay signal by the NOT circuit, and processing the delay signal after signal inversion and the direct signal by the AND circuit to generate the selection signal.
The direct signal input path outputs a direct signal;
the selection signal input path comprises a selection circuit, the selection circuit comprises an AND gate circuit, one input end of the AND gate circuit is connected with the direct signal input path, and the output end of the AND gate circuit outputs a selection signal;
The selector selects either the direct signal or the select signal as the overdrive voltage control signal according to the output signal of the latch signal input path.
When the activation command is performed, the activation enable signal generates a high potential signal, the refresh enable signal maintains a low potential state, the latch generates a high potential output signal, and the selector selects a direct signal as an overdrive voltage control signal according to the high potential output signal of the latch signal input path.
When a refresh command is performed, the refresh enable signal generates a high potential signal, the activation enable signal maintains a low potential state, the latch generates a low potential output signal, and the selector selects the selection signal as the overdrive voltage control signal according to the low potential output signal of the latch signal input path.
Fig. 5 is a schematic diagram of an overall circuit of an apparatus for saving energy during a memory refresh according to an embodiment of the present application.
As shown in fig. 5, the direct signal generation circuit includes: the delay device, the NOT circuit and the AND circuit are sequentially connected with the word line control signal input end in sequence, and the input end of the AND circuit is respectively connected with the word line control signal input end and the NOT circuit output end.
The direct signal is generated by processing the word line control signal by the delay device to generate signal delay, then entering the NOT gate to perform signal inversion, and processing the signal subjected to signal inversion and the word line control signal by the AND gate to generate the direct signal.
The selector selects either the direct signal or the select signal as the overdrive voltage control signal according to the output signal of the latch signal input path.
The overdrive voltage control signal is processed by the NOT circuit to generate an overdrive voltage charging signal.
The word line control signal input end outputs a word line control signal, and the word line control signal and the overdrive voltage charging signal are processed by an AND gate circuit to generate a drive voltage control signal.
The word line control signal input terminal is connected with a ground voltage supply signal, the ground voltage supply signal and the word line control signal are input to the row address decoder input terminal, and the row address decoder output terminal is connected to each word line of the memory cell.
As a preferred embodiment of the invention, the delay means in this embodiment are provided as a delay or delay circuit.
According to the scheme, the power consumption in the refreshing process is reduced by switching the overdrive voltage potential into the drive voltage potential in advance.
The direct signal is processed by the selection circuit to generate the selection signal and switch off the overdrive voltage in advance, so that the voltage of the sense amplifier is converted from the overdrive voltage to the drive voltage, and the specific circuit diagram is shown in fig. 5.
Fig. 6 is a graph showing a voltage variation of a sense amplifier of an apparatus for saving power consumption during a memory refresh process according to an embodiment of the present application.
FIG. 6 shows a graph of the voltage change of the sense amplifier after the overdrive voltage control signal is turned off in advance during the modified refresh process and a graph of the voltage change of the sense amplifier after the overdrive voltage control signal is turned off in advance during the refresh process.
A method for saving energy consumption in the process of refreshing a memory, which uses the device in the embodiment, comprises the following steps:
When amplifying using a sense amplifier, a control signal of an overdrive voltage and a driving voltage is required, and the overdrive voltage is affected by the overdrive voltage control signal.
The word line control signal input end is input to the direct signal generating circuit, and the word line control signal is processed by the direct signal generating circuit to generate a direct signal; the direct signal input path, the select signal input path, and the latch signal input path are input to the selector.
The selector is connected with an SR latch, and when the R, S ends of the SR latch are all in low level, the latch keeps the original state unchanged, and the SR latch does not act on the input low level. When an activation command is performed, the latch generates a high-potential output signal, and the selector selects a direct signal as an overdrive voltage control signal; at the time of a refresh command, the latch generates a low potential output signal, and the selector selects the selection signal as an overdrive voltage control signal. In the refresh command and the activate command, the control signals of the overdrive voltages of different sense amplifiers are used, and the overdrive voltages are turned off in advance, so that the energy consumption in the refresh process is reduced.
Fig. 7 is a waveform diagram of signal control under an activation command according to an embodiment of the present application.
Fig. 10 is a waveform diagram of signal control under a refresh command according to an embodiment of the present application.
As shown in fig. 7 or 10, after an activation or refresh command is issued, the word line control signal is turned on, and the word line control signal is processed by the direct signal generating circuit to generate a direct signal; the direct signal serves as a control signal for the initial overdrive voltage.
The word line control signal is processed by the direct signal generating circuit to generate a direct signal in the following manner:
The word line control signal is processed by the delay device to generate signal delay, and enters the NOT gate to perform signal inversion after generating the signal delay, and the signal after signal inversion and the word line control signal are processed by the AND gate to generate a direct signal; the direct signal is input to the direct signal input path and the select signal input path.
The selection signal input path comprises a selection circuit, a direct signal enters the selection circuit, signal inversion is carried out through a NOT gate after signal delay is generated through a delay device, and the inverted signal and the direct signal are processed through an AND gate circuit to generate a selection signal.
The selection signal is a control signal of the overdrive voltage processed by the selection circuit. After logic processing, the direct signal becomes the select signal.
When the activation command is performed, the activation enable signal generates a high-potential signal, and the refresh enable signal maintains a low-potential state. The SR latch outputs an output signal in a high state so that the selector selects a direct signal as the overdrive voltage control signal, and the time of using the overdrive voltage at the time of activation is identical to that before improvement, as shown in fig. 7.
When a refresh command is performed, the refresh enable signal generates a high-level signal, and the activation enable signal maintains a low-level state. The SR latch outputs an output signal in a low state so that the selector selects the selection signal as the overdrive voltage control signal, and the time for which it maintains a high potential is shortened, thereby realizing a lower time for using the overdrive voltage at the time of refresh than before improvement, as shown in fig. 10.
In order to prevent the overdriving voltage from being used excessively long due to the influence of the manufacturing process, the operating voltage and the operating temperature, thereby increasing the power consumption of the sense amplifier, an overdriving voltage charging signal is used for controlling the turn-on of the voltage comparator.
The comparison end of the voltage comparator is respectively input with the reference voltage and the overdrive voltage of the overdrive voltage, the voltage comparator stabilizes and maintains the overdrive voltage near the reference voltage by comparing the reference voltage and the overdrive voltage, and when the start of the sense amplifier is finished, the overdrive voltage driver stops working.
Meanwhile, a capacitor is connected between the overdrive voltage and the grounding end, the capacitor is arranged between the sense amplifier and the overdrive voltage driver, the capacitor can also play a role in supplying power to the sense amplifier, namely, the overdrive voltage driver is used for charging the capacitor, and the capacitor is used for charging the sense amplifier again, so that fluctuation of voltage can be effectively reduced. Meanwhile, the capacitor can discharge in a period of time when the overdrive voltage driver stops working, so that the overdrive voltage potential is ensured to be unchanged or slowly reduced.
In order to allow the overdrive voltage to respond quickly and charge quickly, the overdrive voltage should not drop too much, i.e. the voltage comparator will not be turned off for a long time.
Referring to a specific structure of an overdrive voltage controller in fig. 2, the overdrive voltage controller includes a switching device, the switching device is a high-level triggered NMOS transistor, an output terminal of the voltage comparator is connected to a gate of the NMOS, and the switching device is disposed on a circuit for connecting a power supply voltage with the overdrive voltage, wherein the power supply voltage has a higher potential than the overdrive voltage, and can charge the overdrive voltage to a potential of a reference voltage after the switching device is triggered. The circuit of the power supply voltage connected with the driving voltage is also provided with a grounding inductor.
In order to control the power supply duration of the overdrive voltage, a circuit of overdrive voltage charging signal control circuit is also arranged on the existing signal control circuit, and the overdrive voltage charging signal is used for controlling the opening and closing of the voltage comparator.
The overdrive voltage control signal is processed by the NOT gate circuit to generate an overdrive voltage charging signal, and the overdrive voltage charging signal and the word line control signal are combined to control the starting of the drive voltage; after the overdrive voltage is turned off, the corresponding drive voltage control signal becomes a high potential state, and the drive voltage supplies power to the sense amplifier.
After the activation command is input, the sense amplifier is started, the overdrive voltage charging signal controls the voltage comparator to start working, signals are output to the switching device, and the power supply voltage is controlled to charge the overdrive voltage to the reference voltage potential; when the driving voltage is the working of the sensing amplifier, the overdrive voltage charging signal turns off the output, and the overdrive voltage potential slowly drops; the word line control signal is connected with the ground voltage power supply signal and input to the row address decoder, and the row address decoder outputs to each word line of the memory cell. Wherein the word line control signal is high triggered. When the signal circuit starts to work, the word line control signal outputs a high level, the ground voltage power supply signal is triggered by the high level, and at the moment, the ground voltage power supply signal is output.
The overdrive voltage charging signal is used for controlling the overdrive voltage power supply circuit, so that the potential of the overdrive voltage can be reduced when the overdrive voltage supplies power to the sense amplifier of the memory array, thereby reducing the power consumption of the sense amplifier. When the overdrive voltage supplies power to the sense amplifier, the overdrive voltage charging signal is turned off to enable the potential of the overdrive voltage to slowly drop, and after the overdrive voltage stops supplying power to the sense amplifier, the overdrive voltage charging signal is turned on to enable the potential of the overdrive voltage to return to the reference potential value. When the potential of the overdrive voltage is higher than the reference voltage, the voltage comparator outputs a low level, the power supply voltage stops supplying power to the overdrive voltage, and the potential of the overdrive voltage is slowly reduced.
The overdrive voltage control signal is processed by the NOT gate circuit to generate an overdrive voltage charging signal, the word line control signal and the overdrive voltage charging signal are processed by the AND gate circuit to generate a drive voltage control signal, when the sense amplifier works, the control signals of the overdrive voltage and the drive voltage are needed, meanwhile, the drive voltage is started after the overdrive voltage is closed, and the corresponding drive voltage control signal becomes a high potential state.
Fig. 8 shows another signal control circuit according to an embodiment of the present application, in order to control the power supply duration of the overdrive voltage, an overdrive voltage charging signal control circuit is provided, where the overdrive voltage charging signal is used to control the on and off of the voltage comparator. Referring specifically to fig. 8, the control signal circuit diagram in fig. 8 includes a word line control signal at an input terminal and a ground voltage supply signal, an overdrive voltage control signal, a driving voltage control signal, a word line signal, and an overdrive voltage charging signal at an output terminal connected to the word line control signal, respectively. When the signal circuit starts to work, the word line control signal outputs a high level, after the signal passes through the internal delay circuit 1, the high level signal reaches the output end of the ground voltage power supply signal after the delay time 1 (the time corresponding to the delay circuit 1), the ground voltage power supply signal is triggered by the high level, and at the moment, the ground voltage power supply signal is output.
When the word line control signal outputs a high level, after the delay time 1 of the delay circuit 1, the input end of the and gate is at a high level, the and gate outputs a high level to the overdrive voltage control signal, and the overdrive voltage control signal starts to be output after being triggered. In order to ensure the integrity of the time sequence, the delay time 1 and the delay time 2 should be continuous, after the delay time 1, both ends of the and gate circuit are high-level input in the period of the delay time 2, and the and gate outputs high level to the overdrive voltage control signal, and at this time, the overdrive voltage control signal starts to be output. After the delay time 2 of the delay circuit 2, the NOT circuit on the delay circuit 2 outputs a low level to the AND gate circuit, the input end of the AND gate circuit is a low level and a high level, and the AND gate circuit outputs a high level to the overdrive voltage control signal.
Fig. 9 is a schematic diagram showing pulse width of each waveform of each signal in the circuit diagram of fig. 8.
Referring specifically to the pulse width diagram of fig. 9, the overdrive voltage control signal is triggered high for the delay time 2, at which time the overdrive voltage powers the sense amplifier. The output principle of the driving voltage control signal is the same as that of the overdrive voltage control signal, and will not be described here again.
The overdrive voltage charging signal comprises two paths, wherein one path is connected to the delay circuit 3 after passing through the delay circuit 1 from the word line control signal, and is connected with a NOT gate circuit and finally connected to the NOT gate circuit, the other path is directly connected to the NOT gate circuit from the word line control signal, and finally the output end of the NOT gate is the overdrive voltage charging signal. The principle of controlling the power supply duration of the overdrive voltage is as follows: the input end of the NAND gate circuit at the output end of the overdrive voltage charging signal is always a high level signal, the NAND gate circuit outputs a high level to the NAND gate circuit only in the delay time 1 and the delay time 3 of the delay circuit 1 and the delay time 3 after the word line control signal becomes a high level, at this time, the NAND gate circuit outputs a low level, the overdrive voltage charging signal stops outputting, and the overdrive voltage charging signals at other times are all high level outputs. That is, the overdrive voltage charging signal does not turn on the voltage comparator only during the delay time 1 and the delay time 3. Referring to fig. 9, in order to ensure the continuity of the timing, delay time 1 and delay time 3 are continuous, and delay time 3 is longer than delay time 2. At this time, in delay time 1+delay time 3, the overdrive voltage charging signal is turned off, delay time 2 is the on time of the overdrive voltage control signal, the voltage comparator is not turned on in a period of time before and after delay time 2, the power supply voltage stops charging the overdrive voltage, and in delay time 2, the overdrive voltage supplies power to the sense amplifier through the capacitor, the potential thereof is slowly reduced, so as to reduce the energy consumption in delay time 2 (due to the manufacturing process, the delay circuit voltage and the temperature). Until the delay time 3 has elapsed, the supply voltage supplies power to the overdrive voltage so that the overdrive voltage potential remains until the arrival of the next charging cycle.
In summary, the application provides a device and a method for saving energy consumption in a memory refreshing process, a word line control signal is processed by a direct signal generating circuit to generate a direct signal, the direct signal is input into a selection signal input path to generate a selection signal, the time for keeping high potential of the selection signal is shortened compared with that of the direct signal, so that the effect of shortening the starting time of overdrive voltage is achieved, the overdrive voltage can be closed in advance in the refreshing process, and the data is not required to be quickly amplified because the reading and writing operations are not required in the refreshing process, so that the energy consumption in the refreshing process is reduced by shortening the starting time of the overdrive voltage potential of a sense amplifier in the refreshing process; the application controls the turn-on time of the voltage comparator through the overdrive voltage control signal, when the overdrive voltage starts to supply power to the sensing amplifier, the overdrive voltage charging signal is turned off, the overdrive voltage slowly drops, and after the overdrive voltage finishes supplying power to the sensing amplifier, the overdrive voltage charging signal is turned on, so that the potential of the overdrive voltage returns to the reference potential value, and the overdrive voltage is changed into the drive voltage with lower potential to supply power to the sensing amplifier, thereby avoiding the overdrive voltage from keeping high potential work for a long time and further achieving the purpose of effectively reducing the power consumption.
The use of certain conventional english terms or letters for the sake of clarity of description of the invention is intended to be exemplary only and not limiting of the interpretation or particular use, and should not be taken to limit the scope of the invention in terms of its possible chinese translations or specific letters.
It should also be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
Claims (14)
1. An apparatus for saving energy during a memory refresh process, comprising:
a word line control signal input, a direct signal generation circuit, a control signal input, and a selector; the control signal input end comprises a direct signal input path, a selection signal input path and a latch signal input path;
the word line control signal input end is connected with the input end of the direct signal generating circuit, the word line control signal is processed by the direct signal generating circuit to generate a direct signal, and the direct signal is input to the direct signal input path and the selection signal input path;
the direct signal input path outputs a direct signal;
The selector controls the selection signal input path to output a direct signal or a selection signal as an overdrive voltage control signal according to the output signal of the latch signal input path.
2. The apparatus of claim 1, wherein the selection signal input path comprises a selection circuit comprising an and circuit having an input coupled to the direct signal input path and an output outputting the selection signal.
3. The apparatus of claim 2, wherein the selection circuit is a delay device, a not gate, and an and gate connected in sequence, and the input terminal of the and gate is connected to the direct signal input path and the output terminal of the not gate, respectively.
4. A device for saving energy in a memory refresh process according to claim 3, wherein the selection signal is generated by processing the direct signal by the delay device to generate a delay signal, inverting the delay signal by the nor circuit, and processing the delayed signal after signal inversion and the direct signal by the and circuit to generate the selection signal.
5. An apparatus for saving energy during a memory refresh according to claim 1, wherein the direct signal generating circuit comprises:
the delay device, the NOT circuit and the AND circuit are sequentially connected with the word line control signal input end in sequence, and the AND circuit input end is respectively connected with the word line control signal input end and the NOT circuit output end.
6. The device for saving energy in a memory refresh process according to claim 5, wherein the direct signal is generated by generating a signal delay after the word line control signal is processed by a delay device, generating a signal delay, then entering a not gate circuit for signal inversion, and generating the direct signal after the signal inversion and the word line control signal are processed by an and gate.
7. A device for saving energy during a memory refresh according to claim 3 or 5, wherein the delay means is arranged as a delay or delay circuit.
8. The apparatus for saving power in a memory refresh process according to claim 4, wherein the enable signal is activated to generate a high potential signal, the refresh enable signal is kept in a low potential state, the latch generates a high potential output signal, and the selector selects the direct signal as the overdrive voltage control signal according to the high potential output signal of the latch signal input path.
9. The apparatus for saving power in a memory refresh process according to claim 4, wherein the refresh enable signal generates a high potential signal, the enable signal is activated to maintain a low potential state, the latch generates a low potential output signal, and the selector selects the selection signal as the overdrive voltage control signal according to the low potential output signal of the latch signal input path when the refresh command is performed.
10. The apparatus for saving energy during a memory refresh process of claim 1, further comprising a voltage module, a sense amplifier, and a memory cell connected in sequence;
the voltage module includes an overdrive voltage supply circuit including: the voltage comparator, the overdrive voltage controller, the overdrive voltage circuit and the drive voltage circuit are connected with the sense amplifier;
The input end of the voltage comparator is respectively input with an overdrive voltage reference voltage and an overdrive voltage, the output end of the voltage comparator is connected to the input end of the overdrive voltage controller, and the output end of the overdrive voltage controller is connected with the overdrive voltage circuit;
The voltage comparator controls the overdrive voltage controller to supply power to the sense amplifier through the overdrive voltage charging signal.
11. The apparatus for saving energy during a memory refresh of claim 10, wherein the overdrive voltage controller includes a power supply voltage that is higher than the overdrive voltage, the voltage comparator output being coupled to a switching device to thereby control the power supply voltage to power the drive voltage;
the switching device is a MOS transistor, the output end of the voltage comparator is connected to the grid electrode of the MOS transistor, and the switching device is arranged on a circuit with the power supply voltage connected with the overdrive voltage.
12. The apparatus for saving energy during a memory refresh of claim 10, further comprising a signal control circuit, the signal control circuit comprising a word line control signal input;
the word line control signal and the overdrive voltage charging signal are processed by an AND gate circuit to generate the drive voltage control signal;
The word line control signal input end is connected with a ground voltage power supply signal, the ground voltage power supply signal and the word line control signal are input to a row address decoder input end, and the row address decoder output end is connected to each word line of the memory unit.
13. A method of saving energy during a memory refresh, characterized in that an arrangement of saving energy during a memory refresh is used according to any of the claims 1-12, comprising the steps of:
the word line control signal input end is input to the direct signal generation circuit, and the word line control signal is processed by the direct signal generation circuit to generate a direct signal;
the direct signal input path, the selection signal input path and the latch signal input path are input to the selector;
The word line control signal is processed by a delay device to generate signal delay, the signal delay is generated and enters an NOT gate to perform signal inversion, and the signal after signal inversion and the word line control signal are processed by an AND gate to generate the direct signal; the direct signal is input to the direct signal input path and the selection signal input path;
The selection signal input path comprises a selection circuit, the direct signal enters the selection circuit, signal delay is generated through a delayer, signal inversion is performed through an NOT gate, and the inverted signal and the direct signal are processed through the AND gate to generate a selection signal;
When an activation command is performed, the latch generates a high-potential output signal, and the selector selects a direct signal as an overdrive voltage control signal; the latch generates a low potential output signal when a refresh command is performed, and the selector selects the selection signal as an overdrive voltage control signal;
the overdrive voltage control signal is processed by the NOT circuit to generate the overdrive voltage charging signal.
14. The method of claim 13, wherein after the command input is activated, when the sense amplifier is turned on, the overdrive voltage charge signal controls the voltage comparator to turn on, outputs a signal to the switching device, and controls the power supply voltage to charge the overdrive voltage to the reference voltage level;
when the driving voltage is the working of the sensing amplifier, the overdrive voltage charging signal turns off the output, and the overdrive voltage potential slowly drops;
the word line control signal is connected with the ground voltage power supply signal and is input to the row address decoder, and the row address decoder outputs the word line control signal to each word line of the memory unit.
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