CN118038796A

CN118038796A - Screen refresh rate adjusting device and related equipment

Info

Publication number: CN118038796A
Application number: CN202211415560.4A
Authority: CN
Inventors: 梁博; 李霄; 贺虎
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-11-11
Filing date: 2022-11-11
Publication date: 2024-05-14
Also published as: WO2024099127A1

Abstract

The embodiment of the application discloses a device for adjusting a screen refresh rate and related equipment. The device comprises a frequency adjusting circuit group; each frequency adjustment circuit in the frequency adjustment circuit group comprises a first input end, a second input end and an output end; the first input end of each frequency adjusting circuit is connected with the control circuit, the second input end of each frequency adjusting circuit is connected with a corresponding GOA circuit in the gate driving GOA circuit group, and the output end of each frequency adjusting circuit is connected with a corresponding AA pixel circuit in the AA pixel circuit group of the display area. By using the embodiment of the application, different refresh rate adjustment can be realized aiming at different display areas on the screen, thereby not only meeting the requirements of users on fluency, but also avoiding unnecessary power consumption waste.

Description

Screen refresh rate adjusting device and related equipment

Technical Field

The present application relates to the field of electronic technologies, and in particular, to a device for adjusting a screen refresh rate and a related device.

Background

Most of the existing terminal equipment can realize dynamic frame rate display, namely, the refresh rate of a screen can be dynamically adjusted. For example, when the user turns on the reading software but does not operate, the refresh rate of the entire screen may be the lowest refresh rate (e.g., 1 Hz), and when the user continues to slide the screen to read quickly, the refresh rate of the entire screen may be increased to the highest refresh rate (e.g., 120 Hz).

However, with the continuous development of terminal products, the use scenes are more and more changeable. Such as the "parallel view" function of a tablet product, most of the display area of one half of the screen is stationary and the other half of the display area may dynamically change as the user browses and slides during use. For another example, the "picture-in-picture" function of the mobile phone product, the user may hover the video displayed in the upper half of the screen while the other display areas of the screen may be the reading area, etc.

Therefore, how to implement adjustment of different refresh rates on different areas of the same light-emitting diode (LED) panel (i.e., on different display areas of one screen) according to the actual needs of the user is a problem to be solved.

Disclosure of Invention

The embodiment of the application provides a device and related equipment for adjusting the refresh rate of a screen, which can realize different refresh rate adjustment aiming at different display areas on the screen, thereby not only meeting the requirements of users on fluency, but also avoiding unnecessary power consumption waste.

In a first aspect, an embodiment of the present application provides a device for adjusting a refresh rate of a screen, where the device includes a frequency adjustment circuit group; each frequency adjustment circuit in the frequency adjustment circuit group comprises a first input end, a second input end and an output end; the first input end of each frequency adjusting circuit is connected with the control circuit, the second input end of each frequency adjusting circuit is connected with a corresponding GOA circuit in the gate driving GOA circuit group, and the output end of each frequency adjusting circuit is connected with a corresponding AA pixel circuit in the AA pixel circuit group of the display area.

In one possible implementation, the frequency adjustment circuit group includes K first frequency adjustment circuits, and the GOA circuit group includes K indium gallium zinc oxide IGZO GOA circuits; the first input ends of the K first frequency adjusting circuits are connected with the control circuit, the second input ends of the K first frequency adjusting circuits are connected with the output ends of the K IGZO GOA circuits in a one-to-one correspondence mode, and the output ends of the K first frequency adjusting circuits are connected with corresponding AA pixel circuits; k is an integer greater than 1.

In one possible embodiment, the control circuit is configured to output a plurality of enable signals to the K first frequency adjustment circuits, where high level frequencies of the plurality of enable signals are different; an ith first frequency adjustment circuit for receiving one of the plurality of enable signals and receiving a first pulse signal output by a corresponding ith IGZO GOA circuit; i=1, 2, 3, … …, K; the ith first frequency adjusting circuit is further configured to adjust the first pulse signal based on the enable signal to obtain a second pulse signal, and output the second pulse signal to a corresponding AA pixel circuit; the screen refresh rate corresponding to the AA pixel circuit is the same as the frequency of the received second pulse signal.

In a possible implementation manner, the frequency adjusting circuit group further comprises P second frequency adjusting circuits, and the GOA circuit group further comprises P low-temperature polysilicon LTPS GOA circuits; the first input ends of the P second frequency adjusting circuits are connected with the control circuit, the second input ends of the P second frequency adjusting circuits are connected with the output ends of the P LTPS GOA circuits in a one-to-one correspondence manner, and the output ends of the P second frequency adjusting circuits are connected with corresponding AA pixel circuits; p is an integer greater than 1.

In one possible embodiment, the control circuit is configured to output a plurality of enable signals to the P second frequency adjustment circuits, where low level frequencies of the plurality of enable signals are different; a j second frequency adjustment circuit, configured to receive one of the enable signals, and receive a third pulse signal output by a corresponding j LTPS GOA circuit; j=1, 2, 3, … …, P; the j second frequency adjusting circuit is further configured to adjust the third pulse signal based on the enable signal to obtain a fourth pulse signal, and output the fourth pulse signal to a corresponding AA pixel circuit; the screen refresh rate corresponding to the AA pixel circuit is the same as the frequency of the received fourth pulse signal.

In one possible implementation, the first frequency adjustment circuit includes a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6; the first input end of the first frequency adjusting circuit is connected with the grid electrode of the transistor T1 and the grid electrode of the transistor T4; the second input end of the first frequency adjusting circuit is connected with the grid electrode of the transistor T2 and the grid electrode of the transistor T3; the output end of the first frequency adjusting circuit is connected with the drain electrode of the transistor T5 and the drain electrode of the transistor T6; the source electrode of the transistor T1 is connected with the source electrode of the transistor T2 and the source electrode of the transistor T5; the drain of the transistor T1 is connected with the drain of the transistor T2, the drain of the transistor T3, the gate of the transistor T5 and the gate of the transistor T6; the source of the transistor T3 is connected with the drain of the transistor T4; the source of the transistor T4 is connected to the source of the transistor T6.

In one possible implementation manner, the transistors T1, T2 and T5 are P-type low-temperature polysilicon LTPS thin film transistors TFT; the transistors T3, T4 and T6 are N-type LTPS TFTs.

In one possible implementation, the second frequency adjustment circuit includes a transistor T7, a transistor T8, a transistor T9, a transistor T10, a transistor T11, a transistor T12; the first input end of the second frequency adjusting circuit is connected with the grid electrode of the transistor T7 and the grid electrode of the transistor T9; the second input end of the second frequency adjusting circuit is connected with the grid electrode of the transistor T8 and the grid electrode of the transistor T10; the output end of the second frequency adjusting circuit is connected with the drain electrode of the transistor T11 and the drain electrode of the transistor T12; the source of the transistor T7 is connected with the source of the transistor T11; the drain electrode of the transistor T7 is connected with the source electrode of the transistor T8; the drain of the transistor T8 is connected with the drain of the transistor T9, the drain of the transistor T10, the gate of the transistor T11 and the gate of the transistor T12; the source of the transistor T9 is connected to the source of the transistor T10 and the source of the transistor T12.

In one possible implementation, the transistors T7, T8, T11 are P-type LTPS TFTs; the transistors T9, T10 and T12 are N-type LTPS TFTs.

In one possible implementation, the first frequency adjustment circuit includes a transistor T13, a transistor T14; the IGZO GOA circuit includes a transistor T15; wherein the first input end of the first frequency adjusting circuit is connected with the source electrode of the transistor T13, and the second input end of the first frequency adjusting circuit is connected with the grid electrode of the transistor T14; the output end of the first frequency adjusting circuit is connected with the drain electrode of the transistor T13 and the drain electrode of the transistor T14; the gate of the transistor T13 is connected to the gate of the transistor T15 in the corresponding IGZO GOA circuit.

In one possible implementation, the first frequency adjustment circuit further includes a capacitor C1; one end of the capacitor C1 is connected to the gate of the transistor T14, and the other end of the capacitor C1 is connected to the drain of the transistor T13 and the drain of the transistor T14.

In one possible implementation, the second frequency adjustment circuit includes a transistor T16, a transistor T17, and a capacitor C2; the LTPS GOA circuit includes a transistor T18; wherein the first input end of the second frequency adjusting circuit is connected with the source electrode of the transistor T17, and the second input end of the second frequency adjusting circuit is connected with the gate electrode of the transistor T17; the output end of the first frequency adjusting circuit is connected with the drain electrode of the transistor T16 and the drain electrode of the transistor T17; one end of the capacitor C2 is connected with the gate of the transistor T17, and the other end of the capacitor C2 is connected with the drain of the transistor T16 and the drain of the transistor T17; the gate of the transistor T16 is connected to the gate of the transistor T18 in the LTPS GOA circuit, and the source of the transistor T16 is connected to the source of the transistor T18.

By the method provided in the first aspect, a frequency adjusting circuit is arranged between each AA pixel circuit and each GOA circuit, and the frequency adjusting circuit can adjust the frequency of the output signal of the GOA circuit under the action of the enabling signal output by the control circuit, and the adjusted signal is input into the AA pixel circuit. Thus, the embodiment of the application can realize different refresh rates in different areas of one screen. Therefore, various application scenes can be matched, the high refresh rate is provided in the local area with the high refresh rate, and meanwhile, the low refresh rate is provided in the local area without the high refresh rate, so that the actual requirements of users are met, the power consumption of the display driver integrated chip and the SoC (system on chip) is saved, and unnecessary power consumption waste is avoided.

In a second aspect, an embodiment of the present application provides a method for adjusting a screen refresh rate, which is applied to a terminal device, where the terminal device includes an adjusting device for screen refresh rate; the apparatus includes a frequency adjustment circuit set; each frequency adjustment circuit in the frequency adjustment circuit group comprises a first input end, a second input end and an output end; the first input end of each frequency adjusting circuit is connected with a control circuit, the second input end of each frequency adjusting circuit is connected with a corresponding GOA circuit in a gate driving GOA circuit group, and the output end of each frequency adjusting circuit is connected with a corresponding AA pixel circuit in a display area AA pixel circuit group; the method comprises the following steps:

Outputting a plurality of enable signals to the frequency adjustment circuit group through the control circuit; the high level frequency or the low level frequency of the plurality of enable signals is different; receiving, by each frequency adjustment circuit in the set of frequency adjustment circuits, one of the plurality of enable signals, and receiving a pulse signal output by a corresponding GOA circuit; adjusting the pulse signals based on the enabling signals through each frequency adjusting circuit to obtain adjusted pulse signals, and outputting the adjusted pulse signals to corresponding AA pixel circuits; the screen refresh rate corresponding to the AA pixel circuit is the same as the frequency of the received adjusted pulse signal.

In one possible implementation, the frequency adjustment circuit group includes K first frequency adjustment circuits, and the GOA circuit group includes K indium gallium zinc oxide IGZO GOA circuits; the first input ends of the K first frequency adjusting circuits are connected with the control circuit, the second input ends of the K first frequency adjusting circuits are connected with the output ends of the K IGZO GOA circuits in a one-to-one correspondence mode, and the output ends of the K first frequency adjusting circuits are connected with corresponding AA pixel circuits; k is an integer greater than 1; the method specifically comprises the following steps:

Outputting a plurality of enable signals to the K first frequency adjusting circuits through the control circuit, wherein the high level frequencies of the plurality of enable signals are different; receiving, by an ith first frequency adjustment circuit, one of the plurality of enable signals, and receiving a first pulse signal output by a corresponding ith IGZO GOA circuit; i=1, 2,3, … …, K; the first pulse signal is adjusted based on the enabling signal through an ith first frequency adjusting circuit to obtain a second pulse signal, and the second pulse signal is output to a corresponding AA pixel circuit; the screen refresh rate corresponding to the AA pixel circuit is the same as the frequency of the received second pulse signal.

In a possible implementation manner, the frequency adjusting circuit group further comprises P second frequency adjusting circuits, and the GOA circuit group further comprises P low-temperature polysilicon LTPS GOA circuits; the first input ends of the P second frequency adjusting circuits are connected with the control circuit, the second input ends of the P second frequency adjusting circuits are connected with the output ends of the P LTPS GOA circuits in a one-to-one correspondence manner, and the output ends of the P second frequency adjusting circuits are connected with corresponding AA pixel circuits; p is an integer greater than 1; the method specifically comprises the following steps:

Outputting, by the control circuit, a plurality of enable signals to the P second frequency adjustment circuits, the plurality of enable signals having different low level frequencies; receiving one of the plurality of enable signals through a j-th second frequency adjusting circuit, and receiving a third pulse signal output by a corresponding j-th LTPS GOA circuit; j=1, 2,3, … …, P; the j second frequency adjusting circuit is used for adjusting the third pulse signal based on the enabling signal to obtain a fourth pulse signal, and outputting the fourth pulse signal to the corresponding AA pixel circuit; the screen refresh rate corresponding to the AA pixel circuit is the same as the frequency of the received fourth pulse signal.

It should be appreciated that, in the method provided in the second aspect of the present application, the technical solution of the first aspect of the present application is consistent, and the specific content and the beneficial effects thereof may refer to an adjusting device for a screen refresh rate provided in the first aspect, which is not described herein.

In a third aspect, an embodiment of the present application provides a terminal device, where the terminal device includes a screen, where the screen includes a display area AA pixel circuit group and the screen refresh rate adjusting device according to any one of the first aspect, and the AA pixel circuit group is connected to the screen refresh rate adjusting device; the terminal device further comprises a processor and a memory which are connected with the screen.

The terminal device may be an intelligent wearable device, a smart phone, a tablet computer, a notebook computer, a desktop computer, a vehicle-mounted computer, and a household appliance with a screen, such as a television, a refrigerator with a display screen, and the like, or may be an intelligent robot with a screen, and the embodiment of the application is not limited in particular.

In a fourth aspect, an embodiment of the present application provides a terminal device, where the terminal device includes a processor configured to support the terminal device to perform a corresponding function in the method for adjusting a screen refresh rate according to any one of the second aspects. The terminal device may also include a memory for coupling with the processor, which holds the program instructions and data necessary for the terminal device. The terminal device may also include a communication interface for the terminal device to communicate with other devices or a communication network.

In a fifth aspect, an embodiment of the present application provides a computer readable storage medium storing a computer program, where the computer program when executed by a processor implements the method flow for adjusting a screen refresh rate according to any one of the second aspects.

In a sixth aspect, an embodiment of the present application provides a computer program, the computer program including instructions that, when executed by a computer, cause the computer to perform the method flow of adjusting a screen refresh rate according to any one of the second aspects.

In a seventh aspect, an embodiment of the present application provides a chip, where the chip includes a processor and a communication interface, where the processor is configured to invoke and execute instructions from the communication interface, and when the processor executes the instructions, cause the chip to execute the method flow for adjusting a screen refresh rate according to any one of the second aspects.

In an eighth aspect, an embodiment of the present application provides a chip system, where the chip system includes the device for adjusting a screen refresh rate according to any one of the first aspects, and the device is configured to implement a function related to a flow of any one of the methods for adjusting a screen refresh rate provided in the second aspect. In one possible design, the system-on-chip further includes a memory for storing program instructions and data necessary for the method of adjusting the screen refresh rate. The chip system can be composed of chips, and can also comprise chips and other discrete devices.

Drawings

FIG. 1 is a schematic diagram of dynamic adjustment of screen refresh rate.

FIG. 2 is a schematic diagram of another dynamic adjustment of screen refresh rate.

Fig. 3 is a schematic circuit diagram of adjusting a refresh rate of a screen according to an embodiment of the present application.

Fig. 4 is a schematic diagram of another circuit structure for adjusting a refresh rate of a screen according to an embodiment of the present application.

Fig. 5 is a schematic structural diagram of a device for adjusting a screen refresh rate according to an embodiment of the present application.

Fig. 6 is a schematic structural diagram of a frequency adjustment circuit according to an embodiment of the present application.

Fig. 7 is a schematic diagram of a VFR circuit for IGZO GOA according to an embodiment of the present application.

Fig. 8 is a schematic diagram of another VFR circuit for IGZO GOA according to an embodiment of the present disclosure.

Fig. 9 is a schematic diagram of a VFR circuit for an IGZO GOA according to an embodiment of the present application.

FIG. 10 is a schematic diagram of a VFR circuit for LTPS GOA according to one embodiment of the present application.

FIG. 11 is a schematic diagram of another VFR circuit for LTPS GOA according to one embodiment of the present application.

Fig. 12 is a schematic diagram of frequency adjustment of a pulse signal according to an embodiment of the present application.

Fig. 13 is a schematic diagram of frequency adjustment of a pulse signal according to an embodiment of the present application.

Fig. 14 is a schematic diagram showing an effect of screen refresh rate adjustment according to an embodiment of the present application.

Fig. 15 is a schematic diagram of an overall circuit structure for adjusting a refresh rate of a screen according to an embodiment of the present application.

FIG. 16 is a schematic diagram showing the effect of another screen refresh rate adjustment provided by an embodiment of the present application.

FIG. 17 is a schematic diagram showing the effect of still another screen refresh rate adjustment provided by an embodiment of the present application.

Fig. 18 is a flowchart of a method for adjusting a screen refresh rate according to an embodiment of the present application.

Detailed Description

Embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application.

The terms first and second and the like in the description and in the claims and in the drawings are used for distinguishing between different objects and not for describing a particular sequential order. Furthermore, the terms "comprising," "including," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus. It will be understood that when an element is referred to as being "coupled" to "or" connected "to another element or elements, it can be directly or indirectly connected to the other element or elements.

It should be understood that in the present application, "at least one (item)" means one or more, and "a plurality" means two or more. "and/or" for describing the association relationship of the association object, the representation may have three relationships, for example, "a and/or B" may represent: only a, only B and both a and B are present, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b or c may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or plural.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein may be combined with other embodiments.

As used in this specification, the terms "component," "module," "system," and the like are intended to refer to a computer-related entity, either hardware, firmware, a combination of hardware and software, or software in execution. For example, a component may be, but is not limited to being, a process running on a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a processor and the processor can be a component. One or more components may reside within a process and/or thread of execution and a component may be localized on one computer and/or distributed between 2 or more computers. Furthermore, these components can execute from various computer readable media having various data structures stored thereon. The components may communicate by way of local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from two components interacting with one another in a local system, distributed system, and/or across a network such as the internet with other systems by way of the signal).

First, in order to facilitate understanding of the embodiments of the present application, technical problems to be solved by the present application are further analyzed and presented. In the prior art, regarding dynamic adjustment of the screen refresh rate, various technical schemes are included, and the following exemplary two schemes are listed.

Scheme one:

Referring to fig. 1, fig. 1 is a schematic diagram showing dynamic adjustment of a screen refresh rate. As shown in fig. 1, a terminal device (for example, a tablet computer) includes a screen 10, which turns on a "parallel view" function in response to a user operation, and the screen 10 includes two display areas of a primary catalog 101 and a secondary catalog 102.

As shown in fig. 1, if the terminal device does not receive any operation by the user, the refresh rate of the screen 10 may be 1Hz (for example, the lowest refresh rate supported by the screen 10), that is, the refresh rates of the display areas of the primary catalog 101 and the secondary catalog 102 are both 1Hz.

As shown in fig. 1, if the terminal device receives a sliding operation of the user on the secondary catalog 102, the refresh rate of the screen 10 may be increased from 1Hz to 120Hz (for example, the highest refresh rate supported by the screen 10), that is, the refresh rates of the display areas of the primary catalog 101 and the secondary catalog 102 are both 120Hz.

Scheme II:

referring to fig. 2, fig. 2 is a schematic diagram showing another dynamic adjustment of the screen refresh rate. As shown in fig. 2, when a terminal device (for example, a smart phone) includes a screen 10, the terminal device turns on a "picture-in-picture" video hover function in response to a user operation, the screen 10 includes two display areas, that is, a video area 103 and a reading area 104.

As shown in fig. 2, if the terminal device does not receive any operation by the user and the frame rate of the currently playing video is 60fps, the refresh rate of the screen 10 is 60Hz, that is, the refresh rates of the video area 103 and the reading area 104 are 60Hz. Or if the frame rate of the currently playing video is 30fps, the refresh rate of the screen 10 may be 30Hz, i.e. in case the terminal device does not receive any operation of the user, the refresh rate of the screen 10 may be determined by the frame rate of the currently playing video.

As shown in fig. 2, when the terminal device receives a sliding operation of the user with respect to the reading area 104, the refresh rate of the screen 10 may be raised from 60Hz (or 30 Hz) to 120Hz (e.g., the highest refresh rate supported by the screen 10), i.e., the refresh rates of the video area 103 and the reading area 104 are both 120Hz.

As described above, although both the first and second schemes can realize dynamic adjustment of the refresh rate of the screen, both schemes can adjust the refresh rate of the entire screen when adjusting the refresh rate, and cannot respectively realize different refresh rate adjustment for different display areas in the screen, so that the application requirements of users for different display areas in the screen cannot be practically and flexibly met, and unnecessary power consumption waste is easily caused.

Therefore, in order to solve the problem that the current dynamic adjustment of the screen refresh rate does not meet the actual service requirement, the technical problem to be actually solved by the application includes the following aspects: a frequency adjustment circuit (e.g., a Variable Frame Rate (VFR) circuit) is provided between a display area (ACTIVE AREA, AA) pixel circuit and a gate drive (GOA) circuit of the screen. And, the VFR circuit is controlled to adjust the pulse signal output from the GOA circuit to the AA pixel circuit (for example, adjust the frequency of the pulse signal) by a corresponding variable frame rate enable (variable frequency _enable) signal, so as to respectively adjust different refresh rates for different display areas in the screen. And then, under the condition of ensuring the use experience of the user, the requirements of the user on the fluency of the high refresh rate are met, and the power consumption of the part with the low refresh rate is saved.

Referring to fig. 3, fig. 3 is a schematic circuit diagram of adjusting a refresh rate of a screen according to an embodiment of the application. As shown in fig. 3, taking the circuit connection of one side of the LED display as an example, the circuit may include EGOA circuits, VFR circuits, and AA pixel circuits. As shown in fig. 3, the EGOA circuit may include a low-temperature polysilicon (low-temperature polycrystalline silicon, LTPS) GOA circuit, an indium gallium zinc oxide (indium gallium zinc oxide, IGZO) GOA circuit, and an emission driving (EOA) circuit. It will be appreciated that an LED display screen typically includes a plurality of AA pixel circuits, each of which may be connected with a corresponding VFR circuit and GOA circuit as shown in fig. 3, to enable individual refresh rate control for each AA pixel circuit.

LTPSGOA circuit for outputting pulse signal for turning on the P type semiconductor device to control LTPS thin film transistor (thin film transistor, TFT) in the AA pixel circuit, thereby controlling corresponding screen refresh rate of the AA pixel circuit.

IGZOGOA circuit for outputting pulse signal for turning on N type semiconductor device to control IGZO TFT in AA pixel circuit, and further control corresponding screen refresh rate of AA pixel circuit.

And an emission drive (EOA) circuit for outputting a pulse signal for turning on the N-type semiconductor device (the pulse signal is specifically a pulse signal for adjusting the light emitting duty ratio and thus the display brightness) so as to control an Emission (EM) TFT in the AA pixel circuit and thus control the corresponding screen refresh rate of the AA pixel circuit.

It should be noted that, in general, the pulse signal output to the AA pixel circuit by the IGZOGOA circuit can adjust the screen refresh rate, and further, the pulse signal output to the AA pixel circuit by the LTPSGOA circuit can be combined to adjust the screen refresh rate. Alternatively, if the pulse signal frequencies of the two are different, the screen refresh rate is generally adjusted based on the pulse signal output by the IGZO GOA circuit. In some possible embodiments, when the LED display is in Direct Current (DC) mode, the screen refresh rate may also be adjusted based on the pulse signal output from the EOA to the AA pixel circuit, and so on, which is not particularly limited by the embodiment of the present application.

As shown in fig. 3, an embodiment of the present application is implemented by providing a corresponding VFR circuit between each GOA circuit and the AA pixel circuit. Thus, each VFR circuit can adjust (e.g., adjust the frequency of) the pulse signal output by the GOA circuit connected with the VFR circuit under the control of the corresponding VFE signal, and output the adjusted pulse signal to the AA pixel circuit connected with the VFR circuit, so as to realize the individual refresh rate control of each AA pixel circuit, and further realize that different refresh rate adjustment can be performed for different display areas, thereby not only meeting the actual demands of users, but also avoiding unnecessary power consumption waste.

Referring to fig. 4, fig. 4 is a schematic circuit diagram illustrating another embodiment of a circuit for adjusting a refresh rate of a screen. As shown in fig. 4, symmetrical EGOA circuits and VFR circuits are connected to both sides of the display area. The EGOA circuits, VFR circuits, and AA pixel circuits on both sides are connected to a display driver (DISPLAY DRIVER) integrated chip (INTEGRATED CIRCUIT CHIP, IC). The display driving integrated chip is mainly used for outputting a corresponding VFE signal to each VFR circuit, so that each VFR circuit can adjust (e.g. frequency adjust) a pulse signal output by a corresponding GOA circuit under the control of the VFE signal, and outputs an adjusted pulse waveform to a corresponding AA pixel circuit. It should be appreciated that the VFE signal received by each VFR circuit may be different so that different refresh rates may be achieved in different display areas of the same screen.

Referring to fig. 5, fig. 5 is a schematic structural diagram of a device for adjusting a refresh rate of a screen according to an embodiment of the application. As shown in fig. 5, the screen refresh rate adjusting device 20 may include a frequency adjusting circuit group 201, and the frequency adjusting circuit group 201 includes a plurality of frequency adjusting circuits, each of which may be connected to the control circuit 202. The frequency adjustment circuit may be the VFR circuit described above with respect to fig. 3 or 4, and the control circuit 202 may be the display driver integrated chip described above with respect to fig. 4, or a portion thereof. Further, as shown in fig. 5, the frequency adjustment circuit group 201 is further connected to the GOA circuit group 203, and the GOA circuit group 203 includes a plurality of GOA circuits, and each frequency adjustment circuit may be connected to each frequency adjustment circuit in a one-to-one correspondence. As shown in fig. 5, the frequency adjustment circuit group 201 is further connected to the AA pixel circuit group 204, and the AA pixel circuit group 204 may include a plurality of AA pixel circuits (or include a plurality of rows of AA pixel circuits, where the plurality of rows of AA pixel circuits may form the entire display area of the screen), and each frequency adjustment circuit may be connected to a corresponding AA pixel circuit in the AA pixel circuit group 204.

Further, referring to fig. 6, fig. 6 is a schematic structural diagram of a frequency adjusting circuit according to an embodiment of the application. As shown in fig. 6, taking any one of the frequency adjustment circuits 201 (such as the frequency adjustment circuit 2011) as an example, the frequency adjustment circuit 2011 may specifically include a first input terminal, a second input terminal, and an output terminal. The first input end of the frequency adjusting circuit 2011 is connected to the control circuit 202, the second input end of the frequency adjusting circuit 2011 is connected to a corresponding GOA circuit 2031 in the GOA circuit group 203, and the output end of the frequency adjusting circuit 2011 is connected to a corresponding AA pixel circuit 2041 in the AA pixel circuit group 204. As shown in fig. 6, the frequency adjustment circuit 2011 may specifically further include a TFT circuit formed by a plurality of transistors, where the TFT circuit may adjust a pulse signal output by the GOA circuit 2031 under the control of an enable signal output by the control circuit 202, and output the adjusted pulse signal to a corresponding AA pixel circuit, so as to control a refresh rate corresponding to the AA pixel circuit.

Alternatively, the output terminal of the frequency adjustment circuit 2011 may be connected to a plurality of AA pixel circuits in the AA pixel circuit group 204, so as to control the refresh rates corresponding to the plurality of AA pixel circuits at the same time.

Alternatively, the frequency adjustment circuit group 201 may specifically include K first frequency adjustment circuits, and the GOA circuit group 203 may include K IGZO GOA circuits. For example, the frequency adjustment circuit 2011 shown in fig. 6 may be one of K first frequency adjustment circuits, and the GOA circuit 2031 shown in fig. 6 may be one of K IGZO GOA circuits. The first input ends of the K first frequency adjusting circuits are connected with the control circuit 202, the second input ends of the K first frequency adjusting circuits are connected with the output ends of the K IGZO GOA circuits in a one-to-one correspondence manner, and the output ends of the K first frequency adjusting circuits are connected with the corresponding AA pixel circuits. Wherein K is an integer greater than 1.

The control circuit 202 may be configured to output a plurality of enable signals (i.e., a plurality of VFE signals) to the K first frequency adjustment circuits, where the high level frequencies of the plurality of enable signals may be different.

An ith first frequency adjustment circuit (e.g., a frequency adjustment circuit 2011) of the K first frequency adjustment circuits may be configured to receive one enable signal of the plurality of enable signals and to receive a first pulse signal output by a corresponding ith IGZO GOA circuit (e.g., a GOA circuit 2031); i=1, 2, 3, … …, K.

The ith first frequency adjusting circuit may be further configured to adjust the first pulse signal (e.g. adjust the frequency of the first pulse signal) based on the enable signal, obtain a second pulse signal, and output the second pulse signal to the corresponding AA pixel circuit. The screen refresh rate corresponding to the AA pixel circuit is the same as the frequency of the received second pulse signal.

Optionally, the frequency adjustment circuit group 201 further includes P second frequency adjustment circuits, and the GOA circuit group 203 further includes P LTPS GOA circuits. For example, the frequency adjustment circuit 2011 shown in fig. 6 may be one of P second frequency adjustment circuits, and the GOA circuit 2031 shown in fig. 6 may be one of P LTPS GOA circuits. The first input ends of the P second frequency adjusting circuits are connected with the control circuit 202, the second input ends of the P second frequency adjusting circuits are connected with the output ends of the P LTPS GOA circuits in a one-to-one correspondence mode, and the output ends of the P second frequency adjusting circuits are connected with the corresponding AA pixel circuits. Wherein P is an integer greater than 1.

The control circuit 202 may also be configured to output a plurality of enable signals (i.e., a plurality of VFE signals) to the P second frequency adjustment circuits, where the low level frequencies of the plurality of enable signals may be different.

The jth second frequency adjusting circuit of the P second frequency adjusting circuits may be configured to receive one enable signal of the plurality of enable signals, and to receive a third pulse signal output by the corresponding jth LTPS GOA circuit; j=1, 2, 3, … …, P.

The j-th second frequency adjusting circuit may be further configured to adjust the third pulse signal (e.g. adjust the frequency of the third pulse signal) based on the enable signal, obtain a fourth pulse signal, and output the fourth pulse signal to the corresponding AA pixel circuit. The screen refresh rate corresponding to the AA pixel circuit is the same as the frequency of the received fourth pulse signal.

It should be noted that, as described above, when the frequency of the second pulse signal is different from the frequency of the fourth pulse signal, the corresponding AA pixel circuit is controlled based on the second pulse signal corresponding to the IGZO GOA circuit, thereby controlling the corresponding screen refresh rate.

Next, the internal structure of the frequency adjusting circuit according to the embodiment of the present application will be described in detail based on the circuit structure described in the above embodiment with reference to the drawings.

(1) Frequency adjusting circuit for IGZO GOA circuit

Referring to fig. 7, fig. 7 is a schematic diagram of a VFR circuit for IGZO GOA according to an embodiment of the present application. As shown in fig. 7, the VFR1 circuit for IGZO GOA (i.e., the first frequency adjustment circuit described above) may have a 6T (transistor) structure, and specifically may include a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, and a transistor T6.

As shown in fig. 7, the first input terminal of the first frequency adjusting circuit is connected to the gate (G) of the transistor T1 and the gate of the transistor T4; the second input end of the first frequency adjusting circuit is connected with the grid electrode of the transistor T2 and the grid electrode of the transistor T3; the output end of the first frequency adjusting circuit is connected with the drain electrode (drain, D) of the transistor T5 and the drain electrode of the transistor T6. The source of the transistor T1 is connected to the source (S) of the transistor T2 and the source of the transistor T5; the drain electrode of the transistor T1 is connected with the drain electrode of the transistor T2, the drain electrode of the transistor T3, the grid electrode of the transistor T5 and the grid electrode of the transistor T6; the source of the transistor T3 is connected with the drain of the transistor T4; the source of the transistor T4 is connected to the source of the transistor T6.

Alternatively, the transistors T1, T2, T5 may be P-type LTPSTFTs; the transistors T3, T4, T6 may be N-type LTPS TFTs, or the transistors T3, T4, T6 may also be oxide (oxide) TFTs (e.g., IGZO TFTs).

As shown in fig. 7, the VFE1 signal is an enable signal output from the control circuit 202, and the VFE1 signal is input to the gates of the transistors T1 and T4 through the first input terminal. The in1 signal is a pulse signal (i.e., the first pulse signal) output from the IGZO GOA circuit connected to the first frequency adjustment circuit, and the in1 signal is input to the gates of the transistors T2 and T3 through the second input terminal. The out1 signal is a pulse signal (i.e. the second pulse signal) obtained after shaping the in1 signal, and the out1 signal is output to the AA pixel circuit connected to the first frequency adjusting circuit through the output terminal.

As shown in fig. 7, for the IGZOGOA output waveforms turned on at high level, when the VFE1 signal is at a constant high level (Vgatehigh, VGH), the output waveform of the first frequency adjustment circuit can maintain the original IGZOGOA output waveform (i.e. the in1 signal and the out1 signal are consistent), and output to the corresponding AA pixel circuit. When the VFE1 signal is low (Vgatelow, VGL), the first frequency adjustment circuit may shape the output waveform of IGZOGOA to low (i.e., the waveform of the out1 signal is low) and output to the corresponding AA pixel circuit.

Referring to fig. 8, fig. 8 is a schematic diagram of a VFR circuit for IGZO GOA according to another embodiment of the present application. As shown in fig. 8, the VFR1 circuit for IGZO GOA (i.e., the first frequency adjustment circuit described above) may also have a 2T1C structure, and specifically may include a transistor T13, a transistor T14, and a capacitor C1. As shown in fig. 8, a transistor T15, a transistor T25, and a capacitor C3 may be included in the circuit of the IGZO GOA output section.

As shown in fig. 8, a first input end of the first frequency adjusting circuit is connected to a source electrode of the transistor T13 (or the first input end is the source electrode of the transistor T13), and a second input end of the first frequency adjusting circuit is connected to a gate electrode of the transistor T14 (or the second input end is the gate electrode of the transistor T14); the output end of the first frequency adjusting circuit is connected with the drain electrode of the transistor T13 and the drain electrode of the transistor T14. The gate of the transistor T13 is connected to the gate of the transistor T15 in the corresponding IGZO GOA circuit. The source of transistor T14 is connected to a low level (VGL). One end of the capacitor C1 is connected to the gate of the transistor T14, and the other end of the capacitor C1 is connected to the drain of the transistor T13 and the drain of the transistor T14. The source of the transistor T15 is connected to a high level (VGH), and the drain of the transistor T15 is connected to the drain of the transistor T25 and the gate of the transistor T14. The source of transistor T25 is connected to a low level (VGL). One end of the capacitor C3 is connected to the gate of the transistor T15, and the other end of the capacitor C3 is connected to the source of the transistor T15.

Alternatively, the transistors T13, T14, and T15, T25 may be the same P-type TFT.

As shown in fig. 8, the out1 'signal is an output signal of the IGZO GOA circuit, and is identical to the in1 signal shown in fig. 7, and the out1' signal may be further output to the IGZO GOA circuit in the next row. The capacitor C1 may be used to ensure the normal output of the transistor T14, i.e. to ensure the reliability of the out1 signal.

As shown in fig. 8, the transistor T13 in the first frequency adjustment circuit may use the gate control signal of the transistor T15 in the IGZO GOA circuit, so that the number of transistors may be reduced, the circuit structure of the first frequency adjustment circuit is simplified, the influence of the frame of the screen is reduced, and the user experience is improved. Correspondingly, the first frequency adjusting circuit of the 2T1C structure may also realize the above functions through control of the VFE1 signal under the condition of borrowing the control signal of the IGZO GOA circuit, and the description of the corresponding embodiment of fig. 7 may be referred to specifically, and will not be repeated here.

Referring to fig. 9, fig. 9 is a schematic diagram of a VFR circuit for IGZO GOA according to another embodiment of the present application. As shown in fig. 9, the VFR1 circuit for IGZO GOA (i.e., the first frequency adjustment circuit described above) may have a 2T structure, and may specifically include a transistor T13 and a transistor T14. Specific circuit structures and functions may be described with reference to the corresponding embodiment of fig. 8, and will not be described herein.

As shown in fig. 9, the embodiment of the application can further reduce the capacitance C1 in the first frequency adjusting circuit, and further reduce the number of devices, thereby greatly simplifying the circuit structure, reducing the influence of the frame of the screen, and improving the user experience. Correspondingly, in the case of borrowing the control signal of the IGZO GOA circuit, the first frequency adjusting circuit with the 2T structure may also realize the above functions through the control of the VFE1 signal, and the description of the corresponding embodiment of fig. 7 may be referred to specifically, and will not be repeated here.

(2) Frequency adjusting circuit for LTPS GOA circuit

Referring to fig. 10, fig. 10 is a schematic diagram of a VFR circuit for LTPS GOA according to an embodiment of the present application. As shown in fig. 10, the VFR2 circuit for LTPS GOA (i.e., the second frequency adjustment circuit described above) may have a 6T structure, and specifically may include a transistor T7, a transistor T8, a transistor T9, a transistor T10, a transistor T11, and a transistor T12.

As shown in fig. 10, the first input terminal of the second frequency adjusting circuit is connected to the gate of the transistor T7 and the gate of the transistor T9; a second input end of the second frequency adjusting circuit is connected with the grid electrode of the transistor T8 and the grid electrode of the transistor T10; the output end of the second frequency adjusting circuit is connected with the drain electrode of the transistor T11 and the drain electrode of the transistor T12. The source of the transistor T7 is connected to the source of the transistor T11; the drain of the transistor T7 is connected with the source of the transistor T8; the drain of the transistor T8 is connected with the drain of the transistor T9, the drain of the transistor T10, the gate of the transistor T11 and the gate of the transistor T12; the source of the transistor T9 is connected to the source of the transistor T10 and the source of the transistor T12.

Alternatively, the transistors T7, T8, T11 may be P-type LTPS TFTs; the transistors T9, T10, and T12 may be N-type LTPS TFTs, or the transistors T9, T10, and T12 may be oxide TFTs (e.g., IGZO TFTs).

As shown in fig. 10, the VFE2 signal is an enable signal output from the control circuit 202, and the VFE2 signal is input to the gates of the transistor T7 and the transistor T9 through the first input terminal. The in2 signal is a pulse signal (i.e., the third pulse signal) output from the LTPS GOA circuit connected to the second frequency adjustment circuit, and the in2 signal is input to the gates of the transistors T8 and T10 through the second input terminal. The out2 signal is a pulse signal (i.e. the fourth pulse signal) obtained after shaping the in2 signal, and the out2 signal is output to the AA pixel circuit connected to the second frequency adjusting circuit through the output terminal.

As shown in fig. 10, for the LTPS GOA output waveform turned on at low level, when the VFE2 signal is at a constant low level (VGL), the output waveform of the second frequency adjustment circuit can maintain the original LTPSGOA output waveform (i.e. the in2 signal is consistent with the out2 signal) and output to the corresponding AA pixel circuit. When the VFE2 signal is at a high level (VGH), the second frequency adjustment circuit may shape the output waveform of the LTPS GOA to a high level (i.e., the waveform of the out2 signal is at a high level) and output the same to the corresponding AA pixel circuit.

Referring to fig. 11, fig. 11 is a schematic diagram of a VFR circuit for LTPS GOA according to another embodiment of the present application. As shown in fig. 11, the VFR2 circuit for LTPS GOA (i.e., the second frequency adjustment circuit described above) may also have a 2T1C structure, and may specifically include a transistor T16, a transistor T17, and a capacitor C2. As shown in fig. 11, the LTPS GOA output section may include a transistor T18, a transistor T28, a capacitor C4, and a capacitor C5.

As shown in fig. 11, a first input end of the second frequency adjusting circuit is connected to a source electrode of the transistor T17 (or the first input end is the source electrode of the transistor T17), and a second input end of the second frequency adjusting circuit is connected to a gate electrode of the transistor T17 (or the second input end is the gate electrode of the transistor T17); the output end of the first frequency adjusting circuit is connected with the drain electrode of the transistor T16 and the drain electrode of the transistor T17. One end of the capacitor C2 is connected to the gate of the transistor T17, and the other end of the capacitor C2 is connected to the drain of the transistor T16 and the drain of the transistor T17. The gate of the transistor T16 is connected to the gate of the transistor T18 in the LTPS GOA circuit, and the source of the transistor T16 and the source of the transistor T18 are connected to a high level (VGH). The drain of the transistor T18 is connected to the drain of the transistor T28 and the gate of the transistor T17. The source of transistor T28 is connected to a low level (VGL). One end of the capacitor C4 is connected to the gate of the transistor T18, the other end of the capacitor C4 is connected to the source of the transistor T18, one end of the capacitor C5 is connected to the gate of the transistor T28, and the other end of the capacitor C4 is connected to the drain of the transistor T28.

Alternatively, the transistors T16, T17, and T18, T28 may be the same P-type TFT.

As shown in fig. 11, the out2 'signal is an output signal of the LTPS GOA circuit, and is identical to the in2 signal shown in fig. 10, and the out2' signal may be further output to the LTPS GOA circuit in the next row. The capacitor C2 may be used to ensure the normal output of the transistor T17, i.e. to ensure the reliability of the out2 signal.

As shown in fig. 11, the transistor T16 in the second frequency adjustment circuit may use the gate control signal of the transistor T18 in the LTPS GOA circuit, so that the number of transistors may be reduced, the circuit structure of the second frequency adjustment circuit is simplified, the influence of the frame of the screen is reduced, and the user experience is improved. Correspondingly, the second frequency adjusting circuit of the 2T1C structure can also realize the above functions through control of the VFE2 signal under the condition of borrowing the control signal of the LTPS GOA circuit, and the description of the corresponding embodiment of fig. 10 is specifically referred to and will not be repeated here.

Referring to fig. 12, fig. 12 is a schematic diagram illustrating frequency adjustment of a pulse signal according to an embodiment of the application. As shown in fig. 12, the frequencies of the pulse signals directly output from the IGZOGOA circuit and the LTPSGOA circuit are 120Hz. If the level of the VFE1/VFE2 signal input to the VFR circuit is controlled to be low/high, the frequency of the pulse signals output by the corresponding IGZOGOA circuit and LTPSGOA circuit can be adjusted by the VFR circuit, for example, to be 30Hz, and the adjusted pulse signals are output to the corresponding AA pixel circuit, and accordingly, the refresh rate of the AA pixel circuit is also adjusted to be 30Hz.

Further, referring to fig. 13, fig. 13 is a schematic diagram illustrating frequency adjustment of a pulse signal according to an embodiment of the application.

As shown in fig. 13, the frequency of the pulse signal directly output from the IGZOGOA circuit is 120Hz. If the VFE1 signal inputted to the first frequency adjustment circuit maintains a high level, the frequency of the pulse signal outputted after being shaped by the first frequency adjustment circuit will remain unchanged, and also be 120HZ. As shown in fig. 13, if the VFE1 signal is set to a high level at a frequency of 30Hz, the frequency of the pulse signal output after being shaped by the first frequency adjustment circuit is also adjusted to 30Hz. Or if the VFE1 signal is set to a high level at a frequency of 60Hz, the frequency of the pulse signal output after being shaped by the first frequency adjustment circuit will also be adjusted to 60Hz.

Similarly, as shown in fig. 13, the frequency of the pulse signal directly output from the LTPSGOA circuit is 120Hz. If the VFE2 signal inputted to the second frequency adjustment circuit maintains a low level, the frequency of the pulse signal outputted after being shaped by the second frequency adjustment circuit will remain unchanged, and also be 120HZ. As shown in fig. 13, if the VFE2 signal is set to a low level at a frequency of 30Hz, the frequency of the pulse signal output after being shaped by the second frequency adjustment circuit is also adjusted to 30Hz. Or if the VFE2 signal is set to a low level according to the frequency of 60Hz, the frequency of the pulse signal output after being shaped by the second frequency adjusting circuit is also adjusted to 60Hz.

Referring to fig. 14, fig. 14 is a schematic diagram showing an effect of screen refresh rate adjustment according to an embodiment of the present application. As shown in fig. 14, the display screen may include a total of L AA pixel circuits arranged in rows, i.e., L rows of AA pixel circuits.

As shown in fig. 15, the VFE1 signal received by the first frequency adjustment circuit correspondingly connected to the AA pixel circuits of rows 1 to M and m+n+1 to L is at a constant high level, and the VFE2 signal received by the second frequency adjustment circuit correspondingly connected to the AA pixel circuits of rows 1 to M and m+n+1 to L is at a constant low level, so that the refresh rate corresponding to the AA pixel circuits of rows 1 to M and m+n+1 to L maintains the highest refresh rate of 120Hz.

As shown in fig. 15, the VFE1 signal received by the first frequency adjustment circuit correspondingly connected to the m+1 to m+n rows of AA pixel circuits is set to a high level at a frequency of 60Hz, and the VFE2 signal received by the second frequency adjustment circuit correspondingly connected to the m+1 to m+n rows of AA pixel circuits is set to a low level at a frequency of 60Hz, where the refresh rate corresponding to the m+1 to m+n rows of AA pixel circuits is 60Hz.

Therefore, the embodiment of the application can realize the refresh rate adjustment of a plurality of different gears for different display areas based on the highest refresh rate. The refresh rate of the plurality of gears is typically divisible by the highest refresh rate. For example, with a highest refresh rate of 120Hz, a refresh rate adjustment of a plurality of different gears, e.g., 120Hz,60Hz,30Hz,24Hz,15Hz,10Hz,1Hz, etc., may be achieved.

Referring to fig. 15, fig. 15 is a schematic diagram of an overall circuit structure for adjusting a refresh rate of a screen according to an embodiment of the application. As shown in fig. 15, a circuit on the display screen side is still taken as an example, and the circuit may include a plurality of IGZO GOA circuits, a plurality of first frequency adjustment circuits, a plurality of LTPS GOA circuits, a plurality of second frequency adjustment circuits, and a plurality of AA pixel circuits. As shown in fig. 15, the plurality of IGZO GOA circuits may specifically include IGZO GOA-1, IGZO GOA-2, IGZO GOA-3, IGZO GOA-4, and the like. The plurality of first frequency adjustment circuits may include, in particular, VFR-11, VFR-12, VFR-13, VFR-14, and the like. The plurality of LTPS GOA circuits may include, in particular, LTPS GOA-1, LTPS GOA-2, LTPS GOA-3, LTPS GOA-4, LTPS GOA-5, LTPS GOA-6, LTPS GOA-7, LTPS GOA-8, etc. The plurality of second frequency adjustment circuits may include, in particular, VFR-21, VFR-22, VFR-23, VFR-24, VFR-25, VFR-26, VFR-27, VFR-28, and the like. The plurality of AA pixel circuits may include an AA pixel circuit-1, an AA pixel circuit-2, an AA pixel circuit-3, an AA pixel circuit-4, an AA pixel circuit-5, an AA pixel circuit-6, an AA pixel circuit-7, an AA pixel circuit-8, etc.

As shown in fig. 15, a plurality of IGZO GOA circuits such as IGZO GOA-1, IGZO GOA-2, IGZO GOA-3, IGZO GOA-4, etc. may be sequentially arranged and connected in rows. The plurality of first frequency adjustment circuits of VFR-11, VFR-12, VFR-13, VFR-14, etc. may be arranged in a row-by-row order and connected. The LTPS GOA circuits such as LTPS GOA-1, LTPS GOA-2, LTPS GOA-3, LTPS GOA-4, LTPS GOA-5, LTPS GOA-6, LTPS GOA-7, LTPS GOA-8 and the like can be sequentially arranged and connected in rows. A plurality of second frequency adjustment circuits such as VFR-21, VFR-22, VFR-23, VFR-24, VFR-25, VFR-26, VFR-27, VFR-28, etc. may be arranged in sequence in a row and connected. AA pixel circuits-1, AA pixel circuit-2, AA pixel circuit-3, AA pixel circuit-4, AA pixel circuit-5, AA pixel circuit-6, AA pixel circuit-7, AA pixel circuit-8, and the like may be sequentially arranged and connected in rows.

As shown in fig. 15, in1 is an input signal of the IGZO GOA-1, and may specifically be a signal input to the IGZO GOA-1 by a display driving integrated chip (such as the control circuit 202 described in fig. 5). out1 'is an output signal of the IGZO GOA-1 (for example, the 120Hz pulse signal shown in fig. 12), and out1' may be input to the VFR-11 connected thereto and the IGZO GOA-2 of the next row, respectively, as input signals of the VFR-11 and the IGZO GOA-2. Note that in1 and out1 'have the same waveform, and out1' is one clock later than in 1. out1 is an output signal of the VFR-11, specifically, a signal obtained by shaping out1' by the VFR-11, and out1 may be input to the AA pixel circuit-1 and the AA pixel circuit-2 respectively to control the refresh rates corresponding to the AA pixel circuit-1 and the AA pixel circuit-2. Alternatively, the number of IGZO GOA circuits and the number of first frequency adjusting circuits may be equal to the number of AA pixel circuits, which are connected in one-to-one correspondence, which is not particularly limited in the embodiment of the present application.

As shown in FIG. 15, in2 is an input signal of LTPS GOA-1, and may specifically be a signal input to LTPS GOA-1 by the display driver integrated chip. out2 'is the output signal of LTPS GOA-1 (e.g. 120Hz pulse signal as shown in FIG. 12 above), and out2' can be input to the VFR-21 connected thereto and the LTPS GOA-2 of the next row, respectively, as the input signals of the VFR-21 and the LTPS GOA-2. Note that in2 and out2 'have the same waveform, and out2' is one clock later than in 2. out2 is an output signal of the VFR-21, specifically, a signal obtained by shaping out2' by the VFR-21, and out2 may be input to the AA pixel circuit-1 to control the refresh rate corresponding to the AA pixel circuit-1. The circuits of the other rows are the same and will not be described in detail here.

Take the frequency of the output signal of each IGZO GOA circuit as 120Hz as an example. As shown in fig. 15, the display driver ics may input the VFE-11 signal to the VFR-11 and the VFR-14 signal, respectively, and the VFE-11 signal is at a constant high level, and then the VFR-11 and the VFR-14 circuits maintain the output signals of the IGZO GOA-1 and the IGZO GOA-4 circuits and input the output signals to the AA pixel circuit-1, the AA pixel circuit-2, the AA pixel circuit-7 and the AA pixel circuit-8 under the control of the VFE-11 signal. Accordingly, the refresh rates corresponding to the AA pixel circuits-1, AA pixel circuit-2, AA pixel circuit-7, and AA pixel circuit-8 are also maintained at 120 Hz. As shown in fig. 15, the display driver integrated chip may input the VFE-12 signal to the VFR-12 and the VFR-13 signal, respectively, and the VFE-12 signal is set to a high level at a frequency of 30Hz, and then the VFR-12 and the VFR-13 circuits shape the output signals of the IGZO GOA-2 and IGZO GOA-3 circuits to 30Hz by the control of the VFE-12 signal, and output the output signals to the AA pixel circuit-3, the AA pixel circuit-4, the AA pixel circuit-5, and the AA pixel circuit-6. Correspondingly, the refresh rates corresponding to the AA pixel circuits-3, AA pixel circuit-4, AA pixel circuit-5 and AA pixel circuit-6 are also adjusted to 30Hz.

Take the frequency of the output signal of each LTPS GOA circuit as 120Hz as an example. Correspondingly, the display driving integrated chip can also input VFE-21 signals to the VFR-21, the VFR-22, the VFR-27 and the VFR-28 respectively, and the VFE-21 signals are in a constant low level, so that the output signals of the LTPS GOA-1, the LTPS GOA-2, the LTPS GOA-7 and the LTPS GOA-8 are maintained by the control of the VFE-21 signals through the VFR-21 circuits, and are output to the AA pixel circuit-1, the AA pixel circuit-2, the AA pixel circuit-7 and the AA pixel circuit-8. Accordingly, the refresh rates corresponding to the AA pixel circuits-1, AA pixel circuit-2, AA pixel circuit-7, and AA pixel circuit-8 are also maintained at 120 Hz. As shown in FIG. 15, the display driver IC may also input VFE-22 signals to VFR-23, VFR-24, VFR-25, and VFR-26, respectively, and the VFE-22 signals are set to low level at a frequency of 30Hz, so that the VFR-23, VFR-24, VFR-25, and VFR-26 circuits shape the output signals of the LTPS GOA-3, LTPS GOA-4, LTPS GOA-5, and LTPS GOA-6 circuits to 30Hz by the control of the VFE-22 signals, and output the output signals to the AA pixel circuits-3, AA pixel circuits-4, AA pixel circuits-5, and AA pixel circuits-6. Correspondingly, the refresh rates corresponding to the AA pixel circuits-3, AA pixel circuit-4, AA pixel circuit-5 and AA pixel circuit-6 are also adjusted to 30Hz.

As shown in fig. 15, the embodiment of the application finally realizes that the refresh rate of 1-2 rows and 7-8 rows of pixel circuits in the display screen is 120Hz and the refresh rate of 3-6 rows of pixel circuits is 30Hz by controlling the plurality of first frequency adjusting circuits and the plurality of second frequency adjusting circuits by a plurality of different enabling signals, thereby realizing the adjustment of different refresh rates on different display areas of the same screen.

For example, referring to fig. 16, fig. 16 is a schematic diagram illustrating an effect of another screen refresh rate adjustment according to an embodiment of the present application. As shown in fig. 16, when a terminal device (e.g., a smart phone) turns on a "picture-in-picture" video hover function in response to a user operation, the screen 10 may include two display areas, a video area 103 and a reading area 104.

As shown in fig. 16, if the terminal device does not receive any operation by the user and the frame rate of the currently played video is 60fps, the refresh rate of the video area 103 is 60Hz and the refresh rate of the reading area 104 is 1Hz. As shown in fig. 16, when the terminal device receives a sliding operation of the user with respect to the reading area 104, the refresh rate of the reading area 104 may be raised to 120Hz, and the refresh rate of the video area 103 may be maintained at 60Hz. Alternatively, as shown in fig. 16, in response to a user operation, the position of the video area 103 may be adjusted to be moved up and down, and the reading area 104 may be divided into two areas up and down by the video area 103 as a background, which will not be described in detail herein.

Further, referring to fig. 17, fig. 17 is a schematic diagram illustrating an effect of still another screen refresh rate adjustment according to an embodiment of the present application. As shown in fig. 17, in some multi-application scenarios, the embodiments of the present application may implement 4 different refresh rates on 4 display areas of the same screen simultaneously through control of 4 different VFE signals, and the division of the display areas with different refresh rates may be adjusted based on the display content. As shown in fig. 17, the screen 10 may include four display areas, where the content is status bar, video, comment and social contact, where the refresh rate of the status bar display area is 1Hz, the refresh rate of the video display area is 30Hz, the refresh rate of the comment display area is 10Hz, and the refresh rate of the social contact display area is 60Hz, so that various actual demands of users can be met, user experience is improved, and unnecessary power consumption waste caused by high refresh rate is avoided.

In summary, the embodiment of the application provides a device for adjusting a screen refresh rate, which can realize different refresh rates in different areas of a display screen. Therefore, various application scenes can be matched, the high refresh rate is provided in the local area needing the high refresh rate, and meanwhile, the low refresh rate is provided in the local area needing no high refresh rate, so that the actual requirements of users are met, and unnecessary power consumption waste is avoided.

Based on the description of the embodiment of the device, the application also provides a method for adjusting the screen refresh rate. Referring to fig. 18, fig. 18 is a flowchart illustrating a method for adjusting a refresh rate of a screen according to an embodiment of the present application. The method can be applied to terminal equipment such as intelligent wearable equipment, smart phones, tablet computers, notebook computers, desktop computers, vehicle-mounted computers, household appliances with screens such as televisions, refrigerators with display screens and the like, intelligent robots with screens and the like, and the embodiment of the application is not limited in particular. The terminal device may comprise means for adjusting the screen refresh rate; the apparatus includes a frequency adjustment circuit set; each frequency adjustment circuit in the frequency adjustment circuit group comprises a first input end, a second input end and an output end; the first input end of each frequency adjusting circuit is connected with the circuit, the second input end of each frequency adjusting circuit is connected with a corresponding GOA circuit in the gate driving GOA circuit group, and the output end of each frequency adjusting circuit is connected with a corresponding AA pixel circuit in the AA pixel circuit group of the display area. The method of adjusting the screen refresh rate may include the following steps S301 to S303.

Step S301, outputting a plurality of enabling signals to a frequency adjusting circuit group through a control circuit; the high level frequency or the low level frequency of the plurality of enable signals is different.

Step S302, receiving, by each frequency adjustment circuit in the frequency adjustment circuit group, one enable signal of the plurality of enable signals, and receiving a pulse signal output by the corresponding GOA circuit.

Step S303, through each frequency adjusting circuit, the pulse signals are adjusted based on the enabling signals, the adjusted pulse signals are obtained, and the adjusted pulse signals are output to the corresponding AA pixel circuits.

The screen refresh rate corresponding to the AA pixel circuit is the same as the frequency of the received adjusted pulse signal.

It should be understood that the above method flows may be specifically described with reference to the corresponding embodiments of fig. 3 to 17, and will not be described herein.

In one implementation manner, each method flow in the method for adjusting the screen refresh rate described in the embodiment of the present application may be implemented specifically on a piece, hardware, or a combination thereof. The hardware implementation manner may include logic circuits, algorithm circuits, analog circuits or the like. The software implemented manner may include program instructions, which may be considered a software product, stored in a memory, and executable by a processor to perform related functions.

The embodiment of the present application also provides a computer readable storage medium, where the computer readable storage medium may store a program, where the program when executed by a processor causes the processor to perform some or all of the steps described in any one of the above method embodiments.

The embodiment of the present application also provides a computer program, where the computer program includes instructions, when the computer program is executed by a multi-core processor, enable the processor to perform some or all of the steps described in any one of the above method embodiments.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments. It should be noted that, for simplicity of description, the foregoing method embodiments are all described as a series of acts, but it should be understood by those skilled in the art that the present application is not limited by the order of acts described, as some steps may be performed in other orders or concurrently in accordance with the present application. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily required for the present application.

In the several embodiments provided by the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, such as the above-described division of units, merely a division of logic functions, and there may be additional manners of dividing in actual implementation, such as multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, or may be in electrical or other forms.

The units described above as separate components may or may not be physically separate, and components shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units described above, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on this understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server or a network device, etc., in particular may be a processor in the computer device) to perform all or part of the steps of the above-mentioned method of the various embodiments of the present application. Wherein the aforementioned storage medium may comprise: various media capable of storing program codes, such as a U-disc, a removable hard disk, a magnetic disk, a compact disk, a read-only memory (ROM), a Double Data Rate (DDR), a flash memory (flash), or a random access memory (random access memory, RAM), etc.

The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. An apparatus for adjusting a refresh rate of a screen, the apparatus comprising a set of frequency adjustment circuits; each frequency adjustment circuit in the frequency adjustment circuit group comprises a first input end, a second input end and an output end; wherein,

The first input end of each frequency adjusting circuit is connected with the control circuit, the second input end of each frequency adjusting circuit is connected with a corresponding GOA circuit in the gate driving GOA circuit group, and the output end of each frequency adjusting circuit is connected with a corresponding AA pixel circuit in the AA pixel circuit group of the display area.

2. The apparatus of claim 1, wherein the set of frequency adjustment circuits comprises K first frequency adjustment circuits, the set of GOA circuits comprises K indium gallium zinc oxide IGZO GOA circuits; the first input ends of the K first frequency adjusting circuits are connected with the control circuit, the second input ends of the K first frequency adjusting circuits are connected with the output ends of the K IGZO GOA circuits in a one-to-one correspondence mode, and the output ends of the K first frequency adjusting circuits are connected with corresponding AA pixel circuits; k is an integer greater than 1.

3. The apparatus of claim 2, wherein the device comprises a plurality of sensors,

The control circuit is used for outputting a plurality of enabling signals to the K first frequency adjusting circuits, and the high level frequencies of the enabling signals are different;

An ith first frequency adjustment circuit for receiving one of the plurality of enable signals and receiving a first pulse signal output by a corresponding ith IGZO GOA circuit; i=1, 2, 3, … …, K;

The ith first frequency adjusting circuit is further configured to adjust the first pulse signal based on the enable signal to obtain a second pulse signal, and output the second pulse signal to a corresponding AA pixel circuit; the screen refresh rate corresponding to the AA pixel circuit is the same as the frequency of the received second pulse signal.

4. The apparatus of claim 3, wherein the set of frequency adjustment circuits further comprises P second frequency adjustment circuits, the set of GOA circuits further comprising P low temperature polysilicon LTPS GOA circuits; the first input ends of the P second frequency adjusting circuits are connected with the control circuit, the second input ends of the P second frequency adjusting circuits are connected with the output ends of the P LTPS GOA circuits in a one-to-one correspondence manner, and the output ends of the P second frequency adjusting circuits are connected with corresponding AA pixel circuits; p is an integer greater than 1.

5. The apparatus of claim 4, wherein the device comprises a plurality of sensors,

The control circuit is used for outputting a plurality of enabling signals to the P second frequency adjusting circuits, and the low level frequencies of the enabling signals are different;

a j second frequency adjustment circuit, configured to receive one of the enable signals, and receive a third pulse signal output by a corresponding j LTPS GOA circuit; j=1, 2, 3, … …, P;

The j second frequency adjusting circuit is further configured to adjust the third pulse signal based on the enable signal to obtain a fourth pulse signal, and output the fourth pulse signal to a corresponding AA pixel circuit; the screen refresh rate corresponding to the AA pixel circuit is the same as the frequency of the received fourth pulse signal.

6. A device according to any one of claims 2-3, wherein the first frequency adjustment circuit comprises a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6; wherein,

The first input end of the first frequency adjusting circuit is connected with the grid electrode of the transistor T1 and the grid electrode of the transistor T4; the second input end of the first frequency adjusting circuit is connected with the grid electrode of the transistor T2 and the grid electrode of the transistor T3; the output end of the first frequency adjusting circuit is connected with the drain electrode of the transistor T5 and the drain electrode of the transistor T6;

The source electrode of the transistor T1 is connected with the source electrode of the transistor T2 and the source electrode of the transistor T5; the drain of the transistor T1 is connected with the drain of the transistor T2, the drain of the transistor T3, the gate of the transistor T5 and the gate of the transistor T6; the source of the transistor T3 is connected with the drain of the transistor T4; the source of the transistor T4 is connected to the source of the transistor T6.

7. The device of claim 6, wherein the transistors T1, T2, T5 are P-type low temperature polysilicon LTPS thin film transistors TFTs; the transistors T3, T4 and T6 are N-type LTPS TFTs.

8. The apparatus of any of claims 4-5, wherein the second frequency adjustment circuit comprises a transistor T7, a transistor T8, a transistor T9, a transistor T10, a transistor T11, a transistor T12; wherein,

The first input end of the second frequency adjusting circuit is connected with the grid electrode of the transistor T7 and the grid electrode of the transistor T9; the second input end of the second frequency adjusting circuit is connected with the grid electrode of the transistor T8 and the grid electrode of the transistor T10; the output end of the second frequency adjusting circuit is connected with the drain electrode of the transistor T11 and the drain electrode of the transistor T12;

The source of the transistor T7 is connected with the source of the transistor T11; the drain electrode of the transistor T7 is connected with the source electrode of the transistor T8; the drain of the transistor T8 is connected with the drain of the transistor T9, the drain of the transistor T10, the gate of the transistor T11 and the gate of the transistor T12; the source of the transistor T9 is connected to the source of the transistor T10 and the source of the transistor T12.

9. The apparatus of claim 8, wherein the transistors T7, T8, T11 are P-type LTPS TFTs; the transistors T9, T10 and T12 are N-type LTPS TFTs.

10. A device according to any one of claims 2-3, wherein the first frequency adjustment circuit comprises a transistor T13, a transistor T14; the IGZO GOA circuit includes a transistor T15; wherein,

The first input end of the first frequency adjusting circuit is connected with the source electrode of the transistor T13, and the second input end of the first frequency adjusting circuit is connected with the grid electrode of the transistor T14; the output end of the first frequency adjusting circuit is connected with the drain electrode of the transistor T13 and the drain electrode of the transistor T14; the gate of the transistor T13 is connected to the gate of the transistor T15 in the corresponding IGZO GOA circuit.

11. The apparatus of claim 10, wherein the first frequency adjustment circuit further comprises a capacitor C1; one end of the capacitor C1 is connected to the gate of the transistor T14, and the other end of the capacitor C1 is connected to the drain of the transistor T13 and the drain of the transistor T14.

12. The apparatus of any of claims 4-5, wherein the second frequency adjustment circuit comprises a transistor T16, a transistor T17, a capacitor C2; the LTPS GOA circuit includes a transistor T18; wherein,

The first input end of the second frequency adjusting circuit is connected with the source electrode of the transistor T17, and the second input end of the second frequency adjusting circuit is connected with the grid electrode of the transistor T17; the output end of the first frequency adjusting circuit is connected with the drain electrode of the transistor T16 and the drain electrode of the transistor T17; one end of the capacitor C2 is connected with the gate of the transistor T17, and the other end of the capacitor C2 is connected with the drain of the transistor T16 and the drain of the transistor T17; the gate of the transistor T16 is connected to the gate of the transistor T18 in the LTPS GOA circuit, and the source of the transistor T16 is connected to the source of the transistor T18.

13. A terminal device comprising a screen comprising a display area AA pixel circuit-group and a screen refresh rate adjustment device according to any one of claims 1-12, the AA pixel circuit-group being connected to the screen refresh rate adjustment device; the terminal device further comprises a processor and a memory which are connected with the screen.