CN118019321A

CN118019321A - Semiconductor structure and forming method thereof

Info

Publication number: CN118019321A
Application number: CN202211349137.9A
Authority: CN
Inventors: 李营慧; 王士欣
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-10-31
Filing date: 2022-10-31
Publication date: 2024-05-10
Also published as: WO2024092947A1

Abstract

Embodiments of the present disclosure provide a semiconductor structure and a method of forming the same, wherein the semiconductor structure includes: a substrate; the substrate comprises a plurality of active areas which are arranged at intervals along a first direction; a conductive plug located on the surface of the active region and extending into the substrate; a conductive structure located on the conductive plug; wherein the conductive structure is not self-aligned with the conductive plug.

Description

Semiconductor structure and forming method thereof

Technical Field

The present disclosure relates to the field of semiconductor technology, and relates to, but is not limited to, a semiconductor structure and a method of forming the same.

Background

In the existing preparation process of the semiconductor device, with the increase of the etching layer number and the etching depth, the bottom layer etching liquid is easy to be lost or accumulated, so that the bottom structure is damaged. For example, in the fabrication process of a dynamic random access memory (Dynamic Random Accsess Memory, DRAM), a multi-layer structure is usually etched in one step, and a bit line structure and a bit line contact plug are simultaneously formed, which easily causes over-etching, under-etching or tilting of the bottom bit line contact plug.

Disclosure of Invention

In view of the above, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same.

In a first aspect, embodiments of the present disclosure provide a semiconductor structure, comprising:

a substrate; the substrate comprises a plurality of active areas which are arranged at intervals along a first direction;

a conductive plug located on the active area surface and extending into the substrate;

a conductive structure located on the conductive plug; wherein the conductive structure is not self-aligned with the conductive plug.

In some embodiments, the conductive plugs have a dimension in the first direction that is less than a dimension of the conductive structures in the first direction.

In some embodiments, the conductive plug has a dimension in the first direction that is less than a dimension of the active region in the first direction.

In some embodiments, further comprising: the protective layer is positioned on the side wall of the conductive plug;

An edge of the protective layer is aligned with an edge of the conductive structure and the active region.

In a second aspect, embodiments of the present disclosure provide a method for forming a semiconductor structure, the method comprising:

Providing a substrate; the substrate comprises a plurality of active areas which are arranged at intervals along a first direction;

forming a conductive plug extending into the substrate on the surface of the active region;

And forming a conductive structure on the conductive plug.

In some embodiments, forming a conductive plug at the active area surface extending into the substrate, comprising:

Forming an initial conductive contact structure on the surface of the active region;

and etching back the initial conductive contact structure to form the conductive plug and the gap.

In some embodiments, the conductive plugs have a dimension in the first direction that is less than a dimension in the first direction of an active region located at a bottom of the conductive plugs.

In some embodiments, the method further comprises:

a dielectric layer is formed in the void.

In some embodiments, forming a conductive structure on the conductive plug includes:

Forming a functional material layer on the dielectric layer and the conductive plug;

And etching the functional material layer to form the conductive structure.

In some embodiments, the functional material layer includes an initial conductive layer and an initial insulating layer; forming a conductive structure material layer on the dielectric layer and the conductive plug, including:

And depositing conductive materials and insulating materials on the surfaces of the dielectric layer and the conductive plug in sequence to form the initial conductive layer and the initial insulating layer.

In some embodiments, the etching the functional material layer to form the conductive structure includes:

And etching the initial insulating layer and the initial conducting layer in sequence until the dielectric layer is exposed, so as to form the conducting structure.

In some embodiments, after forming the conductive structure, the method further comprises:

and etching the dielectric layer to form a protective layer positioned on the side wall of the conductive plug.

And etching the initial insulating layer, the initial conducting layer and the dielectric layer in sequence to form the conducting structure and a protective layer positioned on the side wall of the conducting plug.

In some embodiments, the base further comprises a substrate comprising the active region; forming an initial conductive contact structure on the surface of the active region, including:

forming an isolation layer on the surface of the substrate;

sequentially etching the isolation layer and the substrate to form an etching groove;

and forming the initial conductive contact structure in the etched groove.

In some embodiments, the base further comprises a substrate comprising the active region; forming an initial conductive contact structure on the surface of the active region, and further comprising:

forming an isolation layer and a bottom metal layer on the surface of the substrate;

Sequentially etching the bottom metal layer, the isolation layer and the substrate to form an etching groove;

and forming the initial conductive contact structure in the etched groove.

Forming a side wall isolation layer on the surfaces of the conductive structure and the conductive plug; the side wall isolation layer comprises a first side wall layer, a second side wall layer and a third side wall layer which are sequentially arranged from inside to outside.

The embodiment of the disclosure provides a semiconductor structure and a forming method thereof, wherein the semiconductor structure comprises: a conductive plug on the surface of the active region and extending into the substrate, and a conductive structure on the conductive plug; the conductive structure is not self-aligned with the conductive plug. Because the conductive structure and the conductive plug are not self-aligned, it can be seen that the conductive structure and the conductive plug in the embodiment of the disclosure are not formed by a one-step etching process, so that defects such as over etching, tilting or insufficient etching of the conductive plug in the process of forming the conductive plug can be avoided. Accordingly, the embodiments of the present disclosure may provide a semiconductor structure with few defects, complete structure, and excellent performance.

Drawings

In the drawings (which are not necessarily drawn to scale), like numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example and not by way of limitation, various embodiments discussed herein.

Fig. 1 is a schematic flow chart of a method for forming a semiconductor structure according to an embodiment of the disclosure;

Fig. 2a to 2j are schematic structural diagrams during the formation of a semiconductor structure according to an embodiment of the present disclosure;

Fig. 3a to 3e are schematic structural views of another semiconductor structure forming process according to an embodiment of the present disclosure;

fig. 4 is a schematic flow chart of another method for forming a semiconductor structure according to an embodiment of the disclosure.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present disclosure.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Before describing the embodiments of the present disclosure, three directions describing the three-dimensional structure that may be used in the following embodiments are defined, and may include X-axis, Y-axis, and Z-axis directions, for example, in a cartesian coordinate system. The substrate may include a top surface at the front side and a bottom surface at the back side opposite the front side; the direction intersecting (e.g., perpendicular to) the top and bottom surfaces of the substrate is defined as the third direction, ignoring the flatness of the top and bottom surfaces. In the direction of the top surface and the bottom surface of the substrate (i.e., the plane in which the substrate is located), two directions intersecting each other (e.g., perpendicular to each other) are defined, for example, an arrangement direction of the active regions or an arrangement direction of the conductive structures may be defined as a first direction, an extension direction of the conductive structures may be defined as a second direction, and the plane direction of the substrate may be determined based on the first direction and the second direction. In the embodiment of the disclosure, the first direction, the second direction and the third direction may be perpendicular to each other, and in other embodiments, the first direction, the second direction and the third direction may not be perpendicular. In the embodiment of the disclosure, the first direction is defined as an X-axis direction, the second direction is defined as a Y-axis direction, and the third direction is defined as a Z-axis direction.

An embodiment of the present disclosure provides a method for forming a semiconductor structure, and fig. 1 is a schematic flow chart of the method for forming a semiconductor structure provided in the embodiment of the present disclosure, as shown in fig. 1, the method for forming a semiconductor structure includes the following steps:

Step S101, providing a substrate; the substrate includes a plurality of active regions spaced apart along a first direction.

In an embodiment of the disclosure, the base includes at least a substrate; the active region is formed in a substrate, which may be a silicon substrate, and may include other semiconductor elements, such as: germanium (Ge), or include semiconductor compounds such as: silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or include other semiconductor alloys such as: silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), indium aluminum arsenide (AlInAs), gallium aluminum arsenide (AlGaAs), indium gallium arsenide (GaInAs), indium gallium phosphide (GaInP), and/or indium gallium arsenide phosphide (GaInAsP) or combinations thereof.

In some embodiments, the substrate further comprises shallow trench isolation structures between the active regions, i.e. the substrate comprises active regions and shallow trench isolation structures alternately arranged along the first direction. The shallow trench isolation structure is used to isolate two active regions adjacent to each other along the first direction, and it is also understood that the active regions are defined by the shallow trench isolation structure.

In other embodiments, the substrate may also include other functional structures, such as buried word line structures.

In step S102, a conductive plug extending into the substrate is formed on the surface of the active region.

In the disclosed embodiment, a portion of the conductive plug is located on the surface of the substrate, and another portion extends into the substrate in the thickness direction (i.e., the third direction) of the substrate to contact the active region. The material of the conductive plugs may be polysilicon.

In some embodiments, the conductive plugs have a dimension in the first direction that is less than a dimension in the first direction of the active region at the bottom of the conductive plugs.

In the embodiment of the disclosure, the conductive plug may be a bit line contact plug. In other embodiments, the conductive plugs may also be storage node contact plugs.

Step S103, forming a conductive structure on the conductive plug.

In the embodiment of the disclosure, the conductive structure is electrically connected with the conductive plug, and the conductive structure may be a bit line. In other embodiments, the conductive structure may also be a landing pad or the like.

According to the method for forming the semiconductor structure, the conductive plug is formed first, and then the conductive structure located on the surface of the conductive plug is formed. Because the conductive plug and the conductive structure can be respectively formed through two technological processes, the etching layer number and the etching depth in each technological process can be reduced, and the defects of over etching, inclination, insufficient etching and the like of the conductive plug at the bottom layer can be avoided.

Fig. 2a to 2j are schematic structural views of a semiconductor structure in a forming process according to an embodiment of the present disclosure, and the forming process of the semiconductor structure according to the embodiment of the present disclosure is described in detail below with reference to fig. 2a to 2 j.

First, referring to fig. 2a to 2e, steps S101 and S102 may be performed.

In some embodiments, the base comprises a substrate; the substrate includes active regions and shallow trench isolation structures alternately arranged along a first direction.

In some embodiments, forming a conductive plug extending into the substrate at the active area surface may include the steps of: forming an initial conductive contact structure on the surface of the active region; and etching back the initial conductive contact structure to form a conductive plug and a gap.

In some embodiments, forming an initial conductive contact structure on the active region surface may include the steps of: forming an isolation layer on the surface of the substrate; sequentially etching the isolation layer and the substrate to form an etching groove; an initial conductive contact structure is formed in the etched recess.

In implementation, the initial conductive contact structure may be formed, for example: forming a first photoresist layer with a first preset pattern on the surface of the isolation layer; the first preset pattern exposes the isolation layer positioned on the surfaces of the active region and part of the shallow trench isolation structure; etching to remove the exposed isolation layer, the active region below the isolation layer and part of the shallow trench isolation structure through the first photoresist layer to form an etched groove; and filling conductive contact materials in the etched grooves to form initial conductive contact structures.

As shown in fig. 2a, the substrate 10 includes active regions 101 and shallow trench isolation structures 102 alternately arranged in the X-axis direction; the substrate 10 is formed on a surface thereof with an isolation layer 20 and a first photoresist layer 21 having a first predetermined pattern a exposing the isolation layer 20 on a portion of the active region 101 and a portion of the surface of the shallow trench isolation structure 102. In the disclosed embodiment, the isolation layer 20 may be a silicon oxide layer, and the isolation layer 20 is used to isolate the active region 101 from other functional structures located on the surface of the substrate 10, for example, conductive structures (such as bit line or storage node contacts) that isolate the active region from the surface of the substrate.

As shown in fig. 2b, the exposed isolation layer 20, as well as the active region 101 and part of the shallow trench isolation structure 102 located under the isolation layer 20, are etched away by means of the first photoresist layer 21, forming etched recesses 22a. In the embodiment of the present disclosure, the dimension d1 of the etched recess 22a in the X-axis direction is greater than the dimension d2 of the top of the active region 101 located under the etched recess 22a in the X-axis direction, so that the active region can be electrically connected to a conductive plug formed later over a larger area.

In some embodiments, referring to fig. 2b, after forming the etched recess 22a, the method of forming the semiconductor structure further comprises: and removing the first photoresist layer. For example, the first photoresist layer may be removed by a dry or wet etching technique.

As shown in fig. 2c, the etched recesses 22a are filled with a conductive contact material to form initial conductive contact structures 22b. The top surface of the initial conductive contact structure 22b is flush with the top surface of the isolation layer 20. The conductive contact material may be any material with good conductivity, such as polysilicon.

In some embodiments, back-etching the initial conductive contact structure, forming the conductive plugs and voids may include the steps of: forming a second photoresist layer with a second preset pattern on the surfaces of the isolation layer and the initial conductive contact structure, wherein the second preset pattern exposes part of the initial conductive contact structure; and removing the exposed part of the initial conductive contact structure through etching the second photoresist layer to form a conductive plug.

As shown in fig. 2d, a second photoresist layer 23 having a second preset pattern B is formed on the surfaces of the isolation layer 20 and the initial conductive contact structure 22B, and the second preset pattern B exposes a portion of the initial conductive contact structure 22B.

As shown in fig. 2e, the exposed portion of the initial conductive contact structure 22b is etched away by the first photoresist layer 23 using a dry etching process, forming a conductive plug 22 and a void H between the isolation layer 20 and the conductive plug 22.

In the disclosed embodiment, the conductive plugs 22 may be bit line contact plugs.

In some embodiments, referring to fig. 2e, after forming the conductive plugs 22, the method of forming the semiconductor structure further includes: and removing the second photoresist layer. The second photoresist layer may be removed, for example, by dry or wet etching techniques.

In some embodiments, after forming the conductive plug, the method of forming the semiconductor structure further comprises: a dielectric layer is formed in the void.

With continued reference to fig. 2e, the voids H are filled with a dielectric material to form a dielectric layer 24 as shown in fig. 2 f. The dielectric material may be silicon nitride.

It should be noted that, with continued reference to fig. 2e, in the embodiment of the disclosure, the dimension d3 of the conductive plug 22 in the X-axis direction is smaller than the dimension d2 of the active region 101 at the bottom of the conductive plug 22 in the X-axis direction. Therefore, in the process of forming the conductive structure by subsequent etching, partial dielectric layers can be ensured to remain on the side walls of the conductive plugs, so that the conductive plugs are protected from being damaged by the reserved dielectric layers.

Next, referring to fig. 2f to 2h, step S103 may be performed.

In some embodiments, forming the conductive structure on the conductive plug may include the steps of: forming a functional material layer on the dielectric layer and the conductive plug; and etching the functional material layer to form a conductive structure.

In some embodiments, the functional material layer includes an initial conductive layer and an initial insulating layer; forming the conductive structure material layer on the dielectric layer and the conductive plug may include the steps of: and sequentially depositing a conductive material and an insulating material on the surfaces of the dielectric layer and the conductive plug to form an initial conductive layer and an initial insulating layer.

With continued reference to fig. 2f, a conductive material and an insulating material are sequentially deposited on the surfaces of the isolation layer 20, the dielectric layer 24, and the conductive plugs 22 to form an initial conductive layer 25a and an initial insulating layer 26a.

In the embodiment of the present disclosure, the initial conductive layer 25a and the initial insulating layer 26a may be formed by any one of the following deposition processes: a chemical vapor deposition (Chemical Vapor Deposition, CVD) process, a physical vapor deposition (Physical Vapor Deposition, PVD) process, an atomic layer deposition (Atomic Layer Deposition, ALD) process, a spin-on process, a coating process, a thin film process, or the like.

In the embodiment of the disclosure, the conductive material may be tungsten, cobalt, copper, aluminum, nickel, titanium nitride, etc.; the insulating material may be silicon oxide.

In some embodiments, etching the functional material layer, forming the conductive structure may include the steps of: and etching the initial insulating layer and the initial conducting layer in sequence until the dielectric layer is exposed, so as to form the conducting structure. In implementation, for example, a third photoresist layer having a third preset pattern may be formed on the surface of the initial insulating layer, where the third preset pattern includes a plurality of third sub-patterns arranged at intervals along the first direction; the third sub-pattern exposes a portion of the initial insulating layer; and etching the initial insulating layer and the initial conducting layer through the third photoresist layer to transfer the third preset pattern into the initial conducting layer and the initial insulating layer, so as to form a conducting structure.

As shown in fig. 2g, a third photoresist layer 27 having a third preset pattern is formed on the surface of the initial insulating layer 26 a; the third preset pattern includes a plurality of third sub-patterns C arranged in the X-axis direction, the third sub-patterns C exposing a portion of the preliminary insulating layer 26a.

As shown in fig. 2g and 2h, the initial insulating layer 26a and the initial conductive layer 25a are etched through the third photoresist layer 27, and the exposed initial insulating layer 26a and the initial conductive layer 25a under the exposed initial insulating layer 26a are removed to transfer a third predetermined pattern into the initial conductive layer 25a and the initial insulating layer 26a, thereby forming a conductive structure 28 composed of the conductive layer 25 and the insulating layer 26.

It should be noted that the conductive layer 25 in the embodiment of the present disclosure is one layer, and in other embodiments, the conductive layer 25 may be formed of two or more conductive layers.

In some embodiments, after forming conductive structure 28, the dielectric layer continues to be etched down, forming a protective layer on the sidewalls of the conductive plugs.

As shown in fig. 2i, the etching of the dielectric layer 24 is continued through the third photoresist layer 27 to transfer the third predetermined pattern into the dielectric layer 24. At this time, a portion of the dielectric layer 24 remains on the sidewall of the conductive plug 22, and the remaining portion of the dielectric layer 24 forms a protective layer 24a on the sidewall of the conductive plug 22.

In the embodiment of the disclosure, the initial conductive layer, the initial insulating layer and the dielectric layer are etched step by step, so that the depth of each etching can be reduced, and the probability of damage such as over-etching, under-etching or inclination of the conductive plug at the bottom layer caused by overlarge etching depth is further reduced.

In some embodiments, referring to fig. 2i, after forming the conductive plugs 22, the method of forming the semiconductor structure further includes: and removing the third photoresist layer. The third photoresist layer may be removed, for example, by a dry or wet etching technique.

In some embodiments, etching the functional material layer to form the conductive structure may also include the steps of: and sequentially etching the initial insulating layer, the initial conductive layer and the dielectric layer to form a conductive structure and a protective layer positioned on the side wall of the conductive plug.

With continued reference to fig. 2g and 2i, the initial insulating layer 26a, the initial conductive layer 25a and the dielectric layer 24 are etched through the third photoresist layer 27 to transfer a third predetermined pattern to the initial conductive layer 25a, the initial insulating layer 26a and the dielectric layer 24, forming a conductive structure 28 formed by the conductive layer 25 and the insulating layer 26, and the sidewall of the conductive plug 22 remains with a portion of the dielectric layer 24, and the remaining portion of the dielectric layer 24 forms a protective layer 24a located on the sidewall of the conductive plug 22.

In the disclosed embodiment, the conductive structures may be bit lines, with conductive structures 28 extending in the Y-axis direction.

It should be noted that, in the embodiment of the present disclosure, the dimension of the conductive plug in the first direction is smaller than the dimension of the conductive structure in the first direction, so that during the process of etching the dielectric layer, a portion of the dielectric layer remains on the sidewall of the conductive plug 22, so as to form a protection layer located on the sidewall of the conductive plug.

In the embodiment of the disclosure, the initial conductive structure conductive layer, the initial conductive structure insulating layer and the dielectric layer are etched in one step, so that the complexity of the preparation process of the semiconductor structure can be simplified, and the manufacturing cost of the semiconductor structure can be reduced.

In some embodiments, after forming the conductive structure 28, the method of forming the semiconductor structure further comprises: and forming a side wall isolation layer on the surfaces of the conductive structure and the conductive plug, wherein the side wall isolation layer comprises a first side wall layer, a second side wall layer and a third side wall layer which are sequentially arranged from inside to outside.

As shown in fig. 2j, a sidewall spacer 29 is formed on the surfaces of the conductive structure 28 and the conductive plug 22, where the sidewall spacer 29 includes a first sidewall layer 29a, a second sidewall layer 29b, and a third sidewall layer 29c sequentially arranged from inside to outside.

In the embodiment of the present disclosure, the sidewall spacer 29 is used to isolate the conductive structure from other functional structures formed later, so as to prevent leakage. The first sidewall layer 29a and the third sidewall layer 29c may be silicon nitride layers, and the second sidewall layer 29b may be a silicon oxide layer. The first side wall layer and the dielectric layer can be made of the same material, so that pollution to the formed conductive plug can be avoided.

In the embodiment of the disclosure, the conductive plug and the conductive structure are respectively formed through two etching processes, so that the number of etching layers and the etching depth in each etching process are reduced, the defects of over etching, inclination or insufficient etching of the conductive plug at the bottom layer are avoided, and the preparation yield of the semiconductor structure is improved.

Fig. 3a to 3e are schematic structural views of another semiconductor structure forming process according to an embodiment of the present disclosure, and the forming process of the semiconductor structure according to the embodiment of the present disclosure is described in detail below with reference to fig. 3a to 3 e.

In some embodiments, forming an initial conductive contact structure on the active region surface may include the steps of: forming an isolation layer and a bottom metal layer on the surface of the substrate; sequentially etching the bottom metal layer, the isolation layer and the substrate to form an etching groove; an initial conductive contact structure is formed in the etched recess.

As shown in fig. 3a, the base includes a substrate 10, and the substrate 10 includes active regions 101 and shallow trench isolation structures 102 alternately arranged along the X-axis direction; the substrate 10 has an isolation layer 20, an underlying metal layer 31 and a first photoresist layer 21 having a first predetermined pattern a formed on a surface thereof, the first predetermined pattern a exposing the underlying metal layer 31 on a surface of a portion of the active region 101 and a portion of the shallow trench isolation structure 102. In the disclosed embodiment, the underlying metal layer 31 may be a polysilicon layer.

It should be noted that, the shallow trench isolation structure 102 is filled with an isolation material, and the isolation material is also generally formed on the surface of the active region 101 due to the process, and the isolation material on the surface of the active region 101 is not shown in fig. 3 a.

As shown in fig. 3b, the exposed underlying metal layer 31, isolation layer 20, and substrate (including active region 101 and shallow trench isolation structure 102) underlying isolation layer 20 are etched away by first photoresist layer 21, forming etched recesses 22a.

As shown in fig. 3c, the etched recesses 22a are filled with a conductive contact material, forming an initial conductive contact structure 22b. The conductive contact material may be any material with good conductivity, such as polysilicon.

In the disclosed embodiment, a portion of the initial conductive contact structure 22b is located on the surface of the substrate 10, and another portion extends into the interior of the substrate 10 in the thickness direction (i.e., the Z-axis direction) of the substrate 10 to contact the active region 101. In the embodiment of the present disclosure, the dimension of the initial conductive contact structure 22b extending into the substrate 10 in the X-axis direction is larger than the dimension of the active region in the X-axis direction, i.e., the initial conductive contact structure 22b extending into the substrate 10 extends into the shallow trench isolation structures 102 on both sides of the active region 101 in the Y-axis direction.

Next, the initial conductive contact structure 22b is etched, forming conductive plugs 22 and voids H as shown in fig. 3 d.

In some embodiments, after forming the initial conductive contact structure, the method of forming the semiconductor structure further comprises: and filling a dielectric material in the gap H to form a dielectric layer.

In some embodiments, after forming the dielectric layer, the method of forming the semiconductor structure further includes: a conductive structure 28 as shown in fig. 3e is formed on the conductive plug 22. The conductive structure 28 includes a conductive layer 25 on a surface of the conductive plug 22, and an insulating layer 26 on a surface of the conductive layer 25.

In some embodiments, after forming dielectric layer 24, the method of forming the semiconductor structure further comprises: a protective layer 24a is formed on the sidewalls of the conductive plugs 22 as shown in fig. 3 e. In the embodiment of the present disclosure, the protective layer 24a may be formed by etching the dielectric layer and leaving a portion of the dielectric layer on the sidewall of the conductive plug 22.

It should be noted that, the conductive structure 28 and the protective layer 24a in the embodiment of the disclosure may be formed by a one-step etching process or may be formed by a two-step etching process. The conductive structure and the protective layer are formed through two-step etching, so that the depth of each etching can be reduced, and the probability of damage such as over-etching, insufficient etching or inclination of a conductive plug at the bottom layer caused by overlarge etching depth is further reduced. The conductive structure and the protective layer are formed by one-step etching, so that the complexity of the preparation process of the semiconductor structure can be simplified, and the manufacturing cost of the semiconductor structure can be reduced.

In some embodiments, after forming the protective layer, the method of forming the semiconductor structure further comprises: sidewall spacers (not shown) are formed on the surfaces of conductive structures 28 and conductive plugs 22.

In some embodiments, the sidewall spacer may be one layer or multiple layers, for example, the sidewall spacer includes a first sidewall layer, a second sidewall layer, and a third sidewall layer sequentially arranged from inside to outside. The first side wall layer, the second side wall layer and the third side wall layer can be of a silicon nitride-silicon oxide-silicon nitride structure or of a silicon nitride-air gap-silicon nitride structure.

It should be noted that, the forming process of the dielectric layer, the conductive structure, the protective layer and the sidewall spacer in the embodiment of the present disclosure is similar to the forming process of the dielectric layer, the conductive structure, the protective layer and the sidewall spacer in the above embodiment, and will not be repeated here.

The embodiment of the disclosure further provides a method for forming a semiconductor structure, and fig. 4 is another flow chart of the method for forming a semiconductor structure provided in the embodiment of the disclosure, as shown in fig. 4, the method for forming a semiconductor structure includes the following steps:

step S401, providing a substrate; the substrate includes a plurality of active regions spaced apart along a first direction.

In some embodiments, the base comprises a substrate; the substrate comprises active regions and shallow trench isolation structures alternately arranged along the X-axis direction.

In step S402, an initial conductive contact structure is formed on the surface of the active region.

In the disclosed embodiment, a portion of the initial conductive contact structure is located on the surface of the substrate, and another portion extends into the substrate in the thickness direction (i.e., the Z-axis direction) of the substrate to contact the active region. In the embodiment of the disclosure, the dimension of the initial conductive contact structure extending into the substrate is larger than the dimension of the active region in the X-axis direction, that is, the initial conductive contact structure extending into the substrate extends into the shallow trench isolation structures on both sides of the active region along the Y-axis direction. The material of the initial conductive contact structure may be polysilicon.

In some embodiments, the substrate surface is further formed with an isolation layer, or an isolation layer and a bottom metal layer, through which the initial conductive contact structure extends, or through which the initial conductive contact structure extends.

Step S403, etching back the initial conductive contact structure to form a conductive plug and a void.

In step S404, a dielectric layer is formed in the void.

In step S405, a functional material layer is formed on the dielectric layer and the conductive plugs.

In some embodiments, the functional material layer includes an initial conductive layer and an initial insulating layer; forming a conductive structure material layer on the dielectric layer and the conductive plug, including: and sequentially depositing a conductive material and an insulating material on the surfaces of the dielectric layer and the conductive plug to form an initial conductive layer and an initial insulating layer.

In step S406, the functional material layer is etched to form a conductive structure on the conductive plug.

In some embodiments, etching the layer of functional material to form a conductive structure on the conductive plug includes: and etching the initial insulating layer and the initial conducting layer in sequence until the dielectric layer is exposed, so as to form the conducting structure.

In an embodiment of the present disclosure, the conductive structure may be a bit line structure, and the conductive plug may be a bit line contact plug.

In the embodiment of the disclosure, after the conductive structure is formed, the dielectric layer in contact with the conductive plug may not be etched, so that the process complexity of the semiconductor structure may be simplified, and the formed conductive plug may not be damaged.

In addition, in the embodiment of the disclosure, the conductive plug and the conductive structure are respectively formed through two etching processes, so that defects of insufficient etching, excessive etching or inclination of the conductive plug caused by one-step etching of the structure with high depth-to-width ratio in the related art can be overcome.

The embodiment of the disclosure also provides a semiconductor structure as shown in fig. 2j, which is formed by the method for forming the semiconductor structure in the embodiment. The semiconductor structure includes: a substrate; the substrate comprises a plurality of active areas which are arranged at intervals along a first direction; a conductive plug located on the surface of the active region and extending into the substrate; a conductive structure located on the conductive plug; wherein the conductive structure is not self-aligned with the conductive plug.

As shown in fig. 2j, in the embodiment of the present disclosure, the base includes a substrate 10, and the substrate 10 includes active regions 101 and shallow trench isolation structures 102 alternately arranged along the X-axis direction. Conductive plugs 22 extend into substrate 10 and are located at the surface of active region 101. The conductive structure 28 includes a conductive layer 25 and an insulating layer 26 on a surface of the conductive layer 25. In the disclosed embodiment, the conductive layer 25 may be a metal tungsten layer and the insulating layer 26 may be a silicon oxide layer.

In some embodiments, the conductive plugs 22 have a dimension in the X-axis direction that is smaller than a dimension in the X-axis direction of the active region 101.

In some embodiments, the dimension of conductive plugs 22 in the X-axis direction is less than the dimension of conductive structures 28 in the X-axis direction.

In some embodiments, referring to fig. 2j, the semiconductor structure further comprises: a protective layer 24a on the sidewall of the conductive plug 22; the edges of the protective layer 24a are aligned with the edges of the conductive structures 28 and the active region 101.

In some embodiments, the semiconductor structure further includes an isolation layer 20 on the surface of the substrate 10, the isolation layer 20 being used to isolate the substrate 10 from other functional structures formed on the surface of the substrate 10.

In some embodiments, referring to fig. 2j, the semiconductor structure further comprises: and a sidewall spacer 29 on the surface of the conductive structure 28 and the conductive plug 22. The sidewall spacer 29 includes a first sidewall layer 29a, a second sidewall layer 29b, and a third sidewall layer 29c sequentially arranged from inside to outside. The sidewall spacers 29 are used to isolate the conductive structures 28 from contact and landing pads with subsequently formed storage nodes to prevent leakage.

According to the semiconductor structure provided by the embodiment of the disclosure, the conductive structure and the conductive plug are not self-aligned, so that the conductive structure and the conductive plug are not formed through one-step etching process, and defects such as over etching, tilting or insufficient etching of the conductive plug in the process of forming the conductive plug can be avoided. Therefore, the embodiment of the disclosure can provide a semiconductor structure with few defects, complete structure and excellent performance.

In addition, the embodiment of the disclosure further provides a semiconductor structure as shown in fig. 3e, where the semiconductor structure in the embodiment of the disclosure is formed by the method for forming the semiconductor structure in the embodiment. The semiconductor structure includes: a substrate; the substrate comprises a plurality of active areas which are arranged at intervals along a first direction; a conductive plug located on the surface of the active region and extending into the substrate; a conductive structure located on the conductive plug; wherein the conductive structure is not self-aligned with the conductive plug.

As shown in fig. 3e, in the embodiment of the present disclosure, the base includes a substrate 10, and the substrate 10 includes active regions 101 and shallow trench isolation structures 102 alternately arranged along the X-axis direction. Conductive plugs 22 extend into substrate 10 and are located at the surface of active region 101. The conductive structure 28 includes a conductive layer 25 and an insulating layer 26 on a surface of the conductive layer 25.

In some embodiments, the dimension of the conductive plugs 22 in the X-axis direction is smaller than the dimension of the active region 101 at the bottom of the conductive plugs 22 in the X-axis direction.

In some embodiments, referring to fig. 3e, the semiconductor structure further comprises: a protective layer 24a on the sidewall of the conductive plug 22; the edges of the protective layer 24a are aligned with the edges of the conductive structures 28 and the active region 101.

In some embodiments, referring to fig. 3e, the semiconductor structure further includes an isolation layer 20 on the surface of the substrate 10, where the isolation layer 20 is used to isolate the substrate 10 from other functional structures formed on the surface of the substrate 10.

In some embodiments, referring to fig. 3e, the semiconductor structure further includes an underlying metal layer 31 on the surface of the isolation layer 20.

According to the semiconductor structure provided by the embodiment of the disclosure, the conductive structure and the conductive plug are not self-aligned, so that the conductive structure and the conductive plug are not formed through one-step etching process, and defects such as over etching, tilting or insufficient etching of the conductive plug in the process of forming the conductive plug can be avoided.

The semiconductor structure provided by the embodiment of the disclosure is formed by the method for forming the semiconductor structure in the embodiment, so that the formed semiconductor structure has few defects, high yield, complete structure and excellent performance.

The semiconductor structure formed by the method provided by the embodiments of the present disclosure is similar to the semiconductor structure in the above embodiments, and for technical features that are not disclosed in detail in the embodiments of the present disclosure, please refer to the above embodiments for understanding, and a detailed description is omitted here.

In several embodiments provided by the present disclosure, it should be understood that the disclosed apparatus and methods may be implemented in a non-targeted manner. The above described device embodiments are only illustrative, e.g. the division of units is only one logical function division, and there may be other divisions in actual implementation, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the components shown or discussed are coupled to each other or directly. The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments.

The above is merely some embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present disclosure, and should be covered in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, comprising:

2. The semiconductor structure of claim 1, wherein a dimension of the conductive plug in the first direction is less than a dimension of the conductive structure in the first direction.

3. The semiconductor structure of claim 2, wherein a dimension of the conductive plug in the first direction is less than a dimension of the active region in the first direction.

4. The semiconductor structure of any one of claims 1 to 3, further comprising: the protective layer is positioned on the side wall of the conductive plug;

5. A method of forming a semiconductor structure, the method comprising:

And forming a conductive structure on the conductive plug.

6. The method of claim 5, wherein forming conductive plugs extending into the substrate at the active area surface comprises:

7. The method of claim 6, wherein a dimension of the conductive plug in the first direction is smaller than a dimension of an active region located at a bottom of the conductive plug in the first direction.

8. The method of claim 6, wherein the method further comprises:

a dielectric layer is formed in the void.

9. The method of claim 8, wherein forming a conductive structure on the conductive plug comprises:

And etching the functional material layer to form the conductive structure.

10. The method of claim 9, wherein the layer of functional material comprises an initial conductive layer and an initial insulating layer; forming a conductive structure material layer on the dielectric layer and the conductive plug, including:

11. The method of claim 10, wherein the etching the functional material layer to form the conductive structure comprises:

12. The method of claim 9, wherein after forming the conductive structure, the method further comprises:

13. The method of claim 9, wherein the etching the functional material layer to form the conductive structure comprises:

14. The method of claim 11 or 13, wherein a dimension of the conductive plug in the first direction is smaller than a dimension of the conductive structure in the first direction.

15. The method of claim 6, wherein the base further comprises a substrate comprising the active region; forming an initial conductive contact structure on the surface of the active region, including:

forming an isolation layer on the surface of the substrate;

and forming the initial conductive contact structure in the etched groove.

16. The method of claim 6, wherein the base further comprises a substrate comprising the active region; forming an initial conductive contact structure on the surface of the active region, and further comprising:

and forming the initial conductive contact structure in the etched groove.

17. The method of any one of claims 5 to 13, wherein after forming the conductive structure, the method further comprises: