CN117992098A - Remote upgrading system and method - Google Patents

Abstract

The present invention relates to the field of programmable logic devices, and in particular, to a remote upgrade system and method. The system transmits the first packet of data through the upper computer, and can judge whether subsequent data need to be transmitted according to the return signal; the analysis and verification module receives data sent by the upper computer and effectively extracts the data sent by the upper computer to obtain effective data; the writing counting module writes the effective data into the flash, counts when each writing is completed, and takes the counting result as a return signal until the remote upgrading is completed. According to the invention, the upper computer judges the return signal before sending the data packet, combines with effectively extracting the data sent by the upper computer, counts when writing the effective data into the flash each time, improves the accuracy and efficiency of remote upgrading, further reduces the cost and improves the user experience.

Description

Remote upgrading system and method

Technical Field

The present invention relates to the field of programmable logic devices, and in particular, to a remote upgrade system and method.

Background

With the development of technology, the market of lidar is also expanding. When fpga program problems or updates occur to the lidar products, if the conventional solution is adopted, all the products need to be recalled first, then manually disassembled, and then the software is updated again. The traditional mode is adopted to influence the user experience on one hand and consume manpower and financial resources on the other hand.

The foregoing is provided merely for the purpose of facilitating understanding of the technical solutions of the present invention and is not intended to represent an admission that the foregoing is prior art.

Disclosure of Invention

The invention mainly aims to provide a remote upgrading system and a remote upgrading method, and aims to solve the technical problems that in the prior art, fpga programs are required to be recalled and then manually disassembled to update software, so that the cost is high and the efficiency is low.

To achieve the above object, the present invention provides a remote upgrade system, including:

the upper computer is used for sending the first packet of data and judging whether the subsequent data need to be sent or not according to the return signal;

The analysis and verification module is used for receiving the data sent by the upper computer and effectively extracting the data sent by the upper computer to obtain effective data;

And the writing counting module is used for writing the effective data into the flash, counting when each writing is completed, and taking the counting result as the return signal until the remote upgrading is completed.

Optionally, the remote upgrade system further includes a packaging and sending module, where the packaging and sending module is configured to receive the return signal, package the return signal, and send the packaged return signal to the upper computer.

Optionally, the parsing and checking module and the packaging and sending module respectively establish communication connection with the upper computer based on ethernet.

Optionally, the parsing and checking module is further configured to parse the received data sent by the upper computer to obtain a UDP packet, and perform effective extraction on the UDP packet to obtain the effective data.

Optionally, the parsing and checking module is further configured to identify a frame header, store the valid data into the FIFO according to the identification result, and check the valid data.

Optionally, the write count module is an instantiated SpiProgrammer module provided by Quickboot.

In addition, in order to achieve the above object, the present invention also provides a remote upgrade method, which includes:

partitioning the flash to obtain a jump area and an upgrade area, wherein the jump area stores jump programs and keyword data, and the upgrade area stores upgrade data;

Judging whether the keyword data comprises a skip field or not, and if so, operating the skip program to skip to the upgrading area;

And loading the upgrade data to complete remote updating.

Optionally, before the partitioning the flash to obtain the jump area and the upgrade area, the method further includes: partitioning the flash to obtain a configuration area, wherein configuration data are stored in the configuration area.

Optionally, after the determining whether the keyword data includes a skip field, if so, running the skip program to skip to the upgrade area, the method further includes: if the key data does not include the jump field, fpga loads the configuration data in the configuration area; based on the configuration data, the fpga configuration is updated.

Optionally, the loading the upgrade data to complete remote updating includes: loading the upgrade data and restarting fpga; based on the upgrade data, the loader in fpga reloads the upgrade area to complete the remote update.

The invention sends the first packet of data through the upper computer, and can judge whether to need to send the subsequent data according to the return signal; the analysis and verification module receives data sent by the upper computer and effectively extracts the data sent by the upper computer to obtain effective data; the writing counting module writes the effective data into the flash, counts when each writing is completed, and takes the counting result as a return signal until the remote upgrading is completed. According to the invention, the upper computer judges the return signal before sending the data packet, combines with effectively extracting the data sent by the upper computer, counts when writing the effective data into the flash each time, improves the accuracy and efficiency of remote upgrading, further reduces the cost and improves the user experience.

Drawings

FIG. 1 is a block diagram of a first embodiment of a remote upgrade system according to the present invention;

FIG. 2 is a flow chart of a remote upgrade implementation of the remote upgrade system of the present invention;

FIG. 3 is a flowchart of a remote upgrade method according to a first embodiment of the present invention;

Fig. 4 is a flowchart of a second embodiment of the remote upgrade method according to the present invention.

The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.

Detailed Description

It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

Referring to fig. 1, fig. 1 is a block diagram illustrating a first embodiment of a remote upgrade system according to the present invention.

As can be seen from fig. 1, in this embodiment, the remote upgrade system includes:

the upper computer 101 is configured to send the first packet of data, and determine, according to the return signal, whether subsequent data needs to be sent;

the analysis and verification module 102 is configured to receive data sent by the upper computer, and effectively extract the data sent by the upper computer to obtain effective data;

And the writing counting module 103 is used for writing the effective data into the flash, counting when each writing is completed, and taking the counting result as the return signal until the remote upgrading is completed.

It should be noted that, the scenario of the present embodiment is to implement remote update on the A7 series fpga based on the ethernet mounting QuickBoot scheme. Wherein Quickboot is a fast start-up technology based on ethernet, which can accelerate the start-up time of the device. fpga is a programmable logic device that can implement different digital circuit functions by configuring programmable logic resources within the device.

Specifically, the upper computer 101 sends the first packet data to the parsing and checking module 102, and then determines whether to send the subsequent second packet data or resend the first packet data according to the determination result of the return signal. The analysis and verification module 102 receives the first packet of data sent by the upper computer 101, extracts the valid data of the data, and sends the data.

Further, the write count module 103 is provided with a counter, and each time valid data is written into the flash, the value of the counter is increased by 1, and the value of the counter is packed into a data packet according to a predetermined format, for example, a fixed-length data packet format is used or a specific frame header and a specific frame tail are added. And then sending the packed return signal to the upper computer through Ethernet communication.

It should be noted that, after the initial value of the counter is 1 and the upper computer 101 sends the first packet data, after the write count module 103 writes the valid data into the flash, the counter is added with 1 and then is added with 2, if the return signal received by the upper computer 101 is 2, the update process is indicated to be normal, the upper computer 101 sends the second packet data, if the return signal received by the upper computer 101 is 1, the write count module 103 does not completely write the valid data in the first packet data into the flash, at this time, the upper computer 101 resends the first packet data until the remote upgrade is completed.

In this embodiment, the upper computer 101 sends the first packet of data, and can determine whether to send the subsequent data according to the return signal; the analysis and verification module receives data sent by the upper computer 101 and effectively extracts the data sent by the upper computer 101 to obtain effective data; the writing counting module writes the effective data into the flash, counts when each writing is completed, and takes the counting result as a return signal until the remote upgrading is completed. In this embodiment, the upper computer 101 determines the return signal before sending the data packet, combines to effectively extract the data sent by the upper computer 101, and counts when writing the effective data into the flash each time, thereby improving the accuracy and efficiency of remote upgrade, further reducing the cost, and improving the user experience.

Based on the first embodiment of the remote upgrade system described above, a second embodiment of the remote upgrade system is now presented.

Based on the above first embodiment, in this embodiment, the remote upgrade system further includes a packaging and transmitting module, where the packaging and transmitting module is configured to receive the return signal, and package the return signal and transmit the packaged return signal to the upper computer.

Specifically, if the write count module 103 completely writes the valid data into the flash, the counter is incremented by 1, and if the write count module 103 does not completely write the valid data into the flash, the counter is unchanged. The write count module 103 transmits the counter value to a packet transmission module, which packets the counter value into a data packet according to a predetermined format and transmits the data packet as a return signal to the host computer 101.

Further, after the upper computer 101 receives the data packet (return signal), the data packet is parsed to extract the counter value, so that the upper computer 101 can perform corresponding processing according to the received counter value, for example, determine whether the data is normal, record the data or perform other operations.

Optionally, the upper computer 101 may send a corresponding feedback signal to the packaging sending module, such as confirmation receiving, retransmission request, etc., according to the need, so as to improve reliability of communication and accuracy of data transmission.

Based on the first embodiment, in this embodiment, the parsing and checking module and the packaging and sending module establish communication connection with the host computer based on ethernet.

Specifically, an appropriate ethernet communication protocol, such as TCP/IP, UDP/IP, etc., is selected according to the actual situation, and appropriate network parameters including IP addresses, subnet masks, gateways, etc., are configured in the upper computer and the lower computer (fpga). In the upper and lower computers (fpga), network connections are established on the assigned IP addresses and ports using a suitable network communications library or tool, such as a Socket programming library.

Further, an analysis and verification module is implemented in the lower computer (fpga) and is used for receiving the data packet from the upper computer, analyzing information in the data packet and verifying the information, so that the analysis and verification module can correctly identify the frame head and the frame tail of the data packet and can verify the integrity and the correctness of the data according to a contracted verification mode. And the packaging and transmitting module is realized in the lower computer (fpga) and is used for packaging the data into data packets according to the processing result of the analysis and verification module and transmitting the data packets to the upper computer, so that the packaging and transmitting module can correctly organize the format of the data packets according to the communication protocol requirements and can transmit the data packets through a network. Logic for realizing data interaction at the upper computer end and the lower computer end respectively comprises data sending and receiving, and analyzing and processing the data according to a format specified by a communication protocol.

Optionally, after establishing communication connection and realizing a data interaction function, verification and debugging can be performed by means of sending test data packets, observing data receiving conditions and the like, so that the stability of communication and the accuracy of data are ensured.

In the embodiment, the upper computer sends the first packet of data, and whether the subsequent data need to be sent or not can be judged according to the return signal; the analysis and verification module receives data sent by the upper computer and effectively extracts the data sent by the upper computer to obtain effective data; the writing counting module writes the effective data into the flash, counts when each writing is completed, and takes the counting result as a return signal until the remote upgrading is completed. In the embodiment, the upper computer judges the return signal before sending the data packet, combines the effective extraction of the data sent by the upper computer, counts the effective data when writing the effective data into the flash each time, improves the accuracy and the efficiency of remote upgrading, further reduces the cost and improves the user experience.

Based on the second embodiment of the remote upgrade system described above, a third embodiment of the remote upgrade system is now presented.

Based on the above second embodiment, in this embodiment, the parsing and checking module is further configured to parse the received data sent by the upper computer to obtain a UDP packet, and effectively extract the UDP packet to obtain the effective data; the analysis and verification module is also used for identifying the frame head, storing the effective data into the FIFO according to the identification result, and verifying the effective data.

Referring to fig. 2, fig. 2 is a flowchart of a remote upgrade implementation of the remote upgrade system according to the present invention;

Specifically, the analysis and verification module receives data from the upper computer. And the analysis and verification module analyzes the data according to the communication protocol and identifies the start and the end of the UDP packet. The fields of the UDP packet, such as destination port, source port, data length, checksum, etc., are parsed according to the format specified by the protocol. And checking the analyzed UDP packet, including checksum verification, length verification, source and destination address verification and the like, so as to ensure the integrity and correctness of the received data and prevent the data from being damaged or tampered. And extracting the effective data part from the UDP packet according to the data format specified by the protocol so as to ensure that the extracted effective data is in a correct format and meets the expected data structure and requirements. The extracted valid data is passed to a subsequent module or memory, such as a FIFO buffer, for subsequent processing or storage. And an appropriate error processing mechanism is realized in the analysis and verification module, including discarding of error data, retransmission request, error counting and the like, so as to ensure that the analysis and verification module can cope with various abnormal conditions and ensure the stability and reliability of the system. Through the steps, the analysis and verification module can effectively process the received data and extract effective parts so that the subsequent modules can further process or store the received data. Meanwhile, the error processing mechanism also ensures that the system can correctly cope when encountering abnormal conditions, and ensures the stability and reliability of the system.

Furthermore, the analysis and verification module can identify the frame head, store the effective data into the FIFO and verify the effective data besides analyzing and verifying the received data and extracting the effective data. After the analysis and verification module receives the data, the received data is compared with a predefined frame head mode, and the data is analyzed and identified to determine the initial position of the frame head. After the frame head is identified, the analysis and verification module extracts the effective data part which needs to be stored in the FIFO from the initial position of the frame head according to the data format specified by the protocol. The analysis and verification module stores the extracted effective data into the FIFO for processing or storage by the subsequent module, and ensures that the data stored into the FIFO are stored according to the correct sequence and format, so that the subsequent module can read and process correctly. The analysis and verification module performs verification on the effective data stored in the FIFO to ensure the integrity and the correctness of the data, and performs checksum verification, such as checksum, CRC and the like, on the effective data according to a verification mode specified by a protocol.

Optionally, in the verification process, the parsing and verification module needs to implement a proper error processing mechanism to process the data with failed verification, such as discarding, retransmitting requests, etc., so as to ensure that the parsing and verification module can timely find and process errors, thereby ensuring the stability and reliability of the system. Through the steps, the analysis and verification module can finish the functions of frame head identification, effective data extraction, FIFO storage, verification and the like of the received data, and provides accurate and reliable data for the subsequent modules.

Based on the second embodiment, in this embodiment, the write count module is an instantiated SpiProgrammer module provided by Quickboot.

It should be noted that, in the fpga design, the spiprogrammer module provided by the exemplary Quickboot scheme is a module for programming a flash memory through the SPI (Serial Peripheral Interface) interface. The SPI interface is typically used for communication and data transfer with external devices (e.g., flash memory, sensors, etc.). The spiprogrammer module allows fpga to load programs or configuration files from flash memory at startup, thus enabling a quick start (Quickboot) function.

Specifically, the functions of the module include:

SPI interface control: and communicating with an external Flash memory, wherein the communication comprises the steps of sending read-write commands, addresses and data.

Programming a flash memory: and writing programs or configuration files required by the FPGA into a Flash memory.

Loading at the starting time: at fpga start-up, a program or configuration file is loaded from flash memory into fpga to achieve quick start-up.

By instantiating the spiprogrammer module provided by the Quickboot scheme, the task of communication and programming with the flash memory in the fpga design can be simplified, the quick starting function is realized, and the starting speed and efficiency of the system are improved.

In this embodiment, the lower computer first identifies the frame header, and checks (64×16 bytes) and puts data into fifo (fifo actual size 511×4 bytes), the number of valid bytes stored in fifo is 64×16=1024byte, fifo write clock 125Mhz, read clock 20Mhz, write 8 bits, and read 32 bits. After the valid data in one packet is fully written into fifo, the SpiProgrammer module is started again, then a flash erasing completion signal, an idle signal and a data verification correct signal are waited, then reading enabling is started to fetch 256 bytes from fifo and transmit the data to the spiflashprogrammer module (fifo is used for extracting 256 bytes once), one packet of data can be written into 4 pages of flash (4 x 256 bytes) by the network, the page programming completion signal SpiWrPageDone is pulled up after 1024 bytes are written, then a counter is added with 1 and used as a return signal for the upper computer by the lower computer, the upper computer 101 sends the next packet of data, and the process is sequentially circulated until updating is completed.

In the embodiment, the upper computer sends the first packet of data, and whether the subsequent data need to be sent or not can be judged according to the return signal; the analysis and verification module receives data sent by the upper computer and effectively extracts the data sent by the upper computer to obtain effective data; the writing counting module writes the effective data into the flash, counts when each writing is completed, and takes the counting result as a return signal until the remote upgrading is completed. In the embodiment, the upper computer judges the return signal before sending the data packet, combines the effective extraction of the data sent by the upper computer, counts the effective data when writing the effective data into the flash each time, improves the accuracy and the efficiency of remote upgrading, further reduces the cost and improves the user experience.

In addition, the embodiment of the invention also provides a remote upgrading method.

Referring to fig. 3, fig. 3 is a flow chart of a first embodiment of a remote upgrade method according to the present invention;

The remote upgrading method comprises the following steps:

s1: partitioning the flash to obtain a jump area and an upgrade area, wherein the jump area stores jump programs and keyword data, and the upgrade area stores upgrade data;

S2: judging whether the keyword data comprises a skip field or not, and if so, operating the skip program to skip to the upgrading area;

s3: and loading the upgrade data to complete remote updating.

Specifically, in the Quickboot scheme, the flash is divided into a skip area (Quickboot head), an upgrade area (Update Bitstream), and a configuration area (Golden Bitstream). Wherein the jump area (Quickboot head) includes a key and a jump program. fpga reading data from the 0 address of the flash, if the data of the key address is displayed as off, ignoring the jump program, and loading a configuration area (Golden Bitstream); if the current value is on, executing a jump procedure, and jumping to an upgrade area (Update Bitstream) for loading, thereby realizing remote updating.

Further, a SpiProgrammer module provided by the Quickboot scheme illustrated in the fpga design is configured to write an Update area (Update Bitstream) file into a flash, generate a Bitstream file in VIVADO, regenerate an xxx_design.mcs file, place a Perl script provided by the Quickboot scheme under a directory where the xxx_design.mcs file is located, and generate an initial.mcs file and an updata.mcs file. And solidifying the initial.mcs file into fpga, and then sending a package by the upper computer according to a communication protocol agreed with the lower computer, so as to finally finish remote updating.

By generating a bit stream (bitstream) file in VIVADO, and further generating a mcs file for configuration and startup of fpga. Through the Perl script provided by Quickboot scheme, an initial.mcs file and an updata.mcs file are generated, so that the remote upgrade of fpga is finished, and smooth completion of the upgrade is ensured.

In the embodiment, a jump area and an upgrade area are obtained by partitioning a flash, wherein the jump area stores jump programs and keyword data, and the upgrade area stores upgrade data; then judging whether the key word data comprises a skip field or not, and if so, operating a skip program to skip to an upgrade area; finally, the upgrade data is loaded to complete remote updating, so that different upgrade requirements can be met, the upgrade efficiency is improved, and the upgrade cost is reduced.

Referring to fig. 4, fig. 4 is a flowchart illustrating a remote upgrade method according to a second embodiment of the present invention.

Based on the first embodiment of the remote upgrade method, in this embodiment, after step S2, the method further includes:

S2a: if the key data does not include the jump field, fpga loads the configuration data in the configuration area;

s2b: updating the fpga configuration based on the configuration data;

Specifically, if the key data does not include a jump field, fpga will load the configuration data in the configuration area. Then, based on these configuration data, fpga will perform configuration updates. This means fpga will update its current configuration state with the new configuration data in the configuration area without performing any jumps or other operations. The updated configuration data will be loaded fpga to implement new functionality or performance improvements, or to fix the previous problem.

Further, the configuration update fpga is implemented in the above manner without performing any jump operations. By loading new configuration data in the configuration area fpga, its current configuration state can be updated, thereby enabling the addition of new functionality, improvement of performance, or repair of previous problems without interrupting the current operating state. This approach simplifies the configuration update process, improves the flexibility and maintainability of the system, and reduces the time and resource consumption required for configuration update.

Based on the above second embodiment, a third embodiment of the remote upgrade method of the present invention is presented. In this embodiment, step S3 includes:

s31: loading the upgrade data and restarting fpga;

s32: based on the upgrade data, the loader in fpga reloads the upgrade area to complete remote updating;

Specifically, fpga loads upgrade data sent by the upper computer, the data includes new configuration information or program code, and fpga restarts to apply the new configuration information or program code after the upgrade data is loaded. The loader reloads the upgrade area, i.e. the area where the new configuration information or program code is located, and after reloading the upgrade area, fpga completes remote update, so that the new configuration information or program code can be run, and the update or repair of the function is realized.

Further, by restarting fpga and reloading the upgrade area, fpga may apply new configuration information or program code to complete the remote update. This approach allows for updates fpga at run-time without downtime, thereby enabling continuous operation of the system and seamless updates. Remote updates can be used to add new functionality, improve performance, or fix problems before, while reducing downtime of the system, improving availability and flexibility of the system.

In the embodiment, a jump area and an upgrade area are obtained by partitioning a flash, wherein the jump area stores jump programs and keyword data, and the upgrade area stores upgrade data; then judging whether the key word data comprises a skip field or not, and if so, operating a skip program to skip to an upgrade area; finally, the upgrade data is loaded to complete remote updating, so that different upgrade requirements can be met, the upgrade efficiency is improved, and the upgrade cost is reduced.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.

The foregoing embodiment numbers of the present invention are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.

From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. read-only memory/random-access memory, magnetic disk, optical disk), comprising instructions for causing a terminal device (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to perform the method according to the embodiments of the present invention.

The foregoing description is only of the preferred embodiments of the present invention, and is not intended to limit the scope of the invention, but rather is intended to cover any equivalents of the structures or equivalent processes disclosed herein or in the alternative, which may be employed directly or indirectly in other related arts.

Claims (10)

1. A remote upgrade system, comprising:

the upper computer is used for sending the first packet of data and judging whether the subsequent data need to be sent or not according to the return signal;

The analysis and verification module is used for receiving the data sent by the upper computer and effectively extracting the data sent by the upper computer to obtain effective data;

And the writing counting module is used for writing the effective data into the flash, counting when each writing is completed, and taking the counting result as the return signal until the remote upgrading is completed.

2. The remote upgrade system according to claim 1, further comprising a packaging and transmitting module, wherein the packaging and transmitting module is configured to receive the return signal, and to package the return signal and transmit the packaged return signal to the upper computer.

3. The remote upgrade system of claim 2, wherein the parsing and checking module and the packaging and transmitting module establish communication connection with the upper computer based on ethernet, respectively.

4. The remote upgrade system according to claim 1, wherein the parsing and checking module is further configured to parse the received data sent by the upper computer to obtain a UDP packet, and effectively extract the UDP packet to obtain the valid data.

5. The remote upgrade system of claim 4, wherein the parsing and checking module is further configured to identify a frame header, store the valid data into the FIFO according to the identification result, and check the valid data.

6. The remote upgrade system of claim 1, wherein the write count module is an instantiated SpiProgrammer module provided by Quickboot.

7. A method of remote upgrade, comprising:

partitioning the flash to obtain a jump area and an upgrade area, wherein the jump area stores jump programs and keyword data, and the upgrade area stores upgrade data;

Judging whether the keyword data comprises a skip field or not, and if so, operating the skip program to skip to the upgrading area;

And loading the upgrade data to complete remote updating.

8. The remote upgrade method according to claim 7, wherein before the partitioning the flash to obtain the jump area and the upgrade area, the method further comprises:

Partitioning the flash to obtain a configuration area, wherein configuration data are stored in the configuration area.

9. The remote upgrade method according to claim 8, wherein after said determining whether the key data includes a jump field, if so, running the jump program to jump to the upgrade area, further comprising:

if the key data does not include the jump field, fpga loads the configuration data in the configuration area;

based on the configuration data, the fpga configuration is updated.

10. The remote upgrade method of claim 7, wherein the loading the upgrade data to complete a remote upgrade comprises:

loading the upgrade data and restarting fpga;

based on the upgrade data, the loader in fpga reloads the upgrade area to complete the remote update.