CN117990962A - Probe card and chip test system - Google Patents

Abstract

The present disclosure provides a probe card and a chip test system, including: a substrate comprising a working surface and a non-working surface opposite to the working surface, the substrate being provided with a printed circuit; the probe is arranged on the working surface of the substrate; the tester channel is arranged on the working surface of the substrate and used for connecting a tester; the probe channel is electrically connected with the tester channel through a circuit on the substrate and is used for connecting the probe; the lead wire preset end is arranged on the working surface of the substrate and is connected with an external lead wire, the external lead wire is used for being connected with a signal input end of an oscilloscope, and the lead wire preset end is electrically connected with the channel of the tester through a circuit on the substrate; and a controllable switch disposed on a path between the lead presets and the tester channel. The method and the device can be used for rapidly and accurately checking the reasons of the failure of the test items and improving the test and debugging progress.

Description

Probe card and chip test system

Technical Field

The present disclosure relates to the field of semiconductor technology, and in particular, to a probe card and a chip testing system.

Background

The CP (Chip Probe) test is an important step in the processing of semiconductor integrated circuits, which is an electrical parameter measurement and performance test performed prior to dicing in order to verify the consistency of the design specifications of the integrated circuits. CP test systems are a sophisticated set of test equipment that generally include three parts: a tester (tester), a probe station (prober), a probe Card (probe Card). The tester is connected with the probe card and provides a test signal; the probe station carries the test wafer and is connected with the probe card, thereby achieving the purpose of testing the wafer. Under normal conditions, after the tester inputs a series of electric signals to the chip, the chip end outputs a series of electric signals, and after the tester receives the chip output, the tester can measure and compare voltage or current and the like, thereby judging whether the chip functions or parameters are qualified according to the measured result. If the feedback signal received by the testing machine is consistent with the expected value, the test item is qualified; if the signal received by the tester is inconsistent with the expectation, the test item fails. In the test process, if the test item fails, the reason of the failure of the test item may need to be further checked, however, the existing CP test system is often low in efficiency in the check process, and the problem cannot be quickly and accurately checked.

Disclosure of Invention

The invention aims to provide a probe card and a chip test system, which can rapidly and accurately check the reasons of failure of test items and improve test and debugging progress. The specific scheme is as follows:

According to a first aspect of the present disclosure, there is provided a probe card comprising: a substrate comprising a working surface, the substrate being provided with a printed circuit; the probe is arranged on the working surface of the substrate; the tester channel is arranged on the working surface of the substrate and used for connecting a tester; the probe channel is arranged on the working surface of the substrate and is electrically connected with the tester channel through a circuit on the substrate, and the probe channel is used for connecting the probe; the lead wire preset end is arranged on the working surface of the substrate and is connected with an external lead wire, the external lead wire is used for being connected with the signal input end of the oscillograph, and the lead wire preset end is electrically connected with the channel of the tester through a circuit on the substrate; the controllable switch is arranged on a passage between the lead preset and the tester channel; the controllable switch is configured to be in an open state at the beginning of a test, and the controllable switch is transitioned from the open state to a closed state in response to a first instruction of the testing machine if a test item of the test chip fails.

Optionally, the controllable switch is a multi-path selection switch, one end of the multi-path selection switch is connected with the lead preset end, and multi-path selection ends of the multi-path selection switch are respectively connected with different channels of the tester; the controllable switch is configured to gate a specified one of the tester channels in response to a second instruction of the tester.

Optionally, the probe card includes a plurality of lead presets and a plurality of controllable switches, and each lead preset corresponds to one of the controllable switches.

Optionally, the switch is a relay.

Optionally, the tester channels are symmetrically arranged along the edge of the working surface; the probe channel is arranged between the tester channel and the probe; the lead wire preset end is arranged between the tester channel and the probe.

Optionally, the probe channels are symmetrically distributed with respect to the center of the substrate, and the lead wire preset ends are symmetrically distributed with respect to the center of the substrate.

According to a second aspect of particular embodiments of the present disclosure, the present disclosure provides a chip test system comprising: the probe card is connected with the signal input end of the oscillometric device through the lead wire preset end and the external lead wire, wherein the testing machine further comprises: and a controller configured to control the controllable switch to switch between a closed state and an open state.

Optionally, the controller is configured to: providing a test signal to a test chip; acquiring a response signal of the test chip based on the test signal; judging whether the test item passes or not according to the response signal; if the test item does not pass, sending the first instruction to the controllable switch to enable the controllable switch to be changed from an open state to a closed state, so that a signal on the test chip is connected to the oscillometric device; and if the test item passes, marking the test chip as qualified.

Optionally, the controller is further configured to: judging a reason for the test item not passing according to the oscillometric device, wherein the reason is a chip self reason or a test environment reason; if the reason causing the test item to fail is a test environment reason, keeping the controllable switch in a closed state, and waiting for debugging the test environment; if the reason is the reason of the chip, marking the test chip as unqualified

Optionally, the controller is further configured to: when the input waveform of the test chip output by the oscillometric device is consistent with the test signal and the waveform of the response signal is inconsistent with the preset output waveform of the test chip, judging that the reason causing the test item to fail is the reason of the chip.

Compared with the prior art, the scheme of the embodiment of the disclosure can rapidly and accurately check the reasons of the failure of the test item and improve the test and debugging progress.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort. In the drawings:

fig. 1 is a schematic diagram of a conventional CP test system.

Fig. 2 schematically illustrates a structural diagram of a chip test system according to an embodiment of the present invention.

Fig. 3 schematically illustrates a structure of a probe card according to an embodiment of the present invention.

Fig. 4 schematically illustrates a structure of a controllable switch according to an embodiment of the present invention.

Fig. 5 is a flowchart of a test method according to an embodiment of the present invention.

Fig. 6 is a schematic structural diagram of a testing device according to an embodiment of the present invention.

Fig. 7 is a schematic diagram of an electronic device connection structure according to an embodiment of the present invention.

Detailed Description

For the purpose of promoting an understanding of the principles and advantages of the disclosure, reference will now be made in detail to the drawings, in which it is apparent that the embodiments described are only some, but not all embodiments of the disclosure. Based on the embodiments in this disclosure, all other embodiments that a person of ordinary skill in the art would obtain without making any inventive effort are within the scope of protection of this disclosure.

The terminology used in the embodiments of the disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used in this disclosure of embodiments and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, the "plurality" generally includes at least two.

It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

It should be understood that although the terms first, second, third, etc. may be used in embodiments of the present disclosure, these descriptions should not be limited to these terms. These terms are only used to distinguish one from another. For example, a first may also be referred to as a second, and similarly, a second may also be referred to as a first, without departing from the scope of embodiments of the present disclosure.

The words "if", as used herein, may be interpreted as "at … …" or "at … …" or "in response to a determination" or "in response to a detection", depending on the context. Similarly, the phrase "if determined" or "if detected (stated condition or event)" may be interpreted as "when determined" or "in response to determination" or "when detected (stated condition or event)" or "in response to detection (stated condition or event), depending on the context.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a product or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such product or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a commodity or device comprising such elements.

Alternative embodiments of the present disclosure are described in detail below with reference to the drawings.

Fig. 1 is a diagram illustrating an application scenario illustrating a semiconductor electrical testing system at a wafer stage, i.e., CP (Chip Probe) testing system 10, according to an embodiment of the present invention. The electrical test of the semiconductor at the wafer stage refers to testing the wafer before the chip is unpacked, so that the chip with problems can be removed before the chip is packaged, and the subsequent packaging cost is saved.

CP test system 10 is a sophisticated test set that generally includes three parts: a tester (tester) 11, a probe station (prober) 12, a probe Card (probe Card) 13. The tester 11 is integrated circuit testing equipment, and is controlled by a testing program to generate a testing signal; the probe station 12 is a device for carrying a wafer, and can perform alignment of the wafer and alignment of the probe card; the probe card 13 is hardware for carrying probes, and the probe card 13 connects the probes with signal channels of the tester 11.

With respect to the connection of the various components of the CP test system 10, the tester 11 is connected to the probe card 13, providing test signals; the probe station 12 carries a test wafer and is connected to a probe card 13. Specifically, the probe station 12 carries the probe card 13 and the test wafer, and is responsible for the functions of transferring the test wafer, aligning the probe tip position on the probe card 13, and the like, so as to align the signal pin position of the test wafer with the probe tip position of the probe to ensure normal contact.

Under normal conditions, after the tester 11 inputs a series of electrical signals to the chip, the chip end outputs a series of electrical signals, and after the tester 11 receives the chip output, measurement and comparison of voltage or current and the like can be performed, so that whether the chip functions or parameters are qualified or not is judged according to the measurement result.

If the feedback signal received by the tester 11 is consistent with the expectation, the test item is qualified; conversely, if the signal received by tester 11 is inconsistent with the expectation, the test item fails. When a test item fails, there are generally two possibilities, one is a problem with the chip and the other is a problem with the test environment. In the process of checking the failure reasons of the test items, the input and output signal waveforms of the chip are usually required to be observed, and the check is performed step by step.

However, the existing CP test system 10 tends to be inefficient in checking the test environment, and cannot quickly and accurately check the problem. For example, although some existing testers have waveform tools, which can grasp the waveform of the chip to find the failure position and perform appropriate debugging, the waveform tools of the testers have waveform drawing by running test items multiple times, so that the time required for drawing the waveform is long, and the waveform drawing is not a real-time signal, and affects the debugging progress.

In order to solve the above technical problems, an embodiment of the present invention provides a probe card, including:

a substrate comprising a working surface and a non-working surface opposite to the working surface, the substrate being provided with a printed circuit;

The probe is arranged on the working surface of the substrate;

the tester channel is arranged on the working surface of the substrate and used for connecting a tester;

The probe channel is electrically connected with the tester channel through a circuit on the substrate and is used for connecting the probe;

The lead wire preset end is arranged on the working surface of the substrate and is connected with an external lead wire, the external lead wire is used for being connected with a signal input end of an oscilloscope, and the lead wire preset end is electrically connected with the channel of the tester through a circuit on the substrate; and

And the controllable switch is arranged on a passage between the lead preset and the channel of the testing machine, is configured to be in an open state at the beginning of testing, and is converted from the open state to the closed state in response to a first instruction of the testing machine if a test item of the testing chip fails.

The probe card provided by the embodiment of the application can be used for rapidly and accurately checking the reasons of the failure of the test item and improving the test and debugging progress.

In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

Referring to fig. 2 to fig. 4 together, the embodiment of the present application provides a probe card 130, where the probe card 130 can be matched with a tester 110, a probe station 120, etc. to implement CP testing, and the probe card 130 can be further matched with an oscillometric device to observe waveforms of output signals of chips in real time.

Specifically, the probe card 130 includes: a substrate 131, probes 132, and lead presets 133. The substrate 131 includes two opposite surfaces, wherein the surface facing the test wafer is a working surface of the substrate 131, and the surface facing away from the test wafer is a non-working surface of the substrate 131. The probes 132 and the lead pre-terminals 133 are disposed on the working surface of the substrate 131.

The substrate 131 is, for example, a printed circuit board (PCB board). The substrate 131 is provided with a circuit for electrically connecting the probes 132 and electrically connecting pads (pads) on a test wafer through the probes 132, thereby inspecting the test wafer. In some embodiments, the substrate 131 is a disk-like structure.

The substrate 131 is provided with various types of channels, and in some embodiments, the substrate 13 is provided with a tester channel 1311 for connection with the tester 110 and a probe channel 1312 for connection with the probe 132. The tester channel 1311 is a channel connected to the tester 110, the probe channel 1312 is a channel connected to the probe 132, and the tester channel 1311 and the probe channel 1312 are connected through the internal circuit trace of the substrate 131. For convenience of distinction, the circuit between the tester channel 1311 and the probe channel 1312 is referred to as a first circuit, and the circuit between the probe channel 1312 and the probe 132 is referred to as a second circuit, wherein the first and second circuits may be printed circuits provided on the substrate 131. The tester 110 is electrically connected to the probes 132 via the tester channels 1311 through the first circuit, the probe channels 1312, and the second circuit.

The tester channels 1311 may have multiple groups (groups), such as the probe card 130 shown in fig. 3 having 12 groups of tester channels 1311, and the particular number and distribution of tester channels 1311 may be determined based on the actual test chips. The tester channels 1311 may be disposed along the working surface edge, and the tester channels 1311 may be symmetrically distributed with respect to the center of the substrate 131. As a specific example, as shown in fig. 3, the tester channels 1311 are disposed on the working surface of the substrate 131, and the tester channels 1311 are disposed symmetrically around the circumferential edge of the working surface in total of 12 groups.

The probe channels 1312 may have a plurality of sets, for example, the probe card 130 shown in FIG. 3 has 2 sets of probe channels 1312, namely probe channels 1312a and probe channels 1312b, respectively, and the specific number and distribution of the probe channels 1312 may be determined according to the actual test chip. The probe channels 1312 may be disposed inside the tester channel 1311, i.e., on the side near the center of the substrate 131. In particular, the probe channel 1312 may be disposed between the tester channel 1311 and a probe region formed by the probes 132. As a specific example, as shown in fig. 3, the probe channels 1312 are provided on the working surface of the substrate 131, and the probe channels 1312 are distributed symmetrically with respect to the center of the substrate 131 in 2 groups, namely, the probe channels 1312a and the probe channels 1312 b.

The probes 132 are disposed on the working surface of the substrate 131, and in some embodiments, the working surface of the substrate 131 is provided with a probe head, and the probes 132 are disposed on the working surface of the probe head, that is, the probes 132 are connected with the substrate 131 through the probe head. The probe region formed by the probes 132 is located in the central region of the substrate, and the specific number and distribution of the probes 132 can be determined according to the actual test chip.

The tester 110 generates test electric signals under the control of a test program, the tester 110 is connected with the probe card 130, the test electric signals are transmitted to the needle points of the probes 132 on the probe card 130, and the needle points of the probes 132 are directly connected with signal pins of a test wafer, so that the transmission of the electric signals is realized.

The lead wire preset end 133 is disposed on the working surface of the substrate 131, the lead wire preset end 133 is used for connecting an external lead wire 150, one end of the external lead wire 150 is connected with the lead wire preset end 133 on the substrate 131, and the other end is connected with the input end of the oscilloscope 140. The lead presets 133 are electrically connected to the tester channels 1311 through printed circuitry within the substrate 131.

The pin terminals 133 may be more than one, such as the probe card 130 shown in fig. 3 having 8 pin terminals 133, the 8 pin terminals 133 being divided into two groups and disposed between the tester channel 1311 and the probe area. The specific number and distribution of the lead presets 133 may be determined based on the actual test chip.

In some embodiments, the connection path between the lead pre-set 133 and the tester channel 1311 may be controlled by a controllable switch 135, the controllable switch 135 being provided in the path between the lead pre-set 133 and the tester channel 1311, the controllable switch 135 being configured to be in an open state at the start of a test, and the controllable switch 135 being configured to transition from an open state to a closed state in response to a first instruction of the tester if a test item of the test chip fails. The controllable switch 135 between the lead pre-amble 133 and the tester channel 1311 is closed when the lead pre-amble 133 needs to communicate with the tester channel 1311, and the controllable switch 135 between the lead pre-amble 133 and the tester channel 1311 is opened when the lead pre-amble 133 does not need to communicate with the tester channel 1311. The on/off of the controllable switch 135 may be controlled by a control command, for example, a control command sent by the testing machine 110. In some embodiments, the controllable switch 135 may be a relay.

It can be seen that in the debugging stage, whether the chip pin signal is transmitted to the input end of the oscilloscope 140 through the external lead 150 can be selected only by controlling the on/off of the controllable switch 150, so that the waveform of the chip pin signal can be observed on the oscilloscope 140 in real time.

During normal wafer testing, the controllable switch 135 may be always in an off state, in which the lead pre-set end 133 is kept disconnected from the tester channel 1311, so that the external lead 150 on the lead pre-set end 133 is also kept in an off state with the chip pins, which do not affect the stability of the function due to the external longer lead.

When a debugging process encounters a problem, the controllable switch 135 can be changed from an open state to a closed state, and in the state, the lead preset end 133 is communicated with the tester channel 1311, so that the external lead 150 on the lead preset end 133 is communicated with a chip pin, a signal on the chip can be led out to the oscilloscope 140 through the external lead 150 for observation, and whether the input of the signal is correct or not is also confirmed while the signal is output.

In some embodiments, controllable switch 135 is a multiplexing switch by which lead presets 133 can be switched between multiple sets of tester channels 1311. The controllable switch 135 may gate a given one of the tester channels in response to a second instruction of the tester. Specifically, referring to fig. 4, the controllable switch 135 is a multi-path selection switch, one end of the multi-path selection switch is connected to the lead preset end 133, and the multi-path selection ends of the multi-path selection switch are respectively connected to different tester channels 1311, so that the multi-path selection switch can select between the tester channel a and the tester channel b. The lead presets 133 are switched to connect to different tester channel resources, and the waveform signals of the different tester channels can be displayed on the external oscilloscope 140. In this embodiment, by setting the multiple switches 135, signals of different chip pins can be detected in time periods under the condition that one lead preset terminal 133 is connected with the oscilloscope.

In some embodiments, the probe card 130 includes a plurality of the lead presets 133 and a plurality of the controllable switches 135, each of the lead presets 133 corresponding to one of the controllable switches 135.

It can be seen that the probe card provided by the embodiment can observe the waveform of the chip pin in real time, and the whole process from finding out the failure of the test item to observing the waveform of the pin in real time through the oscilloscope is not needed to take down or move the wafer from the probe station, i.e. the probe card provided by the embodiment can realize in-situ detection, thereby rapidly and accurately detecting the failure reason of the test item and improving the test and debugging progress.

Referring to fig. 2, an embodiment of the present application further provides a wafer testing system, including: the probe card 130 is the probe card 130 provided with the lead preset end 133 in the foregoing embodiment, and the lead preset end 133 is connected with the oscilloscope through a lead 150.

The tester 110, the probe station 120, and the probe card 130 may cooperate with each other to realize a wafer test, and the probe card 130 may further cooperate with the oscilloscope 140, so as to observe the waveform of the chip output signal in real time through the oscilloscope.

The tester 110 is integrated circuit test equipment, and is controlled by a test program to generate a test signal; the probe station 120 is a device for carrying a wafer, and can perform alignment of the wafer and alignment of the probe card; the probe card 130 is a piece of hardware carrying probes, and the probe card 130 connects the probes with signal channels of the tester 110.

The tester 110 is connected with the probe card 130 and provides test signals; the probe station 120 carries a test wafer and is connected to a probe card 130. Specifically, the probe station 120 carries the probe card 130 and the test wafer, and is responsible for the functions of transferring the test wafer, aligning the probe tip position on the probe card 130, and the like, so as to align the signal pin position of the test wafer with the probe tip position of the probe to ensure normal contact.

After the tester 110 inputs a series of electrical signals to the chip, the chip end outputs a series of electrical signals, and after the tester 110 receives the chip output, the tester 110 can measure and compare the voltage or the current, etc., so as to judge whether the chip functions or parameters are qualified according to the measured result. If the feedback signal received by the tester 110 is consistent with the expectation, the test item is qualified; in contrast, if the signal received by the tester 110 is inconsistent with the expected signal, the test item fails, when the test failure occurs, the tester 110 controls the controllable switch 135 on the probe card 130 to switch from the open state to the closed state, and in the closed state, the lead preset end 133 is communicated with the tester channel 1311, so that the external lead 150 on the lead preset end 133 is communicated with the chip pin, the signal on the chip can be led out to the oscilloscope 140 through the external lead 150 for observation, and the signal output is confirmed, and meanwhile, whether the signal input is correct or not is also confirmed.

In some embodiments, the tester 110 further comprises: a controller for controlling the controllable switch 135 to switch between a closed state and an open state.

In some embodiments, the controller is further to: providing a test signal to a test chip; acquiring a response signal of the test chip based on the test signal; judging whether the test item passes or not according to the response signal; if the test item does not pass, sending the first instruction to the controllable switch to enable the controllable switch to be changed from an open state to a closed state, so that a signal on the test chip is connected to the oscillometric device; and if the test item passes, marking the test chip as qualified.

In some embodiments, the controller is further to: judging a reason for the test item not passing according to the oscillometric device, wherein the reason is a chip self reason or a test environment reason; if the reason causing the test item to fail is a test environment reason, keeping the controllable switch in a closed state, and waiting for debugging the test environment; if the reason is the reason of the chip, marking the test chip as unqualified.

In some embodiments, the controller is further to: when the input waveform of the test chip output by the oscillometric device is consistent with the test signal and the waveform of the response signal is inconsistent with the preset output waveform of the test chip, judging that the reason causing the test item to fail is the reason of the chip, and marking the test chip as qualified.

It can be seen that the wafer test system provided by the embodiment can observe waveforms of pins of chips in real time, and the whole process from finding out failure of a test item to observing waveforms of pins in real time through an oscilloscope does not need to take down or move a wafer from a probe station, i.e. the wafer test system provided by the embodiment can realize in-situ detection, so that the cause of failure of the test item can be rapidly and accurately detected, and the test and debugging progress is improved.

Referring to fig. 5, an embodiment of the present application further provides a testing method, which may be used for the probe card and the wafer testing system. The test method comprises the following steps:

Step S101, providing a test signal to a test chip;

step S102, obtaining a response signal of the test chip based on the test signal;

Step S103, judging whether the test item passes or not according to the response signal;

Step S104, if the test item does not pass, controlling the controllable switch on the probe card to be changed from an open state to a closed state, so that a signal on the test chip is connected to the oscilloscope; and if the test item passes, marking the test chip as qualified.

In some embodiments, after step S104, the method may further include:

step S105, judging a reason causing the test item to fail according to the display result of the oscilloscope, wherein the reason is a chip self reason or a test environment reason;

Step S106, if the reason is the reason of the testing environment, keeping the controllable switch in a closed state, and waiting for a user to debug the testing environment by using the oscilloscope; if the reason is the reason of the chip, marking the test chip as unqualified.

Specifically, there are two reasons for the test item failing, one is the problem of the chip itself, namely the failure of the chip, and the other is the problem of the test environment, namely the problem occurring in the development process of the test program, and the test program needs to be debugged. In the process of debugging the test program, the controllable switch can be controlled to be in a closed state all the time, and the test program is debugged through the external oscilloscope.

During normal wafer testing, the controllable switch 135 may be always in an off state, in which the lead pre-set end 133 is kept disconnected from the tester channel 1311, so that the external lead 150 on the lead pre-set end 133 is also kept in an off state with the chip pins, which do not affect the stability of the function due to the external longer lead.

When a debugging process encounters a problem, the controllable switch 135 can be changed from an open state to a closed state, and in the state, the lead preset end 133 is communicated with the tester channel 1311, so that the external lead 150 on the lead preset end 133 is communicated with a chip pin, a signal on the chip can be led out to the oscilloscope 140 through the external lead 150 for observation, and whether the input of the signal is correct or not can be confirmed while the output of the signal is confirmed.

The disclosure further provides an embodiment of a device adapted to the above embodiment, which is configured to implement the method steps described in the above embodiment, and the explanation based on the meaning of the same names is the same as that of the above embodiment, which has the same technical effects as those of the above embodiment, and is not repeated herein.

Referring to fig. 6, an embodiment of the present application further provides a testing apparatus, including:

a signal providing module 101 for providing a test signal to a test chip;

A signal acquisition module 102, configured to acquire a response signal of the test chip based on the test signal;

a judging module 103, configured to judge whether the test item passes according to the response signal;

The switch control module 104 is configured to control the switch on the probe card to switch from an open state to a closed state if the test item fails, so that a signal on the test chip is connected to an oscilloscope;

and the marking module 105 is used for marking the test chip as qualified if the test item passes.

It can be seen that, by using the test method and the test device provided by the embodiment, the waveform of the chip pin can be observed in real time, and the whole process from the detection item failure discovery to the real-time observation of the pin waveform through the oscilloscope is unnecessary to take down or move the wafer from the probe station, i.e. the test method and the test device provided by the embodiment can realize in-situ detection, thereby rapidly and accurately checking the failure reason of the test item and improving the test and debugging progress.

The embodiment of the application further provides electronic equipment, which comprises: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the one processor to enable the at least one processor to perform the method steps described in the embodiments above. Fig. 7 shows a schematic diagram of an electronic device suitable for implementing an embodiment of the application.

The electronic device in the embodiment of the present application may be the testing machine 10.

The tester 10 mainly performs functional testing of a wafer to be tested, and the tester 10 may be generally configured as a workstation for external control during wafer testing. The test machine 10 may be comprised of a series of modular electronic hardware, typically including a CPU control module (FPGA master), a system power module (power panel), vector memory, terminal circuitry, dc modules, timing modules, system clock signal modules, light source control modules, and the like. The types of the test machine 10 can be classified into a logic test machine, a memory test machine, a mixed signal test machine, and the like according to the test function. Common test items include Open Short (Open Short), leakage current (leak), IDD, functional, etc. The specific test procedure may use different testers 10 for different types of chips.

Various test programs may be run on the test machine 10, for example, a test program may be configured to: generating test voltage, test current and time sequence signals required by the device to be tested, reading the output response of the test signals, and judging whether the device to be tested is good or not according to the output response. In some embodiments, the methods and apparatus provided by the present disclosure may be implemented as a separate test program on the test machine 10, or may be implemented as a sub-module of a test program on the test machine 10.

As shown in fig. 7, the electronic device may include a processing means (e.g., a central processor, a graphics processor, etc.) 401, which may perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM) 402 or a program loaded from a storage means 408 into a Random Access Memory (RAM) 403. In the RAM403, various programs and data required for the operation of the electronic device are also stored. The processing device 401, the ROM 402, and the RAM403 are connected to each other by a bus 405. An input/output (I/O) interface 405 is also connected to bus 405.

In general, the following devices may be connected to the I/O interface 405: input devices 406 including, for example, a touch screen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; an output device 405 including, for example, a Liquid Crystal Display (LCD), a speaker, a vibrator, etc.; storage 408 including, for example, magnetic tape, hard disk, etc.; and a communication device 405. The communication means 405 may allow the electronic device to communicate with other devices wirelessly or by wire to exchange data. While fig. 7 shows an electronic device having various means, it is to be understood that not all of the illustrated means are required to be implemented or provided. More or fewer devices may be implemented or provided instead.

In particular, according to embodiments of the present disclosure, the processes described above with reference to flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the method shown in the flowcharts. In such an embodiment, the computer program may be downloaded and installed from a network via communication device 405, or from storage device 408, or from ROM 402. The above-described functions defined in the methods of the embodiments of the present disclosure are performed when the computer program is executed by the processing device 401.

It should be noted that the computer readable medium described in the present disclosure may be a computer readable signal medium or a computer readable storage medium, or any combination of the two. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this disclosure, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present disclosure, however, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with the computer-readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: electrical wires, fiber optic cables, RF (radio frequency), and the like, or any suitable combination of the foregoing.

The computer readable medium may be contained in the electronic device; or may exist alone without being incorporated into the electronic device.

Computer program code for carrying out operations of the present disclosure may be written in one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The units involved in the embodiments of the present disclosure may be implemented by means of software, or may be implemented by means of hardware. Wherein the names of the units do not constitute a limitation of the units themselves in some cases.

Claims (10)

1. A probe card, comprising:

A substrate comprising a working surface, the substrate being provided with a printed circuit;

The probe is arranged on the working surface of the substrate;

the tester channel is arranged on the working surface of the substrate and used for connecting a tester;

the probe channel is arranged on the working surface of the substrate and is electrically connected with the tester channel through a circuit on the substrate, and the probe channel is used for connecting the probe;

The lead wire preset end is arranged on the working surface of the substrate and is connected with an external lead wire, the external lead wire is used for being connected with the signal input end of the oscillograph, and the lead wire preset end is electrically connected with the channel of the tester through a circuit on the substrate; and

The controllable switch is arranged on a passage between the lead preset and the channel of the tester; the controllable switch is configured to be in an open state at the beginning of a test, and the controllable switch is transitioned from the open state to a closed state in response to a first instruction of the testing machine if a test item of the test chip fails.

2. The probe card of claim 1, wherein the controllable switch is a multi-way selection switch, one end of the multi-way selection switch is connected with the lead preset end, and the multi-way selection ends of the multi-way selection switch are respectively connected with different channels of the tester; the controllable switch is configured to gate a specified one of the tester channels in response to a second instruction of the tester.

3. The probe card of claim 1, wherein the probe card comprises a plurality of said lead presets and a plurality of said controllable switches, one for each of said lead presets.

4. The probe card of claim 1, wherein the controllable switch is a relay.

5. The probe card of claim 1 wherein,

The tester channels are symmetrically arranged along the edge of the working surface;

the probe channel is arranged between the tester channel and the probe;

the lead wire preset end is arranged between the tester channel and the probe.

6. The probe card of claim 4, wherein the probe channels are symmetrically distributed with respect to a center of the substrate, and the lead presets are symmetrically distributed with respect to the center of the substrate.

7. A chip testing system, comprising: a testing machine, a probe station, and a probe card according to any one of claims 1-6, wherein the probe card is connected to the signal input end of the oscillometric device through the lead pre-set end and the external lead, and wherein the testing machine further comprises:

and a controller configured to control the controllable switch to switch between a closed state and an open state.

8. The chip testing system of claim 7, wherein the controller is configured to:

Providing a test signal to a test chip;

acquiring a response signal of the test chip based on the test signal;

judging whether the test item passes or not according to the response signal;

If the test item does not pass, sending the first instruction to the controllable switch to enable the controllable switch to be changed from an open state to a closed state, so that a signal on the test chip is connected to the oscillometric device; and if the test item passes, marking the test chip as qualified.

9. The chip testing system of claim 8, wherein the controller is further configured to:

judging a reason for the test item not passing according to the oscillometric device, wherein the reason is a chip self reason or a test environment reason; and

If the reason causing the test item to fail is a test environment reason, keeping the controllable switch in a closed state, and waiting for debugging the test environment;

if the reason is the reason of the chip, marking the test chip as unqualified.

10. The chip testing system of claim 9, wherein the controller is further configured to:

when the input waveform of the test chip output by the oscillometric device is consistent with the test signal and the waveform of the response signal is inconsistent with the preset output waveform of the test chip, judging that the reason causing the test item to fail is the reason of the chip.