CN117979747A

CN117979747A - Display substrate, preparation method thereof and display device

Info

Publication number: CN117979747A
Application number: CN202410139402.3A
Authority: CN
Inventors: 汪锐; 何小玲; 张润鑫; 胡明; 曾超; 邱海军; 吴新银; 郝学光
Original assignee: BOE Technology Group Co Ltd; Chongqing BOE Display Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chongqing BOE Display Technology Co Ltd
Priority date: 2024-01-31
Filing date: 2024-01-31
Publication date: 2024-05-03

Abstract

A display substrate, a manufacturing method thereof and a display device. The display substrate comprises a plurality of first areas and a plurality of second areas which are alternately arranged; in a direction perpendicular to the display substrate, the display region includes a driving structure layer and a light emitting structure layer; the driving structure layer of the first area comprises a plurality of pixel driving circuits, the driving structure layer of the second area comprises at least one grid driving device and/or at least one signal wire, the light emitting structure layer of the first area comprises a plurality of first light emitting devices, and the light emitting structure layer of the second area comprises a plurality of second light emitting devices; at least one first light emitting device in the first region is connected to at least one pixel driving circuit in the first region, and at least one second light emitting device in the second region is connected to at least one pixel driving circuit in the first region. The grid driving circuit and the signal wiring are arranged in the display area, so that the space of the frame area is not occupied, and the frame width of the display device is effectively reduced.

Description

Display substrate, preparation method thereof and display device

Technical Field

The invention relates to the technical field of display, in particular to a display substrate, a preparation method thereof and a display device.

Background

Organic LIGHT EMITTING Diodes (OLED) and Quantum-dot LIGHT EMITTING Diodes (QLED) are active light emitting display devices, and have advantages of self-luminescence, wide viewing angle, high contrast ratio, low power consumption, extremely high reaction speed, light weight, flexibility, low cost, and the like. With the continuous development of Display technology, a Flexible Display device (Flexible Display) using an OLED or a QLED as a light emitting device and a thin film transistor (Thin Film Transistor, abbreviated as TFT) for signal control has become a mainstream product in the current Display field.

At present, the prior OLED display device has the problems of large frame width and the like.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

The technical problem to be solved by the present disclosure is to provide a display substrate, a manufacturing method thereof, and a display device, so as to solve the problem of the existing display device that the width of a frame is large.

In one aspect, the present disclosure provides a display substrate including a plurality of first regions and a plurality of second regions, the first regions and the second regions having a shape of a bar extending along a second direction, the plurality of first regions and the plurality of second regions being alternately arranged along a first direction, the first direction and the second direction intersecting; in the direction perpendicular to the display substrate, the display region includes a driving structure layer disposed on a base and a light emitting structure layer disposed on a side of the driving structure layer away from the base; the driving structure layer of the first area comprises a plurality of pixel driving circuits, the driving structure layer of the second area comprises at least one grid driving device and/or at least one signal wire, the light emitting structure layer of the first area comprises a plurality of first light emitting devices, and the light emitting structure layer of the second area comprises a plurality of second light emitting devices; at least one first light emitting device in the first region is connected to at least one pixel driving circuit in the first region, and at least one second light emitting device in the second region is connected to at least one pixel driving circuit in the first region.

In an exemplary embodiment, the driving structure layer of the first region includes a plurality of circuit repeating units, a front projection of at least one circuit repeating unit on the substrate has a first area, the light emitting structure layer of the first region includes a plurality of light emitting repeating units, a front projection of at least one light emitting repeating unit on the substrate has a second area, and a ratio of the first area to the second area is 0.95 to 1.05; at least one circuit repeating unit includes m+m pixel driving circuits, and at least one light emitting repeating unit includes M first light emitting devices; m is an integer multiple of 2 or an integer multiple of 3, and M is a positive integer greater than or equal to 1.

In an exemplary embodiment, the pixel driving circuits in the at least one circuit repeating unit include at least a first pixel driving circuit and a second pixel driving circuit, the at least one first pixel driving circuit being connected to the at least one first light emitting unit, an orthographic projection of the at least one first pixel driving circuit on the substrate at least partially overlapping an orthographic projection of the at least one first light emitting device on the substrate; the at least one second pixel driving circuit is connected with the at least one second light emitting device through an anode connecting wire, and the orthographic projection of the at least one second pixel driving circuit on the substrate is not overlapped with the orthographic projection of the at least one second light emitting device on the substrate.

In an exemplary embodiment, the second region has a first centerline, the first centerline being a straight line bisecting the second region in the first direction and extending along the second direction; the second region includes at least a first side repeating unit located on a side opposite to the first direction of the first center line and a second side repeating unit located on a side of the first direction of the first center line, each of the first side repeating unit and the second side repeating unit includes N second light emitting devices, N being an integer multiple of 3 or an integer multiple of 4.

In an exemplary embodiment, the first region includes at least a first side region located at a side opposite to the first direction of the second region and a second side region located at a side of the first direction of the second region; at least one second light emitting device in the first side repeating unit is connected to at least one second pixel driving circuit in the first side region through an anode connection line, and at least one second light emitting device in the second side repeating unit is connected to at least one second pixel driving circuit in the second side region through an anode connection line.

In an exemplary embodiment, the first side region includes at least a first circuit repeating unit located on a side of the second region opposite to the first direction and a second circuit repeating unit located on a side of the first circuit repeating unit away from the second region; the second side region includes at least an eleventh circuit repeating unit located on one side of the second region in the first direction and a twelfth circuit repeating unit located on one side of the eleventh circuit repeating unit away from the second region; the first side repeating unit includes a first light emitting device group and a second light emitting device group sequentially arranged along the first direction, and the second side repeating unit includes a third light emitting device group and a fourth light emitting device group sequentially arranged along the first direction; at least one second light emitting device of the first light emitting device group is connected with at least one second pixel driving circuit of the first circuit repeating unit through a first anode connecting wire, at least one second light emitting device of the second light emitting device group is connected with at least one second pixel driving circuit of the second circuit repeating unit through a second anode connecting wire, at least one second light emitting device of the third light emitting device group is connected with at least one second pixel driving circuit of the eleventh circuit repeating unit through an eleventh anode connecting wire, and at least one second light emitting device of the fourth light emitting device group is connected with at least one second pixel driving circuit of the twelfth circuit repeating unit through a twelfth anode connecting wire.

In an exemplary embodiment, the second length of the at least one second anode connection line is greater than the first length of the at least one first anode connection line, and the fourth length of the at least one twelfth anode connection line is greater than the third length of the at least one eleventh anode connection line, the first length, the second length, the third length, and the fourth length being dimensions of the first direction.

In an exemplary embodiment, the third length of the at least one eleventh anode connection line is greater than the first length of the at least one first anode connection line, and the fourth length of the at least one twelfth anode connection line is greater than the second length of the at least one second anode connection line.

In an exemplary embodiment, the material of the anode connection line is a metal material or the material of the anode connection line is a transparent conductive material.

In an exemplary embodiment, the first light emitting device and the second light emitting device each include an anode, the anode of at least one second light emitting device is connected to at least one second pixel driving circuit through the anode connection line, the at least one anode connection line has a shape of a straight line or a folded line extending along the first direction, and an orthographic projection of the at least one anode connection line on the substrate at least partially overlaps an orthographic projection of the anode of at least one first light emitting device on the substrate.

In an exemplary embodiment, the first region further includes at least one dummy connection line, the shape of the at least one dummy connection line being linear or folded-in extending along the first direction, and an orthographic projection of the at least one dummy connection line on the substrate at least partially overlaps an orthographic projection of an anode of the at least one first light emitting device on the substrate.

In an exemplary embodiment, the first region includes at least a normal region, which is a region where the anode connection line is not provided, and a connection line region, which is a region where the anode connection line is provided; the orthographic projection of at least one anode in the normal region on the substrate at least partially overlaps with the orthographic projection of K1 dummy connection lines on the substrate, the orthographic projection of at least one anode in the connection line region on the substrate at least partially overlaps with the orthographic projections of K2 dummy connection lines and K3 anode connection lines on the substrate, k1=k2+k3, K1, K2, and K3 are positive integers greater than or equal to 1.

In an exemplary embodiment, the arrangement of the dummy connection line in the normal region is the same as the arrangement of the dummy connection line and the anode connection line in the connection line region, and the arrangement is any one or more of the following: the position of the connection lines in the second direction, the width of the connection lines, the spacing between adjacent connection lines, the width and the spacing being the dimensions of the second direction.

In an exemplary embodiment, the routing density of the dummy connection line in the normal region is the same as the routing densities of the dummy connection line and the anode connection line in the connection line region, the routing density being an area of the connection line per unit area.

In an exemplary embodiment, at least one dummy connection line is connected to at least one signal connection line through at least one trace connection line, the trace connection line has a shape of a straight line or a folded line extending along the second direction, the trace connection line is disposed between two anodes adjacent in the first direction, and an orthographic projection of the trace connection line on the substrate does not overlap with an orthographic projection of the anode on the substrate.

In an exemplary embodiment, the signal connection line has a shape of a straight line or a folded line extending along the first direction; at least one signal connection line is connected with a first power line serving as the signal line and the main body part extends along the second direction to form a net-shaped communication structure for transmitting a first power signal, and/or at least one signal connection line is connected with a second power line serving as the signal line and the main body part extends along the second direction to form a net-shaped communication structure for transmitting a second power signal, and/or at least one signal connection line is connected with an initial signal line serving as the signal line and the main body part extends along the second direction to form a net-shaped communication structure for transmitting an initial signal.

In an exemplary embodiment, the at least one gate driving device includes a plurality of gate driving circuits sequentially arranged along the second direction and cascade-connected, the at least one gate driving circuit being connected to a first clock signal line and a second clock signal line, the first clock signal line and the second clock signal line having a shape of a straight line or a folded line extending along the second direction; in at least one second region, an orthographic projection of the first power line on the substrate at least partially overlaps an orthographic projection of the first and second clock signal lines on the substrate, and/or an orthographic projection of the second power line on the substrate at least partially overlaps an orthographic projection of the first and second clock signal lines on the substrate, and/or an orthographic projection of the initial signal line on the substrate at least partially overlaps an orthographic projection of the first and second clock signal lines on the substrate.

In an exemplary embodiment, in the second direction, at least one signal connection line is disposed between two gate driving circuits in cascade.

On the other hand, the disclosure also provides a display device, which comprises the display substrate.

In still another aspect, the present disclosure also provides a method for manufacturing a display substrate including a plurality of first regions and a plurality of second regions, the first regions and the second regions having a shape of a bar extending along a second direction, the plurality of first regions and the plurality of second regions being alternately arranged along a first direction, the first direction and the second direction intersecting; the preparation method comprises the following steps:

Forming a driving structure layer on a substrate; the driving structure layer of the first area comprises a plurality of pixel driving circuits, and the driving structure layer of the second area comprises at least one grid driving device and/or at least one signal wire;

Forming a light-emitting structure layer on one side of the driving structure layer away from the substrate; the light emitting structure layer of the first region includes a plurality of first light emitting devices, the light emitting structure layer of the second region includes a plurality of second light emitting devices, at least one first light emitting device of the first region is connected with at least one pixel driving circuit of the first region, and at least one second light emitting device of the second region is connected with at least one pixel driving circuit of the first region.

The display substrate comprises a first area, a second area, a pixel driving circuit, a grid driving circuit and a signal wire, wherein the first area and the second area are alternately arranged in a display area, the second area is provided with the grid driving circuit and the signal wire, the grid driving circuit and the signal wire are arranged in the display area, the space of a frame area is not occupied, and the frame width of the display device is effectively reduced.

Other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

Drawings

The accompanying drawings are included to provide an understanding of the technical aspects of the present disclosure, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present disclosure and together with the embodiments of the disclosure, not to limit the technical aspects of the present disclosure.

FIG. 1 is a schematic diagram of a display device;

FIG. 2 is a schematic diagram of a display substrate;

FIG. 3A is a schematic plan view of a display area of a display substrate;

FIG. 3B is a schematic plan view of a display area of another display substrate;

FIG. 4 is a schematic cross-sectional view of a display area of a display substrate;

fig. 5 is an equivalent circuit diagram of a pixel driving circuit;

FIG. 6 is a schematic diagram of a scan driving device;

fig. 7 is a schematic structural view of a display substrate according to an exemplary embodiment of the present disclosure;

FIGS. 8 and 9 are enlarged views of area A of FIG. 7;

fig. 10 is a schematic diagram illustrating connection between a pixel driving circuit and a light emitting device according to an embodiment of the disclosure;

FIG. 11 is a schematic diagram illustrating connection between a pixel driving circuit and a light emitting device according to another embodiment of the disclosure;

FIG. 12 is a schematic diagram of a virtual drive circuit according to an exemplary embodiment of the present disclosure;

FIG. 13 is a schematic view of an anode connection line according to an exemplary embodiment of the present disclosure;

FIG. 14 is a schematic illustration of a second zone arrangement according to an exemplary embodiment of the present disclosure;

FIG. 15 is an enlarged view of area D of FIG. 14;

FIG. 16 is an enlarged view of area E of FIG. 14;

fig. 17 and 18 are schematic diagrams of a gate lead in accordance with an exemplary embodiment of the present disclosure.

Reference numerals illustrate:

10-a first region; 10A-a first side region; 10B-a second side region;

10-1-normal region; 10-2-connecting line region; 20-a second region;

20A-a first side repeat unit; 20B-a second side repeat unit; 30-an anode connecting wire;

31-a first anode connection line; 32-a second anode connection line; 33-a third anode connection line;

34-fourth anode connection line; 40-anode; 41-dummy connection lines;

42-wiring connecting lines; 50-signal connection lines; 60-signal wiring;

61-a first power line; 62-a second power line; 63—an initial signal line;

64-data signal lines; 80-an integrated circuit; 81-gate lead-out;

100—a display area; 101-a substrate; 102-a driving structure layer;

103-a light emitting structure layer; 104-packaging structure layer; 200—binding area;

300-border area.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail hereinafter with reference to the accompanying drawings. Note that embodiments may be implemented in a number of different forms. One of ordinary skill in the art can readily appreciate the fact that the manner and content may be varied into a wide variety of forms without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure should not be construed as being limited to the following description of the embodiments. Embodiments of the present disclosure and features of embodiments may be combined with each other arbitrarily without conflict.

The scale of the drawings in this disclosure may be referred to in the actual process, but is not limited thereto. For example: the width-to-length ratio of the channel, the thickness and the spacing of each film layer, and the width and the spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the number shown in the drawings, the drawings described in the present disclosure are only schematic structural drawings, and one mode of the present disclosure is not limited to the shapes or values shown in the drawings, etc.

The ordinal numbers of "first", "second", "third", etc. in the present specification are provided to avoid mixing of constituent elements, and are not intended to be limited in number.

In the present specification, for convenience, words such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, which indicate an azimuth or a positional relationship, are used to describe positional relationships of constituent elements with reference to the drawings, only for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or elements referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus are not to be construed as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the respective constituent elements are described. Therefore, the present invention is not limited to the words described in the specification, and may be appropriately replaced according to circumstances.

In this specification, the terms "mounted," "connected," and "connected" are to be construed broadly, unless explicitly stated or limited otherwise. For example, it may be a fixed connection, a removable connection, or an integral connection; may be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intermediate members, or may be in communication with the interior of two elements. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art in the specific context.

In this specification, a transistor means an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and a source electrode (a source electrode terminal, a source region, or a source electrode), and a current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, a channel region refers to a region through which current mainly flows.

In this specification, the first electrode may be a drain electrode, the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using a transistor having opposite polarity, or in the case of a change in the direction of current during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Therefore, in this specification, "source electrode" and "drain electrode" may be exchanged, and "source terminal" and "drain terminal" may be exchanged.

In this specification, "electrically connected" includes a case where constituent elements are connected together by an element having some electric action. The "element having a certain electric action" is not particularly limited as long as it can transmit and receive an electric signal between the constituent elements connected. Examples of the "element having some electric action" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.

In the present specification, "parallel" means a state in which two straight lines form an angle of-10 ° or more and 10 ° or less, and therefore, a state in which the angle is-5 ° or more and 5 ° or less is also included. The term "perpendicular" refers to a state in which two straight lines form an angle of 80 ° or more and 100 ° or less, and thus includes an angle of 85 ° or more and 95 ° or less.

In this specification, "film" and "layer" may be exchanged with each other. For example, the "conductive layer" may be sometimes replaced with a "conductive film". In the same manner, the "insulating film" may be replaced with the "insulating layer" in some cases.

The triangle, rectangle, trapezoid, pentagon or hexagon, etc. in this specification are not strictly defined, but may be approximated to triangle, rectangle, trapezoid, pentagon or hexagon, etc., and there may be some small deformation due to tolerance, and there may be lead angles, arc edges, deformation, etc. The term "about" in this disclosure refers to values that are not strictly limited to the limits, but are allowed to fall within the limits of the process and measurement errors.

Fig. 1 is a schematic structural diagram of a display device. As shown in fig. 1, the display device may include a timing controller connected to the data driving device and the scan driving device, respectively, the data driving device connected to the plurality of data signal lines (D1 to Dn), respectively, and the scan driving device connected to the plurality of scan signal lines (S1 to Sm) and the plurality of light emitting signal lines (E1 to Eo), respectively, and a pixel array. The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, and at least one sub-pixel Pxij may include a circuit unit and a light emitting unit, the circuit unit may include at least a pixel driving circuit, the pixel driving circuit is respectively connected with a scan signal line, a light emitting signal line, and a data signal line, the light emitting unit may include a light emitting device, and the light emitting device is connected with the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide gray values and control signals suitable for specifications of the data driving apparatus to the data driving apparatus, may provide clock signals, scan start signals, emission stop signals, etc. suitable for specifications of the scan driving apparatus to the scan driving apparatus. The data driving apparatus may generate the data voltages to be supplied to the data signal lines D1, D2, D3, … …, and Dn using the gray values and the control signals received from the timing controller. For example, the data driving apparatus may sample the gray value using a clock signal, and apply the data voltage corresponding to the gray value to the data signal lines D1 to Dn in pixel row units, n may be a natural number. The scan driving means may include at least one scan signal driver and at least one light emitting signal driver. The scan signal driver may generate the scan signals to be supplied to the scan signal lines S1, S2, S3, … …, and Sm by receiving a clock signal, a scan start signal, and the like from the timing controller. For example, the scan signal driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm. For example, the scan signal driver may be configured in the form of a shift register, and may sequentially generate the scan signals in such a manner that the scan start signal supplied in the form of an on-level pulse is transmitted to the next stage circuit under the control of the clock signal, and m may be a natural number. The emission signal driver may generate emission signals to be supplied to the emission signal lines E1, E2, E3, … …, and Eo by receiving a clock signal, an emission stop signal, and the like from the timing controller. For example, the light emission signal driver may sequentially supply the emission signal having the off-level pulse to the light emission signal lines E1 to Eo. For example, the light emitting signal driver may be configured in the form of a shift register, and may generate the emission signal in such a manner that the emission stop signal provided in the form of a cut-off level pulse is sequentially transmitted to the next stage circuit under the control of the clock signal, o may be a natural number. In an exemplary embodiment, the pixel array may be disposed on the display substrate.

Fig. 2 is a schematic structural diagram of a display substrate. As shown in fig. 2, the display substrate may include a display area 100, a bonding area 200 at one side of the display area 100, and a bezel area 300 at the other side of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area including a plurality of subpixels Pxij constituting a pixel array, the plurality of subpixels Pxij being configured to display a moving picture or a still image, and the display area 100 may be referred to as an effective area (ACTIVE AREA, abbreviated as AA). In an exemplary embodiment, the display substrate may employ a flexible substrate, and thus the display substrate may be deformable, such as curled, bent, folded, or rolled.

In an exemplary embodiment, the bonding area 200 may include a lead out area, a bent area, a driving chip area, and a bonding pin area sequentially disposed in a direction away from the display area, the lead out area being connected to the display area 100, including at least a data lead out. The bending region is connected to the lead-out region and may include at least a composite insulating layer provided with grooves configured to bend the binding region to the back surface of the display region. The driver chip region may include an integrated circuit (INTEGRATED CIRCUIT, simply referred to as an IC) configured to connect with a plurality of data pinouts. The Bonding Pad region may include a Bonding Pad (Bonding Pad) configured to be bonded to an external flexible circuit board (Flexible Printed Circuit, abbreviated as FPC).

In an exemplary embodiment, the bezel area 300 may include a circuit area, a power line area, a crack dam area, and a cutting area sequentially disposed in a direction away from the display area 100. The circuit region is connected to the display region 100, and may include at least a gate driving device connected to the scan signal line and the light emitting signal line in the display region 100. The power line region is connected to the region and may include at least a frame power lead extending in a direction parallel to an edge of the display region to be connected to a cathode in the display region 100. The crack dam region is connected to the power line region and may include at least a plurality of cracks provided on the composite insulating layer. The cutting region is connected to the crack dam region and may include at least cutting grooves provided on the composite insulating layer, the cutting grooves being configured such that the cutting devices cut along the cutting grooves, respectively, after all the film layers of the display substrate are prepared.

In an exemplary embodiment, the outlet region in the bonding region 200 and the power line region in the bezel region 300 may be provided with a barrier, which may extend in a direction parallel to the display region edge, which is an edge of one side of the display region bonding region or the bezel region, forming a ring-shaped structure surrounding the display region 100.

Fig. 3A is a schematic plan view of a display area in a display substrate. As shown in fig. 3A, the display region may include a plurality of pixel units F arranged in a matrix, and at least one pixel unit F may include a first subpixel P1, a second subpixel P2, a third subpixel P3, and a fourth subpixel P4. Each sub-pixel may include a circuit unit and a light emitting unit, the circuit unit may include at least a pixel driving circuit, the pixel driving circuit is connected to the scan signal line, the light emitting signal line, and the data signal line, respectively, and the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light emitting unit under control of the scan signal line and the light emitting signal line. The light emitting unit may include a light emitting device connected to the pixel driving circuit of the sub-pixel, the light emitting device being configured to emit light of a corresponding brightness in response to a current output from the pixel driving circuit of the sub-pixel.

In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) emitting red light, the second subpixel P2 and the fourth subpixel P4 may be green subpixels (G) emitting green light, and the third subpixel P3 may be blue subpixels (B) emitting blue light. In an exemplary embodiment, the shape of the sub-pixels may be rectangular, diamond, pentagonal, or hexagonal, and the four sub-pixels may be arranged in an RGBG manner.

Fig. 3B is a schematic plan view of a display area of another display substrate. As shown in fig. 3B, the pixel unit F may include three sub-pixels, the first sub-pixel P1 may be a red sub-pixel emitting red light, the second sub-pixel P2 may be a green sub-pixel emitting green light, the third sub-pixel P3 may be a blue sub-pixel emitting blue light, and the three sub-pixels may be arranged in Real RGB.

In other exemplary embodiments, three or four sub-pixels may be arranged in a horizontal or vertical juxtaposition, etc., and the disclosure is not limited thereto.

Fig. 4 is a schematic cross-sectional structure of a display area in a display substrate, illustrating the structure of four sub-pixels in the display area. As shown in fig. 4, on a plane perpendicular to the display substrate, the display region may include a driving structure layer 102 disposed on the base 101, a light emitting structure layer 103 disposed on a side of the driving structure layer 102 away from the base 101, and a package structure layer 104 disposed on a side of the light emitting structure layer 103 away from the base 101. In some possible implementations, the display area may include other film layers, such as a touch structure layer, etc., which are not limited herein.

In an exemplary embodiment, the substrate 101 may be a flexible substrate, or may be a rigid substrate. The driving structure layer 102 may include a plurality of circuit units, and each circuit unit may include at least a pixel driving circuit. The light emitting structure layer 103 may include a plurality of light emitting units, each of which may include a light emitting device, which may include at least an anode connected to the pixel driving circuit, an organic light emitting layer connected to the anode, and a cathode connected to the organic light emitting layer, and the organic light emitting layer emits light of a corresponding color under the driving of the anode and the cathode. The packaging structure layer 104 may include a first packaging layer, a second packaging layer and a third packaging layer, which are stacked, where the first packaging layer and the third packaging layer may be made of inorganic materials, the second packaging layer may be made of organic materials, and the second packaging layer is disposed between the first packaging layer and the third packaging layer, so as to form an inorganic material/organic material/inorganic material stacked structure, which can ensure that external water vapor cannot enter the light emitting structure layer 103.

Fig. 5 is an equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in fig. 5, the pixel driving circuit may adopt a 7T2C structure including 7 transistors (first transistor T1 to seventh transistor T7) and 2 capacitors (first capacitor C1 and second capacitor C2), and is connected to 9 signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, light emitting signal line EM, reference signal line REF, initial signal line INIT, DATA signal line DATA, and first power supply line VDD), respectively.

In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the second pole of the first transistor T1, the first pole of the sixth transistor T6, and the gate electrode of the third transistor T3, the second node N2 is connected to the second pole of the fourth transistor T4, the second pole of the sixth transistor T6, and the second end of the second capacitor C2, the third node N3 is connected to the second pole of the third transistor T3, the second pole of the seventh transistor T7, and the second end of the first capacitor C1, and the fourth node N4 is connected to the second pole of the second transistor T2, the first end of the first capacitor C1, and the first end of the second capacitor C2.

In an exemplary embodiment, the first transistor T1 may be referred to as a first reset transistor, a gate electrode of the first transistor T1 is connected to the first scan signal line S1, a first pole of the first transistor T1 is connected to the reference signal line REF, and a second pole of the first transistor T1 is connected to the first node N1.

In an exemplary embodiment, the second transistor T2 may be referred to as a second reset transistor, the gate electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the reference signal line REF, and the second electrode of the second transistor T2 is connected to the fourth node N4.

In an exemplary embodiment, the third transistor T3 may be referred to as a driving transistor, a gate electrode of the third transistor T3 is connected to the first node N1, a first pole of the third transistor T3 is connected to a second pole of the fifth transistor T5, and a second pole of the third transistor T3 is connected to the third node N3.

In an exemplary embodiment, the fourth transistor T4 may be referred to as a DATA writing transistor, the gate electrode of the fourth transistor T4 is connected to the third scan signal line S3, the first pole of the fourth transistor T4 is connected to the DATA signal line DATA, and the second pole of the fourth transistor T4 is connected to the second node N2.

In an exemplary embodiment, the fifth transistor T5 may be referred to as a light emission control transistor, the gate electrode of the fifth transistor T5 is connected to the light emission signal line EM, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first electrode of the third transistor T3.

In an exemplary embodiment, the sixth transistor T6 may be referred to as a data control transistor, the gate electrode of the sixth transistor T6 is connected to the fourth scan signal line S4, the first electrode of the sixth transistor T6 is connected to the first node N1, and the second electrode of the sixth transistor T6 is connected to the second node N2.

In an exemplary embodiment, the seventh transistor T7 may be referred to as a third reset transistor, the gate electrode of the seventh transistor T7 is connected to the second scan signal line S2, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the third node N3.

In the exemplary embodiment, the first electrode of the light emitting device EL is connected to the third node N3, and the second electrode of the light emitting device EL is connected to the second power line VSS. The light emitting device EL may be an OLED including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked, or a QLED including a first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode) stacked.

In an exemplary embodiment, the first power line VDD is configured to supply a constant first voltage signal to the pixel driving circuit, the second power line VSS is configured to supply a constant second voltage signal to the light emitting device, and the first voltage signal is a high level signal and the second voltage signal is a low level signal. The reference signal line and the initial voltage signal may be constant voltage signals, and the disclosure is not limited herein.

In an exemplary embodiment, seven transistors of the pixel driving circuit may be P-type transistors or may be N-type transistors. The same type of transistor is adopted in the pixel driving circuit, so that the process flow can be simplified, the process difficulty of the display panel is reduced, and the yield of products is improved. In some possible implementations, the seven transistors of the pixel drive circuit may include a P-type transistor and an N-type transistor.

In an exemplary embodiment, seven transistors of the pixel driving circuit may employ low temperature polysilicon thin film transistors, or may employ oxide thin film transistors, or may employ low temperature polysilicon thin film transistors and oxide thin film transistors. The active layer of the low-temperature polysilicon thin film transistor adopts low-temperature polysilicon (Low Temperature Poly-Silicon, LTPS for short), and the active layer of the Oxide thin film transistor adopts an Oxide semiconductor (Oxide). The low-temperature polycrystalline silicon thin film transistor has the advantages of high mobility, quick charging and the like, the Oxide thin film transistor has the advantages of high electron mobility, low working voltage, low leakage current and the like, the low-temperature polycrystalline silicon thin film transistor and the Oxide thin film transistor are integrated on one display substrate to form a LTPO (Low Temperature Polycrystalline +oxide) display substrate, the advantages of the low-temperature polycrystalline silicon thin film transistor and the Oxide thin film transistor can be utilized, low-frequency driving can be realized, power consumption can be reduced, and display quality can be improved.

Fig. 6 is a schematic structural diagram of a scan driving device. In an exemplary embodiment, the scan driving means may include gate driving means (scan signal driver) providing a scan signal and gate driving means (light emission signal driver) providing a light emission control signal. The gate driving device may include a plurality of gate driving circuits (GOA circuits) connected in cascade, the GOA circuits converting clock signals into on/off voltages, respectively outputting the on/off voltages to the display area, the multi-stage GOA circuits being connected to the scanning signal lines or the light emitting signal lines in the plurality of cell lines, and sequentially outputting the on voltages by the respective GOA circuits in turn, thereby realizing progressive scanning of the plurality of cell lines in the display area. As shown in fig. 6, the gate driving apparatus may include a first stage GOA circuit, a second stage GOA circuit, a third stage GOA circuit, … …, and the first stage GOA circuit may generate a scan signal OUT1 to be supplied to the pixel driving circuit of the first cell line in the display region according to an initial signal supplied from the initial signal line STV, a clock signal supplied from the clock signal line CLK/CLKB, and a signal supplied from the high-level signal line VGH/low-level signal line VGL, etc. The i-th stage GOA circuit may generate the scan signal OUTi to be supplied to the pixel driving circuit of the i-th cell row in the display area according to the scan signal OUTi-1 generated by the i-1 th stage GOA circuit, the first clock signal supplied from the first clock signal line CLK, the second clock signal supplied from the second clock signal line CLKB, the high level signal supplied from the high level signal line VGH, the low level signal supplied from the low level signal line VGL, and the like, i being a positive integer greater than 1.

Currently, with the increasing resolution of display devices, in order to ensure reliability and functionality of the bezel area, the bezel width of the conventional display device is about 1.5mm or more. Resolution (Pixels Per Inch, PPI for short) refers to the number of pixel units in a unit area, which may be referred to as pixel density, and the higher the PPI value, the higher the density the display device can display a picture, and the more detail the picture is. The resolution is improved, so that the number of the grid driving circuits in the frame area is increased, the occupied area of the grid driving circuits is increased, the width of the power supply leads in the frame area is increased, the impedance and the voltage drop of the power supply leads are reduced, the uniformity of display brightness is ensured, and the difficulty of reducing the width of the frame is high due to the structure of the grid driving circuits in the frame area.

In order to effectively reduce the frame width of the display device and achieve a narrow frame of the display device, exemplary embodiments of the present disclosure provide a display substrate in which a gate driving device is disposed in a display area (GATE DRIVER IN AA, abbreviated as GIA). In an exemplary embodiment, the display substrate may include at least a display region and a bezel region located at least one side of the display region. The display region may include a plurality of first regions and a plurality of second regions, and the first regions and the second regions may have a bar shape extending along the second direction, and the plurality of first regions and the plurality of second regions may be alternately arranged along the first direction, and the first direction and the second direction may intersect. In a direction perpendicular to the display substrate, the display region may include a driving structure layer disposed on the base and a light emitting structure layer disposed on a side of the driving structure layer away from the base. The driving structure layer of the first region may include a plurality of pixel driving circuits, the driving structure layer of the second region may include at least one gate driving device and/or at least one signal trace, and the light emitting structure layers of the first and second regions may include a plurality of light emitting devices; at least one light emitting device in the first region is connected to at least one pixel driving circuit in the first region, and at least one light emitting device in the second region is connected to at least one pixel driving circuit in the first region.

In an exemplary embodiment, the driving structure layer of the first region may include a plurality of circuit repeating units, an orthographic projection of the circuit repeating units on the substrate has a first area, and the light emitting structure layer of the first region may include a plurality of light emitting repeating units, an orthographic projection of the light emitting repeating units on the substrate has a second area, and a ratio of the first area to the second area is 0.95 to 1.05; the at least one circuit repeating unit may include m+m pixel driving circuits, and the at least one light emitting repeating unit may include M first light emitting devices; m is an integer multiple of 2 or an integer multiple of 3, and M is a positive integer greater than or equal to 1.

In an exemplary embodiment, the light emitting structure layer of the second region may include a first side repeating unit and a second side repeating unit, each including N light emitting devices, N being an integer multiple of 3 or an integer multiple of 4.

In an exemplary embodiment, the pixel driving circuit in the at least one circuit repeating unit may include at least a first pixel driving circuit and a second pixel driving circuit, the light emitting device in the at least one light emitting repeating unit may include a first light emitting device, and the light emitting device in the at least one second repeating unit may include a second light emitting device; at least one first pixel driving circuit is connected with at least one first light emitting unit, and the orthographic projection of the at least one first pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the at least one first light emitting device on the substrate; the at least one second pixel driving circuit is connected with the at least one second light emitting device through an anode connecting wire, and the orthographic projection of the at least one second pixel driving circuit on the substrate is not overlapped with the orthographic projection of the at least one second light emitting device on the substrate.

In an exemplary embodiment, the driving structure layer of the first region further includes at least one dummy connection line, the at least one dummy connection line having a shape of a straight line or a folded line extending along the first direction, and an orthographic projection of the at least one dummy connection line on the substrate at least partially overlaps an orthographic projection of an anode of the at least one first light emitting device on the substrate.

Fig. 7 is a schematic structural view of a display substrate according to an exemplary embodiment of the present disclosure. As shown in fig. 7, the display substrate may include at least a display region and a bezel region located at least one side of the display region on a plane parallel to the display substrate. The display region may include a plurality of first regions 10 and a plurality of second regions 20, and the first regions 10 and the second regions 20 may each have a bar shape extending along the second direction Y, and the plurality of first regions 10 and the plurality of second regions 20 may be alternately arranged along the first direction X to form the GIA structure, and the first direction X and the second direction Y intersect.

In an exemplary embodiment, the widths of the plurality of first regions 10 may be substantially the same, the widths of the plurality of second regions 20 may be substantially the same, the widths of the first regions 10 and the second regions 20 may be different, and the widths may be the dimensions of the first direction X. For example, the width of the at least one first region 10 may be greater than the width of the at least one second region 20.

In an exemplary embodiment, the display region may include a driving structure layer disposed on the base and a light emitting structure layer disposed on a side of the driving structure layer remote from the base in a direction perpendicular to the display substrate. The driving structure layer of the first region 10 may include a plurality of circuit units, which may include at least a pixel driving circuit, and the driving structure layer of the second region 20 may include a gate driving device and/or a signal trace. The light emitting structure layer of the first region 10 may include a plurality of first light emitting cells, the first light emitting cells may include at least a first light emitting device, the light emitting structure layer of the second region 20 may include a plurality of second light emitting cells, the second light emitting cells may include at least a second light emitting device, and the pixel driving circuit of the first region 10 is configured to provide driving signals to the first light emitting device in the first region 10 and the second light emitting device in the second region 20 to drive the corresponding first light emitting device and second light emitting device to emit light.

In an exemplary embodiment, the circuit unit referred to in the present disclosure refers to a region divided by a pixel driving circuit, and the light emitting unit referred to in the present disclosure refers to a region divided by a light emitting device. In an exemplary embodiment, the positions of both the light emitting unit and the circuit unit may be corresponding, or the positions of both the light emitting unit and the circuit unit may not be corresponding, which is not limited herein. In the following description, the position, shape, size, and the like of the pixel driving circuit are equivalent to the position, shape, size, and the like of the circuit unit, and the position, shape, size, and the like of the light emitting device are equivalent to the position, shape, size, and the like of the light emitting unit.

In an exemplary embodiment, the driving structure layer of the at least one first region 10 may include a plurality of circuit repeating units. The circuit repeating unit is a basic unit constituting the driving structure layer of the first region 10, and the driving structure layer of the first region 10 can be constituted by repeating and continuously disposing the circuit repeating unit along the first direction X and the second direction Y.

In an exemplary embodiment, the light emitting structure layer of at least one first region 10 may include a plurality of light emitting repeating units. The light emitting repeating unit is a basic unit constituting the light emitting structure layer of the first region 10, and the light emitting structure layer of the first region 10 can be constituted by repeating and continuously disposing the light emitting repeating unit along the first direction X and the second direction Y.

In an exemplary embodiment, the locations of the plurality of circuit repeating units and the plurality of light emitting repeating units in the at least one first region 10 may be in one-to-one correspondence, an orthographic projection of the at least one circuit repeating unit on the substrate may have a first area, an orthographic projection of the at least one light emitting repeating unit on the substrate may have a second area, and a ratio of the first area to the second area may be about 0.95 to 1.05, i.e., the orthographic projection area of the circuit repeating unit on the substrate may be substantially the same as the orthographic projection area of the light emitting repeating unit on the substrate.

In an exemplary embodiment, the size of the at least one circuit repeating unit in the first direction X and the size of the at least one light emitting repeating unit in the first direction X may be substantially the same, and the size of the at least one circuit repeating unit in the second direction Y and the size of the at least one light emitting repeating unit in the second direction Y may be substantially the same.

In an exemplary embodiment, the at least one circuit repeating unit may include m+m pixel driving circuits sequentially disposed along the first direction X, and the at least one light emitting repeating unit may include M first light emitting devices sequentially disposed along the first direction X, that is, an area of orthographic projection of the m+m pixel driving circuits on the substrate is substantially the same as an area of orthographic projection of the M first light emitting devices on the substrate.

In an exemplary embodiment, the plurality of pixel driving circuits may be substantially the same size in the at least one circuit repeating unit. In the present disclosure, the size of the pixel driving circuit refers to the size of the orthographic projection of the pixel driving circuit on the substrate. When the front projection of the pixel driving circuit on the substrate is rectangular, the size may include any one or more of the following: the length in the first direction X, the length in the second direction Y, and the area of the orthographic projection are orthographically projected. When the orthographic projection of the pixel driving circuit on the substrate is circular or elliptical, the dimensions may include any one or more of the following: radius of orthographic projection, major and minor axes of orthographic projection, area of orthographic projection.

In an exemplary embodiment, the plurality of first light emitting devices may be substantially the same size in the at least one light emitting repeating unit. In the present disclosure, the size of the light emitting device refers to the size of the orthographic projection of the light emitting device on the substrate. When the orthographic projection of the light emitting device on the substrate is rectangular, the dimensions may include any one or more of the following: the length in the first direction X, the length in the second direction Y, and the area of the orthographic projection are orthographically projected. When the orthographic projection of the light emitting device on the substrate is circular or elliptical, the dimensions may include any one or more of the following: radius of orthographic projection, major and minor axes of orthographic projection, area of orthographic projection.

In an exemplary embodiment, in at least one first region 10, the driving structure layer may set the pixel driving circuit in a compressed manner, and the light emitting structure layer sets the first light emitting device in a normal (non-compressed) manner. For example, in a normal mode, one circuit repeating unit may be provided with M pixel driving circuits, and one light emitting repeating unit may be provided with M first light emitting devices. In the compression mode, the number of the pixel driving circuits arranged in the circuit repeating unit can be increased by adopting transverse compression, and M pixel driving circuits are newly added on the basis of the previous M pixel driving circuits, so that M+m pixel driving circuits can be arranged in one circuit repeating unit. Since the light emitting structure layer adopts a normal manner, M first light emitting devices are still disposed in the light emitting repeating unit, and the area occupied by the m+m pixel driving circuits is substantially the same as the area occupied by the M first light emitting devices.

In an exemplary embodiment, for a pixel arrangement of Real RGB, M may be an integer multiple of 3, such as 3, 6, 9, 12, 15, or 18, and M may be a positive integer greater than or equal to 1, such as 1, 2, or 3.

In an exemplary embodiment, for a pixel arrangement to be an RGGB arrangement, M may be an integer multiple of 2, such as 2, 4,6, 8, 10 or 12, and M may be a positive integer greater than or equal to 1, such as 1,2 or 3.

In one exemplary embodiment, one light emitting repeating unit may include 18 first light emitting devices sequentially disposed along the first direction X, and one circuit repeating unit may include 21 pixel driving circuits sequentially disposed along the first direction X, i.e., m=18, m=3.

In another exemplary embodiment, one light emitting repeating unit may include 6 first light emitting devices sequentially disposed along the first direction X, and one circuit repeating unit may include 7 pixel driving circuits sequentially disposed along the first direction X, i.e., m=6, m=1.

In an exemplary embodiment, the light emitting structure layer of the at least one second region 20 may include a first side repeating unit and a second side repeating unit, and the first side repeating unit and the second side repeating unit may each include N second light emitting devices sequentially disposed along the first direction X.

In an exemplary embodiment, N may be an integer multiple of 3, such as 3, 6, 9, or 12, for the pixel arrangement to be Real RGB.

In an exemplary embodiment, N may be an integer multiple of 4, such as 4, 8, 12, or 16, for a pixel arrangement to be an RGGB arrangement.

In an exemplary embodiment, the size of the second light emitting device in the second region 20 may be substantially the same as the size of the first light emitting device in the first region 10, and the arrangement of the plurality of second light emitting devices in the second region 20 may be substantially the same as the arrangement of the plurality of first light emitting devices in the first region 10.

In an exemplary embodiment, in the at least one second region 20, each of the first and second side repeating units may include 6 second light emitting devices sequentially disposed along the first direction X, i.e., the light emitting structure layer of the second region 20 includes 12 second light emitting devices sequentially disposed along the first direction X.

In an exemplary embodiment, the driving structure layer of the second region 20 is provided with the gate driving device and/or the signal wiring, and the pixel driving circuit is not provided, and the second light emitting device of the second region 20 needs to be connected to the pixel driving circuit in the first region 10 through the anode connection line.

Fig. 8 and 9 are enlarged views of a region a in fig. 7, fig. 8 illustrates a structure of a driving structure layer in the region a, and fig. 9 illustrates a structure of a light emitting structure layer in the region a. As shown in fig. 8 and 9, the plurality of pixel driving circuits in the first region 10 may include a first pixel driving circuit Q1 and a second pixel driving circuit Q2, the first region 10 includes a plurality of first light emitting devices F1, and the second region 20 includes a plurality of second light emitting devices F2.

In an exemplary embodiment, at least one first pixel driving circuit Q1 in the first region 10 is connected to at least one first light emitting unit F1 in the first region 10, an orthographic projection of the at least one first pixel driving circuit Q1 on the substrate at least partially overlaps an orthographic projection of the at least one first light emitting device F1 on the substrate, and the first pixel driving circuit Q1 is configured to provide a driving signal to the connected first light emitting device F1 to drive the corresponding first light emitting device F1 to emit light. In some examples, the plurality of first pixel driving circuits Q1 and the plurality of first light emitting devices F1 may be in a one-to-one relationship, i.e., one first pixel driving circuit Q1 may be connected to one first light emitting device F1 configured to drive the connected one first light emitting device F1 to emit light; or the plurality of first pixel driving circuits Q1 and the plurality of first light emitting devices F1 may be in a one-to-many relationship, i.e., one first pixel driving circuit Q1 may be connected to the plurality of first light emitting devices F1 and configured to drive the connected plurality of first light emitting devices F1 to emit light; or the plurality of first pixel driving circuits Q1 and the plurality of first light emitting devices F1 may be in a many-to-one relationship, i.e., the plurality of first pixel driving circuits Q1 may be connected to one first light emitting device F1 and configured to drive the first light emitting device F1 to emit light.

In an exemplary embodiment, at least one second pixel driving circuit Q2 in the first region 10 is connected to at least one second light emitting device F2 in the second region 20 through an anode connection line, an orthographic projection of the at least one second pixel driving circuit Q2 on the substrate does not overlap with an orthographic projection of the at least one second light emitting device F2 on the substrate, and the second pixel driving circuit Q2 is configured to provide a driving signal to the connected second light emitting device F2 to drive the corresponding second light emitting device F2 to emit light. In some examples, the plurality of second pixel driving circuits Q2 and the plurality of second light emitting devices F2 may be in a one-to-one relationship, i.e., one second pixel driving circuit Q2 may be connected to one second light emitting device F2 configured to drive the connected one second light emitting device F2 to emit light; or the plurality of second pixel driving circuits Q2 and the plurality of second light emitting devices F2 may be in a one-to-many relationship, i.e., one second pixel driving circuit Q2 may be connected to the plurality of second light emitting devices F2, configured to drive the connected plurality of second light emitting devices F2 to emit light; or the plurality of second pixel driving circuits Q2 and the plurality of second light emitting devices F2 may be in a many-to-one relationship, i.e., the plurality of second pixel driving circuits Q2 may be connected to one second light emitting device F2 and configured to drive the second light emitting device F2 to emit light.

In an exemplary embodiment, the first and second pixel driving circuits Q1 and Q2 may be substantially the same in size, and the first and second light emitting devices F1 and F2 may be substantially the same in size.

In an exemplary embodiment, the driving structure layer of the second region 20 may include at least one gate driving device, or include at least one signal trace, or may include at least one gate driving device and at least one signal trace.

In an exemplary embodiment, the at least one gate driving device may include any one or more of the following: a first gate driver for outputting the first scanning signal line S1, a second gate driver for outputting the second scanning signal line S2, a third gate driver for outputting the third scanning signal line S3, a fourth gate driver for outputting the fourth scanning signal line S4, and a fifth gate driver for outputting the light emitting signal line EM. The at least one signal trace may comprise any one or more of: the first power line, the second power line, the initial signal line.

Fig. 10 is a schematic diagram illustrating connection between a pixel driving circuit and a light emitting device according to an exemplary embodiment of the present disclosure, and is an enlarged view of a region B in fig. 7. As shown in fig. 10, the second region 20 may be located between two first regions 10, and the two first regions 10 may include a first side region 10A located at one side of the second region 20 in the opposite direction of the first direction X and a second side region 10B located at one side of the second region 20 in the first direction X. The second region 20 may have a first center line O1, and the first center line O1 may be a straight line bisecting the second region 20 in the first direction X and extending along the second direction Y. The second region 20 includes at least a first side repeating unit 20A located on the opposite side of the first centerline O1 from the first direction X and a second side repeating unit 20B located on the first side of the first centerline O1 from the first direction X. At least one second light emitting device F2 in the first side repeating unit 20A may be connected to at least one second pixel driving circuit Q2 in the first side region 10A through an anode connection line, and at least one second light emitting device F2 in the second side repeating unit 20B may be connected to at least one second pixel driving circuit Q2 in the second side region 10B through an anode connection line, i.e., the second light emitting device F2 and the second pixel driving circuit Q2 located on the same side of the first center line O1 are correspondingly connected.

In an exemplary embodiment, the driving structure layer of the first region 10 is provided with a plurality of circuit repeating units, the light emitting structure layer of the first region 10 is provided with a plurality of light emitting repeating units, the driving structure layer of the second region 20 is provided with a gate driving device and/or a signal trace (not shown), and the light emitting structure layer of the second region 20 is provided with a first side repeating unit 20A and a second side repeating unit 20B.

In an exemplary embodiment, the driving structure layer of the first side region 10A may include at least a first circuit repeating unit 201 and a second circuit repeating unit 202, the first circuit repeating unit 201 may be located at a side of the second region 20 opposite to the first direction X, and the second circuit repeating unit 202 may be located at a side of the first circuit repeating unit 201 remote from the second region 20. The driving structure layer of the second side region 10B may include at least an eleventh circuit repeating unit 211 and a twelfth circuit repeating unit 212, and the eleventh circuit repeating unit 211 may be located at one side of the second region 20 in the first direction X, and the twelfth circuit repeating unit 212 may be located at one side of the eleventh circuit repeating unit 211 remote from the second region 20.

In an exemplary embodiment, the first, second, eleventh, and twelfth circuit repeating units 201, 202, 211, and 212 may each include 18 first pixel driving circuits Q1 and 3 second pixel driving circuits Q2, and among the at least one circuit repeating unit, the 18 first pixel driving circuits Q1 may be sequentially disposed along the first direction X and the 3 second pixel driving circuits Q2 may be disposed at one side of the first direction X of the first pixel driving circuits Q1.

In the exemplary embodiment, since the second pixel driving circuit Q2 in the circuit repeating unit is located at one side of the first direction X of the first pixel driving circuit Q1, the position of the second pixel driving circuit Q2 in the first circuit repeating unit 201 and the position of the second pixel driving circuit Q2 in the eleventh circuit repeating unit 211 are asymmetric with respect to the first center line O1, and the position of the second pixel driving circuit Q2 in the second circuit repeating unit 202 and the position of the second pixel driving circuit Q2 in the twelfth circuit repeating unit 212 are asymmetric with respect to the first center line O1.

In an exemplary embodiment, the light emitting structure layer of the first side region 10A may include at least a first light emitting repeating unit 301 and a second light emitting repeating unit 302, the first light emitting repeating unit 301 may be located at a side of the second region 20 opposite to the first direction X, and the second light emitting repeating unit 302 may be located at a side of the first light emitting repeating unit 301 remote from the second region 20. The light emitting structure layer of the second side region 10B may include at least an eleventh light emitting repeated unit 311 and a twelfth light emitting repeated unit 312, and the eleventh light emitting repeated unit 311 may be located at one side of the second region 20 in the first direction X, and the twelfth light emitting repeated unit 312 may be located at one side of the eleventh light emitting repeated unit 311 remote from the second region 20.

In an exemplary embodiment, the first, second, eleventh, and twelfth light emitting repeating units 301, 302, 311, and 312 may each include 18 first light emitting devices F1. The first light emitting device F1 may include a red light emitting device, a green light emitting device, and a blue light emitting device, and the red light emitting device, the green light emitting device, and the blue light emitting device may be periodically disposed along the first direction X.

In an exemplary embodiment, the first and second side repeating units 20A and 20B in the second region 20 may each include 6 second light emitting devices F2. The second light emitting device F2 may include a red light emitting device, a green light emitting device, and a blue light emitting device, and the red light emitting device, the green light emitting device, and the blue light emitting device may be periodically disposed along the first direction X.

In the exemplary embodiment, in at least one first region 10, the positions of one circuit repeating unit correspond one by one to the positions of one light emitting repeating unit, and the size of the circuit repeating unit is substantially the same as the size of the light emitting repeating unit, which corresponds to the area occupied by 21 pixel driving circuits being substantially the same as the area occupied by 18 light emitting devices.

In an exemplary embodiment, the position of the first circuit repeating unit 201 may correspond to the position of the first light emitting repeating unit 301, the position of the second circuit repeating unit 202 may correspond to the position of the second light emitting repeating unit 302, the position of the eleventh circuit repeating unit 211 may correspond to the position of the eleventh light emitting repeating unit 311, and the position of the twelfth circuit repeating unit 212 may correspond to the position of the twelfth light emitting repeating unit 312.

In an exemplary embodiment, in the corresponding circuit repeating unit and light emitting repeating unit, at least one first light emitting device F1 is directly connected to at least one first pixel driving circuit Q1, an orthographic projection of the at least one first light emitting device F1 on a substrate at least partially overlaps an orthographic projection of the at least one first pixel driving circuit Q1 on the substrate, and the first pixel driving circuit Q1 is configured to provide a driving signal to the connected first light emitting device F1 to drive the corresponding first light emitting device F1 to emit light.

In an exemplary embodiment, at least one second light emitting device F2 in the second region 20 is connected to at least one second pixel driving circuit Q2 in the first region 10 through an anode connection line, an orthographic projection of the at least one second light emitting device F2 on the substrate does not overlap with an orthographic projection of the at least one second pixel driving circuit Q2 on the substrate, and the second pixel driving circuit Q2 is configured to provide a driving signal to the connected second light emitting device F2 to drive the corresponding second light emitting device F2 to emit light.

In an exemplary embodiment, the first side repeating unit 20A may include at least a first light emitting device group and a second light emitting device group sequentially disposed along the first direction X, and the second side repeating unit 20B may include at least a third light emitting device group and a fourth light emitting device group sequentially disposed along the first direction X, and each light emitting device group may include 3 second light emitting devices F2. The 6 second light emitting devices F2 of the first and second light emitting device groups may be connected to the 6 second pixel driving circuits Q2 of the first side region 10A, and the 6 second light emitting devices F2 of the third and fourth light emitting device groups may be connected to the 6 second pixel driving circuits Q2 of the second side region 10B.

In an exemplary embodiment, the positions of the first light emitting device group in the first side repeating unit 20A and the fourth light emitting device group in the second side repeating unit 20B may be mirror-symmetrical with respect to the first center line O1, and the positions of the second light emitting device group in the first side repeating unit 20A and the third light emitting device group in the second side repeating unit 20B may be mirror-symmetrical with respect to the first center line O1.

In an exemplary embodiment, 3 second light emitting devices F2 of the first light emitting device group in the first side repeating unit 20A may be connected to 3 second pixel driving circuits Q2 in the first circuit repeating unit 201 through first anode connection lines 31, respectively, and 3 second light emitting devices F2 of the second light emitting device group in the first side repeating unit 20A may be connected to 3 second pixel driving circuits Q2 in the second circuit repeating unit 202 through second anode connection lines 32, respectively.

In an exemplary embodiment, 3 second light emitting devices F2 of the third light emitting device group in the second side repeating unit 20B may be connected to 3 second pixel driving circuits Q2 in the eleventh circuit repeating unit 211 through the third anode connection line 33, and 3 second light emitting devices F2 of the fourth light emitting device group in the second side repeating unit 20B may be connected to 3 second pixel driving circuits Q2 in the twelfth circuit repeating unit 212 through the fourth anode connection line 34.

In an exemplary embodiment, since the second circuit repeating unit 202 is located at a side of the first circuit repeating unit 201 remote from the second region 20, a distance of the second pixel driving circuit Q2 from the first center line O1 in the second circuit repeating unit 202 is greater than a distance of the second pixel driving circuit Q2 from the first center line O1 in the first circuit repeating unit 201, such that a second length of the at least one second anode connection line 32 is greater than a first length of the at least one first anode connection line 31, and the first length and the second length may be the dimensions of the first direction X.

In the exemplary embodiment, since the twelfth circuit repeating unit 212 is located at a side of the eleventh circuit repeating unit 211 remote from the second region 20, a distance of the second pixel driving circuit Q2 from the first center line O1 in the twelfth circuit repeating unit 212 is greater than a distance of the second pixel driving circuit Q2 from the first center line O1 in the eleventh circuit repeating unit 211, such that a fourth length of the at least one fourth anode connecting line 34 is greater than a third length of the at least one third anode connecting line 33, and the third length and the fourth length may be the size of the first direction X.

In the exemplary embodiment, since the second pixel driving circuit Q2 in the circuit repeating unit is located at one side of the first pixel driving circuit Q1 in the first direction X, the distance between the second pixel driving circuit Q2 and the first center line O1 in the eleventh circuit repeating unit 211 is greater than the distance between the second pixel driving circuit Q2 and the first center line O1 in the first circuit repeating unit 201, the distance between the second pixel driving circuit Q2 and the first center line O1 in the twelfth circuit repeating unit 212 is greater than the distance between the second pixel driving circuit Q2 and the first center line O1 in the second circuit repeating unit 202, such that the lengths of the anode connecting lines at both sides of the second region 20 are different, the third length of the at least one third anode connecting line 33 is greater than the first length of the at least one first anode connecting line 31, and the fourth length of the at least one fourth anode connecting line 34 is greater than the second length of the at least one second anode connecting line 32.

In an exemplary embodiment, the distance of the second pixel driving circuit Q2 from the first center line O1 in the second circuit repeating unit 202 may be greater than the distance of the second pixel driving circuit Q2 from the first center line O1 in the eleventh circuit repeating unit 211, and thus the second length of the at least one second anode connection line 32 may be greater than the third length of the at least one third anode connection line 33.

Fig. 11 is a schematic diagram illustrating connection between a pixel driving circuit and a light emitting device according to another exemplary embodiment of the present disclosure, and is an enlarged view of a region B in fig. 7. The connection structure of the pixel driving circuit and the light emitting device of the present embodiment is substantially the same as that described in fig. 10, except that the circuit repeating unit of the present embodiment includes 6 first pixel driving circuits Q1 and 1 second pixel driving circuits Q2, and the light emitting repeating unit includes 6 first light emitting devices F1.

As shown in fig. 11, the driving structure layer of the first side region 10A may include at least a twenty-first circuit repeating unit 221, a twenty-second circuit repeating unit 222, a twenty-third circuit repeating unit 223, and a twenty-fourth circuit repeating unit 224, which are sequentially disposed in a direction away from the second region 202. The driving structure layer of the second side region 10B may include at least a thirty-first circuit repeating unit 231, a thirty-second circuit repeating unit 232, a thirty-third circuit repeating unit 233, a thirty-fourth circuit repeating unit 234, a thirty-fifth circuit repeating unit 235, and a thirty-sixth circuit repeating unit 236, which are sequentially disposed in a direction away from the second region 202.

In an exemplary embodiment, the twenty-first to twenty-fourth circuit repeating units 221 to 224, the thirty-first to thirty-sixth circuit repeating units 231 to 236 may each include 6 first pixel driving circuits Q1 and 1 second pixel driving circuit Q2, and among the at least one circuit repeating unit, the 6 first pixel driving circuits Q1 may be sequentially disposed along the first direction X and the 1 second pixel driving circuit Q2 may be disposed at one side of the first pixel driving circuit Q1 in the first direction X.

In the exemplary embodiment, since the second pixel driving circuit Q2 in the circuit repeating unit is located at one side of the first pixel driving circuit Q1 in the first direction X, the positions of the second pixel driving circuit Q2 in the circuit repeating unit at the corresponding positions at both sides of the second region are asymmetric with respect to the first center line O1. For example, the position of the second pixel driving circuit Q2 in the twenty-first circuit repeating unit 221 and the position of the second pixel driving circuit Q2 in the thirty-first circuit repeating unit 231 are asymmetric with respect to the first center line O1.

In an exemplary embodiment, the light emitting structure layer of the first side region 10A may include at least a twenty-first light emitting repeating unit 321, a twenty-second light emitting repeating unit 322, a twenty-third light emitting repeating unit 323, and a twenty-fourth light emitting repeating unit 324 sequentially disposed in a direction away from the second region 202. The light emitting structure layer of the second side region 10B may include at least a thirty-first light emitting repeating unit 331, a thirty-second light emitting repeating unit 332, a thirty-third light emitting repeating unit 333, a thirty-fourth light emitting repeating unit 334, a thirty-fifth light emitting repeating unit 335, and a thirty-sixth light emitting repeating unit 336, which are sequentially disposed in a direction away from the second region 202.

In an exemplary embodiment, the twenty-first to twenty-fourth light-emitting repeated units 321 to 324, the thirty-first to thirty-sixth light-emitting repeated units 331 to 336 may each include 6 first light-emitting devices F1, and the first and second side repeated units 20A and 20B may each include 6 second light-emitting devices F2.

In an exemplary embodiment, 3 second light emitting devices F2 of the first light emitting device group in the first side repeating unit 20A may be connected to the second pixel driving circuits Q2 in the twenty-first to twenty-third circuit repeating units 221 to 223 through the first anode connection line 31, respectively, and 3 second light emitting devices F2 of the second light emitting device group in the first side repeating unit 20A may be connected to the second pixel driving circuits Q2 in the twenty-fourth to twenty-sixth circuit repeating units 224 to 2 through the second anode connection line 32, respectively.

In an exemplary embodiment, 3 second light emitting devices F2 of the third light emitting device group in the second side repeating unit 20B may be connected to the second pixel driving circuits Q2 in the thirty-first through thirty-third circuit repeating units 231 through 233 through third anode connection lines 33, respectively, and 3 second light emitting devices F2 of the fourth light emitting device group in the second side repeating unit 20B may be connected to the second pixel driving circuits Q2 in the thirty-fourth through thirty-sixth circuit repeating units 234 through 236 through fourth anode connection lines 34, respectively.

In an exemplary embodiment, the second length of the at least one second anode connection line 32 is greater than the first length of the at least one first anode connection line 31, and the fourth length of the at least one fourth anode connection line 34 is greater than the third length of the at least one third anode connection line 33.

In an exemplary embodiment, the third length of the at least one third anode connection line 33 is greater than the first length of the at least one first anode connection line 31, and the fourth length of the at least one fourth anode connection line 34 is greater than the second length of the at least one second anode connection line 32.

In an exemplary embodiment, the first, second, third, and fourth anode connection lines 31, 32, 33, and 34 may be a metal material such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), or molybdenum (Mo), or an alloy material composed of a metal such as aluminum neodymium (AlNd) or molybdenum niobium (MoNb), or a single-layer structure, or a multi-layer composite structure such as Ti/Al/Ti, or the like.

In another exemplary embodiment, the first, second, third and fourth anode connection lines 31, 32, 33 and 34 may employ a transparent conductive material such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). Since Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO) film is thin and transparent, anode flatness can be improved, and defects such as screen-off watermarks (Mura) can be improved.

In yet another exemplary embodiment, a plurality of anode connection lines may be provided in one conductive layer, or may be provided in two or more conductive layers, which is not limited herein.

In an exemplary embodiment, the aforementioned light emitting device is connected to the pixel driving circuit through an anode connection line, meaning that an anode of the light emitting device is connected to the pixel driving circuit through an anode connection line.

Fig. 12 is a schematic diagram of a virtual driving circuit according to an exemplary embodiment of the disclosure, which is an enlarged view of a region C in fig. 7. As shown in fig. 12, in at least one first region 10, the driving structure layer may include a plurality of first circuit units, which may include at least a first pixel driving circuit Q1, a plurality of second circuit units, which may include at least a second pixel driving circuit Q2, and at least one dummy circuit unit, which may include at least a dummy driving circuit Q3.

In the exemplary embodiment, in at least one first region 10, the positions and structures of the first and second pixel driving circuits Q1 and Q2 are substantially the same as those of the foregoing embodiment, and the structure, arrangement, size, and the like of the dummy driving circuit Q3 may be substantially the same as those of the second pixel driving circuit Q2, except that the dummy driving circuit Q3 is not connected to any light emitting device.

In an exemplary embodiment, among the plurality of circuit repeating units of the first region, a second pixel driving circuit in a part of the circuit repeating units is connected to a second light emitting device in a second region located on the opposite side of the first direction X of the first region, a second pixel driving circuit in another part of the circuit repeating units is connected to a second light emitting device in a second region located on the first side of the first direction X of the first region, and M pixel driving circuits are connected to a first light emitting device in a corresponding light emitting repeating unit, among the remaining circuit repeating units, M pixel driving circuits are connected as virtual driving circuits, which are not connected to either the first light emitting device or the second light emitting device.

In an exemplary embodiment, the dummy driving circuit Q3 may be disposed at a middle position of the first region in the first direction X on a side of the second pixel driving circuit Q2 remote from the second region 20.

Fig. 13 is a schematic view of an anode connection line according to an exemplary embodiment of the present disclosure. As shown in fig. 13, each of the first light emitting device and the second light emitting device may include an anode, wherein the connection of the first light emitting device to the first pixel driving circuit means that the anode of the first light emitting device is connected to the first pixel driving circuit, and the connection of the second light emitting device to the second pixel driving circuit means that the anode of the second light emitting device is connected to the second pixel driving circuit through the anode connection line.

In an exemplary embodiment, the anodes of the light emitting structure layers in the first and second regions 10 and 20 may be arranged in a real RGB manner or may be arranged in an RGBG manner, and the disclosure is not limited herein.

In an exemplary embodiment, the anode connecting line 30 may have a shape of a straight line or a folded line in which the main body portion extends along the first direction X, and the front projection of the anode connecting line 30 on the substrate at least partially overlaps with the front projection of at least one anode 40 in the first region 10 on the substrate, and the anode connecting line 30 may be a transverse connecting line.

In the present disclosure, a extending along the B direction means that a may include a main portion and a sub portion connected to the main portion, the main portion being a line, a line segment, or a bar-shaped body, the main portion extending along the B direction, and the main portion extending along the B direction for a length greater than that of the sub portion extending along other directions. The "a extends in the B direction" referred to in the following description means that the main body portion of a extends in the B direction.

In an exemplary embodiment, the anode connection lines 30 may be disposed as symmetrically as possible with respect to the anode 40 to ensure anode flatness.

In an exemplary embodiment, at least one first region 10 may be provided with at least one dummy connection line 41, the dummy connection line 41 may have a shape of a straight line or a folded line in which a body portion extends along the first direction X, an orthographic projection of the dummy connection line 41 on the substrate at least partially overlaps an orthographic projection of the at least one anode 40 on the substrate, the dummy connection line 41 is configured to promote flatness of the anode, and the dummy connection line 41 may serve as another lateral connection line.

In the exemplary embodiment, since the anode connection line 30 is disposed at a partial position in the first region 10, the first region 10 may be divided into a normal region 10-1 and a connection line region 10-2 in the first direction X according to the presence or absence of the anode connection line 30, the normal region 10-1 may be a region in which the anode connection line 30 is not disposed, and the connection line region 10-2 may be a region in which the anode connection line 30 is disposed.

In an exemplary embodiment, the orthographic projection of at least one anode 40 in the normal region 10-1 on the substrate overlaps at least partially with the orthographic projection of K1 dummy connection lines 41 on the substrate, i.e., the number of overlapping anodes 40 in the normal region 10-1 with the lateral connection lines is K1.

In an exemplary embodiment, the front projection of at least one anode 40 in the interconnect line region 10-2 on the substrate at least partially overlaps the front projection of K2 dummy interconnect lines 41 on the substrate, and the front projection of that anode 40 on the substrate at least partially overlaps the front projection of K3 anode interconnect lines 30 on the substrate, i.e., the number of overlapping of one anode 40 in the interconnect line region 10-2 with the lateral interconnect lines is k2+k3.

In an exemplary embodiment, the number of overlapping of at least one anode 40 and the lateral connecting line in the normal region 10-1 and the number of overlapping of at least one anode 40 and the lateral connecting line in the connecting line region 10-2 may be substantially the same, i.e., k1=k2+k3, where K1, K2, and K3 are positive integers greater than or equal to 1.

In an exemplary embodiment, the arrangement of the lateral connection lines (dummy connection lines) in the normal region 10-1 may be substantially the same as the arrangement of the lateral connection lines (dummy connection lines and anode connection lines) in the connection line region 10-2, and the arrangement may be any one or more of the following: the position of the transverse connection line in the second direction Y, the width of the transverse connection line, the spacing between adjacent transverse connection lines. In an exemplary embodiment, the width and the pitch may be the dimensions of the second direction Y.

In an exemplary embodiment, the routing density of the lateral bond wires in the normal region 10-1 may be substantially the same as the routing density of the lateral bond wires in the bond wire region 10-2, which may be any one or more of the following: the area of the transverse connection line in the unit area, the sum of the widths of the transverse connection lines in the unit area, and the sum of the lengths of the transverse connection lines in the unit area, wherein the length can be the size of the first direction X, and the width can be the size of the second direction Y.

In the exemplary embodiment, since the anode connection line is not provided in the normal region and the anode connection line is provided in the connection line region, there is a problem in that the lateral connection line under the anode is not uniform in the first region. According to the method, the dummy connecting line is arranged in the first area, so that the overlapping quantity of the anodes and the transverse connecting lines in the normal area and the connecting line area is basically the same, the uniformity of the transverse connecting lines below the anodes is effectively improved, the flatness of the anodes is effectively improved, the color cast is effectively improved, and the display quality is improved. In addition, by arranging the arrangement modes of the transverse connecting lines in the normal area and the connecting line area to be basically the same or similar, the wiring densities of the transverse connecting lines in the normal area and the connecting line area are basically the same or similar, and defects such as screen quenching watermarks (Mura) are not easy to occur, so that the display quality is improved.

In an exemplary embodiment, the dummy connection line 41 may be connected with the signal connection line 50 through the trace connection line 42. The signal connection line 50 may have a linear or folded shape in which a main body portion extends along the first direction X, and the trace connection line 42 may have a linear or folded shape in which a main body portion extends along the second direction Y, a first end of the trace connection line 42 being connected to the signal connection line 50, and a second end of the trace connection line 42 being connected to one or more dummy connection lines 41.

In an exemplary embodiment, the trace connecting lines 42 may be disposed between adjacent anodes 40 in the first direction X, and the orthographic projection of the trace connecting lines 42 on the substrate does not overlap with the orthographic projection of the anodes 40 on the substrate, so that the flatness of the anodes is not affected.

In an exemplary embodiment, the signal connection lines 50 transmitting the same signal may be disposed at intervals of one or more cell rows in the second direction Y. For example, the signal connection lines 50 transmitting the same signal may be disposed in odd cell rows. As another example, the signal connection lines 50 transmitting the same signal may be disposed in even cell rows.

In an exemplary embodiment, the display substrate may include a plurality of conductive layers sequentially disposed on a base in a direction perpendicular to the display substrate. In one embodiment, the dummy connection line 41, the trace connection line 42, and the signal connection line 50 may be disposed in the same conductive layer, and the dummy connection line 41, the trace connection line 42, and the signal connection line 50 may be an integral structure connected to each other. In another embodiment, the dummy connection line 41, the trace connection line 42, and the signal connection line 50 may be disposed in different conductive layers, and the dummy connection line 41, the trace connection line 42, and the signal connection line 50 may be connected to each other through a via. In still another embodiment, 2 of the dummy connection lines 41, the trace connection lines 42, and the signal connection lines 50 are disposed in one conductive layer, and the other 1 is disposed in another conductive layer, which is not limited herein.

In an exemplary embodiment, the plurality of conductive layers may include at least a first gate metal layer, a second gate metal layer, a first source drain metal layer, a second source drain metal layer, and a third source drain metal layer sequentially disposed in a direction away from the substrate, and at least one of the dummy connection line 41, the trace connection line 42, and the signal connection line 50 may be disposed in the third source drain metal layer.

In an exemplary embodiment, the plurality of conductive layers may include at least a shielding layer, a first gate metal layer, a second gate metal layer, a first source drain metal layer, and a second source drain metal layer sequentially disposed in a direction away from the substrate, and at least one of the dummy connection line 41, the trace connection line 42, and the signal connection line 50 may be disposed in the shielding layer.

In one exemplary embodiment, the signal connection line 50 of the main body portion extending along the first direction X may be connected with the first power line of the main body portion extending along the second direction Y, not only forming a mesh-shaped communication structure transmitting the first power signal, but also effectively increasing the routing density of the first power line, further reducing the resistance of the first power line, reducing the voltage drop of the first power signal, reducing the power consumption, and improving the display uniformity.

In another exemplary embodiment, the signal connection line 50 of the main body portion extending along the first direction X may be connected to the second power line of the main body portion extending along the second direction Y, not only forming a mesh-shaped communication structure transmitting the second power signal, but also effectively increasing the routing density of the second power line, further reducing the resistance of the second power line, reducing the voltage drop of the second power signal, and improving the display uniformity.

In still another exemplary embodiment, the signal connection line 50 of which the main body portion extends along the first direction X may be connected to the initial signal line of which the main body portion extends along the second direction Y, not only forming a net-shaped communication structure transmitting the initial signal, but also effectively increasing the routing density of the initial signal line, further reducing the resistance of the initial signal line, reducing the voltage drop of the initial signal, enhancing the driving capability of the initial signal, and improving defects such as cross-talk and watermark caused by insufficient driving capability of the initial signal.

In an exemplary embodiment, the light emitting structure layer may include at least an anode conductive layer disposed at a side of the driving structure layer away from the substrate, a pixel defining layer disposed at a side of the anode conductive layer away from the substrate, an organic light emitting layer disposed at a side of the pixel defining layer away from the substrate, and a cathode disposed at a side of the organic light emitting layer away from the substrate. The anode conductive layer may include a plurality of anodes, the pixel defining layer may include a plurality of pixel openings exposing the anodes, and the organic light emitting layer is connected to the anodes through the pixel openings.

In an exemplary embodiment, the light emitting structure layer may further include at least one auxiliary cathode, which may be disposed in the same layer as the anode, an orthographic projection of the auxiliary cathode on the substrate at least partially overlaps an orthographic projection of the second power line (signal connection line connected to the second power line) on the substrate, and the auxiliary cathode is connected to the second power line (signal connection line connected to the second power line) through an auxiliary via hole, and the auxiliary cathode is configured to be connected to a cathode formed later.

In an exemplary embodiment, after the organic light emitting layer is formed, a connection hole exposing the auxiliary cathode may be formed using a laser drilling such that the cathode is connected with the auxiliary cathode through the connection hole.

In an exemplary embodiment, a plurality of auxiliary cathodes may be periodically disposed along the first direction X and the second direction Y, and the auxiliary cathodes having a mesh-shaped communication structure are formed on the display substrate, so that uniformity of the second power signal in the display substrate may be further improved, display uniformity may be improved, and display quality may be improved.

In some other embodiments, the auxiliary cathode may not be disposed in the light emitting structure layer, and the cathode in the light emitting structure layer is directly connected to the second power line (the signal connection line 50 connected to the second power line) using the connection hole, which is not limited herein.

In an exemplary embodiment, the pixel defining layer may employ a black organic material such as black polyimide or acryl or black polyethylene terephthalate. Because the pixel definition layer can cover wires such as anode connecting wires, dummy connecting wires and the like, the reflectivity of the signal wires can be reduced, and defects such as screen-off watermarks and the like can be effectively improved.

Fig. 14 is a schematic diagram of a second zone arrangement according to an exemplary embodiment of the present disclosure. As shown in fig. 14, the plurality of second regions 20 may include a first sub-region 20-1, a second sub-region 20-2, a third sub-region 20-3, a fourth sub-region 20-4, a fifth sub-region 20-5, a sixth sub-region 20-6, … …, an (n-5) th sub-region 20- (n-5), an (n-4) th sub-region 20- (n-4), an (n-3) th sub-region 20- (n-3), an (n-2) th sub-region 20- (n-2), an (n-1) th sub-region 20- (n-1), and an (n-th sub-region 20-n, which are sequentially disposed along the first direction X.

In an exemplary embodiment, for the scan driving means including 5 sets of gate driving means, the first sub-region 20-1 and the n-th sub-region 20-n may be provided with a first gate driving means 121 outputting the first scan signal line S1, the second sub-region 20-2 and the (n-1) -th sub-region 20- (n-1) may be provided with a second gate driving means 122 outputting the second scan signal line S2, the third sub-region 20-3 and the (n-2) -th sub-region 20- (n-2) may be provided with a third gate driving means 123 outputting the third scan signal line S3, the fourth sub-region 20-4 and the (n-3) -th sub-region 20- (n-3) may be provided with a fourth gate driving means 124 outputting the fourth scan signal line S4, the fifth sub-region 20-5 and the (n-4) -th sub-region 20- (n-4) may be provided with a fifth gate driving means 125 outputting the light emitting signal line EM, forming a bilateral driving structure of 5 sets of gate driving means.

In an exemplary embodiment, each group of gate driving devices may include a plurality of gate driving circuits connected in cascade, each stage of gate driving circuits being connected to a plurality of pixel driving circuits in one unit row through a scan signal line or a light emitting signal line, and supplying a scan signal or a light emitting control signal to the plurality of pixel driving circuits in the unit row.

In an exemplary embodiment, the plurality of pixel driving circuits in the first region and the plurality of gate driving circuits in the second region may be simultaneously prepared using the same process, without adding an additional patterning process. In some possible embodiments, one film layer or two film layers may be added to the second region for some special display effect (such as shading, light transmission uniformity, etc.) or display optimization, and the disclosure is not limited herein.

In an exemplary embodiment, the scanning driving device may not be limited to 5 groups of gate driving devices, but also to a double-side driving structure, and the scanning driving device may include other groups of gate driving devices and single-side driving structures, which are not limited herein.

In an exemplary embodiment, at least one of the sixth sub-area 20-6 to the (n-5) th sub-area 20- (n-5) may be provided with at least one signal trace 60, and the signal trace 60 may include any one or more of the following: a first power line 61, a second power line 62, and an initial signal line 63.

In one exemplary embodiment, each of the sixth sub-region 20-6 to (n-5) th sub-region 20- (n-5) may be provided with the first power line 61 to reduce the resistance of the first power line 61, reduce the voltage drop of the first power signal, reduce power consumption, and improve display uniformity.

In another exemplary embodiment, each of the sixth sub-region 20-6 to (n-5) th sub-region 20- (n-5) may be provided with the second power line 62 to reduce the resistance of the second power line 62, reduce the voltage drop of the second power signal, and improve the display uniformity.

In still another exemplary embodiment, each of the sixth sub-area 20-6 to (n-5) th sub-area 20- (n-5) may be provided with an initial signal line 63 to reduce the resistance of the initial signal line 63, reduce the voltage drop of the initial signal, enhance the driving capability of the initial signal, and improve the defects of cross-stripes and watermarks caused by the insufficient driving capability of the initial signal.

In still another exemplary embodiment, each of the sixth sub-area 20-6 to (n-5) th sub-area 20- (n-5) may be provided with the first power line 61 and the second power line 62, respectively, or may be provided with the first power line 61 and the initial signal line 63, respectively, or may be provided with the second power line 62 and the initial signal line 63, respectively, or may be provided with the first power line 61, the second power line 62 and the initial signal line 63, respectively, and the disclosure is not limited thereto.

In an exemplary embodiment, since the driving structure layers in the sixth sub-region 20-6 to (n-5) th sub-region 20- (n-5) are not provided with the gate driving means, the driving structure layers of these sub-regions may be provided with the dummy driving circuits, which may be substantially the same in structure, arrangement, and size as the pixel driving circuits in the first region, except that the dummy driving circuits are not connected to any light emitting device.

In an exemplary embodiment, at least one of the first to fifth sub-areas 20-1 to 20-5, the (n-4) th sub-area 20-n may further be provided with at least one signal trace 60, and the signal trace 60 may include any one or more of the following: a first power line 61, a second power line 62, and an initial signal line 63.

In an exemplary embodiment, the gate driving device may be disposed at a middle position of the sub-region in the first direction X in at least one of the first sub-region 20-1 to the fifth sub-region 20-5 and the (n-4) th sub-region 20-n, and the signal traces 60 may be disposed at one side or both sides of the gate driving device in the first direction X, respectively. For example, at least one sub-region may be provided with at least one first power line 61 and at least one initial signal line 63, and the first power line 61 and the initial signal line 63 may be disposed at both sides of the gate driving device. As another example, at least one sub-region may be provided with at least one second power line 62 and at least one initial signal line 63, and the second power line 62 and the initial signal line 63 may be disposed at both sides of the gate driving device. For another example, at least one sub-region may be provided with at least one first power line 61, at least one second power line 62, and at least one initial signal line 63, and the first power line 61, the second power line 62, and the initial signal line 63 may be disposed at both sides of the gate driving device.

In an exemplary embodiment, in a direction perpendicular to the display substrate, the signal trace 60 may be disposed on a side of the clock signal line away from the substrate, and the signal trace 60 for transmitting the direct current signal may shield the clock signal line, so as to avoid coupling between an anode connection line connected to the light emitting device and the clock signal line, affect stability of anode voltages in the gate driving device and the light emitting device, and improve driving performance of the gate driving device.

In one embodiment, each of the first to fifth sub-areas 20-1 to 20-5 and the (n-4) th sub-area 20-n may be provided with a first power line 61, and a front projection of the first power line 61 on the substrate at least partially overlaps with a front projection of a clock signal line on the substrate in the gate driving device, so that not only the clock signal may be shielded, but also a resistance of the first power line 61 may be further reduced, a voltage drop of the first power signal may be reduced, power consumption may be reduced, and display uniformity may be improved.

In another embodiment, each of the first to fifth sub-areas 20-1 to 20-5 and the (n-4) th sub-area 20-n may be provided with a second power line 62, and the orthographic projection of the second power line 62 on the substrate at least partially overlaps with the orthographic projection of the clock signal line on the substrate in the gate driving device, so that not only the clock signal may be shielded, but also the resistance of the second power line 62 may be further reduced, the voltage drop of the second power signal may be reduced, and the display uniformity may be improved.

In still another embodiment, each of the first to fifth sub-areas 20-1 to 20-5 and the (n-4) th sub-areas 20- (n-4) to 20-n may be provided with an initial signal line 63, and an orthographic projection of the initial signal line 63 on the substrate and an orthographic projection of a clock signal line in the gate driving device on the substrate at least partially overlap, so that not only the clock signal may be shielded, but also a resistance of the initial signal line 63 may be further reduced, a voltage drop of the initial signal may be reduced, a driving capability of the initial signal may be enhanced, and defects such as cross-stripes and watermarks caused by a driving capability shortage of the initial signal may be improved.

In still another exemplary embodiment, each of the first to fifth sub-areas 20-1 to 20-5, the (n-4) th sub-area 20-n may be provided with the first and second power lines 61 and 62, respectively, or may be provided with the first and initial signal lines 61 and 63, respectively, or may be provided with the second and initial signal lines 62 and 63, respectively, or may be provided with the first, second and initial signal lines 61, 62 and 63, respectively, and the disclosure is not limited thereto.

In an exemplary embodiment, the display area may be further provided with signal connection lines extending along the first direction X, the laterally extending signal connection lines being interconnected with the vertically extending signal traces, and a mesh-shaped communication structure is formed throughout the display area.

Fig. 15 is an enlarged view of a region D in fig. 14, illustrating the structure of the gate driving circuit and the signal wiring in the second region. As shown in fig. 15, a plurality of gate driving circuits GOA may be sequentially arranged along the second direction Y, and at least one gate driving circuit GOA may be connected to the scan start signal line STV, the first clock signal line CLK, the second clock signal line CLKB, the high level signal line VGH, and the low level signal line VGL, respectively.

In an exemplary embodiment, the scan start signal line STV, the first clock signal line CLK, the second clock signal line CLKB, the high level signal line VGH, and the low level signal line VGL may have a straight line or a folded line shape extending along the second direction Y, the high level signal line VGH may be disposed at one side of the gate driving circuit GOA in the first direction X, and the other gate signal lines may be disposed at one side of the gate driving circuit GOA in the opposite direction of the first direction X.

In an exemplary embodiment, one side of the high-level signal line VGH in the first direction X may be provided with at least one or more of the first power line 61 and the initial signal line 63, and the opposite side of the scan start signal line STV in the first direction X may be provided with at least one or more of the first power line 61 and the initial signal line 63, and the shape of the first power line 61 and the initial signal line 63 may be a straight line or a folded line extending along the second direction Y.

In an exemplary embodiment, the gate driving circuit GOA and the region where the gate signal line are located may be provided with at least one second power line 62, and the shape of the second power line 62 may be a straight line or a folded line extending along the second direction Y. The second power lines 62 may be plural, and the widths of the plural second power lines 62 may be the same or may be different, or may be combined into one wider one. The orthographic projection of the second power line 62 on the substrate at least partially overlaps with the orthographic projections of the first clock signal line CLK and the second clock signal line CLKB on the substrate, so that the second power line 62 can shield the clock signal, avoid the coupling of the connection line connecting the light emitting device and the clock signal line, and improve the driving performance of the gate driving device.

In an exemplary embodiment, the shape of the signal connection line 50 may be a straight line or a folded line extending along the first direction X, and in the second direction Y, the signal connection line 50 may be disposed between the two gate driving circuits GOA in cascade, completing the lateral bridging.

In an exemplary embodiment, at least one of the laterally extending signal connection lines 50 may be connected to the vertically extending first power line 61 to form an overall network communication structure for transmitting the first power signal within the display area, and/or at least one of the laterally extending signal connection lines 50 may be connected to the vertically extending second power line 62 to form an overall network communication structure for transmitting the second power signal within the display area, and/or at least one of the laterally extending signal connection lines 50 may be connected to the vertically extending initial signal line 63 to form an overall network communication structure for transmitting the initial signal within the display area, which is not limited herein.

Fig. 16 is an enlarged view of the area E in fig. 14, illustrating a connection structure of signal lines in the dummy driving circuit. As shown in fig. 16, the pixel driving circuits (first pixel driving circuit and second pixel driving circuit) in the first region 10 may include a storage capacitor and a plurality of transistors, and are connected to the data signal line 64, the first power line 61, and the initial signal line 63, respectively. The structure of the dummy driving circuit in part of the second region 20 may be substantially the same as that of the pixel driving circuit in the first region, but the data signal line 64, the first power line 61, and/or the initial signal line 63 connected to the dummy driving circuit may be connected to the signal connection line 50 through the via hole K, respectively. When the signal connection line 50 is configured to be connected to the second power line 62, shorting the longitudinal signal lines, which are originally used to transmit the data signal, the first power signal, and/or the initial signal, to the second power line 62 through the signal connection line 50 may maximize the routing density of the second power line 62.

Fig. 17 and 18 are schematic diagrams of a gate lead in accordance with an exemplary embodiment of the present disclosure. In an exemplary embodiment, the display substrate may include at least the display region 100 and the bonding region 200 located at one side of the display region 100 in the second direction Y. The display region 100 may include first regions 10 and second regions 20 alternately arranged along the first direction X, the first regions 10 may include a plurality of pixel driving circuits, and the second regions 20 may include a plurality of gate driving circuits. The bonding region 200 may include at least a driving chip region, and the driving chip region may include at least an integrated circuit (INTEGRATED CIRCUIT, abbreviated as IC) 80, the integrated circuit 80 being configured to be connected with a plurality of data-out lines (not shown) configured to be connected with a plurality of data-signal lines in the plurality of first regions 10 and a plurality of gate-out lines 81 configured to be connected with a scan start signal line STV, a first clock signal line CLK, a second clock signal line CLKB, a high-level signal line VGH, and a low-level signal line VGL in the plurality of second regions 20.

In an exemplary embodiment, for a bonding structure in which a Chip is bonded to a flexible substrate (Chip On Pi, abbreviated as COP), the gate lead 81 may be connected to pins On both sides of the integrated circuit 80, so that the integrated circuit 80 provides gate signals to the gate driving circuits in the plurality of second regions 20, as shown in fig. 17. Alternatively, the integrated circuit 80 may supply the gate signals to the gate driving circuits in the plurality of second regions 20 by wiring in a region between the output pins (pins on the side of the integrated circuit 80 close to the display region) and the input pins (pins on the side of the integrated circuit 80 far from the display region) such that the gate lead lines 81 are connected to the output pins and the pitches of the plurality of gate lead lines 81 are substantially the same, as shown in fig. 18. Alternatively, the integrated circuit 80 may provide the gate signals to the gate driving circuits in the plurality of second regions 20 by arranging the gate signals in an insertion order with the data signals, which is not limited herein.

In an exemplary embodiment, for a binding structure in which a Chip is bound to a Chip On Film (COF for short), a gate lead may be arranged On a flexible circuit board FPC, so that an integrated circuit provides gate signals to gate driving circuits in a plurality of second areas.

The exemplary embodiment of the disclosure provides a display substrate, through alternately setting up first region and second region in the display region, first region sets up pixel drive circuit, second region sets up gate drive circuit and signal wiring, all set up gate drive circuit and signal wiring in the display region, do not occupy the space in frame region, effectively reduced display device's frame width, the frame width can reduce to below 0.5mm, has improved the screen and has taken up by the percentage, is favorable to realizing comprehensive screen display.

According to the embodiment of the disclosure, the pixel driving circuit is arranged in the first area in a compression mode, so that the pixel driving circuit in the first area is connected with the light emitting device in the second area, normal display can be realized in both the first area and the second area, the display resolution is not affected, and the realization of high display resolution is facilitated.

According to the embodiment of the disclosure, the dummy connecting line is arranged, so that the uniformity of the transverse connecting line below the anode can be effectively improved, the flatness of the anode can be effectively improved, the color cast is effectively improved, and the display quality is improved. According to the embodiment of the disclosure, the arrangement modes of the transverse connecting lines in the normal area and the connecting line area are basically the same or similar, the wiring densities of the transverse connecting lines in the normal area and the connecting line area are basically the same or similar, defects such as screen quenching watermarks (Mura) are not easy to occur, and the display quality is improved.

According to the embodiment of the disclosure, the dummy connecting wire is connected with the signal lead, so that the wiring density of the signal lead is effectively increased, the resistance of the signal lead can be further reduced, the voltage drop of signals is reduced, the power consumption is reduced, and the display uniformity is improved.

According to the embodiment of the disclosure, the main body part is connected with the signal lead wire extending along the second direction along the signal connecting wire extending along the first direction, and the whole netlike communication structure is formed in the display area, so that the resistance of the signal lead wire can be effectively reduced, the voltage drop of signals is reduced, the uniformity of the signals in the display substrate can be effectively improved, the display uniformity is effectively improved, and the display quality are improved.

According to the embodiment of the disclosure, the signal lead is overlapped with the clock signal wire, and the clock signal wire can be shielded by the signal wire for transmitting the direct current signal, so that the driving performance of the grid driving device is effectively improved.

According to the embodiment of the disclosure, the auxiliary cathode is arranged to form the netlike communication structure on the display substrate, so that the uniformity of the second power supply signal in the display substrate can be further improved, the display uniformity is improved, and the display quality are improved.

According to the embodiment of the disclosure, the black pixel definition layer is arranged, so that the reflectivity of the signal wiring can be reduced, and defects such as screen extinction watermarking can be effectively improved.

The preparation process of the embodiment of the disclosure can be well compatible with the existing preparation process, and has the advantages of simple process implementation, easy implementation, high production efficiency, low production cost and high yield.

The foregoing illustrated structure of the present disclosure is merely an exemplary illustration, and in exemplary embodiments, the corresponding structure may be modified according to actual needs, and the present disclosure is not limited thereto.

In an exemplary embodiment, the display substrate of the present disclosure may be applied to a display device having a pixel driving circuit, such as an OLED, a quantum dot display (QLED), a light emitting diode display (Micro LED or Mini LED), or a quantum dot light emitting diode display (QDLED), etc., which is not limited herein.

The disclosure also provides a preparation method of the display substrate, so as to manufacture the display substrate provided by the embodiment. In an exemplary embodiment, the display substrate includes a plurality of first regions and a plurality of second regions, the first and second regions having a shape of a bar extending along a second direction, the plurality of first and second regions being alternately arranged along a first direction, the first and second directions crossing; the preparation method can comprise the following steps:

The disclosure also provides a display device, which comprises the display substrate. The display device may be: any product or component with display function such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like can be spliced into a cylindrical, surrounding screen, spherical and other borderless display, and the embodiment of the invention is not limited to the above.

While the embodiments disclosed in the present disclosure are described above, it should be noted that the above-described embodiments are merely exemplary and not limiting. Accordingly, the present disclosure is not limited to what has been particularly shown and described herein. Various modifications, substitutions, or omissions may be made in the form and details of the implementations without departing from the scope of the disclosure.

Claims

1. A display substrate characterized by comprising a plurality of first regions and a plurality of second regions, the first regions and the second regions having a shape of a bar extending along a second direction, the plurality of first regions and the plurality of second regions being alternately arranged along a first direction, the first direction and the second direction intersecting; in the direction perpendicular to the display substrate, the display region includes a driving structure layer disposed on a base and a light emitting structure layer disposed on a side of the driving structure layer away from the base; the driving structure layer of the first area comprises a plurality of pixel driving circuits, the driving structure layer of the second area comprises at least one grid driving device and/or at least one signal wire, the light emitting structure layer of the first area comprises a plurality of first light emitting devices, and the light emitting structure layer of the second area comprises a plurality of second light emitting devices; at least one first light emitting device in the first region is connected to at least one pixel driving circuit in the first region, and at least one second light emitting device in the second region is connected to at least one pixel driving circuit in the first region.

2. The display substrate of claim 1, wherein the driving structure layer of the first region comprises a plurality of circuit repeating units, a front projection of at least one circuit repeating unit on the substrate has a first area, the light emitting structure layer of the first region comprises a plurality of light emitting repeating units, a front projection of at least one light emitting repeating unit on the substrate has a second area, and a ratio of the first area to the second area is 0.95 to 1.05; at least one circuit repeating unit includes m+m pixel driving circuits, and at least one light emitting repeating unit includes M first light emitting devices; m is an integer multiple of 2 or an integer multiple of 3, and M is a positive integer greater than or equal to 1.

3. The display substrate according to claim 2, wherein the pixel driving circuits in the at least one circuit repeating unit comprise at least a first pixel driving circuit and a second pixel driving circuit, the at least one first pixel driving circuit being connected to the at least one first light emitting unit, an orthographic projection of the at least one first pixel driving circuit onto the substrate at least partially overlapping an orthographic projection of the at least one first light emitting device onto the substrate; the at least one second pixel driving circuit is connected with the at least one second light emitting device through an anode connecting wire, and the orthographic projection of the at least one second pixel driving circuit on the substrate is not overlapped with the orthographic projection of the at least one second light emitting device on the substrate.

4. A display substrate according to claim 3, wherein the second region has a first center line which is a straight line dividing the second region in the first direction and extending along the second direction; the second region includes at least a first side repeating unit located on a side opposite to the first direction of the first center line and a second side repeating unit located on a side of the first direction of the first center line, each of the first side repeating unit and the second side repeating unit includes N second light emitting devices, N being an integer multiple of 3 or an integer multiple of 4.

5. The display substrate according to claim 4, wherein the first region includes at least a first side region located on a side of the second region opposite to the first direction and a second side region located on a side of the second region opposite to the first direction; at least one second light emitting device in the first side repeating unit is connected to at least one second pixel driving circuit in the first side region through an anode connection line, and at least one second light emitting device in the second side repeating unit is connected to at least one second pixel driving circuit in the second side region through an anode connection line.

6. The display substrate according to claim 5, wherein the first side region includes at least a first circuit repeating unit and a second circuit repeating unit, the first circuit repeating unit being located on a side of the second region opposite to the first direction, the second circuit repeating unit being located on a side of the first circuit repeating unit away from the second region; the second side region includes at least an eleventh circuit repeating unit located on one side of the second region in the first direction and a twelfth circuit repeating unit located on one side of the eleventh circuit repeating unit away from the second region; the first side repeating unit includes a first light emitting device group and a second light emitting device group sequentially arranged along the first direction, and the second side repeating unit includes a third light emitting device group and a fourth light emitting device group sequentially arranged along the first direction; at least one second light emitting device of the first light emitting device group is connected with at least one second pixel driving circuit of the first circuit repeating unit through a first anode connecting wire, at least one second light emitting device of the second light emitting device group is connected with at least one second pixel driving circuit of the second circuit repeating unit through a second anode connecting wire, at least one second light emitting device of the third light emitting device group is connected with at least one second pixel driving circuit of the eleventh circuit repeating unit through an eleventh anode connecting wire, and at least one second light emitting device of the fourth light emitting device group is connected with at least one second pixel driving circuit of the twelfth circuit repeating unit through a twelfth anode connecting wire.

7. The display substrate of claim 6, wherein a second length of at least one second anode connection line is greater than a first length of at least one first anode connection line, a fourth length of at least one twelfth anode connection line is greater than a third length of at least one eleventh anode connection line, the first length, the second length, the third length, and the fourth length being dimensions of the first direction.

8. The display substrate of claim 7, wherein a third length of the at least one eleventh anode connection line is greater than the first length of the at least one first anode connection line, and a fourth length of the at least one twelfth anode connection line is greater than the second length of the at least one second anode connection line.

9. A display substrate according to claim 3, wherein the material of the anode connection line is a metal material or the material of the anode connection line is a transparent conductive material.

10. A display substrate according to claim 3, wherein the first light emitting device and the second light emitting device each comprise an anode, the anode of at least one second light emitting device is connected to at least one second pixel driving circuit by the anode connection line, the shape of at least one anode connection line is a straight line or a folded line extending along the first direction, and the orthographic projection of at least one anode connection line on the substrate at least partially overlaps the orthographic projection of the anode of at least one first light emitting device on the substrate.

11. The display substrate of claim 10, wherein the first region further comprises at least one dummy connection line, the at least one dummy connection line having a shape that is linear or folded along the first direction, an orthographic projection of the at least one dummy connection line on the substrate at least partially overlapping an orthographic projection of an anode of the at least one first light emitting device on the substrate.

12. The display substrate according to claim 11, wherein the first region includes at least a normal region and a connection line region, the normal region being a region where the anode connection line is not provided, the connection line region being a region where the anode connection line is provided; the orthographic projection of at least one anode in the normal region on the substrate at least partially overlaps with the orthographic projection of K1 dummy connection lines on the substrate, the orthographic projection of at least one anode in the connection line region on the substrate at least partially overlaps with the orthographic projections of K2 dummy connection lines and K3 anode connection lines on the substrate, k1=k2+k3, K1, K2, and K3 are positive integers greater than or equal to 1.

13. The display substrate according to claim 12, wherein the arrangement of the dummy connection lines in the normal region is the same as the arrangement of the dummy connection lines and the anode connection lines in the connection line region, the arrangement being any one or more of: the position of the connection lines in the second direction, the width of the connection lines, the spacing between adjacent connection lines, the width and the spacing being the dimensions of the second direction.

14. The display substrate according to claim 12, wherein a wiring density of the dummy connection lines in the normal region is the same as a wiring density of the dummy connection lines and the anode connection lines in the connection line region, the wiring density being an area of the interconnect lines per unit area.

15. The display substrate according to claim 11, wherein at least one dummy connection line is connected to at least one signal connection line through at least one trace connection line, the trace connection line has a shape of a straight line or a folded line extending along the second direction, the trace connection line is disposed between two anodes adjacent in the first direction, and an orthographic projection of the trace connection line on the substrate does not overlap with an orthographic projection of the anode on the substrate.

16. The display substrate according to claim 15, wherein the signal connection line has a shape of a straight line or a folded line extending along the first direction; at least one signal connection line is connected with a first power line serving as the signal line and the main body part extends along the second direction to form a net-shaped communication structure for transmitting a first power signal, and/or at least one signal connection line is connected with a second power line serving as the signal line and the main body part extends along the second direction to form a net-shaped communication structure for transmitting a second power signal, and/or at least one signal connection line is connected with an initial signal line serving as the signal line and the main body part extends along the second direction to form a net-shaped communication structure for transmitting an initial signal.

17. The display substrate according to claim 16, wherein at least one gate driving device includes a plurality of gate driving circuits which are sequentially arranged along the second direction and are cascade-connected, the at least one gate driving circuit being connected to a first clock signal line and a second clock signal line, the first clock signal line and the second clock signal line having a shape of a straight line or a folded line extending along the second direction; in at least one second region, an orthographic projection of the first power line on the substrate at least partially overlaps an orthographic projection of the first and second clock signal lines on the substrate, and/or an orthographic projection of the second power line on the substrate at least partially overlaps an orthographic projection of the first and second clock signal lines on the substrate, and/or an orthographic projection of the initial signal line on the substrate at least partially overlaps an orthographic projection of the first and second clock signal lines on the substrate.

18. The display substrate according to claim 17, wherein in the second direction at least one signal connection line is provided between two gate driving circuits in cascade.

19. A display device comprising the display substrate according to any one of claims 1 to 18.

20. A method for manufacturing a display substrate, the display substrate including a plurality of first regions and a plurality of second regions, the first regions and the second regions having a shape of a bar extending along a second direction, the plurality of first regions and the plurality of second regions being alternately arranged along a first direction, the first direction and the second direction intersecting; the preparation method comprises the following steps: