CN117971751A - High-efficiency SPI and multi-channel UART conversion system and method - Google Patents
High-efficiency SPI and multi-channel UART conversion system and method Download PDFInfo
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The invention relates to the technical field of onboard embedded computer data processing, and discloses a high-efficiency SPI and multi-channel UART conversion system and method.
Description
Technical Field
The invention relates to the technical field of onboard embedded computer data processing, and discloses a high-efficiency SPI and multi-channel UART conversion system and method.
Background
The universal asynchronous receiver Transmitter (Universal Asynchronous Receiver/Transmitter, UART) interface is a commonly used data communication interface, and RS232, RS422 and RS485 interfaces derived based on UART interfaces have been widely used in the fields of aviation, avionics and vehicle-mounted embedded computers.
With the trend of high performance and complexity of embedded computing technology, the number of cross-linked UART interfaces between various computer devices is continuously increasing, and the transmission rate requirement of UART interfaces is also continuously increasing, and the requirement of embedded computer development cannot be met only by using UART interfaces of a processor (CPU). Therefore, the technology of converting a data interface (or data bus) into a plurality of high-rate UART interfaces has become a technology which has to be broken through in the field of embedded data processing, especially in the development of embedded computers.
The SPI interface is the most widely used low-speed serial transmission protocol in the embedded computing field. The SPI has the advantages that the transmission protocol is simple, and the SPI master device and the slave device exchange transmission data according to bits according to the SPI transmission protocol. The SPI interface contains 4 signal lines in total, SCK (SPI clock signal, 1 bit of SPI data for every 1 clock cycle), ss# (SPI chip select signal, when the chip select signal is valid, the master device starts data transmission with the slave device), MOSI (SPI data output signal, serial data sent from the master device to the slave device), and MISO (SPI data input signal, serial data sent from the slave device to the master device). The SPI transmission protocol does not prescribe byte data transmitted by the SPI, and the data format conforming to the SPI transmission protocol is as follows: the 0-7 bit data table is SPI transmission operation code, 8-39 bit data is SPI transmission address, and every 8 subsequent bit data is effective data actually transmitted by SPI.
The transmission protocol of the SPI can analyze that when the single byte transmission is performed between the master device and the slave device of the SPI, the efficiency is 8/48=16.67%, and when the SPI performs multi-byte continuous transmission, the transmission efficiency is gradually improved along with the increase of the number of transmission bytes. For example, when SPI performs 2-byte transmission, the transmission efficiency is 29.63%; the transmission efficiency is 44.44% when 4 bytes are transmitted, and 61.54% when 8 bytes are transmitted; the transmission efficiency is 76.19% when 16 bytes are transmitted, and 92.75% when 64 bytes are transmitted; 256 bytes, and the efficiency of the transmission is 98.08%. Therefore, when the upper computer (SPI master device) accesses the FPGA (SPI slave device) in a multi-byte continuous transmission mode, the SPI interface has higher access efficiency. For example, when the host computer continuously accesses 64 bytes of data at a single time with a 24MHz clock, the SPI interface speed is about 2.78MB/s, and the speed can meet the full-load communication requirement of the multi-path low-speed interface of the embedded computer.
Therefore, the SPI multi-byte continuous access UART interface can realize efficient conversion between SPI and UART receiving. However, the characteristics of the UART interface determine that the SPI cannot directly and continuously access the UART interface. Because, in order to achieve efficient receiving and transmitting of UART data, the UART interface has a receive FIFO and a transmit FIFO added therein for buffering the data. The access UART interface is in effect an SPI interface accessing the UART interface internal FIFO. Therefore, the data process of the UART interface is read by the upper computer: 1) The upper computer reads the UART interface state and judges whether the UART interface is received or not; 2) The upper computer reads UART receiving data. If the upper computer directly reads UART interface data by adopting an SPI interface, the SPI reading efficiency is 8/96=8.3, and high-efficiency data conversion between the SPI and the UART cannot be realized.
Disclosure of Invention
The invention aims to provide a high-efficiency SPI and multi-channel UART conversion system and method, which can realize continuous multi-byte reading or writing of UART interface data by an SPI interface of an upper computer, realize high-efficiency data conversion of the SPI interface and the multi-channel UART interface, have lower utilization rate of FPGA resources, and have higher data conversion efficiency and wide applicability.
In order to achieve the technical effects, the technical scheme adopted by the invention is as follows:
A high efficiency SPI and multi-UART conversion system, comprising: the system comprises a data buffer channel, an SPI interface data transmission unit, a UART interface and a UART interface data access unit; wherein:
The data buffer channel comprises a UART receiving FIFO and a UART sending FIFO and is used for buffering data of the SPI interface data transmission unit and the UART interface data access unit;
The SPI interface data transmission unit is used for continuously receiving serial SPI data of the upper computer, converting the SPI data into parallel data and putting the parallel data into the UART sending FIFO; or continuously reading the data in the data cache and converting the data into serial SPI data;
The UART interface is used for receiving or transmitting UART serial data;
the UART interface data access unit is used for transferring the data of the UART interface into the UART receiving FIFO or writing the data of the UART sending FIFO into the UART interface.
Further, a UART receiving FIFO and a UART transmitting FIFO are arranged between the SPI interface data transmission unit and each UART interface.
Further, the system also comprises an SPI and UART data conversion unit, wherein the SPI and UART data conversion unit is used as an arbitration mechanism for controlling the access of the SPI interface data transmission unit and the UART interface data access unit to the UART receiving FIFO and the UART sending FIFO; the SPI and UART data conversion unit provides the number of effective data which can be read in the UART receiving FIFO to the upper computer, and the upper computer prohibits the UART interface data access unit from writing data into the UART receiving FIFO in the process of continuously reading data from the UART receiving FIFO.
Further, the capacities of the UART receive FIFO and the UART transmit FIFO of the data buffer channel are less than or equal to 128 bytes, and the lengths of the data for SPI continuous multi-byte reading and continuous multi-byte writing are at most 64 and at least 1.
In order to achieve the above technical effects, the present invention further provides a high-efficiency SPI and multi-UART conversion method, including:
when the upper computer performs data transmission operation from SPI to UART:
The SPI interface data transmission unit continuously receives serial SPI data of the upper computer, converts the SPI data into parallel data, and puts the parallel data into the UART sending FIFO;
The UART interface data access unit writes the data of the UART sending FIFO into the UART interface;
UART interface completes the data transmission of upper computer;
When the upper computer performs data reading operation from UART to SPI:
the UART interface receives external data, and the UART interface data access unit writes the data of the UART interface into the UART receiving FIFO;
After the upper computer initiates SPI continuous reading operation, the SPI interface data transmission unit converts parallel data of the UART receiving FIFO into SPI interface data and continuously transmits the SPI interface data to the upper computer.
Further, the length of the SPI data is 64 bytes, and if the length of the SPI data is greater than 64 bytes in the process of the data transmission operation from the SPI to the UART, the upper computer performs SPI reading or writing operation for a plurality of times by taking 64 bytes as the maximum data load each time.
Compared with the prior art, the invention has the following beneficial effects: the upper computer of the invention performs data interaction with the UART interface by adopting an SPI multi-byte continuous access mode, can realize continuous multi-byte reading or writing of UART interface data by the SPI interface of the upper computer, realizes high-efficiency data conversion between the SPI interface and a plurality of UART interfaces, has lower utilization rate of FPGA resources, has higher data conversion efficiency and wide applicability, and can be used for various FPGA hardware platforms.
Drawings
FIG. 1 is a block diagram of a high-efficiency SPI and multi-channel UART conversion system in accordance with embodiments 1 or 2;
1, a data buffer channel; 2. SPI interface data transmission unit; 3. UART interfaces; 4. UART interface data access unit; 5. UART receives the FIFO; 6. UART send FIFO; 7. SPI and UART data conversion unit.
Detailed Description
The present invention will be described in further detail with reference to the following examples and drawings. It should not be construed that the scope of the above subject matter of the present invention is limited to the following embodiments, and all techniques realized based on the present invention are within the scope of the present invention.
Example 1
Referring to fig. 1, a high efficiency SPI and multi-UART conversion system, comprising: the system comprises a data buffer channel 1, an SPI interface data transmission unit 2, a UART interface 3 and a UART interface data access unit 4; wherein:
the data buffer channel 1 comprises a UART receiving FIFO5 and a UART sending FIFO6, and is used for buffering data of the SPI interface data transmission unit 2 and the UART interface data access unit 4;
the SPI interface data transmission unit 2 is used for continuously receiving serial SPI data of the upper computer, converting the SPI data into parallel data and putting the parallel data into the UART sending FIFO6; or continuously reading the data in the data cache and converting the data into serial SPI data;
UART interface 3, is used for receiving or sending UART serial data;
And the UART interface data access unit 4 is used for transferring the data of the UART interface 3 into the UART receiving FIFO5 or writing the data of the UART sending FIFO6 into the UART interface 3.
In this embodiment, the SPI interface data transmission unit 2, as an SPI slave device, may perform at least 4 kinds of SPI operations, including at least one byte read, one byte write, continuous multi-byte read, and continuous multi-byte write, with the upper computer, and the UART interface data access unit 4 may automatically perform the functions of the data in the external FIFO of the UART interface 3 and the internal FIFO of the UART interface 3. After the data receiving function of the UART interface data access unit 4 is enabled, referring to the data process of reading the UART interface 3 by the upper computer, continuously inquiring the internal FIFO state of the UART interface 3, if the internal FIFO is inquired that the data exists, reading the data, and writing the data into the corresponding receiving FIFO of the UART interface 3. After the upper computer initiates SPI continuous writing operation, the data transmitting function of the UART interface data access unit 4 is enabled, data is read from the UART transmitting FIFO6, and the data is written into the UART internal FIFO until all SPI data are transferred and then stop working. The upper computer performs data interaction with the UART interface 3 by adopting an SPI multi-byte continuous access mode, so that the SPI interface of the upper computer can continuously read or write the UART interface 3 data in a multi-byte manner, the SPI interface and the multi-channel UART interface 3 can realize high-efficiency data conversion, the FPGA resource utilization rate is lower, and the data conversion efficiency and the wide applicability are higher.
In this embodiment, a UART receiving FIFO5 and a UART transmitting FIFO6 are disposed between the SPI interface data transmission unit 2 and each UART interface 3, and are used for buffering the transmitting data and the receiving data of the SPI interface 3. The capacity of the UART receiving FIFO5 and the UART transmitting FIFO6 of the data buffer channel 1 is less than or equal to 128 bytes, so that the universality of the high-efficiency SPI and multi-channel UART conversion system on various FPGA (or CPLD) hardware platforms is ensured. In this embodiment, the data length of SPI continuous multi-byte reading and continuous multi-byte writing is at most 64 and at least 1.
The high-efficiency SPI and multipath UART conversion system further comprises an SPI and UART data conversion unit 7, wherein the SPI and UART data conversion unit 7 is used as an arbitration mechanism to control the access of the SPI interface data transmission unit 2 and the UART interface data access unit 4 to the UART receiving FIFO5 and the UART sending FIFO 6; the SPI and UART data conversion unit 7 provides the number of the effective data which can be read in the UART receiving FIFO5 for the upper computer, and the upper computer prohibits the UART interface data access unit 4 from writing data into the UART receiving FIFO5 in the process of continuously reading the data from the UART receiving FIFO 5. In addition, when the SPI interface data transmission unit 2 starts writing data to the UART transmit FIFO6 after the upper computer initiates a continuous multi-byte write operation, the SPI and UART data conversion unit 7 is responsible for enabling the UART interface data access unit 4 to transmit data, and counting the number of data written to the UART transmit FIFO6 and the number of data read from the UART transmit FIFO 6. When the SPI interface data transmission unit 2 completes data transmission of the SPI continuous multi-byte write operation and the UART transmit FIFO6 is the same as the write data in number as the read data in number, the UART interface data access unit 4 is prohibited from transmitting data. The SPI and UART data conversion unit 7 counts the number of data in the UART receiving FIFO5 from the UART interface data access unit 4, and provides the data to the upper computer for the upper computer to continuously read the data in the UART receiving FIFO5 in a plurality of bytes. After the SPI interface data transmission unit 2 initiates continuous multi-byte reading operation, the UART interface data access unit 4 is forbidden to receive data so as to ensure that no new data exists in the UART receiving FIFO5 at the moment, and after the SPI interface data transmission unit 2 completes data transmission of the SPI continuous multi-byte reading operation, the UART interface data access unit 4 is enabled again to receive data.
In this embodiment, continuous multi-byte reading or writing of UART interface 3 data by the SPI interface of the upper computer can be realized through the cooperative work of the three functional units of the SPI interface data transmission unit 2, the UART interface data access unit 4, and the SPI and UART data conversion unit 7. When the SPI clock is 24MHz, the data throughput of the SPI interface is 2.7MB/s when the upper computer is in data interaction with the UART interface 3 through the SPI interface, so that the full duplex and full load transmission of the UART interface 3 with the 120-path baud rate of 115200bps or the 15-path baud rate of 921600bps can be realized, and the transmission performance is 11 times that of the transmission of the UART interface 3 directly accessed by the SPI interface.
Example 2
Referring to fig. 1, in this embodiment, the data interaction between the upper computer and the UART interface 3 in the FPGA is performed by adopting an SPI multi-byte continuous access manner, which is described in detail in the high-efficiency SPI and multi-channel UART conversion method of the present invention, and includes the following steps:
step 1, an upper computer judges whether to perform UART interface 3 data transmission operation or UART interface 3 data receiving operation;
if the upper computer performs the data transmission operation from the SPI to the UART, the following operation is executed:
step 2a, the SPI interface data transmission unit 2 continuously receives serial SPI data of the upper computer, converts the SPI data into parallel data, and puts the parallel data into the UART sending FIFO6;
The data transmission format of the self-defined SPI multi-byte write operation in this embodiment is that 0 to 7 bits are SPI operation code 0x0a,8 to 17 bits are UART transmit FIFO6 reference numbers, each reference number corresponds to 1 UART interface 3 in the FPGA, 16 to 39 bits are reserved, and 8 bits after 40 bits are SPI actually transmitted data. The SPI multi-byte write operation data load is determined by the upper computer. The data load range of the SPI in this embodiment is 1 byte to 64 bytes. After the upper computer initiates SPI multi-byte writing operation, the SPI interface data transmission unit 2 in the FPGA receives SPI operation codes of 0x0A, and the received SPI effective transmission data are written into the corresponding UART sending FIFO6 one by one according to the marks of the UART sending FIFO6, wherein the size of the UART sending FIFO6 is 128 bytes.
Step 3a, the UART interface data access unit 4 writes the data of the UART transmit FIFO6 into the UART interface 3;
In this embodiment, the UART interface data access unit 4 starts to read the data in the UART transmitting FIFO6, and the UART writes the data in the FIFO into the UART interface 3 according to the data interaction manner of the conventional upper computer and the UART interface 3, thereby completing the data transmission of the upper computer. In the process of transmitting data by the upper computer, when the SPI interface data transmission unit 2 recognizes that the operation code is 0x0A, continuous data writing operation information is reported to the SPI and UART data conversion unit 7, the SPI and UART data conversion unit 7 counts the number of data received by the UART transmission FIFO6, and the UART interface data access unit 4 is enabled to transfer the data in the UART transmission FIFO6 to the corresponding UART interface 3. After the upper computer finishes SPI continuous data reading operation, the SPI and UART data conversion unit 7 judges that the UART interface data access unit 4 finishes UART receiving FIFO5 data reading, and related operation of the UART interface data access unit 4 is forbidden.
If the upper computer performs the data reading operation from the UART to the SPI, the following operation is executed:
Step 2b, the UART interface 3 receives external data, and the UART interface data access unit 4 writes the data of the UART interface 3 into the UART receiving FIFO5;
In this embodiment, the data format of the custom SPI multi-byte read operation is that bits 0 to 7 are SPI operation code 0x0b, bits 8 to 17 are UART receive FIFO5 reference numbers, each reference number corresponds to 1 UART interface 3 in the FPGA, bits 16 to 39 are reserved, and 8 bits after 40 bits are SPI actually transmitted data. The SPI multi-byte read operation data load is determined by the upper computer. The data payload of the SPI ranges from 1 byte to 64 bytes. Before the upper computer initiates SPI multi-word reading operation, the SPI single-byte reading operation is initiated first, the number of effective data in the UART receiving FIFO5 corresponding to one UART interface 3 is obtained from the SPI and UART data conversion unit 7 of the FPGA, so that the effective load of the SPI multi-byte reading operation is determined, the maximum effective load of the SPI multi-byte reading operation of the upper computer is 64 bytes, and when the number of the effective data in the UART receiving FIFO5 obtained by the upper computer is greater than 64, the upper computer initiates multiple SPI multi-byte reading operation to read all the data in the UART receiving FIFO 5. After the SPI interface data transmission unit 2 in the FPGA receives the SPI operation code of 0x0B, the SPI and UART data conversion unit 7 writes the data in the UART receiving FIFO5 into the SPI interface data transmission unit 2 according to the mark number of the UART receiving FIFO 5. The UART transmit FIFO6 in this embodiment is 256 bytes in size.
And 3b, after the upper computer initiates SPI continuous reading operation, the SPI interface data transmission unit 2 converts the parallel data of the UART receiving FIFO5 into SPI interface data and continuously transmits the SPI interface data to the upper computer.
In this embodiment, the UART interface data access unit 4 continuously reads UART data received by the UART interface 3 according to a data interaction manner between the conventional upper computer and the UART interface 3, and writes UART received data into the UART receiving FIFO5, and the upper computer can perform SPI continuous data reading operation on the UART receiving FIFO 5. In the process of receiving data by the upper computer, the UART interface data access unit 4 continuously writes the data received by the UART interface 3 into the UART receiving FIFO5, and meanwhile, the SPI and UART data conversion unit 7 counts the number of the data received by the UART receiving FIFO 5. When the upper computer starts to receive data of a certain UART receiving FIFO5, the SPI and UART data converting unit 7 prohibits the UART interface data accessing unit 4 from writing data from the UART interface 3 to the UART receiving FIFO5, so as to ensure that data in the UART receiving FIFO5 is not increased. After the upper computer reads all the data in the UART receiving FIFO5, the SPI and UART data converting unit 7 reclassifies the amount of data received by the UART receiving FIFO5, and resumes the UART interface data accessing unit 4 writing data from the UART interface 3 to the UART receiving FIFO 5.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (6)
1. A high efficiency SPI and multi-UART conversion system, comprising: the system comprises a data buffer channel (1), an SPI interface data transmission unit (2), a UART interface (3) and a UART interface data access unit (4); wherein:
the data buffer channel (1) comprises a UART receiving FIFO (5) and a UART sending FIFO (6) which are used for buffering the data of the SPI interface data transmission unit (2) and the UART interface data access unit (4);
The SPI interface data transmission unit (2) is used for continuously receiving serial SPI data of the upper computer, converting the SPI data into parallel data and putting the parallel data into the UART sending FIFO (6); or continuously reading the data in the data cache and converting the data into serial SPI data;
the UART interface (3) is used for receiving or transmitting UART serial data;
And the UART interface data access unit (4) is used for transferring the data of the UART interface (3) into the UART receiving FIFO (5) or writing the data of the UART sending FIFO (6) into the UART interface (3).
2. The high-efficiency SPI and multi-UART conversion system according to claim 1, wherein a UART receiving FIFO (5) and a UART transmitting FIFO (6) are provided between the SPI interface data transmission unit (2) and each UART interface (3).
3. The high-efficiency SPI and multi-UART conversion system according to claim 1, further comprising an SPI and UART data conversion unit (7), the SPI and UART data conversion unit (7) controlling access to the UART receive FIFO (5), the UART transmit FIFO (6) by the SPI interface data transmission unit (2) and the UART interface data access unit (4) as arbitration means; the SPI and UART data conversion unit (7) provides the number of the effective data which can be read in the UART receiving FIFO (5) for the upper computer, and the upper computer prohibits the UART interface data access unit (4) from writing data into the UART receiving FIFO (5) in the process of continuously reading the data from the UART receiving FIFO (5).
4. The efficient SPI and multi-lane UART conversion system according to claim 1, wherein the UART receive FIFO (5) and UART transmit FIFO (6) of the data buffer channel (1) have a capacity of 128 bytes or less, and the SPI continuous multi-byte read and continuous multi-byte write has a data length of at most 64 and at least 1.
5. A method for converting a high-efficiency SPI and multiple UART, the method being based on the high-efficiency SPI and multiple UART conversion system according to any one of claims 1 to 4, comprising:
when the upper computer performs data transmission operation from SPI to UART:
The SPI interface data transmission unit (2) continuously receives serial SPI data of the upper computer, converts the SPI data into parallel data, and puts the parallel data into the UART sending FIFO (6);
The UART interface data access unit (4) writes the data of the UART sending FIFO (6) into the UART interface (3);
UART interface (3) completes the data transmission of upper computer;
When the upper computer performs data reading operation from UART to SPI:
The UART interface (3) receives external data, and the UART interface data access unit (4) writes the data of the UART interface (3) into the UART receiving FIFO (5);
After the upper computer initiates SPI continuous reading operation, the SPI interface data transmission unit (2) converts parallel data of the UART receiving FIFO (5) into SPI interface data and continuously sends the SPI interface data to the upper computer.
6. The method of claim 5, wherein the upper computer continuously reads or transmits the SPI data with a length of 64 bytes, and if the length of the SPI data is greater than 64 bytes during the data transmission operation from the SPI to the UART, the upper computer performs multiple SPI read or write operations with a maximum data load of 64 bytes each time.
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