CN117970740A - Photomask of large-size spliced product and on-line measuring and positioning method - Google Patents
Photomask of large-size spliced product and on-line measuring and positioning method Download PDFInfo
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- CN117970740A CN117970740A CN202211306560.0A CN202211306560A CN117970740A CN 117970740 A CN117970740 A CN 117970740A CN 202211306560 A CN202211306560 A CN 202211306560A CN 117970740 A CN117970740 A CN 117970740A
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- 238000000034 method Methods 0.000 title claims abstract description 44
- 230000008569 process Effects 0.000 claims abstract description 24
- 238000001259 photo etching Methods 0.000 claims abstract description 9
- 238000005259 measurement Methods 0.000 claims description 59
- 238000010586 diagram Methods 0.000 claims description 23
- 238000012795 verification Methods 0.000 claims description 5
- 235000012431 wafers Nutrition 0.000 description 78
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 230000004075 alteration Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000011002 quantification Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Abstract
The application provides a photomask of a large-size spliced product and an on-line measuring and positioning method, wherein the photomask of the large-size spliced product comprises the following components: at least two exposure unit areas having different functions but the same size; the four corners of each exposure unit area are provided with locking angle patterns which are mirror symmetry, and the locking angle patterns are positioned in the chip area of the exposure unit area; when the photomask is adopted to carry out a splicing photoetching process on a wafer, the locking angle patterns are spliced on the wafer to form a cross mark, and the cross mark divides the whole chip area of the wafer into a plurality of measuring units with the same size, wherein each measuring unit corresponds to one exposure unit area. The photomask of the large-size spliced product and the on-line measuring and positioning method can enlarge the on-line measuring range and monitor the process difference on the wafer level.
Description
Technical Field
The application relates to the field of semiconductor process manufacturing, in particular to a photomask of a large-size spliced product and an on-line measuring and positioning method.
Background
In the chip manufacturing process, process parameters such as a critical dimension (CD, critical dimension), an interlayer alignment (OVL), a film Thickness (THK) and the like are detected in real time on line (inline), so that the accuracy and stability of chip manufacturing can be effectively ensured, the expected device characteristics of the chip are realized, and a locking angle pattern (locking counter) needs to be designed as a reference point of alignment (alignment) in on-line measurement.
With the diversification of the demands of chip applications, the demands of large-size products, such as image sensors, develop towards larger pixel sizes and pixel arrays, and the device sizes exceed the upper limit of the machine, such as photolithography, measurement, and the like, so that one-dimensional and two-dimensional stitching (stitching) photolithography processes are generated, the photomask (mask) is divided into different exposure unit areas according to functions and demands, and the different exposure unit areas are respectively exposed and finally stitched together to form a complete exposure area (shot) on the surface of the wafer (wafer).
Based on measurement requirements, a locking angle pattern is arranged at the crossing position of the cutting lines (scribing lines), but the shot size divided according to the position of the locking angle pattern still exceeds the upper limit of the dimension of the measuring machine. In order to solve the problem of on-line measurement of large-size spliced products, at present, special graphic design is performed on a part of the die (WAFER PARTIAL DIE) area of a wafer, and the image area with the locking angle pattern is repeatedly exposed to form a measurement unit. However, the measurement units with the locking angle pattern division can only be at the edge (edge) area of the wafer, and the process variation on the wafer level (WAFER LEVEL) can not be monitored, which may result in large device performance variation between the center and the edge of the wafer.
Disclosure of Invention
The application aims to solve the technical problems that the online measurement range of a large-size spliced product is small, and the process difference on the wafer level can not be monitored.
In order to solve the above technical problems, the present application provides a photomask for a large-sized splice product, comprising: at least two exposure unit areas having different functions but the same size; the four corners of each exposure unit area are provided with locking angle patterns which are mirror symmetry, and the locking angle patterns are positioned in the chip area of the exposure unit area; when the photomask is adopted to carry out a splicing photoetching process on a wafer, the locking angle patterns are spliced on the wafer to form a cross mark, and the cross mark divides the whole chip area of the wafer into a plurality of measuring units with the same size, wherein each measuring unit corresponds to one exposure unit area.
In some embodiments of the application, the exposure unit area is square.
In some embodiments of the application, the locking angle pattern is a quarter pattern of the cross logo.
In some embodiments of the application, the locking angle pattern has dimensions of 30×30 μm 2～45×45μm2.
In some embodiments of the application, the cross-shaped logo has dimensions of 60 x 60 μm 2～90×90μm2.
The application also provides a method for online measurement and positioning, which comprises the following steps: forming a cross mark on the wafer through a splicing photoetching process by using the photomask of the large-size spliced product; forming a wafer measurement unit diagram on the wafer through the cross mark; and positioning according to the coordinates of the point to be measured by taking the geometric center of the cross mark of any one exposure unit area in the wafer measurement unit diagram as the origin of coordinates.
In some embodiments of the present application, a method of forming a wafer measurement cell map includes: two cross marks at diagonal positions are arbitrarily selected on the wafer, and a measuring unit is framed; and generating a wafer measurement unit diagram according to the repeated units of the measurement unit.
In some embodiments of the present application, the method of forming a wafer measurement cell map further comprises: and checking the wafer measurement unit diagram, and judging whether the check is successful or not according to whether a group of two cross marks positioned at the diagonal positions can be found in the edge area of the wafer.
In some embodiments of the present application, if at least one set of two cross marks located at diagonal positions is found in the edge area of the wafer, the verification of the wafer measurement cell map is determined to be successful.
In some embodiments of the present application, if a set of two cross marks located at diagonal positions are not found in the edge region of the wafer, it is determined that the wafer measurement cell map is not verified successfully.
Compared with the prior art, the photomask of the large-size spliced product and the on-line measuring and positioning method have the following beneficial effects:
The photomask of the large-size spliced product is formed by splicing the wafers to form a cross mark by enabling the sizes of the exposure unit areas to be identical and arranging mirror symmetry locking angle patterns on the four corners of each exposure unit area, so that the cross mark divides the whole chip area of the wafers into a plurality of measuring units with the same size when the photomask is subjected to splicing photoetching technology on the wafers, the measuring units completely meet the detection requirement of a measuring machine, the limitation that the measuring range of the prior art is small and the measuring area can only be positioned at the edges of the wafers is broken, and further, the process difference on the wafer level can be monitored.
Drawings
The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals refer to like structure throughout the several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and that the drawings are for illustration and description only and are not intended to limit the scope of the application, as other embodiments may equally well accomplish the inventive intent in this disclosure. It should be understood that the drawings are not to scale. Wherein:
FIG. 1 is a schematic diagram of an exposure area formed by repeatedly exposing a large-sized splice product of the prior art to light through an exposure unit area;
FIG. 2 is a schematic diagram of the prior art for solving the problem of online measurement of large-size splice products;
FIG. 3 is a schematic diagram of a photomask of a large-sized splice product according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a structure of a reticle according to an embodiment of the present application after performing a photolithography process on a wafer to form a cross mark;
FIG. 5 is a schematic diagram of a wafer measurement cell according to an embodiment of the present application.
Detailed Description
The following description provides specific applications and requirements of the application to enable any person skilled in the art to make and use the application. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
Referring to fig. 1, the prior art divides a photomask of a large-sized splice product into different exposure unit areas, for example, an exposure unit area a, an exposure unit area B, an exposure unit area C, an exposure unit area D, according to functions and requirements, and sets a locking angle pattern at a position where cut lines cross. During measurement, an exposure area is defined on the wafer surface according to the position of the locking angle pattern, as shown by the thick line frame in fig. 1. However, the size of the exposure area exceeds the upper limit of the dimension of the measuring machine, so that online measurement cannot be realized.
As shown in fig. 2, in order to solve the problem of online measurement of large-size spliced products, special graphic design is performed on a part of the die area of a wafer, an exposure unit area (i.e., an image area) with a locking angle pattern is repeatedly exposed to form a measurement unit 1, the measurement unit 1 can only be located in a measurable area 2, and the measurable area 2 is only located in an edge area of the wafer, so that the method cannot monitor the difference between the device performances in the middle and the edge of the wafer, and cannot monitor the device uniformity (uniformity) on the wafer level.
In view of the problems that the prior art has a small measurement range and cannot characterize the device performance difference between the middle and the edge of a wafer when carrying out online measurement of a large-size spliced product, the technical scheme of the application provides the photomask of the large-size spliced product.
Referring to fig. 3, a photomask for a large-sized splice product according to an embodiment of the present application includes: the size of the exposure unit areas is identical, and the distribution mode of the exposure unit areas can be determined according to actual conditions. The embodiment of the application is illustrated by taking four symmetrically distributed exposure unit areas as an example. When the splicing photoetching process is carried out, repeated exposure is generally carried out on the exposure unit area with the main function for a plurality of times, and finally, a complete device can be spliced. As an example, the mask of the large-sized stitching product may include an exposure unit area a, an exposure unit area B, an exposure unit area C, and an exposure unit area D having the same size. The dicing lines SL are selectively designed in the exposure unit area according to actual needs, for example, dicing lines are provided in the exposure unit area a, the exposure unit area C, and the exposure unit area D. The exposure unit area can be square, and the regular shape is favorable for splicing multiple repeated exposure to form a complete device.
And a locking angle pattern I is arranged in each exposure unit area, and the locking angle patterns I are positioned on four corners of the exposure unit area and are distributed in a mirror symmetry mode. When the exposure unit regions are spliced, a cross mark can be formed at four corners of each exposure unit region. The locking angle pattern may be a quarter pattern of the cross mark, that is, a quarter pattern of the cross mark is disposed at four corners of each exposure unit area, so that the four exposure unit areas are spliced into a complete cross mark during splicing.
The size of the locking angle pattern is in a reasonable range, and a cross mark formed by the locking angle pattern with a large size is sufficiently striking and convenient to identify. But as the size of the locking angle pattern increases, this means that more wafer real estate is wasted. Therefore, in the embodiment of the application, the locking angle pattern has a size of 30×30 μm 2～45×45μm2, and the size of the cross mark formed by splicing the locking angle pattern on the wafer is 60×60 μm 2～90×90μm2.
The space between the locking angle pattern and other patterns of the exposure unit area is preferably not smaller than 50 μm, so that interference of other patterns in subsequent positioning is avoided.
At present, the locking angle pattern is mostly arranged on the cutting path, and in the wafer on-line monitoring process, the complete device is divided into one measuring unit, but the size of the wafer device spliced into a larger size exceeds the maximum limit of the measuring machine. In the embodiment of the application, the locking angle pattern is arranged in the chip area of the exposure unit area, and each exposure unit area can be used as an independent measurement unit in the wafer online measurement process, so that online multipoint measurement can be realized, and the process can be accurately controlled.
Referring to fig. 4, when the photomask according to the embodiment of the present application is used to perform a stitching lithography process on a wafer, the locking angle pattern is stitched on the wafer to form a cross mark M. The cross mark M divides the whole chip area of the wafer into a plurality of measuring units E with equal size, and each measuring unit E corresponds to one exposure unit area. Therefore, the mask can expand the measurement range from the edge area of the wafer to the whole chip area of the wafer, and the problem that the measurement unit can only be located in the edge area of the wafer (refer to fig. 2) in the prior art can not represent the process variation on the whole wafer level is solved.
In summary, the photomask of the large-size spliced product designed by the embodiment of the application can enable the measuring units to be distributed in the whole chip area of the wafer when the splicing photoetching process is carried out, so that not only the device performance in the middle of the wafer can be monitored, but also the device performance at the edge of the wafer can be monitored, and the problems that the detection range is small and the process variation on the whole wafer level cannot be represented when parameters such as CD/THK/OVL and the like are detected on line in the production process of the large-size spliced product are well solved.
In addition, the embodiment of the application also provides a method for online measurement and positioning, which comprises the following steps:
Step S1: forming a cross mark on the wafer through a splicing photoetching process by using the photomask of the large-size splicing product;
Step S2: forming a wafer measurement unit diagram on the wafer through the cross mark;
step S3: and positioning according to the coordinates of the position to be measured by taking the geometric center of the cross mark of any one exposure unit area in the wafer measurement unit diagram as the origin of coordinates.
In step S1, the main functional area on the photomask of the large-size spliced product is repeatedly exposed for multiple times by adopting a conventional splicing lithography method, and finally a complete device is spliced, specifically, the splicing method is not required, and depends on the requirements of different spliced products. Because the locking angle patterns are arranged at the four corners of each exposure unit area on the photomask, the four corners of the spliced exposure unit areas are spliced to form the cross mark.
Referring to fig. 5, a method for forming a wafer measurement cell map on the wafer W using the cross mark may include: two cross marks at diagonal positions are arbitrarily selected on the wafer W, and a measurement unit E1 is framed. And then generating a wafer measurement unit diagram according to the repeated units of the measurement unit E1. And then, checking the wafer measurement unit diagram, and judging whether the checking is successful according to whether a group of two cross marks positioned at the diagonal positions can be found in the edge area of the wafer W. In fact, the four corners of each square in fig. 5 have cross marks, only two cross marks arbitrarily selected for the frame quantification unit E1 and two cross marks found for verification are shown in the figure.
And in the verification process, if at least one group of two cross marks positioned at the diagonal positions are found in the edge area of the wafer W, judging that the verification of the wafer measurement unit diagram is successful. If a group of two cross marks at the diagonal positions are not found in the edge area of the wafer W, judging that the wafer measuring unit diagram is not verified successfully. As shown in fig. 5, a set of two cross marks at diagonal positions are found at the edge positions of the wafer W, so that the wafer measurement cell map is successfully verified.
After the wafer measurement unit diagram is formed, the geometric center of the cross mark of any one exposure unit area in the wafer measurement unit diagram can be taken as the origin of coordinates O. Since each measurement cell corresponds to one of the exposure cell areas, each square in fig. 5 represents both one exposure cell area and one measurement cell E1. That is, the geometric center of the cross mark of any square in the wafer measurement unit diagram can be used as the origin O of coordinates. And then, according to the known coordinates of the to-be-measured point, positioning the to-be-measured point. In the wafer measurement unit diagram, each measurement unit E1 is independent from each other, and each measurement unit E1 has a respective coordinate system for positioning a respective measurement point to be measured.
After the measuring point to be measured is successfully positioned, the performance of the measuring point to be measured can be detected, for example, the process parameters such as the critical dimension, the interlayer alignment, the film thickness and the like of the measuring point to be measured are detected on line in real time. Because the measuring unit E1 of the embodiment of the application extends over the whole chip area of the wafer, the monitoring of the process difference on the wafer level can be realized, and the uniformity of devices on the wafer level is improved.
After reading this disclosure, those skilled in the art will appreciate that the foregoing application may be presented by way of example only and may not be limiting. Although not explicitly described herein, those skilled in the art will appreciate that the present application is intended to embrace a variety of reasonable alterations, improvements and modifications to the embodiments. Such alterations, improvements, and modifications are intended to be within the spirit and scope of the exemplary embodiments of the application.
It should be understood that the term "and/or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means without intermediate elements. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element in some embodiments could be termed a second element in other embodiments without departing from the teachings of the present application. Like reference numerals or like reference numerals designate like elements throughout the specification.
Furthermore, the present description describes example embodiments with reference to idealized example cross-sectional and/or plan and/or perspective views. Thus, differences from the illustrated shapes, due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.
Claims (11)
1. A photomask for large-size splice products, comprising:
at least two exposure unit areas having different functions but the same size;
The four corners of each exposure unit area are provided with locking angle patterns which are mirror symmetry, and the locking angle patterns are positioned in the chip area of the exposure unit area;
When the photomask is adopted to carry out a splicing photoetching process on a wafer, the locking angle patterns are spliced on the wafer to form a cross mark, and the cross mark divides the whole chip area of the wafer into a plurality of measuring units with the same size, wherein each measuring unit corresponds to one exposure unit area.
2. The large splice product photomask of claim 1, wherein the exposure unit area is square.
3. The large splice product photomask of claim 1, wherein the locking angle pattern is a quarter pattern of the cross mark.
4. The large splice product photomask of claim 1, wherein the locking angle pattern has dimensions of 30 x 30 μm 2～45×45μm2.
5. The large splice product photomask of claim 1, wherein the cross mark has a dimension of 60 x 60 μm 2～90×90μm2.
6. The large-sized splice product photomask according to claim 1, wherein the lock angle pattern is spaced from other patterns by not less than 50 μm in the exposure unit region.
7. A method for online measurement and positioning, comprising:
Forming a cross mark on a wafer through a splicing photoetching process by using the photomask of the large-size spliced product as claimed in any one of claims 1 to 6;
forming a wafer measurement unit diagram on the wafer through the cross mark;
And positioning according to the coordinates of the point to be measured by taking the geometric center of the cross mark of any one exposure unit area in the wafer measurement unit diagram as the origin of coordinates.
8. The method of claim 7, wherein the forming a wafer measurement cell map comprises:
Two cross marks at diagonal positions are arbitrarily selected on the wafer, and a measuring unit is framed;
and generating a wafer measurement unit diagram according to the repeated units of the measurement unit.
9. The method of claim 8, wherein the forming a wafer metrology cell map further comprises: and checking the wafer measurement unit diagram, and judging whether the check is successful or not according to whether a group of two cross marks positioned at the diagonal positions can be found in the edge area of the wafer.
10. The method of claim 9, wherein if at least one set of two cross marks at diagonal positions is found in an edge region of the wafer, determining that the verification of the wafer measurement cell map is successful.
11. The method of claim 9, wherein if a set of two cross marks at diagonal positions is not found in the edge region of the wafer, determining that the wafer measurement cell map is not verified successfully.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211306560.0A CN117970740A (en) | 2022-10-24 | 2022-10-24 | Photomask of large-size spliced product and on-line measuring and positioning method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211306560.0A CN117970740A (en) | 2022-10-24 | 2022-10-24 | Photomask of large-size spliced product and on-line measuring and positioning method |
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| CN117970740A true CN117970740A (en) | 2024-05-03 |
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| CN202211306560.0A Pending CN117970740A (en) | 2022-10-24 | 2022-10-24 | Photomask of large-size spliced product and on-line measuring and positioning method |
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| CN (1) | CN117970740A (en) |
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- 2022-10-24 CN CN202211306560.0A patent/CN117970740A/en active Pending
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