CN117970169B

CN117970169B - Power supply short circuit detection circuit and detection method

Info

Publication number: CN117970169B
Application number: CN202410374196.4A
Authority: CN
Inventors: 张松涛
Original assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Current assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Priority date: 2024-03-29
Filing date: 2024-03-29
Publication date: 2024-06-21
Anticipated expiration: 2044-03-29
Also published as: CN117970169A

Abstract

The invention discloses a power supply short circuit detection circuit and a detection method, wherein the circuit comprises a processing chip, a charging circuit module, an output loop module and a comparison circuit, wherein the output loop module is connected between the charging circuit module and the comparison circuit, and the output loop module is also connected with the processing chip; the output loop module comprises N control loops, each control loop comprises a signal input end, a switching tube and a connecting end, the processing chip is used for starting any one of the N control loops as a target control loop to perform power short circuit detection, the comparison circuit is used for receiving the output voltage of the target control loop, comparing the output voltage with a reference voltage and outputting a high-level or low-level comparison result to the processing chip; the processing chip is used for receiving the comparison result output by the comparison circuit and determining whether the target control loop has a power supply short circuit fault according to the comparison result.

Description

Power supply short circuit detection circuit and detection method

Technical Field

The invention relates to the technical field of electronic circuits, in particular to a power supply short circuit detection circuit and a detection method.

Background

With the increasing number of large data centers, the number of servers contained in the data centers is increased, and accordingly, the probability of server failure is increased, so that the failure detection and maintenance of the servers become an important work task. When a server is started up abnormally, the abnormal operation may be caused by various reasons, and one of the reasons may be that a short circuit problem occurs in the server. The detection method is that whether the short circuit occurs in the server is checked by a field disassembly method, but engineers are required to arrive at the field operation, and the efficiency and the cost of the method for checking whether the short circuit occurs are low by adopting the field disassembly method under the condition that a large number of servers with widely distributed data centers and possibly short circuit faults are unknown in advance.

In addition, another detection method is to use remote power-up processing for the server, which may cause burning out of a short circuit area, and aggravate the short circuit to damage internal circuits of the server.

Disclosure of Invention

In view of the above, the present invention provides a power short circuit detection circuit and a detection method for remotely detecting whether a short circuit occurs in a power circuit inside a server, so as to prevent a maintenance engineer from arriving at a site for disassembly inspection.

In a first aspect, the present invention provides a power short circuit detection circuit, the circuit comprising: the device comprises a processing chip, a charging circuit module, an output loop module and a comparison circuit;

The output loop module is connected between the charging circuit module and the comparison circuit, and is also connected with at least one signal output end of the processing chip;

The output loop module comprises N control loops, each control loop comprises a signal input end, a switching tube and a connecting end, wherein each signal input end is connected with one signal output end of the processing chip and used for receiving one path of control signals output by the processing chip, each connecting end is used for being connected with one power supply loop in the server, the switching tube is arranged between the signal input end and the connecting end and used for controlling the control loop where the switching tube is positioned to be connected or disconnected, and N is more than or equal to 1 and is a positive integer;

The processing chip is used for starting any one of the N control loops, performing power short circuit detection as a target control loop, and controlling other control loops except the target control loop to be in a closed state, wherein the target control loop is powered through the charging circuit module after being started;

The comparison circuit is used for receiving the output voltage of the target control loop, comparing the output voltage with a reference voltage and outputting a high-level or low-level comparison result to the processing chip;

And the processing chip is used for receiving the comparison result output by the comparison circuit and determining whether the power supply short circuit fault occurs in the target control loop according to the comparison result.

The power supply short circuit detection circuit comprises an output loop module, wherein the output loop module comprises N control loops which can be used for connecting a plurality of power supply loops inside a server, one of the N control loops is conducted through a detection enabling signal of a processing chip and any one of the N control loops, short circuit detection of the power supply loop of the server connected with the control loop is started, and an output voltage acquired through a comparison circuit is compared with a reference voltage to obtain a comparison result of high-level or low-level signals, so that short circuit detection of the power supply loop is realized remotely, detection efficiency is improved, and labor cost is saved.

In addition, the detection circuit is used for detecting the short circuit in the server by remotely controlling the output loop module to be started before the server is powered on or when the server cannot be started, so that whether the power loop is short-circuited or not is timely found, whether the maintenance engineer breaks down or not through on-site disassembly detection is avoided, and damage to the inside of the server caused by secondary startup after the short circuit is avoided.

With reference to the first aspect, in one possible implementation manner, the comparing circuit is specifically configured to: when the output voltage is larger than or equal to the reference voltage, outputting a high-level signal to the processing chip; and when the output voltage is smaller than the reference voltage, outputting a low-level signal to the processing chip.

With reference to the first aspect, in another possible implementation manner, the processing chip is specifically configured to: when receiving the high-level signal output by the comparison circuit, determining that the target control loop has no power short-circuit fault; and when receiving the low-level signal output by the comparison circuit, determining that the target control loop has a power short circuit fault. According to the embodiment, short circuit detection of a certain power supply loop in the server is achieved through the comparison circuit, a maintenance engineer is prevented from arriving at the site to disassemble the machine for detection, the detection efficiency is improved, and the labor cost is saved.

With reference to the first aspect, in still another possible implementation manner, the switch tube of each control loop is a MOS tube, a g pole of the MOS tube is connected to the signal input end, a d pole of the MOS tube is connected to the power output end of the charging circuit module, and an s pole of the MOS tube is connected to the connection end;

When the processing chip inputs low-level signals to N signal input ends of the N control loops, the MOS tube of each control loop is disconnected, and each control loop is in a closed state;

when the processing chip outputs a high-level signal to one of the N signal input ends, the MOS tube connected with the signal input end is conducted, a control loop where the conducted MOS tube is located is started, the output loop module supplies power to the control loop, and the comparison circuit starts to collect the output voltage of the control loop.

In this embodiment, by setting the MOS transistor in the control loop, short circuit detection of any loop designated access control loop of the N control loops is achieved, and after all the N control loops are polled and detected, detection operation of the power supply loop inside the server is completed.

With reference to the first aspect, in a further possible implementation manner, the charging circuit module is connected to a dc power source;

The charging circuit module includes: the MOS transistor Q100, the MOS transistor Q101, the triode Q102, the triode Q103, the operational amplifier U1 and a plurality of resistors, wherein the triode Q102 and the triode Q103 form a mirror current source;

The g pole of the MOS tube Q100 is connected with a detection enabling signal, the d pole of the MOS tube Q100 is connected with the non-inverting input end of the operational amplifier U1, and the s pole of the MOS tube Q100 is connected with the ground;

the non-inverting input end of the operational amplifier U1 is also connected with a first resistor R1 and a second resistor R2, the inverting input end of the operational amplifier U1 is grounded through a third resistor R3, and the output end of the operational amplifier U1 is connected with the g pole of the MOS tube Q101; and the d pole of the MOS transistor Q101 outputs current to the output loop through the mirror current source.

With reference to the first aspect, in a further possible implementation manner, the detection enable signal is controlled by the processing chip to output a high level or a low level; the charging circuit module is specifically configured to:

when the detection enabling signal outputs high level, the MOS tube Q100 is closed, low level is output to the non-inverting input end of the operational amplifier U1, and the charging circuit module stops supplying power to the output loop module;

When the detection enabling signal outputs a low level, the MOS transistor Q100 is disconnected, a first voltage V1 is output to the non-inverting input end of the operational amplifier U1, the output end of the operational amplifier U1 outputs a high level to the MOS transistor Q101, the s pole of the MOS transistor Q101 outputs a first current I1 on a third resistor R3, the d pole of the MOS transistor Q101 is connected with a triode Q102 and a triode Q103 of the mirror current source, and the charging circuit module outputs a second current I2 to the output loop module through the mirror current source.

With reference to the first aspect, in a further possible implementation manner, the first voltage V1 is determined by a first relational expression, where the first relational expression is:

Wherein V ₁ is the first voltage, The DC power supply outputs voltage, R1 is a first resistor, and R2 is a second resistor.

Further, the first current I1 is determined by a second relational expression, where the second relational expression is:

Wherein I ₁ is a first current I1, and R3 is a third resistor.

With reference to the first aspect, in a further possible implementation manner, the charging circuit module further includes: a fourth resistor R4 and a fifth resistor R5, wherein the fourth resistor R4 is connected between the dc power supply and the transistor Q102, and the fifth resistor R5 is connected between the dc power supply and the transistor Q103;

The direct current power supply outputs a third current I3 through the fourth resistor R4, and the direct current power supply outputs a fourth current I4 through the fifth resistor R5.

With reference to the first aspect, in a further possible implementation manner, if r4=r5, i3=i4; when the s pole of the MOS transistor Q101 outputs a first current I1 on the third resistor R3, and the mirror current source outputs a second current I2 to the output loop module, the i1=i3, the i2=i4, and the i2=i1.

With reference to the first aspect, in a further possible implementation manner, the comparing circuit includes an operational amplifier U2, a sixth resistor R6 and a seventh resistor R7, where the sixth resistor R6 and the seventh resistor R7 are voltage dividing resistors;

The non-inverting input end of the operational amplifier U2 is connected with the voltage output end of any control loop of the output loop module and is used for collecting the output voltage of any control loop;

The inverting input end of the operational amplifier U2 is grounded through the seventh resistor R7;

the output end of the operational amplifier U2 is connected with the processing chip and is used for outputting a comparison result to the processing chip.

With reference to the first aspect, in a further possible implementation manner, the server includes N power supply loops inside, and each power supply loop is equivalent to a parallel circuit composed of one total capacitor CL and one load resistor RL;

the capacitor CL is used for charging and storing energy, and the load resistor RL is used for shunting.

With reference to the first aspect, in a further possible implementation manner, the processing chip is specifically configured to:

The 1 st to N th power supply loops are controlled to input high-level signals one by one, the detection enabling signals are controlled to take effect, and the charging circuit module is started to supply power to the x-th power supply loop, wherein x is more than or equal to 1 and less than or equal to N;

Calculating the time T (x) for the voltage of the xth power supply loop to climb to a set detection threshold according to the current value output by the charging circuit module and the total capacitance value of the xth power supply loop;

when the time T (x) reaches a preset duration, if a high-level signal output by the comparison circuit is received, determining that the power supply short-circuit fault of the xth power supply loop does not occur; and if the low-level signal is received, determining that the x power supply loop has a short circuit fault.

With reference to the first aspect, in another possible implementation manner, the comparing circuit is further configured to collect, after a delay period T2, an output voltage corresponding to the xth power supply loop when the charging circuit module is started to supply power to the xth power supply loop, where T2 > 2·t1, and T1 is a charging time of the capacitor CL of the xth power supply loop.

With reference to the first aspect, in a further possible implementation manner, when the charging circuit module is started to supply power to the x-th power supply loop, a charging voltage of the power supply is greater than the reference voltage.

Optionally, the processing chip is a complex programmable logic chip CPLD.

In a second aspect, the present invention further provides a power short-circuit detection method, where the method is applied to the power short-circuit detection circuit described in the first aspect, and the method includes:

When an output loop module in the power short circuit detection circuit is connected with N power loops in the server, the processing chip controls the 1 st to N power loops one by one to input high-level signals, controls detection enabling signals in the charging circuit module to take effect, and starts the charging circuit module to supply power to the x power loop, wherein x is more than or equal to 1 and less than or equal to N;

Calculating the time required for the voltage of the xth power supply loop to climb to a set detection threshold according to the current value output by the charging circuit module and the total capacitance value of the xth power supply loop;

And when the time reaches the preset duration, if the processing chip receives the high-level signal output by the comparison circuit, determining that the power short circuit fault does not occur in the x-th power supply loop.

Further, the method further comprises: and if the processing chip receives the low-level signal output by the comparison circuit, determining that the x-th power supply loop has short circuit fault.

According to the method provided by the aspect, the processing chip controls any one of the N control loops to be conducted, short circuit detection of a power loop of a server connected with the control loop is started, output voltage acquired by the comparison circuit is compared with reference voltage, and remote short circuit detection of the power loop is realized, so that whether the power loop is short-circuited or not is remotely controlled and found before the server is powered on or when the server cannot be started, whether the maintenance engineer breaks down on site to detect whether faults occur or not is avoided, and damage to the inside of the server caused by secondary startup after the short circuit is avoided.

In a third aspect, the present invention provides a computer device comprising: the power short circuit detection method according to the second aspect or any one of the corresponding embodiments of the second aspect is implemented by the processor and the memory, the memory and the processor are in communication connection with each other, and the memory stores computer instructions.

Further, the present invention provides a computer-readable storage medium having stored thereon computer instructions for causing a computer to execute the power short circuit detection method according to the second aspect or any one of the embodiments corresponding thereto.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

Fig. 1 is a circuit diagram of a power supply short-circuit detection circuit provided by an embodiment of the invention;

fig. 2 is a schematic diagram of a power supply short circuit detection circuit according to an embodiment of the present invention;

FIG. 3 is a circuit diagram of another power supply short circuit detection circuit according to an embodiment of the present invention;

FIG. 4 is a partial circuit diagram of an output circuit according to an embodiment of the present invention;

fig. 5 is an equivalent circuit diagram of a power supply circuit according to an embodiment of the present invention;

FIG. 6 is a flowchart of a power short circuit detection method according to an embodiment of the present invention;

FIG. 7 is a flow chart of a short circuit detection provided by an embodiment of the present invention;

fig. 8 is a schematic hardware structure of a computer device according to an embodiment of the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The technical scheme of the invention can be applied to the technical field of electronic circuits, and mainly relates to detection of whether short circuit occurs in an internal power supply loop of network equipment such as a server.

Specifically, in the case of abnormal starting of the server, there is a certain probability that a short circuit problem occurs in the service, for example, short circuit phenomenon may be caused by the situations of failure of certain parts, failure of elements, falling of cables or mechanism parts, aging of the interior of the PCB, etc. When various short circuits occur, the server may not be able to obtain a log of the related errors, and thus the maintenance engineer may not be able to remotely obtain the abnormal information of the server.

When the first power-on failure of the server occurs, the maintenance engineer will first check whether the server log has relevant error reporting information, and if so, repair processing will be performed according to the error reporting information prompt.

If no related error information occurs, a general maintenance engineer will try to power up the server once again, and if the server is still unable to power up normally for the second time, the maintenance engineer will check whether the server is abnormal or not on site. The inspection sequence is generally that firstly, whether the appearance of the server is abnormal or not is inspected, and then, the case is opened to inspect whether the cable falls off, obvious elements or parts are damaged or not.

In the process of remote detection on the server in the secondary power-on process, the burning phenomenon of a short circuit area can be caused, and damage caused by the short circuit problem is aggravated. If the maintenance engineer arrives at the site to perform fault inspection, the server needs to be unpacked for inspection to see the inside of the server, and whether the power supply circuits are short-circuited or not needs to be inspected one by one.

Based on the analysis, the embodiment of the invention provides a power supply short circuit detection circuit which is used for remotely detecting whether the short circuit occurs in the server or not and can also specifically judge which power supply loop is short-circuited, so that the detection efficiency is improved, and the labor cost is reduced.

The power short-circuit detection circuit provided in this embodiment is described in detail below.

Referring to fig. 1, a power supply short circuit detection circuit provided in an embodiment of the present invention includes: the device comprises a processing chip, a charging circuit module, an output loop module and a comparison circuit.

The output loop module is connected between the charging circuit module and the comparison circuit, and is also connected with at least one signal output end of the processing chip. Each signal output is connected to one signal input of the output loop module.

The output loop module comprises N control loops, each control loop comprises a signal input end, a switching tube and a connecting end, wherein each signal input end is connected with one signal output end of the processing chip and used for receiving one path of control signals output by the processing chip, each connecting end is used for being connected with one power supply loop inside the server, the switching tube is arranged between the signal input end and the connecting end and used for controlling the control loop where the switching tube is located to be connected or disconnected, and N is more than or equal to 1 and is a positive integer.

The processing chip is used for starting any one of the N control loops, performing power short circuit detection as a target control loop, and controlling other control loops except the target control loop to be in a closed state, wherein the target control loop is powered through the charging circuit module after being started.

And the comparison circuit is used for receiving the output voltage of the target control loop, comparing the output voltage with the reference voltage and outputting a high-level or low-level comparison result to the processing chip.

The comparison circuit is specifically used for outputting a high-level signal to the processing chip when comparing the output voltage with the reference voltage or more; and when the output voltage is smaller than the reference voltage, outputting a low-level signal to the processing chip.

Further, the processing chip is specifically configured to determine that a power supply short-circuit fault does not occur in the target control loop when receiving the high-level signal output by the comparison circuit; when receiving the low level signal output by the comparison circuit, determining that the target control loop has a power short circuit fault.

Optionally, the processing chip is a complex programmable logic chip (Complex Programmable Logic Device, CPLD).

In this embodiment, CPLD control is adopted, a charging circuit module, an output circuit module and a comparison circuit are designed, the CPLD controls the output circuit module to select any output circuit, the charging circuit module is controlled to charge the selected output circuit, the comparison result of the relevant voltage is detected through the comparison module, for example, a high-level signal or a low-level signal is output to the CPLD, finally, the CPLD judges whether a short circuit fault occurs according to the comparison result, and the CPLD records an abnormal log and reports the abnormal log to the system.

Further, as shown in fig. 2, the functions and roles of the modules are as follows:

Processing chips, such as CPLD: the circuit is used for controlling the charging circuit module to work, controlling the output circuit module to select a designated circuit, keeping other unselected circuits in a closed state, recording the comparison result of the comparison circuit, and judging whether the power circuit where the designated circuit is positioned has a short circuit fault or not according to the comparison result.

And the charging circuit module is as follows: the charging circuit module starts to work to charge the output loop module with small current after the control enabling signal of the processing chip is valid, and the charging circuit module is equivalent to a constant current source.

And an output loop module: all power supply loops which need to be detected in the server or on the board are connected through the output loops 1-n, each loop can be controlled through the MOS switch, the CPLD can control that only one output power supply loop is connected to the main loop of the detection circuit at the same time, and other output power supply loops are in a closed state.

Comparison circuit, also called short circuit comparison circuit: the circuit is used for collecting the output voltage of the output circuit, comparing the output voltage with the reference voltage, and outputting a high-level signal to the CPLD when the output voltage is detected to be higher than the reference voltage, wherein the high-level signal is used for indicating that the circuit is normal and no short circuit occurs. When the low-level signal CPLD is output, the circuit is indicated to have short circuit, the detection voltage can keep low voltage/low level and can not climb to be higher than the reference voltage, the output short circuit detection result always keeps low level, the current power supply circuit is indicated to have short circuit, and the short circuit is fed back to the CPLD for recording.

In addition, the processing chip is also used for recording information, when the high-level or low-level signal output by the comparison circuit determines that the power circuit connected with a certain output loop is short-circuited, the processing chip can record the x value of the current detection loop and generate a short-circuit log, and the short-circuit log is reported to the system so as to be convenient for maintenance engineers to check. When the server cannot be started, a maintenance engineer can remotely control the processing chip, send an instruction to execute a related short circuit checking flow, and realize fault detection of all power supply loops in the server.

In one possible implementation, as shown in fig. 3 and 4, in the detection circuit, the output loop module includes 1 to n control loops, corresponding to 1 to n power supply loops. Specifically, the switching tube in each control loop is a MOS tube, for example, N control loops, including N MOS tubes, Q1, Q2, qn. And the MOS transistors are all N-channel MOS transistors.

Further, the g pole (gate) of each MOS tube is connected to the signal input end, and is configured to receive a control signal output from the processing chip, the d pole (drain) of each MOS tube is connected to the power output end of the charging circuit module, and the s pole (source) of each MOS tube is connected to the connection end.

As shown in fig. 4, the g pole of the MOS transistor Q1 is connected to the control signal 1, the d pole is connected to the node 106 corresponding to the power output end, the s pole is connected to the loop 1, and the pin of the loop 1 is the connection end of the first control loop, and is used for connecting to the power loop 1 inside the server. And a first control loop is formed by a control signal input end 1-a connecting end (loop 1) of the MOS tube Q1. Similarly, the second control loop is formed by the control signal input end 2-MOS tube Q2-connecting end (loop 2), and the nth control loop is formed by the control signal input end N-MOS tube Qn-connecting end (loop N).

Specifically, in the detection circuit provided in this embodiment, during design, N power supply loops to be detected on the motherboard are selected, each power supply loop is connected to the detection loop through a MOS tube connected in series, for example, a MOS tube Q1 connected in series on a power supply loop 1 is connected to a node 106, the g pole of the MOS tube is controlled by a "control signal 1" output by the CPLD, when the CPLD outputs a high level to the control signal 1, the MOS tube Q1 is turned on, the loop 1 is connected to the access node 106, and the MOS tube Q1 plays a role of a switch. The 2 nd and 3 … … n loops are connected to the check loop node 106 according to the same method, the CPLD only outputs a high-level signal to one of the control signals 1-n at a time according to the set sequence, and other control signals are kept to be pulled down to ensure the output of low level, so that only one of the MOS transistors Q1 and Q2 … … Qn is in an on state at a time, and other MOS transistors are in an off state.

Under the open state, the MOS tube is conducted, the control loop where the MOS tube is located is connected to the detection loop, and the comparison circuit collects and compares the output voltage on the control loop.

In this embodiment, an output loop module is provided, including N control loops, through CPLD to the control signal of each way, select to carry out short circuit detection to a certain power loop in the server, connect the main loop by the MOS pipe of establishing ties for CPLD inserts the function of detecting the main loop with a certain loop according to the rule, thereby realize the remote detection to the power loop in the server.

Optionally, in some embodiments, the charging circuit module is further connected to a dc power supply.

As shown in fig. 3, the charging circuit module includes: MOS pipe Q100, MOS pipe Q101, triode Q102, triode Q103, operational amplifier U1 and a plurality of resistance, wherein, triode Q102 with triode Q103 constitutes the mirror image current source.

The g pole of the MOS tube Q100 is connected with a detection enabling signal, the d pole of the MOS tube Q100 is connected with the non-inverting input end of the operational amplifier U1, and the s pole of the MOS tube Q100 is connected with the ground. The non-inverting input end of the operational amplifier U1 is also connected with the first resistor R1 and the second resistor R2, the inverting input end of the operational amplifier U1 is grounded through the third resistor R3, and the output end of the operational amplifier U1 is connected with the g pole of the MOS tube Q101; and the d pole of the MOS transistor Q101 outputs current to the output loop through the mirror current source.

Further, the detection enabling signal is controlled by the processing chip to output a high level or a low level; the charging circuit module is specifically configured to close the MOS transistor Q100 when the detection enable signal outputs a high level, output a low level to the non-inverting input terminal of the operational amplifier U1, and stop supplying power to the output circuit module.

When the detection enabling signal outputs a low level, the MOS transistor Q100 is disconnected, a first voltage V1 is output to the non-inverting input end of the operational amplifier U1, the output end of the operational amplifier U1 outputs a high level to the MOS transistor Q101, the s pole of the MOS transistor Q101 outputs a first current I1 on a third resistor R3, the d pole of the MOS transistor Q101 is conducted to the triode Q102 and the triode Q103 of the mirror current source, and the charging circuit module outputs a second current I2 to the output circuit module through the mirror current source.

Specifically, as shown in fig. 3, the node 200 is an input power source of the motherboard, and is typically a 12V dc power source. Node 101 is the input control terminal of the modular section, which is enabled when sense enable_n is low. The detection enable output high/low level is controlled by the CPLD. When node 101 is high, Q100 is on and node 102 is pulled low, at which point the charging circuit module is not supplying power.

When the sense enable_N is low, i.e. node 101 is low, Q100 is off, the voltage at node 102 is divided by R1 and R2, node voltageThe first voltage V1 can be calculated by the relation (1). The first relation is:

（1）。

At this time, the resistance of the node 103 to ground is R3, the constant current of the charging circuit module outputs a first current I1, the first current I1 is determined by the voltage of the node 102 and the resistance value of R3, and further, the first current I1 is determined by a second relational expression, where the second relational expression is:

（2）。

Wherein I ₁ is a first current I1, and R3 is a third resistor.

In this embodiment, the values of R1, R3 and R3 may be adjusted to determine the magnitude of the first current I1 according to the requirement of the load resistor, and the setting of the first current I1 may affect the parameters such as the detected current and the detected time.

Further, the charging circuit module further includes: a fourth resistor R4 and a fifth resistor R5, wherein the fourth resistor R4 is connected between the dc power supply and the transistor Q102, and the fifth resistor R5 is connected between the dc power supply and the transistor Q103. The direct current power supply outputs a third current I3 through a fourth resistor R4, and the direct current power supply outputs a fourth current I4 through a fifth resistor R5.

If r4=r5, i3=i4; when the s pole of the MOS transistor Q101 outputs a first current I1 on the third resistor R3, and the mirror current source outputs a second current I2 to the output loop module, the i1=i3, the i2=i4, and the i2=i1.

Specifically, when the charging circuit module works, the node 104, i.e. the output end of the operational amplifier U1 outputs a high level, and the MOS transistor Q101 works in the variable resistance region, and at this time, Q102 and Q103 are turned on. Q102 and Q103 form a mirror current source, and the resistance values of R4 and R5 are generally set, when r4=r5, the current magnitudes of I3 and I4 are the same at this time, and i3=i1, and since the current i2=i4 of the node 106, the current finally output to the node 106 is also I2, and the second current I2 is the same as the first current I1 at this time.

In this embodiment, a constant current output charging circuit module is added, a switch can be controlled by a signal, and key elements such as an operational amplifier U1, an MOS tube, two triodes and the like are used to realize constant current output, and the output current can be set according to the requirement.

In other embodiments, the comparison circuit includes an operational amplifier U2, a sixth resistor R6, and a seventh resistor R7, where the sixth resistor R6 and the seventh resistor R7 are voltage dividing resistors.

The noninverting input end of the operational amplifier U2 is connected with the voltage output end of any control loop of the output loop module and is used for collecting the output voltage of any control loop. The inverting input end of the operational amplifier U2 is grounded through the seventh resistor R7; and the output end of the U2 is connected with the processing chip and is used for outputting a comparison result to the processing chip.

Specifically, as shown in fig. 3, the node 107 is the reference voltage Vref obtained by dividing the voltage of the node 200 by the sixth resistor R6 and the seventh resistor R7, when the voltage of the node 106 is higher than the voltage of the node 107, that is, an output voltage of the control loop is greater than or equal to the reference voltage Vref, the node 108 output by the operational amplifier U2 is at a high level, which indicates that the loop connected at this time has no short circuit phenomenon, the node 108 is monitored by the CPLD, and the high level signal output by the node 108 is transmitted to the CPLD.

When the voltage at node 106 is always lower than the voltage at node 107, i.e., the output voltage is lower than the reference voltage Vref, this indicates that a short circuit condition has occurred in the circuit.

When one of the control signals is pulled high and node 101 outputs a low level, it is determined whether the level of node 108 is high or low by a delay time T taking into account the charging current I, the total output capacitance C of the loop and the reference voltage Vref set at node 107. And (3) according to the relation (3), calculating the time T, wherein the delay time of the CPLD is longer than T, and then carrying out short circuit detection. The relation (3) is: t=（3）。

The equivalent circuit is shown in fig. 5, and N power supply loops are included in the server, each power supply loop is equivalent to a parallel circuit consisting of a total capacitor CL and a load resistor RL; the capacitor CL is used for charging and storing energy, and the load resistor RL is used for shunting.

Further, the equivalent load capacitance of the loop 1 is CL1, when the loop 1 is connected to the node 106 of the detection circuit, the charging circuit module outputs the second current I2 to charge the capacitor CL1, the charging time t1=cl1·vreference/I2, and the delay reading time is more than 2 times of T1 due to the shunt effect of the resistor RL1, i.e. it is ensured that T >2·t1, and when T is set, the situation of all loops is considered, i.e. it is ensured that T is greater than 2 times of the maximum value of T1 and T2 … … Tn.

In addition, when the reference voltage Vref is set, taking the circuit 1 in fig. 5 as an example, the final charging voltage of the voltage V of the node 106 after the circuit 1 is sufficiently charged by the second current I2 may be calculated by the following formula: v1=i2·rl1.

The reference voltage Vref must be smaller than V1, i.e. Vref < V1, to effectively complete the detection. Therefore, the reference voltage Vref is set by the present embodiment taking into consideration that different V1, V2 … … Vn caused by different RL of all n power supply loops, and Vref is smaller than all voltage values.

In this embodiment, by setting the short circuit comparing circuit, the output voltage of the loop after delay is compared with the set reference voltage Vref, so as to detect whether the current loop is short-circuited.

Optionally, in other embodiments, the processing chip is specifically configured to control the 1 st to nth power supply circuits to input a high level signal one by one, control the detection enable signal to be asserted, and start the charging circuit module to supply power to the xth power supply circuit, where x is greater than or equal to 1 and less than or equal to N, and N is a positive integer.

Calculating the time T (x) for the voltage of the xth power supply loop to climb to a set detection threshold according to the current value output by the charging circuit module and the total capacitance value of the xth power supply loop; when the time T (x) reaches a preset duration, if a high-level signal output by the comparison circuit is received, determining that the power supply short-circuit fault of the xth power supply loop does not occur; and if the low-level signal is received, determining that the x power supply loop has a short circuit fault.

Further, the comparison circuit is further configured to collect an output voltage corresponding to the xth power supply loop after a delay period T2 when the charging circuit module is started to supply power to the xth power supply loop, where T2 > 2·t1, and T1 is a charging time for the capacitor CL of the xth power supply loop.

The detection circuit provided by the embodiment comprises a controllable charging circuit module, and can output a charging current with controllable magnitude according to the total capacitance value of the server loop capacitor to supply power for a power supply loop in the subsequent output loop module.

In addition, N MOS tubes are also arranged in series with N control loops, each control loop comprises a MOS tube and is used for controlling and appointing any loop to be connected into a short circuit detection circuit and sequentially carrying out short circuit detection in turn, so that all power supply loops on a detection server are traversed, and whether short circuit faults occur in the server or not is comprehensively detected.

In the detection circuit of this embodiment, the comparison circuit is used to compare the delayed output voltage of the detection circuit with the set reference voltage Vref to detect whether the current circuit is shorted. The short circuit detection of the power supply loop is realized remotely, the detection efficiency is improved, and the labor cost is saved.

In addition, before the server is powered on or the server can not be started, the remote sending instruction starts the internal short circuit detection, so that the possible power short circuit problem is detected, the on-site operation and disassembly of the machine by a maintenance engineer is avoided, and the damage caused by the re-try of starting is also avoided.

It should be noted that the technical solution may also be used in other systems that need remote detection of short circuits, or perform health check on the circuit to be detected before each power supply system is powered on.

In this embodiment, a power short circuit detection method is also provided, which may be used in the power short circuit detection circuit described in the foregoing embodiment, and fig. 6 is a flowchart of a power short circuit detection method according to an embodiment of the present invention, as shown in fig. 6, where the method includes:

Step S101: when the output loop module in the power short circuit detection circuit is connected with N power loops in the server, the processing chip controls the 1 st to N power loops one by one to input high-level signals, and controls the detection enabling signals in the charging circuit module to take effect, and the charging circuit module is started to supply power to the x power loop, wherein x is more than or equal to 1 and less than or equal to N, and N is a positive integer.

Step S102: calculating the time for the voltage of the xth power supply loop to climb to a set detection threshold according to the current value output by the charging circuit module and the total capacitance value of the xth power supply loop;

step S103: and when the time reaches the preset duration, the processing chip judges whether the high-level signal output by the comparison circuit is received or not.

Step S104: if yes, the processing chip receives the high-level signal output by the comparison circuit, and the power short circuit fault of the xth power supply loop is determined not to occur.

Step S105: if not, the processing chip receives the low-level signal output by the comparison circuit, and the x power supply loop is determined to have short circuit fault.

In one embodiment, as shown in fig. 7, the method specifically includes:

Step 1: after the start of detection, the CPLD sets the control signal x to 0.

Step 2: the CPLD polls the enable control signal x=x+1, whereby in the initial state the value of x is 1, so that x starts from 1 and represents the loop 1 of the control signal 1, which starts from the 1 st power supply loop and detects it.

Step 3: the CPLD pulls the control signal x high and outputs a high-level signal, and at the moment, the x power supply loop is connected into the checking main loop.

Step 4: the CPLD controls the detection enabling signal in the charging circuit module to take effect, and at the moment, the charging circuit module is started to charge the xth power supply loop connected to the checking loop and output a second current I2.

Step 5: according to the current value I2 output by the charging circuit module and the total capacitance value CL of the xth loop, the time T (x) required for the loop voltage to climb to the set detection threshold value Vth is calculated, and after the time T (x) is reached, the comparison circuit outputs a high level signal or a low level signal.

If the comparison circuit outputs a high level to the CPLD, the comparison circuit indicates that no short circuit condition occurs; if the comparison circuit output remains low for the CPLD, it is determined that a short circuit fault has occurred in the current x-loop.

Step 6: the CPLD compares whether the value of x is equal to n, which is the total number of power supply loops.

If x < n, the polling traversal is not finished, and the method returns to the step 2, executes x=x+1, performs short circuit detection of power supply loops of the steps 2 and 3 … …, and continues to circulate the method flows from the step 3 to the step 5.

If x=n, it means that all n loops have completed checking. And (5) finishing the inspection and test. And counting and recording detection results, generating a detection log and reporting the detection log for a maintenance engineer to check.

Further functional descriptions of the above method steps are the same as those of the above circuit configuration embodiments, and reference may be made to the foregoing embodiments shown in fig. 1 to 5, which are not repeated here.

The embodiment of the invention also provides computer equipment, which is provided with the detection circuit shown in the figures 1 to 5.

Referring to fig. 8, a schematic structural diagram of a computer device according to an alternative embodiment of the present invention is shown in fig. 8, where the computer device includes: one or more processors 10, memory 20, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components are communicatively coupled to each other using different buses and may be mounted on a common motherboard or in other manners as desired. The processor may process instructions executing within the computer device, including instructions stored in or on memory to display graphical information of the GUI on an external input/output device, such as a display device coupled to the interface. In some alternative embodiments, multiple processors and/or multiple buses may be used, if desired, along with multiple memories and multiple memories. Also, multiple computer devices may be connected, each providing a portion of the necessary operations (e.g., as a server array, a set of blade servers, or a multiprocessor system). One processor 10 is illustrated in fig. 8.

The processor 10 may be a central processor, a network processor, or a combination thereof. The processor 10 may further include a hardware chip, among others. The hardware chip may be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general-purpose array logic, or any combination thereof.

Wherein the memory 20 stores instructions executable by the at least one processor 10 to cause the at least one processor 10 to perform the power short detection method shown in implementing the above embodiments.

The memory 20 may include a storage program area that may store an operating system, at least one application program required for functions, and a storage data area; the storage data area may store data created from the use of the computer device of the presentation of a sort of applet landing page, and the like. In addition, the memory 20 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, memory 20 may optionally include memory located remotely from processor 10, which may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

Memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk, or solid state disk; the memory 20 may also comprise a combination of the above types of memories.

The computer device further comprises input means 30 and output means 40. The processor 10, memory 20, input device 30, and output device 40 may be connected by a bus or other means, for example in fig. 8.

The input device 30 may receive input numeric or character information and generate key signal inputs related to user settings and function control of the computer apparatus, such as a touch screen, a keypad, a mouse, a trackpad, a touchpad, a pointer stick, one or more mouse buttons, a trackball, a joystick, and the like. The output means 40 may include a display device, auxiliary lighting means (e.g., LEDs), tactile feedback means (e.g., vibration motors), and the like. Such display devices include, but are not limited to, liquid crystal displays, light emitting diodes, displays and plasma displays. In some alternative implementations, the display device may be a touch screen.

The computer device also includes a communication interface for the computer device to communicate with other devices or communication networks.

The embodiments of the present invention also provide a computer readable storage medium, and the method according to the embodiments of the present invention described above may be implemented in hardware, firmware, or as a computer code which may be recorded on a storage medium, or as original stored in a remote storage medium or a non-transitory machine readable storage medium downloaded through a network and to be stored in a local storage medium, so that the method described herein may be stored on such software process on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, a solid state disk or the like; further, the storage medium may also comprise a combination of memories of the kind described above. It will be appreciated that a computer, processor, microprocessor controller or programmable hardware includes a memory component that can store or receive software or computer code that, when accessed and executed by the computer, processor or hardware, implements the power short detection method illustrated by the above embodiments.

Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope of the invention as defined by the appended claims.

Claims

1. A power supply short circuit detection circuit, the circuit comprising: the device comprises a processing chip, a charging circuit module, an output loop module and a comparison circuit, wherein,

The output loop module comprises N control loops, each control loop comprises a signal input end, a switching tube and a connecting end, wherein each signal input end is connected with one signal output end of the processing chip and used for receiving one path of control signals output by the processing chip, each connecting end is used for being connected with one power supply loop in the server, the switching tube is arranged between the signal input end and the connecting end and used for controlling the control loop where the switching tube is positioned to be connected or disconnected, and N is more than or equal to 1 and is a positive integer; the server comprises N power supply loops, wherein each power supply loop is equivalent to a parallel circuit consisting of a total capacitor CL and a load resistor RL; the capacitor CL is used for charging and storing energy, and the load resistor RL is used for shunting;

The processing chip is used for receiving the comparison result output by the comparison circuit and determining whether the target control loop has a power supply short circuit fault or not according to the comparison result;

The processing chip is specifically used for:

The 1 st to N th power supply loops are controlled to input high-level signals one by one, and control detection enabling signals are enabled to take effect, the charging circuit module is started to supply power to the x-th power supply loop, x is more than or equal to 1 and less than or equal to N, and the detection enabling signals are controlled by the processing chip to output high level or low level;

2. The circuit according to claim 1, wherein the comparison circuit is specifically configured to:

when the output voltage is larger than or equal to the reference voltage, outputting a high-level signal to the processing chip;

and when the output voltage is smaller than the reference voltage, outputting a low-level signal to the processing chip.

3. The circuit of claim 2, wherein the processing chip is specifically configured to:

When receiving the high-level signal output by the comparison circuit, determining that the target control loop has no power short-circuit fault;

and when receiving the low-level signal output by the comparison circuit, determining that the target control loop has a power short circuit fault.

4. The circuit of claim 1, wherein the switching tube of each control loop is a MOS tube, a g pole of the MOS tube is connected to the signal input end, a d pole of the MOS tube is connected to the power output end of the charging circuit module, and a s pole of the MOS tube is connected to the connection end;

5. The circuit of claim 4, wherein the charging circuit module is connected to a direct current power source;

6. The circuit of claim 5, wherein the charging circuit module is specifically configured to:

7. The circuit of claim 6, wherein the first voltage V1 is determined by a first relationship:

8. The circuit of claim 7, wherein the first current I1 is determined by a second relationship:

Wherein I ₁ is the first current, and R3 is the third resistance.

9. The circuit of claim 8, wherein the charging circuit module further comprises: a fourth resistor R4 and a fifth resistor R5, wherein the fourth resistor R4 is connected between the dc power supply and the transistor Q102, and the fifth resistor R5 is connected between the dc power supply and the transistor Q103;

10. The circuit of claim 9, wherein if r4=r5, i3=i4;

when the s pole of the MOS transistor Q101 outputs a first current I1 on the third resistor R3, and the mirror current source outputs a second current I2 to the output loop module, the i1=i3, the i2=i4, and the i2=i1.

11. The circuit according to any one of claims 1 to 10, wherein the comparison circuit comprises an operational amplifier U2, a sixth resistor R6 and a seventh resistor R7, wherein the sixth resistor R6 and the seventh resistor R7 are voltage dividing resistors,

12. The circuit of claim 1, wherein the comparison circuit is further configured to collect an output voltage corresponding to an xth power supply loop after a delay period T2 when the charging circuit module is started to supply power to the xth power supply loop, where T2 > 2·t1, and T1 is a charging time of a capacitor CL of the xth power supply loop.

13. The circuit of claim 12, wherein a charging voltage of the power supply is greater than the reference voltage when the charging circuit module is activated to power an x-th power supply loop.

14. The circuit according to any of claims 1-10, wherein the processing chip is a complex programmable logic chip CPLD.

15. A power short detection method, characterized in that the method is applied to the power short detection circuit according to any one of claims 1 to 14, the method comprising:

When an output loop module in the power short circuit detection circuit is connected with N power loops in the server, the processing chip controls the 1 st to N power loops one by one to input high-level signals, and controls detection enabling signals in the charging circuit module to take effect, and starts the charging circuit module to supply power to the x power loop, wherein x is more than or equal to 1 and less than or equal to N, and N is a positive integer;

16. The method of claim 15, wherein the method further comprises:

and if the processing chip receives the low-level signal output by the comparison circuit, determining that the x-th power supply loop has short circuit fault.