CN117957773A

CN117957773A - Filter device

Info

Publication number: CN117957773A
Application number: CN202280062368.3A
Authority: CN
Inventors: 冈野芳久
Original assignee: Murata Manufacturing Co Ltd
Current assignee: Murata Manufacturing Co Ltd
Priority date: 2021-10-07
Filing date: 2022-09-30
Publication date: 2024-04-30
Also published as: WO2023058584A1

Abstract

The invention provides a filter device capable of effectively improving heat dissipation. A filter device (1) is provided with a piezoelectric substrate (2), an input terminal (4) and an output terminal, a1 st ground terminal (6A) and a2 nd ground terminal, a plurality of series arm resonators, a plurality of parallel arm resonators, at least 3, and a mounting substrate (3). The mounting substrate (3) has a1 st outermost layer (3A), a2 nd outermost layer (3D), an intermediate layer (1 st intermediate layer (3B), and a2 nd intermediate layer (3C)), and ground electrodes (1 st ground electrodes (16A, 16C, 16E), and 2 nd ground electrodes) provided on the 1 st outermost layer (3A) and the intermediate layer, respectively, and electrically connected to a ground terminal. A parallel arm resonator (P1) closest to the input terminal (4) is connected to the 1 st ground terminal (6A). The other parallel arm resonators are connected to the 2 nd ground terminal. At least two ground electrodes are provided in at least one of the 1 st outermost layer (3A) and the intermediate layer.

Description

Filter device

Technical Field

The present invention relates to a filter device.

Background

Conventionally, a filter device has been widely used in a mobile phone and the like. Patent document 1 below discloses an example of a filter having an elastic wave resonator. In this filter, a plurality of series resonators and a plurality of parallel resonators are formed on a piezoelectric substrate. All of the series resonators and the parallel resonators are elastic wave resonators. A plurality of pads are provided on the piezoelectric substrate. The plurality of pads includes a transmit pad, a common pad, and a ground pad. The filter is connected to an external circuit via a plurality of pads.

Prior art literature

Patent literature

Patent document 1: japanese patent laid-open No. 2018-078489

Disclosure of Invention

Problems to be solved by the invention

In the filter described in patent document 1, improvement of isolation characteristics is achieved. However, it is difficult to sufficiently improve the heat dissipation.

The invention aims to provide a filter device capable of effectively improving heat dissipation.

Technical scheme for solving problems

The filter device according to the present invention includes: a piezoelectric substrate; an input terminal and an output terminal provided on the piezoelectric substrate; a plurality of ground terminals including a 1 st ground terminal and at least one 2 nd ground terminal provided on the piezoelectric substrate; a plurality of series arm resonators and at least 3 parallel arm resonators formed on the piezoelectric substrate; and a mounting substrate electrically connected to the input terminal, the output terminal, and the plurality of ground terminals, the mounting substrate having: the 1 st surface layer comprises a chip attaching surface; the 2 nd surface layer; at least one intermediate layer disposed between the 1 st and 2 nd outermost layers; and a ground electrode provided on the 1 st outermost layer and the intermediate layer, respectively, and electrically connected to the ground terminal, wherein the parallel arm resonator disposed on the side closest to the input terminal is connected to the 1 st ground terminal, the other plurality of parallel arm resonators are connected to the 2 nd ground terminal, and the ground electrode is made to be two or more in at least one layer of the 1 st outermost layer and the intermediate layer of the mounting substrate.

Effects of the invention

According to the filter device of the present invention, heat radiation can be effectively improved.

Drawings

Fig. 1 is a circuit diagram of a filter device according to embodiment 1 of the present invention.

Fig. 2 is a schematic front cross-sectional view of a filter device according to embodiment 1 of the present invention.

Fig. 3 is a schematic bottom view showing an electrode structure on a piezoelectric substrate according to embodiment 1 of the present invention.

Fig. 4 is a plan view of the 1 st outermost layer of the mounting substrate according to embodiment 1 of the present invention.

Fig. 5 is a plan view of the 1 st intermediate layer of the mounting substrate in embodiment 1 of the present invention.

Fig. 6 is a bottom view of the 2 nd outermost layer of the mounting substrate in embodiment 1 of the present invention.

Fig. 7 is a schematic bottom view showing an electrode structure on a piezoelectric substrate in the comparative example.

Fig. 8 is a heat map on the piezoelectric substrate in the comparative example.

Fig. 9 is a thermal diagram of a piezoelectric substrate according to embodiment 1 of the present invention.

Fig. 10 is a bottom view showing an electrode structure of a parallel arm resonator in embodiment 1 of the present invention.

Fig. 11 is a plan view of the 1 st intermediate layer in embodiment 2 of the present invention.

Fig. 12 is a thermal diagram of a piezoelectric substrate according to embodiment 2 of the present invention.

Fig. 13 is a diagram showing the relationship between input power and output power in embodiment 2 and comparative example of the present invention.

Fig. 14 is a schematic front cross-sectional view of a filter device according to embodiment 3 of the present invention.

Detailed Description

The present invention will be described in detail below with reference to the drawings.

Note that the embodiments described in this specification are illustrative, and partial replacement or combination of structures can be performed between different embodiments.

The filter device 1 has a circuit portion of a ladder filter. More specifically, the filter device 1 has an input terminal 4 and an output terminal 5, a plurality of ground terminals, and a plurality of series arm resonators and a plurality of parallel arm resonators. The input terminal 4, the output terminal 5, and the ground terminal may be formed as electrode pads or may be formed as wirings. In the present embodiment, the input terminal 4, the output terminal 5, and the plurality of ground terminals are configured as electrode pads. The plurality of ground terminals are connected to a ground potential.

The filter device 1 is a transmission filter of Band 40. More specifically, the passband of the filter device 1 is 2300 to 2400MHz. However, the passband of the filter device 1 is not limited to the passband described above. Further, the filter device 1 may be a reception filter. The filter device 1 can be used for a composite filter device such as a duplexer or a multiplexer.

The plurality of series arm resonators of the present embodiment are a series arm resonator S1, a series arm resonator S2, a series arm resonator S3, and a series arm resonator S4. The plurality of parallel arm resonators are a parallel arm resonator P1, a parallel arm resonator P2, a parallel arm resonator P3, and a parallel arm resonator P4. In the filter device 1, all of the series arm resonators and all of the parallel arm resonators are elastic wave resonators.

A series arm resonator S1, a series arm resonator S2, a series arm resonator S3, and a series arm resonator S4 are connected in series with each other between the input terminal 4 and the output terminal 5. A parallel arm resonator P1 is connected between the ground potential and the connection point between the series arm resonator S1 and the series arm resonator S2. A parallel arm resonator P2 is connected between the ground potential and the connection point between the series arm resonator S2 and the series arm resonator S3. A parallel arm resonator P3 is connected between the ground potential and the connection point between the series arm resonator S3 and the series arm resonator S4. A parallel arm resonator P4 is connected between the output terminal 5 and the ground potential. Among the plurality of parallel arm resonators, the parallel arm resonator P1 is arranged on the input terminal 4 side. The circuit configuration of the filter device 1 is not limited to the above-described circuit configuration. As long as at least two series arm resonators and at least 3 parallel arm resonators are provided. However, the total of the series arm resonators and the parallel arm resonators is preferably 6 or more. In this case, the filter characteristics are easy to be improved.

Hereinafter, a specific configuration of the filter device 1 is shown.

Fig. 2 is a schematic front cross-sectional view of the filter device according to embodiment 1. In fig. 2, the electrodes of the elastic wave resonators are shown by a simplified diagram with two diagonal lines added to the rectangle. In fig. 2, a via electrode described later is schematically shown, and the arrangement of the via electrode in fig. 2 and other drawings is not necessarily uniform.

The filter device 1 has a mounting substrate 3 and a piezoelectric substrate 2. In the present embodiment, the piezoelectric substrate 2 is a substrate composed only of a piezoelectric layer. However, the piezoelectric substrate 2 may be a laminated substrate including a piezoelectric layer. A plurality of series arm resonators and a plurality of parallel arm resonators are provided on the piezoelectric substrate 2. Hereinafter, a direction viewed from above in fig. 2 is referred to as a plan view, and a direction viewed from below in fig. 2 is referred to as a bottom view.

Fig. 3 is a schematic bottom view showing an electrode structure on a piezoelectric substrate in embodiment 1. In fig. 3, the electrodes of the respective elastic wave resonators are shown by a schematic diagram in which two diagonal lines are added to a rectangle.

The piezoelectric substrate 2 is provided with an input terminal 4, an output terminal 5, and a plurality of ground terminals. More specifically, the plurality of ground terminals are the 1 st ground terminal 6A and the 2 nd ground terminal 6B. The 1 st ground terminal 6A is connected to the parallel arm resonator P1. On the other hand, a plurality of other parallel arm resonators are commonly connected to the 2 nd ground terminal 6B. Specifically, the 2 nd ground terminal 6B is commonly connected to the parallel arm resonator P2, the parallel arm resonator P3, and the parallel arm resonator P4.

Bumps 7 are provided on the input terminal 4, the output terminal 5, and the plurality of ground terminals, respectively. The plurality of bumps 7 are bonded to the mounting substrate 3. In the present embodiment, the 2 nd ground terminal 6B is one. A plurality of 2 nd ground terminals 6B may be provided. However, by setting the 2 nd ground terminal 6B to be one, the filter device 1 can be made compact.

Returning to fig. 2, the mounting substrate 3 has a1 st outermost layer 3A, a1 st intermediate layer 3B, a 2 nd intermediate layer 3C, and a 2 nd outermost layer 3D. However, the laminated structure of the mounting substrate 3 is not limited to the above-described structure, and at least one intermediate layer may be provided between the 1 st outermost layer 3A and the 2 nd outermost layer 3D. The 1 st outermost layer 3A includes a chip attachment surface 3A.

Fig. 4 is a plan view of the 1 st outermost layer of the mounting substrate in embodiment 1. Fig. 5 is a plan view of the 1 st intermediate layer of the mounting substrate in embodiment 1. Fig. 6 is a bottom view of the 2 nd outermost layer of the mounting substrate in embodiment 1.

As shown in fig. 4, the 1 st outermost layer 3A has a chip-attaching surface 3A provided with an input electrode 14A, an output electrode 15A, and a plurality of ground electrodes. Specifically, the plurality of ground electrodes are the 1 st ground electrode 16A and the 2 nd ground electrode 16B. The input electrode 14A is connected to the input terminal 4. The output electrode 15A is connected to the output terminal 5. The 1 st ground electrode 16A is connected to the 1 st ground terminal 6A. The 2 nd ground electrode 16B is connected to the 2 nd ground terminal 6B. The electrodes on the 1 st outermost layer 3A are connected to the terminals on the piezoelectric substrate 2 via the bumps 7. As described above, the input terminal 4, the output terminal 5, and the plurality of ground terminals are electrically connected to the mounting board 3 via the plurality of bumps 7.

Similarly, as shown in fig. 5, the 1 st intermediate layer 3B is provided with an input electrode 14B, an output electrode 15B, a1 st ground electrode 16C, and a 2 nd ground electrode 16D. Although not shown, the 2 nd intermediate layer 3C is also provided with the same electrode as that of the 1 st intermediate layer 3B. However, the electrodes provided in the 1 st intermediate layer 3B and the 2 nd intermediate layer 3C may have the same shape or may have different shapes.

As shown in fig. 6, the 2 nd outermost layer 3D is provided with an input electrode 14C, an output electrode 15C, a1 st ground electrode 16E, and a2 nd ground electrode 16F. As shown in fig. 2, a plurality of via electrodes 8 are provided on the mounting substrate 3. A plurality of via electrodes 8 penetrate each layer of the mounting substrate 3. The via electrodes 8 of some of the plurality of via electrodes 8 connect the input electrodes of the respective layers to each other. Similarly, the other part of the via electrode 8 connects the output electrodes of the respective layers to each other. The other part of each via electrode 8 connects the 1 st ground electrodes of each layer to each other. A further part of the via electrode 8 connects the 2 nd ground electrodes of the layers to each other. The electrodes of the 2 nd outermost layer 3D are connected to the outside.

A sealing resin layer 9 is provided on the 1 st outermost layer 3A of the mounting substrate 3 so as to cover the piezoelectric substrate 2.

The present embodiment is characterized by having the following structure. 1) The parallel arm resonator P1 disposed on the side closest to the input terminal 4 is connected to the 1 st ground terminal 6A, and the other plurality of parallel arm resonators are connected to the 2 nd ground terminal 6B. 2) In the 1 st surface layer 3A of the mounting board 3, two or more ground electrodes are provided. However, two or more ground electrodes may be provided in at least one of the 1 st outermost layer 3A and the intermediate layer of the mounting substrate 3. This can effectively improve heat dissipation. Hereinafter, this embodiment and the comparative example will be described by comparison.

The circuit configuration in the comparative example is the same as that in the present embodiment. As shown in fig. 7, the comparative example is different from the present embodiment in that the parallel arm resonator P1 and the parallel arm resonator P2 are commonly connected to the 1 st ground terminal 6A. In the comparative example, the parallel arm resonator P3 and the parallel arm resonator P4 are also commonly connected to the 2 nd ground terminal 6B.

In the filter device of the present embodiment and the comparative example, a simulation was performed using the finite element method simulation software Femtet (registered trademark) manufactured by the company Tian Ruanjian, and the temperature was obtained when 1W of power was uniformly applied to each elastic wave resonator.

Fig. 8 is a heat map on the piezoelectric substrate in the comparative example. Fig. 9 is a thermal diagram on a piezoelectric substrate in embodiment 1.

As shown in fig. 8, in the comparative example, the temperature near the center of all elastic wave resonators was 1.62×10 ³ degrees or more. In particular, the parallel arm resonator P2 has a temperature of 1.94X10 ³ [ DEG ] or more near the center. The temperature is also high, i.e., 1.78X10 ³ degrees, near the centers of the series arm resonator S2 and the series arm resonator S3 adjacent to the parallel arm resonator P2.

In contrast, as shown in fig. 9, in embodiment 1, the series arm resonator S1 and the parallel arm resonator P1 do not reach 1.62×10 ³ degrees, and the temperature rise is suppressed. Further, it is found that the high-temperature region is also narrowed in the parallel arm resonator P2, the series arm resonator S2, and the series arm resonator S3.

The parallel arm resonator P1 is arranged on the input terminal 4 side among the plurality of parallel arm resonators. Therefore, when power is applied, the heat is most generated among the plurality of parallel arm resonators. In the comparative example, the parallel arm resonator P1 and the parallel arm resonator P2 are commonly connected to the 1 st ground terminal 6A, and therefore, the efficiency of heat dissipation from the parallel arm resonator P1 and the parallel arm resonator P2 is low. Further, since the parallel arm resonator P2 becomes high temperature, the series arm resonator S2 and the series arm resonator S3 adjacent to the parallel arm resonator P2 also become high temperature.

In contrast, in embodiment 1, the parallel arm resonator P1 and the other parallel arm resonators are connected to the ground terminal. This allows efficient heat dissipation from the parallel arm resonator P1. The parallel arm resonator P2 is connected to a different ground terminal from the parallel arm resonator P1 that generates the most heat. Therefore, the efficiency of heat dissipation of the parallel arm resonator P2 is not easily deteriorated, and the temperature rise in the parallel arm resonator P2 can be suppressed. Accordingly, the temperature rise of the series arm resonator S2 and the series arm resonator S3 adjacent to the parallel arm resonator P2 can be suppressed. As described above, the heat radiation performance of the entire filter device 1 can be improved.

Further, the 1 st ground electrode 16A of the chip attach surface 3A provided on the 1 st outermost layer 3A of the mounting substrate 3 shown in fig. 4 is connected to the 1 st ground terminal 6A, and is not connected to the 2 nd ground terminal 6B. This can reduce the area of the 1 st ground terminal 6A. Therefore, the area of the portion of the 1 st ground terminal 6A facing the series arm resonator or the parallel arm resonator can be reduced. As a result, heat from the elastic wave resonators other than the parallel arm resonator P1 is less likely to propagate to the 1 st ground electrode 16A. Accordingly, heat propagating from the parallel arm resonator P1 through the 1 st ground terminal 6A and the bump 7 can be efficiently dissipated to the outside. On the other hand, heat generated in the other parallel arm resonators and the like is radiated to the outside through the 2 nd ground terminal 6B, the bump 7, and the 2 nd ground electrode 16B. Therefore, heat dissipation can be effectively improved.

In addition, as described above, the area of the portion of the 1 st ground electrode 16A facing the series arm resonator or the parallel arm resonator and the wiring can be reduced, and therefore parasitic capacitance can be reduced.

In addition, two or more ground electrodes may be provided in at least one of the 1 st outermost layer 3A and the intermediate layer of the mounting substrate 3. However, as in embodiment 1, the ground electrode provided on the chip attach surface 3A of the 1 st outermost layer 3A preferably includes the 1 st ground electrode 16A and the 2 nd ground electrode 16B. In the mounting substrate 3, the 1 st outermost layer 3A is closest to the plurality of elastic wave resonators. Therefore, heat is particularly easy to propagate from the elastic wave resonator to the electrode provided on the 1 st outermost layer 3A. Furthermore, the electrode is particularly susceptible to parasitic capacitance. In embodiment 1, the ground electrode is divided into a1 st ground electrode 16A and a2 nd ground electrode 16B. This can further improve heat dissipation and reduce parasitic capacitance.

The 2 nd ground terminal 6B is not necessarily one. The plurality of parallel arm resonators other than the parallel arm resonator P1 may not be commonly connected to the single 2 nd ground terminal 6B. However, as in embodiment 1, it is preferable that a plurality of parallel arm resonators other than the parallel arm resonator P1 are commonly connected to one 2 nd ground terminal 6B. In this case, the number of locations where the 2 nd ground terminal 6B is provided can be reduced. Thus, the filter device 1 can be made compact. Further, when the filter device 1 is miniaturized, the distance between elastic wave resonators and the distance between terminals become short, and heat dissipation is liable to deteriorate. Therefore, the present invention is particularly preferable.

Hereinafter, a specific structure of the elastic wave resonator in embodiment 1 will be described.

Fig. 10 is a bottom view showing an electrode structure of the parallel arm resonator in embodiment 1. In fig. 10, the wiring connected to the parallel arm resonator P1 is omitted.

The parallel arm resonator P1 has a piezoelectric substrate 2. An IDT electrode 12 is provided on the piezoelectric substrate 2. By applying an ac voltage to the IDT electrode 12, an elastic wave is excited. A pair of reflectors 13A and 13B are provided on both sides of the piezoelectric substrate 2 in the elastic wave propagation direction of the IDT electrode 12.

The IDT electrode 12 has 1 st and 2 nd bus bars 17A and 17B, and a plurality of 1 st electrode fingers 18A and a plurality of 2 nd electrode fingers 18B. The 1 st bus bar 17A and the 2 nd bus bar 17B are opposed to each other. One end of each of the 1 st electrode fingers 18A is connected to the 1 st bus bar 17A. One end of each of the plurality of 2 nd electrode fingers 18B is connected to the 2 nd bus bar 17B. The 1 st electrode fingers 18A and the 2 nd electrode fingers 18B are interleaved with each other.

All the elastic wave resonators of the filter device 1 share the piezoelectric substrate 2. Each elastic wave resonator other than the parallel arm resonator P1 also has an IDT electrode and a reflector, similar to the parallel arm resonator P1.

Fig. 11 is a plan view of the 1 st intermediate layer in embodiment 2.

The present embodiment differs from embodiment 1 in that a single ground electrode 26 is provided in the 1 st intermediate layer 23B. Except for the above-described aspects, the filter device of the present embodiment has the same configuration as the filter device 1 of embodiment 1. Accordingly, in the description of the structure other than the 1 st intermediate layer 23B in the present embodiment, reference is made to the drawings and reference numerals for the description of the structure of the 1 st embodiment.

As shown in fig. 4, the 1 st outermost layer 3A is divided into a1 st ground electrode 16A and a2 nd ground electrode 16B. The 1 st ground electrode 16A and the 2 nd ground electrode 16B are commonly connected to one ground electrode 26 shown in fig. 11 via the via electrode 8, respectively. Accordingly, the heat dissipation path for dissipating heat from the 1 st ground terminal 6A and the heat dissipation path for dissipating heat from the 2 nd ground terminal 6B are shared in the mounting substrate.

Here, in the filter device of the present embodiment, the temperature was obtained by performing simulation using the finite element method simulation software described above, and the power of 1W was uniformly applied to each elastic wave resonator.

Fig. 12 is a thermal diagram of the piezoelectric substrate according to embodiment 2.

As is clear from a comparison between fig. 12 and 9, the range of the high temperature can be further narrowed in the present embodiment. In particular, the range of the parallel arm resonator P2 and the series arm resonator S3, which are at high temperatures, is narrowed. As described above, in the present embodiment, the heat dissipation performance can be further improved. This is for the following reason.

In the present embodiment, as in embodiment 1, only the parallel arm resonator P1 disposed on the input terminal 4 side is connected to the 1 st ground terminal 6A. Accordingly, heat can be efficiently dissipated from the parallel arm resonator P1, which generates the most heat when power is applied, to the mounting substrate via the 1 st ground terminal 6A and the bump 7. Further, in the present embodiment, the heat radiation path for radiating heat from the 1 st ground terminal 6A and the heat radiation path for radiating heat from the 2 nd ground terminal 6B are integrated in the mounting substrate. Thus, in embodiment 1, heat from the 1 st ground terminal 6A side can be propagated through the heat dissipation path that originally dissipates heat only from the 2 nd ground terminal 6B. In this way, the heat dissipation path for dissipating heat from the 1 st ground terminal 6A can be enlarged. In the same manner, the heat radiation path for radiating heat from the 2 nd ground terminal 6B to which the parallel arm resonator P2 and the like are connected can be enlarged.

Further, the 1 st outermost layer 3A is provided between the ground electrode 26 provided in the 1 st intermediate layer 23B and each elastic wave resonator. Therefore, even if the area of the ground electrode 26 is increased, heat is less likely to propagate from each elastic wave resonator to the ground electrode 26 via the wires other than the wires. Therefore, the efficiency of heat dissipation from the parallel arm resonator P1 is not easily hindered. Therefore, the heat dissipation performance can be further improved as a whole of the filter device.

In addition, the distance from the ground electrode 26 to each elastic wave resonator is longer than the distance from each electrode provided on the chip attachment surface 3a to each elastic wave resonator. Therefore, the influence of the ground electrode 26 on the parasitic capacitance is relatively small. In this embodiment, the structure of the electrode on the chip attach surface 3a is the same as that of embodiment 1. Thus, parasitic capacitance can be reduced.

Further, in the filter device of the present embodiment and the comparative example, a power application test was performed. The frequency of the input signal is set to the frequency of the high-frequency side end of the band having a small insertion loss including the passband. An LTE modulated signal of the frequency is input from an input terminal, and power output from an output terminal is measured. The comparative example subjected to the power application test is a comparative example shown in fig. 7.

Fig. 13 is a diagram showing the relationship between the input power and the output power in embodiment 2 and the comparative example.

As shown in fig. 13, in the comparative example, the output power becomes a peak around the input power of 29.2 dBm. In contrast, in embodiment 2, even if the input power exceeds 29.2dBm, the output power continues to increase. In embodiment 2, the output power becomes a peak around the input power of 30.2 dBm. In recent years, an output power of 26.5dBm or more is preferable. In the comparative example, this criterion is not satisfied. On the other hand, in embodiment 2, the output power can be set to 26.5dBm or more.

In general, in a region where the input power is small, the larger the input power becomes, the larger the output power becomes. However, in a region where the input power is large, the temperature of each elastic wave resonator increases due to heat generation of each elastic wave resonator. When the temperature of each elastic wave resonator changes, the frequency characteristic of each elastic wave resonator changes. Therefore, the frequency band with a small insertion loss in the filter device becomes a low frequency band according to a change in temperature. Thus, even if the input power of a signal having the same frequency is increased, the signal becomes difficult to pass through the filter device due to the rise in temperature. As a result, the output power peaks.

In contrast, in embodiment 2, the heat radiation performance of the entire filter device can be improved. This suppresses an increase in temperature of each elastic wave resonator, and suppresses a change in frequency characteristics. Thus, even if the input power is increased, the output power can be increased. In this way, the power resistance can be improved.

In embodiment 1 and embodiment 2 described above, the portions constituting the plurality of elastic wave resonators are CSP (Chip Size Package ) types. However, the portion constituting the plurality of elastic wave resonators may be of a WLP (WAFER LEVEL PACKAGE ) type. Hereinafter, this example is shown.

Fig. 14 is a schematic front cross-sectional view of a filter device according to embodiment 3. In fig. 14, electrodes of the elastic wave resonator are shown by a simplified diagram in which two diagonal lines are added in a rectangle.

The present embodiment differs from embodiment 1 in that portions constituting a plurality of elastic wave resonators are of WLP type. Except for the above-described aspects, the filter device of the present embodiment has the same configuration as the filter device 1 of embodiment 1.

The piezoelectric substrate 2 is provided with a support member 34 so as to surround IDT electrodes of a plurality of elastic wave resonators. More specifically, the support member 34 has an opening 34a. The IDT electrodes are located in the opening 34a. The support member 34 covers at least a part of the plurality of terminals such as the input terminal 4 and the 1 st ground terminal 6A.

A cover member 35 is provided on the support member 34 so as to seal the opening 34a. Thereby, a hollow portion surrounded by the cover member 35, the support member 34, and the piezoelectric substrate 2 is provided. In the hollow portion, IDT electrodes of a plurality of elastic wave resonators are arranged.

A plurality of through-electrodes 36 are provided so as to penetrate the cover member 35 and the support member 34. One end of each through electrode 36 is connected to each terminal. The bump 7 is bonded to the other end of each through electrode 36. The plurality of bumps 7 are bonded to the mounting substrate 3.

In the present embodiment, only the parallel arm resonator P1 is connected to the 1 st ground terminal 6A, and the ground electrode is divided into two in the 1 st outermost layer 3A of the mounting substrate 3. As a result, heat dissipation can be effectively improved as in embodiment 1.

Description of the reference numerals

1: A filter device;

2: a piezoelectric substrate;

3: a mounting substrate;

3A: the 1 st surface layer;

3B, 3C: a1 st intermediate layer and a2 nd intermediate layer;

3D: the 2 nd surface layer;

3a: a chip attachment surface;

4: an input terminal;

5: an output terminal;

6A, 6B: a1 st ground terminal and a 2 nd ground terminal;

7: a bump;

8: a via electrode;

9: a sealing resin layer;

12: an IDT electrode;

13A, 13B: a reflector;

14A to 14C: an input electrode;

15A to 15C: an output electrode;

16A, 16B: a1 st ground electrode, a2 nd ground electrode;

16C, 16D: a1 st ground electrode, a2 nd ground electrode;

16E, 16F: a1 st ground electrode, a2 nd ground electrode;

17A, 17B: a1 st bus bar, a 2 nd bus bar;

18A, 18B: electrode finger 1, electrode finger 2;

23B: a1 st intermediate layer;

26: a ground electrode;

34: a support member;

34a: an opening portion;

35: a cover member;

36: a through electrode;

P1 to P4: a parallel arm resonator;

S1-S4: and a series arm resonator.

Claims

1. A filter device is provided with:

A piezoelectric substrate;

An input terminal and an output terminal provided on the piezoelectric substrate;

A plurality of ground terminals including a1 st ground terminal and at least one 2 nd ground terminal provided on the piezoelectric substrate;

a plurality of series arm resonators and at least 3 parallel arm resonators formed on the piezoelectric substrate; and

A mounting board electrically connected to the input terminal, the output terminal, and the plurality of ground terminals,

The mounting substrate has:

The 1 st surface layer comprises a chip attaching surface;

The 2 nd surface layer;

At least one intermediate layer disposed between the 1 st and 2 nd outermost layers; and

A ground electrode provided on the 1 st surface layer and the intermediate layer, respectively, and electrically connected to the ground terminal,

The parallel arm resonators disposed on the most input terminal side are connected to the 1 st ground terminal, and the other plurality of parallel arm resonators are connected to the 2 nd ground terminal, and the number of ground electrodes is two or more in at least one of the 1 st surface layer and the intermediate layer of the mounting substrate.

2. The filter device according to claim 1, wherein,

The ground electrode provided on the chip attach surface of the 1 st surface layer includes a 1 st ground electrode and a2 nd ground electrode, the 1 st ground terminal is connected to the 1 st ground electrode, and the 2 nd ground terminal is connected to the 2 nd ground electrode.

3. The filter device according to claim 2, wherein,

The 1 st ground electrode and the 2 nd ground electrode in the 1 st outermost layer are commonly connected to one of the ground electrodes provided in the intermediate layer.

4. A filter device according to any one of claims 1 to 3, wherein,

And a plurality of parallel arm resonators, among the plurality of parallel arm resonators, other than the parallel arm resonator disposed closest to the input terminal are commonly connected to one of the 2 nd ground terminals.

5. The filter device according to any one of claims 1 to 4, wherein,

The filter means is a transmit filter.