CN117950472A

CN117950472A - Reset method and electronic equipment

Info

Publication number: CN117950472A
Application number: CN202211297359.0A
Authority: CN
Inventors: 张桐恺; 张旭东; 雷奋星
Original assignee: Honor Device Co Ltd
Current assignee: Honor Device Co Ltd
Priority date: 2022-10-21
Filing date: 2022-10-21
Publication date: 2024-04-30
Also published as: WO2024082801A1

Abstract

The embodiment of the application is suitable for the technical field of terminal equipment, and provides a reset method and electronic equipment, wherein the electronic equipment comprises a master device and a slave device, the master device is used for sending clock signals to the slave device, the master device and the slave device perform data interaction based on the clock signals, the slave device sends early warning information to the master device, and the master device performs reset operation when receiving the early warning information, wherein the early warning information is used for indicating that the master device is in an abnormal state, so that the problem of hanging the master device can be solved through the reset operation of the master device.

Description

Reset method and electronic equipment

Technical Field

The present application relates to the technical field of terminal devices, and more particularly, to a reset method and an electronic device.

Background

Electronic devices typically include a plurality of electronic components that are capable of data transfer via a serial peripheral interface (SERIAL PERIPHERAL INTERFACE, SPI) to perform various functions.

The electronic device generally comprises a master device and a plurality of slave devices, wherein the master device sends clock signals to the slave devices so as to enable the electronic devices to keep signal synchronization, and data interaction among the electronic devices is realized. Electromagnetic interference signals in electronic equipment can cause that a slave device cannot receive a clock signal sent by a master device, and further cause that the slave device cannot keep signal synchronization with the master device, and data interaction between the electronic devices cannot be performed, and the phenomenon is called device hanging. In the event of device hang-up, the slave device is typically reset to re-maintain signal synchronization between the master and slave devices. However, at the present stage, the number of electronic devices in the electronic apparatus is increased, or the size of the electronic devices is reduced, and the data interaction between the electronic devices cannot be recovered by adopting the conventional method.

Based on this, how to recover the data interaction between the electronic devices under the condition that the devices are hung up at present becomes a problem to be solved urgently.

Disclosure of Invention

The application provides a resetting method which can effectively restore data interaction among various electronic devices.

In a first aspect, a reset method is provided, where the method is applied to a master device in an electronic device, where the master device is configured to send a clock signal to a slave device, and the master device and the slave device perform data interaction based on the clock signal, and the electronic device includes the master device and the slave device, and the method includes:

receiving early warning information sent by a slave device, wherein the early warning information is used for indicating that a master device is in an abnormal state;

And resetting according to the early warning information.

The reset method provided by the embodiment of the application is applied to the main device in the electronic equipment, the main device is used for sending the clock signal to the auxiliary device, the main device and the auxiliary device perform data interaction based on the clock signal, the auxiliary device sends the early warning information to the main device, and the main device is reset when receiving the early warning information, wherein the early warning information is used for indicating the main device to be in an abnormal state, so that in the trend of the smaller chip size, the main device is influenced by the electromagnetic interference signal in the electronic equipment and is in the abnormal state, the problem of hanging of the main device can be solved through the reset operation of the main device.

In one embodiment, the master device being in an abnormal state includes: in a state where the chip select CS signal is at the first level and no clock signal is sent to the slave device.

It should be appreciated that the first level may be either a high level or a low level, and embodiments of the present application are not limited in this respect.

In one embodiment, the master device being in an abnormal state includes: when the chip select CS signal is at the first level, no data interaction is performed between the master device and the slave device.

In one embodiment, the master device being in an abnormal state includes: the time taken for the chip select CS signal to transition to the first level is less than a preset time period threshold.

In one embodiment, the method further comprises: and sending a reset instruction to the slave device, wherein the reset instruction is used for indicating the slave device to perform a reset operation.

According to the reset method provided by the embodiment of the application, when the master device receives the early warning information sent by the slave device, the master device performs reset operation, then the master device sends a reset instruction to the slave device to instruct the slave device to perform reset operation, namely, in the embodiment of the application, when the master device receives the early warning information sent by the slave device, after the master device performs reset operation on the master device, the master device also sends the reset instruction to the slave device so that the slave device performs reset operation based on the reset instruction, the problem that the device in the electronic equipment is not killed by only performing reset operation on the master device under the condition that the master device and the slave device are abnormal at the same time is avoided, and further the reliability of solving the problem of the device death in the electronic equipment is improved.

In one embodiment, the reset command includes a first reset command or a second reset command, where the first reset command is used to instruct device reset by triggering a reset key of the slave device, and the second reset command is used to instruct device reset of the slave device through the serial peripheral interface SPI interface.

In a second aspect, a reset method is provided, where the reset method is applied to a slave device in an electronic apparatus, where a master device is configured to send a clock signal to the slave device, and the master device and the slave device perform data interaction based on the clock signal, and the electronic apparatus includes the master device and the slave device, and the method includes:

Detecting that the main device is in an abnormal state;

And sending early warning information to the main device, wherein the early warning information is used for indicating that the main device is in an abnormal state.

According to the reset method provided by the embodiment of the application, a slave device sends a first signal to a master device, wherein the first signal is used for requesting data interaction with the master device, and then the slave device detects whether a clock signal sent by the master device is received or not; and if the clock signal sent by the main device is not detected, sending early warning information to the main device. The early warning information is sent when the clock signal is not detected on the basis that the slave device has requested data interaction to the master device, so that the accuracy of the early warning information for indicating that the master device is in an abnormal state is higher, the accuracy of the reset operation of the master device based on the early warning information is further improved, and the problem of device hanging in electronic equipment is more effectively solved.

In one embodiment, the detecting that the master device is in an abnormal state includes: transmitting a first signal to a main device, wherein the first signal is used for requesting data interaction with the main device; detecting whether a clock signal sent by a main device is received or not; if the clock signal sent by the master device is not detected, determining that the master device is in an abnormal state.

It should be appreciated that the first signal may be indicative of an Interrupt (INT) signal.

In one embodiment, the detecting that the master device is in an abnormal state includes: when the chip select CS signal is detected to be at a first level, no data transmission on the master-slave signal line MOSI and the master-slave signal line MISO between the master device and the slave device is detected.

In one embodiment, the detecting that the master device is in an abnormal state includes: the duration taken to detect the conversion of the chip select CS signal to the first level is less than a preset duration threshold.

In a third aspect, there is provided an electronic device comprising means for performing any of the methods of the first aspect. The means may be a chip within the terminal device. The apparatus may include an acquisition unit and a processing unit.

When the device is a chip in the terminal equipment, the processing unit may be a processing unit inside the chip, and the obtaining unit may be an output interface, a pin, a circuit, or the like; the chip may also include memory, which may be memory within the chip (e.g., registers, caches, etc.), or memory external to the chip (e.g., read-only memory, random access memory, etc.); the memory is for storing computer program code which, when executed by the processor, causes the chip to perform any of the methods of the first aspect.

In one possible implementation, the memory is used to store computer program code; a processor executing the computer program code stored in the memory, the processor, when executed, configured to perform: receiving early warning information sent by a slave device, wherein the early warning information is used for indicating that a master device is in an abnormal state; and resetting according to the early warning information.

In a fourth aspect, there is provided an electronic device comprising means for performing any of the methods of the second aspect. The means may be a chip within the terminal device. The apparatus may include an acquisition unit and a processing unit.

When the device is a chip in the terminal equipment, the processing unit may be a processing unit inside the chip, and the obtaining unit may be an output interface, a pin, a circuit, or the like; the chip may also include memory, which may be memory within the chip (e.g., registers, caches, etc.), or memory external to the chip (e.g., read-only memory, random access memory, etc.); the memory is for storing computer program code which, when executed by the processor, causes the chip to perform any of the methods of the second aspect.

In one possible implementation, the memory is used to store computer program code; a processor executing the computer program code stored in the memory, the processor, when executed, configured to perform: detecting that the main device is in an abnormal state; and sending early warning information to the main device, wherein the early warning information is used for indicating that the main device is in an abnormal state.

In a fifth aspect, an electronic device is provided, the electronic device comprising a master device for performing the method as in any of the first aspects and a slave device for performing the method as in any of the second aspects.

In one embodiment, the electronic device comprises a cell phone or tablet, the master device comprises a system on chip, SOC, and the slave device comprises a fingerprint sensor.

In one embodiment, the electronic device comprises a smart wearable device, the master device comprises a micro control unit MCU, and the slave device comprises a heart rate sensor.

In a sixth aspect, there is provided a computer readable storage medium storing computer program code which, when run by a reset apparatus, causes the reset apparatus to perform any one of the reset methods of the first aspect or causes the reset apparatus to perform any one of the reset methods of the second aspect.

In a seventh aspect, there is provided a computer program product comprising: computer program code which, when run by a reset apparatus, causes the reset apparatus to perform any one of the methods of the first aspect or causes the reset apparatus to perform any one of the methods of the second aspect.

The reset method and the electronic equipment provided by the embodiment of the application, wherein the electronic equipment comprises the master device and the slave device, the master device is used for sending the clock signal to the slave device, the master device and the slave device perform data interaction based on the clock signal, the slave device sends the early warning information to the master device, and the master device is subjected to reset operation when receiving the early warning information, wherein the early warning information is used for indicating that the master device is in an abnormal state, so that in the trend of the chip size being smaller and smaller, the master device is influenced by an electromagnetic interference signal in the electronic equipment and is in the abnormal state, the problem of hanging of the master device can be solved through the reset operation of the master device.

Drawings

FIG. 1 is a schematic diagram of a connection relationship between a master device and a slave device;

FIG. 2 is a schematic diagram of signals between a master device and a slave device;

FIG. 3 is a schematic diagram of a hardware system suitable for use with the electronic device of the present application;

FIG. 4 is a schematic diagram of a software system suitable for use with the electronic device of the present application;

fig. 5 is a schematic diagram of an application scenario of a reset method in an embodiment of the present application;

fig. 6 is a schematic diagram of an application scenario of another reset method in an embodiment of the present application;

fig. 7 is a schematic diagram of an application scenario of another reset method in an embodiment of the present application;

FIG. 8 is a schematic flow chart of a reset method according to an embodiment of the present application;

FIG. 9 is a schematic diagram of signals between a master device and a slave device when the master device is in an abnormal state in an embodiment of the present application;

FIG. 10 is a flowchart of another reset method according to an embodiment of the present application;

FIG. 11 is a flowchart of another reset method according to an embodiment of the present application;

FIG. 12 is a flowchart of another reset method according to an embodiment of the present application;

FIG. 13 is a schematic structural diagram of a master device and a slave device according to an embodiment of the present application;

FIG. 14 is a flowchart of another reset method according to an embodiment of the present application;

FIG. 15 is a schematic view of a master device according to the present application;

FIG. 16 is a schematic view of a slave device according to the present application;

fig. 17 is a schematic diagram of a reset electronic device provided by the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. Wherein, in the description of the embodiments of the present application, unless otherwise indicated, "/" means or, for example, a/B may represent a or B; "and/or" herein is merely an association relationship describing an association object, and means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. In addition, in the description of the embodiments of the present application, "plurality" means two or more than two.

The terms "first," "second," "third," and the like, are used below for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", or a third "may explicitly or implicitly include one or more such feature.

For ease of understanding, the description of the concepts related to the embodiments of the application is given in part by way of example for reference.

Serial peripheral interface (SERIAL PERIPHERAL INTERFACE, SPI)

SPI refers to a synchronous serial interface technology, which is a high-speed, full-duplex synchronous communication bus. SPI generally works in a master-slave manner, and is used in a system of one master device and one or more slave devices. Typical SPI requires 4 wires for data transmission, these 4 wires including:

A chip select signal line (SLAVE SELECT/CHIP SELECT, SS/CS) for selecting a slave device that needs to communicate. The IIC master device selects the slave device needing to communicate by sending the slave device address, and the SPI master device does not need to send the slave device address and directly pulls down the corresponding slave device chip selection signal.

Serial Clock (SCK), like the SCL of IIC, clocks SPI communications. Wherein SCK may also be referred to simply as Clock (CLK).

3, Master-slave input signal lines (Master Out Slave In/SERIAL DATA Output, MOSI/SDO), which can only be used by the master to send data to the slave, i.e., master Output, slave input.

4, A master in and slave Out signal line (MASTER IN SLAVE Out/SERIAL DATA Input, MISO/SDI) is only used for the slave to send data to the master, i.e. master Input, and slave output.

Illustratively, as shown in fig. 1 (a), the master device and the slave device are connected by CS, CLK, MOSI, MISO data lines, and an interrupt signal (intterupt, INT) is also present between the master device and the slave device. After the master pulls SS low, it will send a clock signal like the slave. Illustratively, the clock signal sent by the master to the slave is a CLK signal as shown in FIG. 1 (b), comprising two time slots. The master transmits data to the slave device through the MOSI in a first time slot and receives data transmitted from the slave device through the MISO in a second time slot. During data transfer between the master and slave, the SS signal is low.

At present, SPI is generally used in electronic devices to implement data interaction between master devices and slave devices. In general, when a slave device needs to perform data interaction with a master device, an Interrupt (INT) signal (corresponding to a first signal) is transmitted to the master device, and the master device pulls down a CS signal corresponding to the slave device in response to the INT signal, and simultaneously transmits an SCK signal (clock signal) to the slave device. The slave device performs signal synchronization with the master device based on the received clock signal, and performs data interaction with the master device through MISO or MOSI. In general, the slave device has a smaller size and is greatly influenced by electromagnetic interference signals in the electronic equipment, so that in the case of abnormal data interaction between the master device and the slave device, the master device generally sends a reset instruction to the slave device so as to reset the slave device and restore the data interaction between the master device and the slave device. Then as chip technology advances, the size of the host device is also getting smaller and smaller. Meanwhile, more and more electronic devices are arranged in the electronic equipment, electromagnetic interference in the electronic equipment is more and more serious, and the main device is interfered by electromagnetic interference signals, so that the main device is hung up, and further abnormal data interaction between the main device and the auxiliary device is caused. In general, the conventional method for resetting the slave device cannot completely solve the problem of abnormal data interaction between the master device and the slave device in the electronic equipment at the present stage.

For example, in the case of normal communication between the master device and the slave device, as shown in (a) of fig. 2, when the INT signal of the slave device is low, the state of the slave device is an idle state, and the master device may perform data interaction with the slave device. The master device transmits a pulse signal on the CS at each interval for a predetermined period of time, and simultaneously, transmits a clock signal with the pulses on the CS.

When the master device receives the interference of the electromagnetic interference signal and the hang-up phenomenon occurs, as shown in (b) of fig. 2, the state of the slave device is an idle state when the INT signal of the slave device is at a low level, and the master device can perform data interaction with the slave device. The master device transmits a pulse signal on the CS at each interval for a preset period of time, but since the master device is interfered by the electromagnetic signal, the slave device can only receive the pulse signal on the CS and cannot receive the clock signal transmitted by the master device. Since the slave device cannot receive the clock signal sent by the master device, communication synchronization cannot be restored between the master device and the slave device based on the clock signal, and therefore data interaction cannot be restored between the master device and the slave device.

It should be understood that, when the main device receives the interference of the electromagnetic interference signal and the hang-up phenomenon occurs, the abnormal conditions of the CS signal, the CLK signal and the MOSI signal may also occur, which is not limited in the embodiment of the present application.

In view of the above, an embodiment of the present application provides a reset method, applied to a master device in an electronic device, where the master device is configured to send a clock signal to a slave device, where the master device and the slave device perform data interaction based on the clock signal, and send early warning information to the master device from the slave device, and when the master device receives the early warning information, the master device performs a reset operation on the master device, where the early warning information is used to indicate that the master device is in an abnormal state, so that in a trend of a chip size becoming smaller and smaller, the master device is affected by an electromagnetic interference signal in the electronic device and is in an abnormal state, a problem of hanging of the master device can be solved by the reset operation on the master device.

The resetting method provided by the embodiment of the application can be applied to electronic equipment. Optionally, the electronic device includes a terminal device, which may also be referred to as a terminal (terminal), a User Equipment (UE), a Mobile Station (MS), a Mobile Terminal (MT), and so on. The terminal device may be a mobile phone, a smart television, a wearable device, a tablet (Pad), a computer with wireless transceiving function, a Virtual Reality (VR) terminal device, an augmented reality (augmented reality, AR) terminal device, a wireless terminal in industrial control (industrial control), a wireless terminal in unmanned driving (self-driving), a wireless terminal in teleoperation (remote medical surgery), a wireless terminal in smart grid (SMART GRID), a wireless terminal in transportation security (transportation safety), a wireless terminal in smart city (SMART CITY), a wireless terminal in smart home (smart home), or the like. The embodiment of the application does not limit the specific technology and the specific equipment form adopted by the terminal equipment.

By way of example, fig. 3 shows a schematic structural diagram of the electronic device 100. The electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (universal serial bus, USB) interface 130, a charge management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, a sensor module 180, keys 190, a motor 191, an indicator 192, a camera 193, a display 194, and a subscriber identity module (subscriber identification module, SIM) card interface 195, etc. The sensor module 180 may include a pressure sensor 180A, a gyro sensor 180B, an air pressure sensor 180C, a magnetic sensor 180D, an acceleration sensor 180E, a distance sensor 180F, a proximity sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, and the like.

It should be understood that the illustrated structure of the embodiment of the present application does not constitute a specific limitation on the electronic device 100. In other embodiments of the application, electronic device 100 may include more or fewer components than shown, or certain components may be combined, or certain components may be split, or different arrangements of components. The illustrated components may be implemented in hardware, software, or a combination of software and hardware. It should be understood that the illustrated structure of the embodiment of the present application does not constitute a specific limitation on the electronic device 100. In other embodiments of the application, electronic device 100 may include more or fewer components than shown, or certain components may be combined, or certain components may be split, or different arrangements of components. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

The processor 110 may include one or more processing units, such as: the processor 110 may include an application processor (application processor, AP), a modem processor, a graphics processor (graphics processing unit, GPU), an image signal processor (IMAGE SIGNAL processor, ISP), a controller, a memory, a video codec, a digital signal processor (DIGITAL SIGNAL processor, DSP), a baseband processor, and/or a neural Network Processor (NPU), etc. Wherein the different processing units may be separate devices or may be integrated in one or more processors.

The controller may be a neural hub and a command center of the electronic device 100, among others. The controller can generate operation control signals according to the instruction operation codes and the time sequence signals to finish the control of instruction fetching and instruction execution.

A memory may also be provided in the processor 110 for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. The memory may hold instructions or data that the processor 110 has just used or recycled. If the processor 110 needs to reuse the instruction or data, it can be called directly from the memory. Repeated accesses are avoided and the latency of the processor 110 is reduced, thereby improving the efficiency of the system.

In some embodiments, the processor 110 may include one or more interfaces. The interfaces may include an integrated circuit (inter-INTEGRATED CIRCUIT, I2C) interface, an integrated circuit built-in audio (inter-INTEGRATED CIRCUIT SOUND, I2S) interface, a pulse code modulation (pulse code modulation, PCM) interface, a universal asynchronous receiver transmitter (universal asynchronous receiver/transmitter, UART) interface, a mobile industry processor interface (mobile industry processor interface, MIPI), a general-purpose input/output (GPIO) interface, a subscriber identity module (subscriber identity module, SIM) interface, and/or a universal serial bus (universal serial bus, USB) interface, among others.

It should be understood that the interfacing relationship between the modules illustrated in the embodiments of the present application is only illustrative, and is not meant to limit the structure of the electronic device 100. In other embodiments of the present application, the electronic device 100 may also employ different interfacing manners in the above embodiments, or a combination of multiple interfacing manners.

The fingerprint sensor 180H is used to collect a fingerprint. The electronic device 100 may utilize the collected fingerprint feature to unlock the fingerprint, access the application lock, photograph the fingerprint, answer the incoming call, etc.

It should be noted that any of the electronic devices mentioned in the embodiments of the present application may include more or fewer modules in the electronic device 100.

The software system of the electronic device 100 may employ a layered architecture, an event driven architecture, a microkernel architecture, a microservice architecture, or a cloud architecture. In the embodiment of the application, taking an Android system with a layered architecture as an example, a software structure of the electronic device 100 is illustrated.

Fig. 4 is a software configuration block diagram of the electronic device 100 according to the embodiment of the present application.

The layered architecture of the electronic device 100 divides the software into several layers, each with a distinct role and division of labor. The layers communicate with each other through a software interface. In some embodiments, the Android system is divided into four layers, from top to bottom, an application layer, an application framework layer, an Zhuoyun rows (Android runtime) and system libraries, and a kernel layer, respectively.

The application layer may include a series of application packages.

As shown in fig. 4, the application package may include applications for cameras, gallery, calendar, phone calls, maps, navigation, WLAN, bluetooth, music, video, short messages, etc.

The application framework layer provides an application programming interface (application programming interface, API) and programming framework for the application of the application layer. The application framework layer includes a number of predefined functions.

As shown in fig. 4, the application framework layer may include a window manager, a content provider, a view system, a telephony manager, a resource manager, a notification manager, and the like.

The window manager is used for managing window programs. The window manager can acquire the size of the display screen, judge whether a status bar exists, lock the screen, intercept the screen and the like.

The content provider is used to store and retrieve data and make such data accessible to applications. The data may include video, images, audio, calls made and received, browsing history and bookmarks, phonebooks, etc.

The view system includes visual controls, such as controls to display text, controls to display pictures, and the like. The view system may be used to build applications. The display interface may be composed of one or more views. For example, a display interface including a text message notification icon may include a view displaying text and a view displaying a picture.

The telephony manager is used to provide the communication functions of the electronic device 100. Such as the management of call status (including on, hung-up, etc.).

The resource manager provides various resources for the application program, such as localization strings, icons, pictures, layout files, video files, and the like.

The notification manager allows the application to display notification information in a status bar, can be used to communicate notification type messages, can automatically disappear after a short dwell, and does not require user interaction. Such as notification manager is used to inform that the download is complete, message alerts, etc. The notification manager may also be a notification in the form of a chart or scroll bar text that appears on the system top status bar, such as a notification of a background running application, or a notification that appears on the screen in the form of a dialog window. For example, a text message is prompted in a status bar, a prompt tone is emitted, the electronic device vibrates, and an indicator light blinks, etc.

Android run time includes a core library and virtual machines. Android runtime is responsible for scheduling and management of the android system.

The core library consists of two parts: one part is a function which needs to be called by java language, and the other part is a core library of android.

The application layer and the application framework layer run in a virtual machine. The virtual machine executes java files of the application program layer and the application program framework layer as binary files. The virtual machine is used for executing the functions of object life cycle management, stack management, thread management, security and exception management, garbage collection and the like.

The system library may include a plurality of functional modules. For example: surface manager (surface manager), media Libraries (Media Libraries), three-dimensional graphics processing Libraries (e.g., openGL ES), 2D graphics engines (e.g., SGL), etc.

The surface manager is used to manage the display subsystem and provides a fusion of 2D and 3D layers for multiple applications.

Media libraries support a variety of commonly used audio, video format playback and recording, still image files, and the like. The media library may support a variety of audio video encoding formats, such as: MPEG4, h.264, MP3, AAC, AMR, JPG, PNG, etc.

The three-dimensional graphic processing library is used for realizing three-dimensional graphic drawing, image rendering, synthesis, layer processing and the like.

The 2D graphics engine is a drawing engine for 2D drawing.

The kernel layer is a layer between hardware and software. The kernel layer at least comprises a display driver, a camera driver, an audio driver, a sensor driver, a Wi-Fi driver and the like.

It should be noted that, the electronic device according to the embodiment of the present application may include more or fewer modules in the electronic device. For example, the electronic device may also include memory, a timer, and the like.

An application scenario to which the reset method provided by the embodiment of the present application is applied is described below through fig. 5 to 7.

Fig. 5 is a schematic diagram of an application scenario in which a reset method is provided in an embodiment of the present application, where the reset method is applied to a mobile phone, and the mobile phone includes a System on Chip (SoC) and a fingerprint sensor, where the SoC is equivalent to a master device and the fingerprint sensor is equivalent to a slave device. And data interaction is performed between the SoC and the fingerprint sensor through the SPI.

Fig. 6 is a schematic diagram of an application scenario of the application of the reset method provided by the embodiment of the application, where the reset method is applied to an intelligent wearable device. The smart wearable device is an intelligent bracelet. The smart band may be as shown in fig. 6 (a) or as shown in fig. 6 (b), which is not limited in this embodiment of the present application. The intelligent bracelet comprises a micro control unit (Microcontroller Unit, MCU) and a heart rate sensor. The MCU is equivalent to a master device, the heart rate sensor is equivalent to a slave device, and data interaction is performed between the MCU and the heart rate sensor through the SPI.

It should be understood that, in the electronic device to which the reset method provided in the embodiment of the present application is applied, a system including a group of master devices and slave devices may be included, as shown in fig. 7 (a); a system of multiple sets of master and slave devices may also be included, as shown in fig. 7 (b); the embodiments of the present application are not limited in this regard. In a system composed of a set of master devices and slave devices, the number of master devices is 1, and the number of slave devices is greater than and equal to 1, as shown in (c) of fig. 7.

It should be understood that the above description of the application scenario is only an example, and does not constitute a limitation on the scenario to which the embodiments of the present application are applied.

The reset method provided by the embodiment of the application is described in detail below with reference to fig. 8 to 14.

Fig. 8 is a flow chart of a reset method provided by an embodiment of the present application, as shown in fig. 8, where the method is applied to an electronic device, the electronic device includes a master device and a slave device, the master device is configured to send a clock signal to the slave device, and data interaction is performed between the master device and the slave device based on the clock signal, and the method includes:

S101, the slave device sends early warning information to the master device, wherein the early warning information is used for indicating that the master device is in an abnormal state.

It should be appreciated that in some electronic devices, the master device is typically a more processing-power electronic device and the slave device is a less processing-power electronic device. The data interaction between the master device and the slave device can be realized through the SPI bus, wherein the slave device can conduct the data interaction based on the control signal sent by the master device. Illustratively, the master device sends a clock signal to the slave device to synchronize the slave device with the master device based on the clock signal to enable data interaction between the master device and the slave device.

Along with the continuous progress of chip technology, the size of the main device is smaller and smaller, meanwhile, more electronic devices are arranged in the electronic equipment, electromagnetic interference in the electronic equipment is serious, and the main device is also subjected to the condition that the device is hung up due to the interference of electromagnetic interference signals.

Optionally, the master device being in an abnormal state includes: in a state where the chip select CS signal is at the first level and no clock signal is sent to the slave device.

For example, in the case where the master device is jammed by the electromagnetic interference signal, as shown in (a) of fig. 9, the master device has set the CS signal corresponding to the slave device to a preset level (for example, a first level), but is unable to transmit the CLK signal to the slave device, so that the slave device cannot acquire the clock signal to synchronize with the master device, and thus data interaction between the master device and the slave device is impossible. When the slave device detects that the CS signal is at the first level but does not receive the CLK signal, the slave device judges that the master device is abnormal, and the slave device sends early warning information to the master device, wherein the early warning information is used for indicating that the master device is in an abnormal state.

It will be appreciated that in some possible cases, a master device is connected to a plurality of slave devices, each having its corresponding chip select signal line. When the level on one or more chip selection signal lines is set to be a first level by the master device, the data interaction between the master device and the slave device corresponding to the chip selection signal lines is indicated. It should be appreciated that the first level may refer to a high level or a low level, depending on the arrangement, as the embodiments of the present application are not limited in this respect.

Optionally, the master device being in an abnormal state includes: when the chip select CS signal is at the first level, no data interaction is performed between the master device and the slave device.

For example, in the case where the master device is interfered with by the electromagnetic interference signal to cause the device to hang up, as shown in (b) of fig. 9, the master device has set the CS signal corresponding to the slave device to a preset level (e.g., a first level), but there is no data transmission on MOSI and/or MISO. When the slave device detects that the CS signal is at the first level, but data transmission on the MOSI and the MISO is not detected, the slave device judges that the master device is abnormal, and the slave device sends early warning information to the master device, wherein the early warning information is used for indicating that the master device is in an abnormal state.

Optionally, the master device being in an abnormal state includes: the time taken for the chip select CS signal to transition to the first level is less than a preset time period threshold.

For example, in the case where the master device is jammed due to the interference of the electromagnetic interference signal, as shown in (c) of fig. 9, the slave device determines that the master device is in an abnormal state when detecting that the duration Δt for which the master device sets the CS signal to a preset level (first level) is less than a preset duration threshold, and the slave device transmits early warning information for indicating that the master device is in an abnormal state to the master device.

S102, when the main device receives the early warning information, resetting operation is carried out based on the early warning information.

The reset operation refers to operating the device, and the influence of the process with the operation error in the device on the operation of the device is removed. The reset operation of the device may typically be performed by powering down the device, or by clearing processes in the device. Among other things, a reset operation by powering down the device may be referred to as a hard reset operation. Resetting the device by clearing processes in the device may be referred to as a soft reset operation. When the main device receives the early warning information sent by the slave device, the main device can be powered down and restarted to finish the reset operation of the main device. The reset operation of the master device may also be accomplished by clearing the associated processes.

In some possible cases, before the slave device sends the early warning information to the master device, whether the master device is in an abnormal state can be detected, and when the master device is in the abnormal state, the early warning information can be sent to the master device. Described in detail below by way of the embodiment shown in fig. 9.

Fig. 10 is a flowchart of another reset method provided in an embodiment of the present application, where the method is applied to an electronic device, and the electronic device includes a master device and a slave device, where the master device is configured to send a clock signal to the slave device, and the master device and the slave device perform data interaction based on the clock signal, and the method includes:

S201, the slave device sends a first signal to the master device, wherein the first signal is used for requesting data interaction with the master device.

Wherein, when the slave device needs to perform data interaction with the master device, an Interrupt (INT) signal (corresponding to the first signal) is sent to the master device. When the master device receives the interrupt signal, the master device determines that the slave device can perform data interaction. At this time, the master device sets the level of the chip select signal line corresponding to the slave device to the first level and transmits a clock signal to the slave device.

S202, detecting whether a clock signal sent by a master device is received by a slave device; if the clock signal transmitted by the master is not detected, S203 is performed.

When the slave device detects that the level on the chip selection signal line is the first level, if the clock signal sent by the master device is detected, the slave device can synchronize with the master device based on the clock signal, and after synchronization, data interaction is performed with the master device; if the clock signal sent by the master device is not detected, determining that the master device is in an abnormal state.

S203, the slave device sends early warning information to the master device.

The early warning information is sent by the slave device when the chip selection CS signal is at a first level and the master device sending clock signal is not received.

S204, when the main device receives the early warning information, resetting operation is carried out based on the early warning information.

S205, the master device sends a reset instruction to the slave device, wherein the reset instruction is used for indicating the slave device to perform reset operation.

The reset operation refers to performing related operations on the electronic device, and removing the influence of the process of running errors in the device on the operation of the device. The reset operation may typically be performed by powering down the device or by clearing processes in the device. Among other things, a reset operation by powering down the device may be referred to as a hard reset operation. Resetting the device by clearing processes in the device may be referred to as a soft reset operation.

Optionally, the reset instruction includes a first reset instruction and a second reset instruction, the first reset instruction including resetting the device by triggering a reset key of the slave device.

It should be understood that the device reset by triggering the reset key of the slave device refers to a reset operation for a power-down reset of the slave device, that is, the first reset instruction may be a reset instruction by a hard reset operation.

Optionally, the second reset command includes resetting the slave device via the SPI interface.

It should be understood that resetting a slave device through the SPI interface generally refers to clearing a reset operation performed by a process in the slave device through the SPI interface, that is, the second reset instruction may refer to a reset instruction performed by a soft reset operation.

S206, the slave device performs a reset operation based on the reset instruction.

In one possible scenario, the slave device may further continue to detect whether data interaction between the master device and the slave device is performed when the CS signal is detected to be at the first level to determine whether the master device is in an abnormal state. Described in detail below by way of the embodiment shown in fig. 11.

Fig. 11 is a schematic flow chart of a reset method provided in another embodiment of the present application, where the method is applied in an electronic device, and the electronic device includes a master device and a slave device, where the master device is configured to send a clock signal to the slave device, and the master device and the slave device perform data interaction based on the clock signal, as shown in fig. 11, and the method includes:

and S301, when the slave device detects that the chip selection CS signal is at a first level, detecting whether data transmission exists on MOSI and MISO between the master device and the slave device. If not, S302 is performed.

It will be appreciated that when the CS signal is at the first level, data interaction is performed between the master device and the slave device, and at this time, if the slave device detects that there is no data transmission on both the MOSI and MISO, this means that there is no data interaction between the master device and the slave device, which is equivalent to signal anomalies on the MOSI and/or MISO. Such anomalies are created by the interference of the main device with electromagnetic interference signals. Based on this, the slave determines that the master is in an abnormal state.

S302, the slave device sends early warning information to the master device.

And S303, when the main device receives the early warning information, resetting operation is carried out based on the early warning information.

S304, the master device sends a reset instruction to the slave device, wherein the reset instruction is used for indicating the slave device to perform reset operation.

S305, the slave device performs a reset operation based on the reset instruction.

In one possible scenario, the slave device may also detect the length of time it takes for the CS signal to transition to the first level to determine whether the master device is in an abnormal state. This is explained in detail below by way of the embodiment shown in fig. 12.

Fig. 12 is a schematic flow chart of a reset method provided in another embodiment of the present application, where the method is applied in an electronic device, and the electronic device includes a master device and a slave device, and the master device is used to send a clock signal to the slave device, and the master device and the slave device perform data interaction based on the clock signal, as shown in fig. 12, and the method includes:

S401, detecting whether the time length for converting the chip selection CS signal into the first level is smaller than a preset time length threshold value or not from the device, and if yes, executing S402.

The first level is described as a low level.

It will be appreciated that when the master device is operating normally, the master device pulls down the CS signal to the first level when data interaction is required between the master device and the slave device. The time taken for the level of the CS signal to transition to the first level, i.e. the duration of the falling edge of the signal, is typically a preset duration. When the master device receives the electromagnetic interference signal and the interference is abnormal, the time length of the falling edge of the signal is generally short, so that when the time length of the falling edge of the CS signal is smaller than a preset time length threshold value, the slave device determines that the master device is in an abnormal state.

S402, the slave device sends early warning information to the master device.

S403, when the main device receives the early warning information, resetting operation is carried out based on the early warning information.

S404, the master device sends a reset instruction to the slave device, wherein the reset instruction is used for indicating the slave device to perform reset operation.

S405, the slave device performs a reset operation based on the reset instruction.

In one possible scenario, the problem of the master device may also be determined by adding a master device detection module. For example, as shown in fig. 13, the master detection module may include a CS detection sub-module, a CLK detection sub-module, a MOSI detection sub-module, and a MISO detection sub-module. The CS detection sub-module is connected with the CS signal line and is used for detecting CS signals; the CLK detection submodule is connected with the CLK signal line and used for detecting the CLK signal; the MOSI detection submodule is connected with the MOSI signal line and used for detecting MOSI signals; the MISO detection sub-module is connected with the MISO signal line and is used for detecting the MISO signal.

For example, when the master detection module detects that the level of the CS signal is pulled down (set to low), but the CLK signal line has no clock signal, it indicates that the master may be dead, so that early warning information may be sent to the master, so that the master resets the master based on the early warning information.

It should be appreciated that the master device detection module may be integrated in the master device or may be a circuit module disposed outside the master device, which is not limited in this regard by the embodiments of the present application.

In one possible case, the slave devices do not have the function of detecting the clock signal because of weak processing capability of some slave devices, and in this case, the master device can directly perform the reset operation on the master device, without performing the reset operation on the master device when receiving the early warning information sent by the slave device. The following is a detailed description of the embodiment shown in fig. 14.

Fig. 14 is a schematic flow chart of a reset method provided in another embodiment of the present application, where the method is applied in an electronic device, and the electronic device includes a master device and a slave device, and the master device is configured to send a clock signal to the slave device, and the master device and the slave device perform data interaction based on the clock signal, and the method includes:

S501, when the main device detects that the signal on the data line is abnormal, resetting the main device.

It should be understood that the data lines may include the CS signal line, the CLK signal line, the MOSI signal line, and the MISO signal line shown in FIG. 1. When the main device detects that any signal line is abnormal, the main device is reset.

It should be understood that the signal abnormality occurring on any data line may be caused by the master device being in an abnormal state or may be caused by the slave device being in an abnormal state. This is equivalent to the fact that the master device performs a reset operation on itself whenever there is an abnormality in data interaction between the master device and the slave device. That is, there is no need for the slave device to detect whether the master device is in an abnormal state.

S502, the master device sends a reset instruction to the slave device.

S503, the slave device performs a reset operation based on the reset instruction.

The reset method provided by the embodiment of the application is applied to electronic equipment, the electronic equipment comprises a master device and a slave device, the master device is used for sending clock signals to the slave device, and data interaction is carried out between the master device and the slave device based on the clock signals, and the method comprises the following steps: when the master device detects that the signal on the data line is abnormal, the master device is reset, then the master device sends a reset instruction to the slave device, and the slave device performs reset operation based on the reset instruction. According to the reset method provided by the embodiment of the application, the slave device is not required to detect whether the master device is in an abnormal state, so that the reset operation can be actively carried out on the slave device through the master device under the condition that the slave device cannot detect whether the master device is in the abnormal state or not due to weak processing capacity of the slave device, the problem of device hanging of the master device is solved, and further, the data interaction between the electronic devices can be effectively recovered.

It should be understood that, although the steps in the flowcharts in the above embodiments are sequentially shown as indicated by arrows, these steps are not necessarily sequentially performed in the order indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in the flowcharts may include a plurality of sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, the order in which the sub-steps or stages are performed is not necessarily sequential, and may be performed in turn or alternately with at least a portion of the sub-steps or stages of other steps or other steps.

Fig. 15 is a schematic structural diagram of a master device 500 according to an embodiment of the present application.

It should be understood that the master device 500 may perform the reset methods shown in fig. 8 to 14; the master device 500 includes: an acquisition unit 510 and a processing unit 520.

The processing unit 520 is configured to receive early warning information sent by the slave device, where the early warning information is used to indicate that the master device is in an abnormal state;

The processing unit 520 is configured to perform a reset operation according to the early warning information.

In one embodiment, the processing unit 520 is further configured to send a reset instruction to the slave device, where the reset instruction is configured to instruct the slave device to perform a reset operation.

In one embodiment, the reset instruction includes a first reset instruction for instructing device reset by triggering a reset key of the slave device or a second reset instruction for instructing device reset of the slave device through the serial peripheral interface SPI interface.

The main device provided in this embodiment is configured to execute the reset method in the foregoing embodiment, and the technical principles and technical effects are similar and are not described herein again.

The master device 500 is embodied as a functional unit. The term "unit" herein may be implemented in software and/or hardware, without specific limitation.

For example, a "unit" may be a software program, a hardware circuit or a combination of both that implements the functions described above. The hardware circuitry may include Application Specific Integrated Circuits (ASICs), electronic circuits, processors (e.g., shared, proprietary, or group processors, etc.) and memory for executing one or more software or firmware programs, merged logic circuits, and/or other suitable components that support the described functions.

Thus, the elements of the examples described in the embodiments of the present application can be implemented in electronic hardware, or in a combination of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

Fig. 16 is a schematic structural diagram of a slave device 600 according to an embodiment of the present application.

It should be appreciated that the reset method shown in fig. 8-14 may be performed from device 600; the slave device 600 includes: an acquisition unit 610 and a processing unit 620.

The processing unit 620 is configured to detect that the master device is in an abnormal state;

The processing unit 620 is configured to send early warning information to the master device, where the early warning information is used to indicate that the master device is in an abnormal state.

In one embodiment, the processing unit 620 is configured to send a first signal to the master device, where the first signal is used to request data interaction with the master device; detecting whether a clock signal sent by a main device is received or not; if the clock signal sent by the master device is not detected, determining that the master device is in an abnormal state.

The slave device provided in this embodiment is configured to perform the reset method in the foregoing embodiment, and the technical principle and the technical effect are similar and are not described herein again.

The slave device 600 is embodied as a functional unit. The term "unit" herein may be implemented in software and/or hardware, without specific limitation.

Fig. 17 shows a schematic structural diagram of an electronic device provided by the present application. The dashed line in fig. 17 indicates that the unit or the module is optional. The electronic device 700 may be used to implement the reset method described in the method embodiments described above.

The electronic device 700 includes one or more processors 701, which one or more processors 701 may support the electronic device 700 to implement the reset method in the method embodiments. The processor 701 may be a general-purpose processor or a special-purpose processor. For example, the processor 701 may be a central processing unit (central processing unit, CPU), a digital signal processor (DIGITAL SIGNAL processor, DSP), an Application Specific Integrated Circuit (ASIC), a field programmable gate array (field programmable GATE ARRAY, FPGA), or other programmable logic device such as discrete gates, transistor logic, or discrete hardware components.

The processor 701 may be used to control the electronic device 700, execute a software program, and process data of the software program. The electronic device 700 may further comprise a communication unit 705 for enabling input (reception) and output (transmission) of signals.

For example, the electronic device 700 may be a chip, the communication unit 705 may be an input and/or output circuit of the chip, or the communication unit 705 may be a communication interface of the chip, which may be an integral part of a terminal device or other electronic device.

For another example, the electronic device 700 may be a terminal device, the communication unit 705 may be a transceiver of the terminal device, or the communication unit 705 may be a transceiver circuit of the terminal device.

The electronic device 700 may include one or more memories 702 having a program 704 stored thereon, the program 704 being executable by the processor 701 to generate instructions 703 such that the processor 701 performs the impedance matching method described in the above method embodiments according to the instructions 703.

Optionally, the memory 702 may also have data stored therein. Alternatively, processor 701 may also read data stored in memory 702, which may be stored at the same memory address as program 704, or which may be stored at a different memory address than program 704.

The processor 701 and the memory 702 may be provided separately or may be integrated together; for example, integrated on a System On Chip (SOC) of the terminal device.

Illustratively, the memory 702 may be used to store a related program 704 of the reset method provided in the embodiment of the present application, and the processor 701 may be used to call the related program 704 of the reset method stored in the memory 702 when performing the reset, to execute the reset method of the embodiment of the present application; comprising the following steps: receiving early warning information sent by the slave device, wherein the early warning information is used for indicating that the master device is in an abnormal state; and resetting according to the early warning information.

Illustratively, the memory 702 may be used to store a related program 704 of the reset method provided in the embodiment of the present application, and the processor 701 may be used to call the related program 704 of the reset method stored in the memory 702 when performing the reset, to execute the reset method of the embodiment of the present application; comprising the following steps: detecting that the main device is in an abnormal state; and sending early warning information to the main device, wherein the early warning information is used for indicating that the main device is in an abnormal state.

The present application also provides a computer program product which, when executed by the processor 701, implements the reset method of any of the method embodiments of the present application.

The computer program product may be stored in the memory 702, for example, the program 704, and the program 704 is finally converted into an executable object file capable of being executed by the processor 701 through preprocessing, compiling, assembling, and linking.

The application also provides a computer readable storage medium having stored thereon a computer program which when executed by a computer implements the reset method of any of the method embodiments of the application. The computer program may be a high-level language program or an executable object program.

Such as memory 702. The memory 702 may be volatile memory or nonvolatile memory, or the memory 702 may include both volatile and nonvolatile memory. The nonvolatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an erasable programmable ROM (erasable PROM), an electrically erasable programmable EPROM (EEPROM), or a flash memory. The volatile memory may be random access memory (random access memory, RAM) which acts as external cache memory. By way of example, and not limitation, many forms of RAM are available, such as static random access memory (STATIC RAM, SRAM), dynamic random access memory (DYNAMIC RAM, DRAM), synchronous Dynamic Random Access Memory (SDRAM), double data rate synchronous dynamic random access memory (double DATA RATE SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (ENHANCED SDRAM, ESDRAM), synchronous link dynamic random access memory (SYNCHLINK DRAM, SLDRAM), and direct memory bus random access memory (direct rambus RAM, DR RAM).

In the present application, "at least one" means one or more, and "a plurality" means two or more. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b, or c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or plural.

It should be understood that, in various embodiments of the present application, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by the functions and internal logic thereof, and should not constitute any limitation on the implementation process of the embodiments of the present application.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.

In the several embodiments provided by the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the device embodiments described above are merely illustrative; for example, the division of the units is only one logic function division, and other division modes can be adopted in actual implementation; for example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The foregoing is merely illustrative embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about variations or substitutions within the technical scope of the present application, and the application should be covered. Therefore, the protection scope of the application is subject to the protection scope of the claims.

Claims

1. A reset method, wherein the method is applied to a master device in an electronic device, the master device is used for sending a clock signal to a slave device, the master device and the slave device perform data interaction based on the clock signal, and the electronic device comprises the master device and the slave device, and the method comprises:

receiving early warning information sent by the slave device, wherein the early warning information is used for indicating that the master device is in an abnormal state;

And resetting according to the early warning information.

2. The method of claim 1, wherein the master device being in an abnormal state comprises: in a state where the chip select CS signal is at a first level and the clock signal is not sent to the slave device.

3. The method of claim 1, wherein the master device being in an abnormal state comprises: and when the chip selection CS signal is at a first level, data interaction between the master device and the slave device is not performed.

4. The method of claim 1, wherein the master device being in an abnormal state comprises: the time taken for the chip select CS signal to transition to the first level is less than a preset time period threshold.

5. The method according to any one of claims 1 to 4, further comprising:

And sending a reset instruction to the slave device, wherein the reset instruction is used for indicating the slave device to perform reset operation.

6. The method of claim 5, wherein the reset instruction comprises a first reset instruction or a second reset instruction, the first reset instruction being for instructing a device reset by triggering a reset key of the slave device, the second reset instruction being for instructing a device reset of the slave device through a serial peripheral interface, SPI, interface.

7. A reset method, wherein the method is applied to a slave device in an electronic apparatus, the electronic apparatus includes a master device and the slave device, the master device is used for transmitting a clock signal to the slave device, and data interaction is performed between the master device and the slave device based on the clock signal, the method includes:

Detecting that the main device is in an abnormal state;

8. The method of claim 7, wherein the detecting that the master device is in an abnormal state comprises:

transmitting a first signal to the master device, wherein the first signal is used for requesting data interaction with the master device;

Detecting whether the clock signal sent by the master device is received or not;

And if the clock signal sent by the master device is not detected, determining that the master device is in the abnormal state.

9. The method of claim 7, wherein the detecting that the master device is in an abnormal state comprises:

when the chip selection CS signal is detected to be at a first level, the data transmission on a master-slave signal line MOSI and a master-slave signal line MISO between the master device and the slave device is not detected, and the master device is determined to be in an abnormal state.

10. The method of claim 7, wherein the detecting that the master device is in an abnormal state comprises:

And if the time length for converting the chip selection CS signal into the first level is detected to be smaller than the preset time length threshold value, determining that the main device is in an abnormal state.

11. An electronic device comprising a processor and a memory for storing a computer program, the processor being adapted to call and run the computer program from the memory, such that the electronic device performs the method of any of claims 1 to 6.

12. An electronic device comprising a processor and a memory for storing a computer program, the processor being adapted to invoke and run the computer program from the memory, such that the electronic device performs the method of any of claims 7 to 10.

13. An electronic device comprising a master device for performing the method of any one of claims 1 to 6 and a slave device for performing the method of any one of claims 7 to 10.

14. The electronic device of claim 13, wherein the electronic device comprises a cell phone or tablet, the master device comprises a system on chip, SOC, and the slave device comprises a fingerprint sensor.

15. The electronic device of claim 13, wherein the electronic device comprises a smart wearable device, the master device comprises a micro control unit, MCU, and the slave device comprises a heart rate sensor.

16. A computer readable storage medium, characterized in that the computer readable storage medium stores a computer program, which when executed by a processor causes the processor to perform the method of any one of claims 1 to 6 or causes the processor to perform the method of any one of claims 7 to 10.