CN117936600A - Solar cell and photovoltaic module - Google Patents
Solar cell and photovoltaic module Download PDFInfo
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- CN117936600A CN117936600A CN202410064739.2A CN202410064739A CN117936600A CN 117936600 A CN117936600 A CN 117936600A CN 202410064739 A CN202410064739 A CN 202410064739A CN 117936600 A CN117936600 A CN 117936600A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/042—PV modules or arrays of single PV cells
- H01L31/048—Encapsulation of modules
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The application relates to a solar cell and a photovoltaic module, which comprises: a semiconductor substrate including a front surface and a back surface disposed opposite to each other; the semiconductor device comprises a doped conductive layer positioned on the front surface of a semiconductor substrate, a front surface passivation layer and a plurality of grid line electrode groups arranged on the front surface passivation layer, wherein each grid line electrode group comprises a first front surface grid line electrode and a second front surface grid line electrode which are adjacently arranged, and the doping amount of the doped conductive layer is gradually decreased from the first front surface grid line electrode to a symmetrical central area of the first front surface grid line electrode and the second front surface grid line electrode; and a back passivation layer and a back gate line electrode positioned on the back surface of the semiconductor substrate. The doped conductive layer of the solar cell gradually increases the current from the symmetrical central area of the first front grid line electrode and the second front grid line electrode to the first front grid line electrode, and gradually reduces the transmission resistance, so that the current is favorably transmitted transversely in the doped conductive layer, the series resistance is reduced, and the cell efficiency is improved.
Description
The application is claimed in the 28 th year of 2022, which is filed by Chinese patent office under the application number 202210751677.3, the application name of which is the divisional application of the Chinese patent application of solar cell, preparation method thereof and photovoltaic module, and the whole content of which is incorporated by reference.
[ Field of technology ]
The application relates to the technical field of solar photovoltaic modules, in particular to a solar cell and a photovoltaic module.
[ Background Art ]
In crystalline silicon solar cells, the uniformly doped layer in contact with the electrode cannot meet the requirements in two ways simultaneously: on one hand, light doping is needed to reduce Auger recombination and Shockley-Read-Hall recombination, so that the spectral response of a short wave band is improved; on the other hand, high surface concentration is required to be formed by heavy doping, so that ohmic contact is formed between the silicon chip and the metal electrode. Selective doping is often achieved using localized doping techniques to improve cell efficiency.
The local doping technique acts on the emitter, enabling a selective emitter (SE, SELECTIVE EMITTER); the local doping technology acts on the back surface field to realize the contact between the local back surface field and the local electrode, however, the existing selective emitter cannot well match the transmission requirement of current, the reduction of series resistance is limited, and the efficiency improvement of the solar cell is limited.
[ Invention ]
In order to overcome the defects, the application provides a solar cell and a photovoltaic module, which can improve the transverse transmission of current, reduce series resistance and further improve the cell efficiency.
In a first aspect, an embodiment of the present application provides a solar cell, including:
a semiconductor substrate including a front surface and a back surface disposed opposite to each other;
The semiconductor substrate comprises a doped conductive layer, a front passivation layer and a plurality of grid line electrode groups arranged on the front passivation layer, wherein the grid line electrode groups comprise a first front grid line electrode and a second front grid line electrode which are adjacently arranged, the doping amount of the doped conductive layer is gradually decreased from the first front grid line electrode to the symmetrical central area of the first front grid line electrode and the symmetrical central area of the second front grid line electrode, and/or the doping amount of the doped conductive layer is gradually decreased from the second front grid line electrode to the symmetrical central area of the first front grid line electrode and the symmetrical central area of the second front grid line electrode;
and the back passivation layer and the back grid line electrode are positioned on the back of the semiconductor substrate.
In combination with the first aspect, the doping concentration of the doped conductive layer decreases from the first front-side gate line electrode to the symmetric central area of the first front-side gate line electrode and the second front-side gate line electrode in sequence, and/or the doping concentration of the doped conductive layer decreases from the second front-side gate line electrode to the symmetric central area of the first front-side gate line electrode and the second front-side gate line electrode in sequence.
With reference to the first aspect, the thickness of the doped conductive layer decreases from the first front-side gate line electrode to the symmetric central area of the first front-side gate line electrode and the second front-side gate line electrode in sequence, and/or the thickness of the doped conductive layer decreases from the second front-side gate line electrode to the symmetric central area of the first front-side gate line electrode and the second front-side gate line electrode in sequence.
In combination with the first aspect, the height of the front passivation layer decreases from the first front gate line electrode to the symmetric central area of the first front gate line electrode and the second front gate line electrode in sequence, and/or the height of the front passivation layer decreases from the second front gate line electrode to the symmetric central area of the first front gate line electrode and the second front gate line electrode in sequence.
With reference to the first aspect, the symmetric central area of the doped conductive layer from the first front-side gate line electrode to the first front-side gate line electrode and the second front-side gate line electrode comprises N doped conductive areas, wherein N is greater than or equal to 3, and the lengths of the N doped conductive areas decrease sequentially from the first front-side gate line electrode to the symmetric central area of the first front-side gate line electrode and the second front-side gate line electrode; and/or the lengths of the N doped conductive areas are sequentially decreased from the second front-side grid line electrode to the symmetric central areas of the first front-side grid line electrode and the second front-side grid line electrode.
With reference to the first aspect, the doping element in the doped conductive layer includes at least one of boron, gallium, phosphorus, and arsenic.
With reference to the first aspect, the doping concentration difference of the doped conductive layers is 1e18 cm -3～9E20cm-3.
With reference to the first aspect, the doping concentration of the doped conductive layer at the bottom of the first front gate line electrode is 1e19 cm -3～1E21 cm-3; and/or the doping concentration of the doped conductive layer at the bottom of the second front-side grid line electrode is 1E19 cm -3～1E21cm-3.
In a second aspect, an embodiment of the present application provides a photovoltaic module, where the photovoltaic module includes a cover plate, an encapsulating material layer, and a solar cell string, where the solar cell string includes a plurality of solar cells according to the first aspect.
Compared with the prior art, the application has the following steps:
According to the application, the doping amount of the doped conductive layer is gradually decreased from the first front grid line electrode to the symmetrical central area of the first front grid line electrode and the second front grid line electrode, namely the doping area from the first front grid line electrode to the symmetrical central area of the first front grid line electrode and the second front grid line electrode is gradually decreased, so that the current of the doped conductive layer from the symmetrical central area of the first front grid line electrode and the second front grid line electrode to the first front grid line electrode is gradually increased, the transmission resistance is gradually decreased, and the transverse transmission of the current in the doped conductive layer is facilitated, the series resistance is reduced, and the battery efficiency is improved. Similarly, the doping amount of the doped conductive layer is gradually decreased from the second front grid line electrode to the symmetric central area of the first front grid line electrode and the symmetric central area of the second front grid line electrode, so that the transverse transmission of current in the doped conductive layer can be facilitated, the series resistance is reduced, and the battery efficiency is improved. The solar cell provided by the application can further realize gradient doping on the basis of realizing selective doping, and can obviously improve the conversion efficiency of the solar cell.
Additional features and advantages of embodiments of the application will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of embodiments of the application. The objectives and other advantages of embodiments of the application will be realized and attained by the structure particularly pointed out in the written description and drawings.
[ Description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a solar cell according to the present application;
FIG. 2 is a schematic diagram of a solar cell according to the present application;
FIG. 3 is a schematic diagram of a solar cell according to the present application;
FIG. 4 is a schematic diagram of a doped conductive layer with varying thickness of a solar cell according to the present application;
FIG. 5 is a flow chart of the preparation of the solar cell of the present application;
FIG. 6 is a schematic view of a semiconductor substrate according to the present application;
FIG. 7 is a schematic diagram of a structure of forming a heavily doped layer on a surface of a semiconductor substrate according to the present application;
FIG. 8 is a schematic diagram of a doped conductive layer with varying thickness prepared by laser thinning of a heavily doped layer according to the present application;
Fig. 9 is a schematic view of a structure of forming front passivation layers and back passivation layers on front and back surfaces of a semiconductor substrate according to the present application;
FIG. 10 is a schematic diagram of a structure of a doped conductive layer with varying doping concentration according to the present application;
Fig. 11 is a schematic structural view of the photovoltaic module of the present application.
Reference numerals:
1-a semiconductor substrate;
2-doping the conductive layer;
3-a front side passivation layer;
4-front gate line electrode group;
41-a first front-side gate line electrode;
42-a second front side gate line electrode;
5-a backside passivation layer;
6-a back gate line electrode;
7-a heavily doped layer;
8-symmetric central regions of the first front-side gate line electrode and the second front-side gate line electrode;
1000-photovoltaic module;
100-solar cell;
200-a first cover plate;
300-a first packaging adhesive layer;
400-a second packaging adhesive layer;
500-second cover plate.
[ Detailed description ] of the invention
For a better understanding of the technical solution of the present invention, the following detailed description of the embodiments of the present invention refers to the accompanying drawings.
It should be understood that the described embodiments are merely some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
It should be noted that, the terms "upper", "lower", "left", "right", and the like in the embodiments of the present application are described in terms of the angles shown in the drawings, and should not be construed as limiting the embodiments of the present application. In the context of this document, it will also be understood that when an element is referred to as being "on" or "under" another element, it can be directly on the other element or be indirectly on the other element through intervening elements.
It should be noted that the steps illustrated in the flowcharts of the figures may be performed in a computer system such as a set of computer executable instructions, and that although a logical order is illustrated in the flowcharts, the order of the steps of the embodiments is not limited to being performed in order according to the order in which they are arranged in the present specification, and in some cases, the steps may be performed in an order different from that shown or described herein, as appropriate.
In crystalline silicon solar cells, the uniformly doped layer in contact with the electrode cannot simultaneously meet the requirements of reducing recombination and improving ohmic contact of the silicon wafer and the metal electrode, and further, selective emitters have been developed, i.e. selective doping is realized by adopting a local doping technology so as to improve the cell efficiency. The existing selective emitter, the doped conductive layer forms high doping in the metal electrode area, good ohmic contact is realized, series resistance is reduced, low doping is formed in the non-metal electrode area, auger recombination and shock-Read-Hall recombination are reduced, and the spectral response of a short wave band is improved, so that the battery efficiency is improved.
However, the conventional selective emitter forms a uniform low-doped region in a non-metal electrode region, and cannot well match the current transmission requirement, so that the reduction of the series resistance is limited, and the efficiency is improved.
Therefore, in order to further improve the conversion efficiency of the solar cell, the present application proposes a solar cell, as shown in fig. 1, comprising:
A semiconductor substrate 1, the semiconductor substrate 1 including a front surface and a back surface disposed opposite to each other;
The doped conductive layer 2, the front passivation layer 3 and the plurality of grid line electrode groups 4 arranged on the front passivation layer 3 are positioned on the front surface of the semiconductor substrate 1, wherein the grid line electrode groups 4 comprise a first front surface grid line electrode 41 and a second front surface grid line electrode 42 which are adjacently arranged, the doping amount of the doped conductive layer 2 is gradually decreased from the first front surface grid line electrode 41 to a symmetrical central area 8 of the first front surface grid line electrode 41 and the second front surface grid line electrode 42, and/or the doping amount of the doped conductive layer 2 is gradually decreased from the second front surface grid line electrode 42 to the symmetrical central area 8 of the first front surface grid line electrode 41 and the second front surface grid line electrode 42;
a back passivation layer 5 and a back gate line electrode 6 on the back surface of the semiconductor substrate 1.
In the above scheme, the doping amount of the doped conductive layer 2 is gradually decreased from the first front grid line electrode 41 to the symmetric central area 8 of the first front grid line electrode 41 and the second front grid line electrode 42, that is, the doping areas of the first front grid line electrode 41 to the symmetric central area 8 of the first front grid line electrode 41 and the second front grid line electrode 42 are gradually decreased, so that the current of the doped conductive layer 2 from the symmetric central area 8 of the first front grid line electrode 41 and the second front grid line electrode 42 to the first front grid line electrode 41 gradually increases, and the transmission resistance gradually decreases, thereby facilitating the transverse transmission of the current in the doped conductive layer 2, reducing the series resistance and improving the battery efficiency. Similarly, the doping amount of the doped conductive layer 2 decreases from the second front-side gate line electrode 42 to the symmetric central region 8 of the first front-side gate line electrode 41 and the second front-side gate line electrode 42 in sequence, which is also beneficial to the transverse transmission of current in the doped conductive layer 2, thereby reducing the series resistance and improving the battery efficiency. The solar cell provided by the application can further realize gradient doping on the basis of realizing selective doping, and can obviously improve the conversion efficiency of the solar cell.
It is understood that the symmetric center region 8 of the first front-side gate line electrode 41 and the second front-side gate line electrode 42 refers to a region near the symmetry axes of the first front-side gate line electrode 41 and the second front-side gate line electrode 42. Preferably, the symmetric center region 8 of the first front-side gate line electrode 41 and the second front-side gate line electrode 42 refers to a region formed by the symmetry axes of the first front-side gate line electrode 41 and the second front-side gate line electrode 42.
In some embodiments, as shown in fig. 2, the doping amount of the doped conductive layer 2 decreases sequentially from the first front side gate line electrode 41 to the symmetry axis of the first front side gate line electrode 41 and the second front side gate line electrode 42, and/or the doping amount of the doped conductive layer 2 decreases sequentially from the second front side gate line electrode 42 to the symmetry axis of the first front side gate line electrode 41 and the second front side gate line electrode 42.
In the application, the solar cell further comprises a plurality of front main grid lines positioned on the front passivation layer, the grid line electrode group 4 refers to an electrode group formed by two adjacent auxiliary grid lines, the main grid lines are perpendicular to the auxiliary grid lines, the auxiliary grid lines collect current and transmit the current to the main grid lines, and the main grid lines are directly connected with external leads of the cell.
The front surface of the semiconductor substrate 1 is a surface facing the sun (i.e., a light receiving surface), and the back surface of the semiconductor substrate 1 is a surface facing away from the sun (i.e., a back surface).
In some embodiments, the semiconductor substrate 1 is an N-type silicon substrate (or silicon wafer), and may also be a P-type silicon substrate (or silicon wafer), where the N-type silicon substrate is one of a polysilicon substrate, a monocrystalline silicon substrate, a microcrystalline silicon substrate, or a silicon carbide substrate, and the P-type silicon substrate is one of a polysilicon substrate, a monocrystalline silicon substrate, a microcrystalline silicon substrate, or a silicon carbide substrate, and the specific type of the semiconductor substrate 1 is not limited by the embodiments of the present application.
In some embodiments, the thickness of the semiconductor substrate 1 is 60 μm to 240 μm, specifically 60 μm, 80 μm, 90 μm, 100 μm, 120 μm, 150 μm, 200 μm, 240 μm, or the like, and is not limited herein.
In some embodiments, an emitter (emitter not shown in the drawing) may be formed on the surface of the doped conductive layer 2 as required. The emitter is a P-type emitter or an N-type emitter, and when the semiconductor substrate 1 is an N-type silicon substrate, the emitter is a P-type emitter, and the P-type emitter is a boron-doped diffusion layer or a gallium-doped diffusion layer; when the semiconductor substrate 1 is a P-type silicon substrate, the emitter is an N-type emitter, the N-type emitter is a boron-doped diffusion layer or a gallium-doped diffusion layer, and the boron-doped diffusion layer, the gallium-doped diffusion layer, the boron-doped diffusion layer and the gallium-doped diffusion layer are all emitters formed by diffusing doping source atoms to a certain depth on the front surface through a diffusion process by utilizing corresponding doping sources. Illustratively, when preparing the boron doped diffusion layer, the doping source may be liquid boron tribromide or boron trichloride.
In some embodiments, the doping amount of the doped conductive layer 2 between the adjacent first front side gate line electrode 41 and the second front side gate line electrode 42 is decreased and increased. I.e. the doping amount of the conductive doped layer 2 at the bottom of the first front gate line electrode 41 or the conductive doped layer 2 at the bottom of the second front gate line electrode 42 is maximized.
It will be appreciated that the doped conductive layer 2 may also be formed as an emitter, either inside the semiconductor substrate 1 as a whole with the semiconductor substrate 1, or, of course, outside the semiconductor substrate 1 as a separate layer structure.
In some embodiments, since during the operation of the solar cell, the current will be transmitted laterally along the doped conductive layer 2 on the surface of the semiconductor substrate 1 and finally collected by the electrode, in order to improve the transmission of the current in the doped conductive layer, the doping amount of the region close to the gate line electrode needs to be larger, the doping amount of the region far from the gate line electrode is smaller, and the doped conductive layer can form a certain gradient, so as to be beneficial to the transmission of the current, therefore, in order to meet the requirement of the doping amount, the application is implemented by the following specific ways:
As shown in fig. 3, the doping concentration of the doped conductive layer 2 is gradually decreased from the first front gate line electrode 41 to the symmetric central area 8 of the first front gate line electrode 41 and the second front gate line electrode 42, so that the doped conductive layer is gradually decreased from the first front gate line electrode 41 to the symmetric central area 8 of the first front gate line electrode 41 and the second front gate line electrode 42, the total doping amount is gradually decreased, the current is gradually increased, and the transmission resistance is gradually decreased, thereby being beneficial to the transverse transmission of the current in the doped conductive layer 2, improving the filling factor and further improving the battery efficiency. For the same reason, the application can also limit the doping concentration of the doped conductive layer 2 to gradually decrease from the second front grid line electrode 42 to the symmetric central area 8 of the first front grid line electrode 41 and the second front grid line electrode 42, so that the doping amount of the doped conductive layer 2 gradually decreases from the first front grid line electrode 41 to the symmetric central area 8 of the first front grid line electrode 41 and the second front grid line electrode 42, thereby being beneficial to the transverse transmission of current in the doped conductive layer 2, improving the filling factor and further improving the battery efficiency. Of course, the doping concentration distribution of the doped conductive layer 2 is controlled at the same time, so that the doping concentration of the doped conductive layer 2 is reduced from the first front-side gate line electrode 41 to the second front-side electrode gate line 42 and then increased, that is, the transmission resistance of the symmetric central area of the first front-side gate line electrode 41 to the second front-side electrode gate is minimum, which is beneficial to the current transmission to the first front-side gate line electrode 41 and the second front-side electrode gate line 42, thereby improving the filling factor and further improving the battery efficiency. Of course, the center area 8 of symmetry of the first front gate line electrode 41 and the second front gate line electrode 42 may be the symmetry axis of the first gate line electrode 41 and the second gate line electrode 42.
According to the application, the thickness of the doped conductive layer 2 is gradually decreased from the first front grid line electrode 41 to the symmetrical central area 8 of the first front grid line electrode 41 and the second front grid line electrode 42, so that the doping amount of the doped conductive layer 2 is gradually decreased from the first front grid line electrode 41 to the symmetrical central area 8 of the first front grid line electrode 41 and the second front grid line electrode 42, the transverse transmission of current in the doped conductive layer 2 is facilitated, the filling factor is improved, and the battery efficiency is further improved. Illustratively, as shown in fig. 4, the thickness of the doped conductive layer 2 is L1, L2, and L3 in order from the first front surface gate line electrode 41 to the symmetric central region 8 of the first front surface gate line electrode 41 and the second front surface gate line electrode 42, and L1 > L2 > L3, so that the doping amount of the doped conductive layer 2 decreases in order from the first front surface gate line electrode 41 to the symmetric central region 8 of the first front surface gate line electrode 41 and the second front surface gate line electrode 42. For the same reason, the thickness of the doped conductive layer 2 can be controlled to be gradually decreased from the second front-side grid line electrode 42 to the symmetrical central area 8 of the first front-side grid line electrode 41 and the second front-side grid line electrode 42, so that the transverse transmission of current in the doped conductive layer 2 is improved, the filling factor is improved, and the battery efficiency is further improved. Of course, the thickness distribution of the doped conductive layer 2 is controlled simultaneously, so that the thickness of the doped conductive layer 2 is reduced from the first front-side gate line electrode 41 to the second front-side electrode gate line 42 and then increased, the doping amount of the symmetric central area of the first front-side gate line electrode 41 to the second front-side electrode gate is minimum, that is, the transmission resistance is minimum, and the current is beneficial to being transmitted to the first front-side gate line electrode 41 and the second front-side electrode gate line 42, thereby improving the filling factor and further improving the battery efficiency.
In some embodiments, when the thickness of the doped conductive layer 2 decreases from the first front gate line electrode 41 to the symmetric central region 8 of the first front gate line electrode 41 and the second front gate line electrode 42, the height of the front passivation layer 3 decreases from the first front gate line electrode 41 to the symmetric central region 8 of the first front gate line electrode 41 and the second front gate line electrode 42 in sequence, that is, the front passivation layer 3 presents a certain gradient height because the front passivation layer 3 is disposed on the surface of the doped conductive layer 2; when the thickness of the doped conductive layer 2 decreases in sequence from the second front-side gate line electrode 42 to the symmetric central region 8 of the first front-side gate line electrode 41 and the second front-side gate line electrode 42, the height of the front passivation layer 3 decreases in sequence from the second front-side gate line electrode 42 to the symmetric central region 8 of the first front-side gate line electrode 41 and the second front-side gate line electrode 42.
It can be understood that the thickness gradient change of the doped conductive layer 2 and the doping concentration change of the doped conductive layer 2 can be set singly or in combination, so that the doping amount of the doped conductive layer 2 is reduced from the first front surface grid line electrode 41 to the second front surface electrode grid line 42 and then increased, and the doping amount of the symmetric central region 8 of the first front surface grid line electrode 41 to the second front surface electrode grid is minimum.
In some embodiments, the doping element in the doped conductive layer 2 includes at least one of boron, gallium, phosphorus, and arsenic. When the semiconductor substrate 1 is an N-type substrate, the doping element in the doped conductive layer 2 includes at least one of boron and gallium; when the semiconductor substrate 1 is a P-type substrate, the doping element in the doped conductive layer 2 includes at least one of phosphorus and arsenic.
In some embodiments, the doping concentration difference of the doped conductive layer 2 is 1e18 cm -3～9E20 cm-3, for example, 1E18 cm-3、5E18 cm-3、1E19 cm-3、5E19 cm-3、1E20 cm-3、5E20 cm-3 and 9e20 cm -3, and the doping concentration difference of the doped conductive layer 2 is controlled within the above range, so that the lateral resistance loss is ensured to be smaller while the current and the on-voltage are improved.
In some embodiments, the doping concentration of the doped conductive layer 2 at the bottom of the first front gate line electrode 41 is 1E19cm -3～1E21 cm-3, for example, 1E19cm -3、5E19 cm-3、1E20 cm-3、5E20 cm-3 and 1E21 cm -3, the doping concentration of the doped conductive layer 2 at the second front gate line electrode 42 is 1E19cm -3～1E 21cm-3, for example, 1E19cm -3、5E19 cm-3、1E20 cm-3、5E20 cm-3 and 1E21 cm -3, and by controlling the doping concentration of the doped conductive layer 2 at the gate line electrode within the above range, the application ensures that the doped conductive layer 2 between the semiconductor substrate 1 and the gate line electrode is heavily doped, thereby facilitating the formation of good ohmic contact between the semiconductor substrate 1 and the gate line electrode.
In some embodiments, the front passivation layer 3 may include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, etc., or any combination thereof, and the front passivation layer 3 can generate a good passivation effect on the semiconductor substrate 1, which helps to improve the conversion efficiency of the battery. It should be noted that the front passivation layer 3 may also function to reduce reflection of incident light, and may also be referred to as an anti-reflection layer in some examples.
In some embodiments, the thickness of the front passivation layer 3 ranges from 10nm to 120nm, specifically, 10nm, 20nm, 30nm, 42nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, or 120nm, etc., but other values within the above range are also possible, and the present invention is not limited thereto.
In some embodiments, the back passivation layer 5 may include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like, or any combination thereof. When the back passivation layer 5 is a stacked silicon nitride layer and silicon oxide layer or a stacked silicon nitride layer and silicon oxynitride layer, the silicon nitride layer is located on the surface of the doped conductive layer, and the silicon oxide layer or the silicon oxynitride layer is located on the surface of the silicon nitride layer.
In some embodiments, the thickness of the back gate line electrode 6 may be in the range of 70nm to 120nm, specifically 70nm, 80nm, 90nm, 100nm, 120nm, or the like, but may be other values within the above range, and the present invention is not limited thereto.
In some embodiments, the front gate line electrode group 4 and the back gate line electrode 6 are metal gate line electrodes, and the metal gate line electrodes are made of at least one of copper, silver, aluminum, and nickel.
The back grid line electrode 6 comprises a main grid line and a secondary grid line, the secondary grid line is connected with the main grid line, the secondary grid line is used for converging current generated by the solar cell, and the main grid line is used for collecting current on the secondary grid line.
In some embodiments, the plurality of main grid lines are distributed at equal intervals, so that the current collected by each main grid line is more uniform.
The application also provides a preparation method of the solar cell, referring to fig. 5, which is a flowchart of the preparation method of the solar cell, comprising the following steps:
providing a semiconductor substrate 1, wherein the semiconductor substrate 1 comprises a front surface and a back surface which are oppositely arranged;
Forming a doped conductive layer 2, a front passivation layer 3 and a plurality of grid line electrode groups 4 on the front passivation layer 3 on the front surface of the semiconductor substrate 1, wherein the grid line electrode groups 4 comprise a first front surface grid line electrode 41 and a second front surface grid line electrode 42 which are adjacently arranged, the doping amount of the doped conductive layer 2 is gradually decreased from the first front surface grid line electrode 41 to a symmetrical central area 8 of the first front surface grid line electrode 41 and the second front surface grid line electrode 42, and/or the doping amount of the doped conductive layer 2 is gradually decreased from the second front surface grid line electrode 42 to the symmetrical central area 8 of the first front surface grid line electrode 41 and the second front surface grid line electrode 42;
a back passivation layer 5 and a back gate line electrode 6 are formed on the back surface of the semiconductor substrate 1.
In the above scheme, the doping amount of the doped conductive layer 2 is gradually decreased from the first front gate line electrode 41 to the symmetric central region 8 of the first front gate line electrode 41 and the second front gate line electrode 42, that is, the doping regions from the first front gate line electrode 41 to the symmetric central region 8 of the first front gate line electrode 41 and the second front gate line electrode 42 are gradually decreased, the total doping amount is gradually decreased, the current is gradually increased, and the transmission resistance is gradually decreased, so that the transverse transmission of the current in the doped conductive layer 2 is facilitated, the series resistance is reduced, and the battery efficiency is improved. Similarly, the doping amount of the doped conductive layer 2 decreases from the second front gate line electrode 42 to the symmetric central region 8 of the first front gate line electrode 41 and the second front gate line electrode 42 in sequence, which is also beneficial to the transverse transmission of current in the doped conductive layer 2, thereby reducing the series resistance and improving the battery efficiency. The solar cell provided by the application can further realize gradient doping on the basis of realizing selective doping, and can obviously improve the conversion efficiency of the solar cell.
In some embodiments, the front surface of the semiconductor substrate 1 is a surface facing the sun (i.e., a light receiving surface), and the back surface of the semiconductor substrate 1 is a surface facing away from the sun (i.e., a back surface).
Hereinafter, a method for manufacturing a solar cell according to the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application, and the described embodiments are only some embodiments of the present application, not all embodiments.
Step S100, please refer to FIG. 6, a semiconductor substrate 1 is provided;
In some embodiments, the semiconductor substrate 1 is an N-type silicon substrate or a P-type silicon substrate, and the silicon substrate may be a crystalline silicon substrate (silicon substrate), for example, one of a polysilicon substrate, a monocrystalline silicon substrate, a microcrystalline silicon substrate, or a silicon carbide substrate, and the embodiment of the present application is not limited to the specific type of semiconductor substrate.
In some embodiments, the front and back surfaces of the semiconductor substrate 1 may be textured to form a texture or surface texture (e.g., pyramidal structures). The manner of the texturing process may be chemical etching, laser etching, mechanical method, plasma etching, etc., and is not limited herein. Illustratively, the front and rear surfaces of the semiconductor substrate 1 may be textured with NaOH solution, and a pyramidal textured structure may be prepared due to the anisotropy of the etching of NaOH solution.
It can be understood that the surface of the semiconductor substrate 1 is textured by texturing, so as to generate a light trapping effect, increase the light absorption quantity of the solar cell, and improve the conversion efficiency of the solar cell.
In some embodiments, a step of cleaning the semiconductor substrate 1 to remove metal and organic contaminants from the surface may be further included before the texturing process.
In some embodiments, the emitter may be formed on the front surface of the semiconductor substrate 1 by any one or more of high temperature diffusion, slurry doping, or ion implantation. Specifically, the emitter is formed by diffusing boron atoms through a boron source. In some embodiments, the emitter is designed as a selective emitter structure. The boron source may be, for example, diffusion treated with boron tribromide such that the microcrystalline silicon phase of crystalline silicon is converted to the polycrystalline silicon phase. Due to the relatively high concentration of boron on the surface of the semiconductor substrate 1, a borosilicate glass layer (BSG) is usually formed, which has a metal gettering effect and affects the normal operation of the solar cell, requiring subsequent removal.
Step 200, forming a doped conductive layer 2, a front passivation layer 3 and a plurality of gate line electrode groups 4 on the front passivation layer 3 on the front surface of the semiconductor substrate 1, wherein the gate line electrode groups 4 include a first front gate line electrode 41 and a second front gate line electrode 42 which are adjacently disposed, the doping amount of the doped conductive layer 2 decreases from the first front gate line electrode 41 to the symmetric central region 8 of the first front gate line electrode 41 and the second front gate line electrode 42 in sequence, and/or the doping amount of the doped conductive layer 2 decreases from the second front gate line electrode 42 to the symmetric central region 8 of the first front gate line electrode 41 and the second front gate line electrode 42 in sequence.
In step S201, as shown in fig. 7, a heavily doped layer 7 is formed on the front surface of the semiconductor substrate 1.
In some embodiments, the embodiment of the present application is not limited to the specific operation manner of forming the heavily doped layer 7. Illustratively, a conductive layer may be deposited on the surface of the semiconductor substrate 1 by any one of low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition and atmospheric pressure chemical vapor deposition, and then heavily doped to form the heavily doped layer 7.
In some embodiments, the heavily doped layer 7 may be formed by an in situ doping process while the conductive layer is deposited.
In some embodiments, the doping concentration of the heavily doped layer 7 is 1E19cm -3～1E21 cm-3, which may be, for example, 1E19cm -3、5E19 cm-3、1E20 cm-3、5E20 cm-3 and 1E21 cm -3.
Step 202, a multiple laser thinning treatment process is adopted to treat the heavily doped layer 7, and the heavily doped layer 7 is converted into a doped conductive layer 2, specifically:
Dividing the heavily doped layer 7 into N areas from the preset first front grid line electrode 41 to the symmetrical central area 8 of the preset first front grid line electrode 41 and the preset second front grid line electrode 42, wherein N is more than or equal to 3 and is respectively 1 area, 2 area and 3 area … … N area, and performing laser thinning treatment from 1 area to N area respectively to obtain a doped conductive layer 2, wherein the thickness of the doped conductive layer 2 is gradually decreased from the first front grid line electrode 41 to the symmetrical central area 8 of the first front grid line electrode 41 and the second front grid line electrode 42, and the doping amount of the doped conductive layer 2 is gradually decreased from the preset first front grid line electrode 41 to the symmetrical central area of the preset first front grid line electrode 41 and the preset second front grid line electrode 42 as shown in fig. 8; similarly, the heavily doped layer 7 is divided into regions, so that the heavily doped layer 7 is divided into M regions from the preset second front surface grid line electrode 42 to the symmetrical central region 8 of the preset first front surface grid line electrode 41 and the preset second front surface grid line electrode 42, wherein M is more than or equal to 3, and is respectively a1 region, a2 region and a 3 region … … M region, laser thinning processing is respectively carried out from the 1 region to the M region, the doped conductive layer 2 is obtained, and the thickness of the doped conductive layer 2 is gradually decreased from the preset second front surface grid line electrode 42 to the symmetrical central region 8 of the preset first front surface grid line electrode 41 and the preset second front surface grid line electrode 42.
It will be understood that the preset first front-side gate line electrode 41 and the preset second front-side gate line electrode 42 refer to the preset gate line electrode positions. I.e. the dashed lines of the first front gate line electrode 41 and the second front gate line electrode 42 in fig. 8, the gate line electrode has not been actually formed in this step.
In some embodiments, the laser light of the laser thinning process includes a laser light with a wavelength of 200nm to 600nm, and the laser light includes at least one of green light and ultraviolet light, but may also be a laser light with other wavelength ranges, which is not limited herein.
In some embodiments, the laser frequency of the local laser treatment is 100KHz to 1000KHz, and may specifically be 100KHz, 200KHz, 300KHz, 400KHz, 500KHz, 600KHz, 700KHz, 800KHz, 900KHz, and 1000KHz.
In some embodiments, the combined laser energy of the local laser treatment is 100w x cm -2～100000w*cm-2, which may be 100w*cm-2、500w*cm-2、1000w*cm-2、3000w*cm-2、5000w*cm-2、10000w*cm-2、50000w*cm-2 and 100000w x cm -2, for example.
It will be appreciated that the thickness of the doped conductive layer 2 may be made to have a gradient by adjusting the type of laser, the frequency of the laser, the energy of the laser and the time of the laser treatment such that the doping concentration of the doped conductive layer differs by 1e18 cm -3～9E20cm-3.
In step 203, as shown in fig. 9, a front passivation layer 3 and a back passivation layer 5 are formed on the surface of the doped conductive layer 2.
In some embodiments, the front passivation layer 3 may include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like, or any combination thereof. The front passivation layer 3 can generate good passivation effect on the semiconductor substrate 1, and helps to improve the conversion efficiency of the battery. It should be noted that the front passivation layer 3 may also function to reduce reflection of incident light, and may also be referred to as an anti-reflection layer in some examples.
In some embodiments, the thickness of the front passivation layer 3 ranges from 10nm to 120nm, specifically, 10nm, 20nm, 30nm, 42nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, or 120nm, etc., but other values within the above range are also possible, and the present invention is not limited thereto.
In some embodiments, the back passivation layer 5 may include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like, or any combination thereof.
For example, the back passivation layer 5 is composed of silicon nitride, and the silicon nitride film layer can play a role of an antireflection film, and has good insulativity, compactness, stability and masking ability to impurity ions, and can perform passivation on the semiconductor substrate 1, so that the photoelectric conversion efficiency of the solar cell is significantly improved.
In some embodiments, the thickness of the back passivation layer 5 may be in the range of 70nm to 120nm, specifically 70nm, 80nm, 90nm, 100nm or 120nm, or the like, but may be any other value within the above range, and the present invention is not limited thereto.
In some embodiments, when the back passivation layer 5 is a stacked silicon nitride layer and silicon oxide layer or a stacked silicon nitride layer and silicon oxynitride layer, the silicon nitride layer is located on the surface of the semiconductor substrate 1, and the silicon oxide layer or the silicon oxynitride layer is located on the surface of the silicon nitride layer.
In step S204, the back gate electrode 6 penetrating the back passivation layer 5 to contact the semiconductor substrate 1 and the plurality of gate electrode groups 4 penetrating the surface of the front passivation layer 3 to contact the doped conductive layer 2 are formed.
In some embodiments, the front main grid line and the front auxiliary grid line are printed on the front surface of the semiconductor substrate 1 by using slurry, and are dried to form a corresponding front grid line electrode group, the back main grid line and the back auxiliary grid line are printed on the back surface of the semiconductor substrate 1 by using slurry, are dried to form a corresponding back grid line electrode, and finally the dried battery piece is sintered to obtain the solar cell, wherein the structure of the solar cell is shown in fig. 1.
The specific materials of the front grid line electrode group and the back grid line electrode are not limited in the embodiment of the application. For example, the front gate line electrode is a silver electrode or a silver/aluminum electrode, and the back gate line electrode is a silver electrode or a silver/aluminum electrode.
In the present application, the respective operation steps may be performed sequentially or may be performed out of order unless otherwise specified. The embodiment of the application does not limit the sequence of the steps for preparing the solar cell, and can be adjusted according to the actual production process.
The application also provides another preparation method of the solar cell, unlike the preparation method, the step 200 comprises the following steps:
Step S201, performing diffusion treatment on the front surface of the semiconductor substrate 1 by using a mask method to obtain a doped conductive layer 2, so as to obtain a doping concentration of the doped conductive layer 2 which decreases gradually from the first front surface gate line electrode 41 to the symmetric central region 8 of the first front surface gate line electrode 41 and the second front surface gate line electrode 42; and/or the doping concentration of the doped conductive layer 2 decreases sequentially from the second front side gate line electrode 42 to the symmetric central region 8 of the first front side gate line electrode 41 and the second front side gate line electrode 42.
Specifically, the front surface of the semiconductor substrate 1 is divided into regions, diffusion treatment is sequentially performed on each region from the position of the preset first front surface grid line electrode 41 to the direction of the symmetrical central region 8 of the preset first front surface grid line electrode 41 and the second front surface grid line electrode 42, a masking layer is formed in advance in the non-diffused region, during the diffusion treatment, the concentration of the doping source in the diffusion treatment is sequentially reduced from the preset first front surface grid line electrode 41 to the direction of the symmetrical central region 8 of the preset first front surface grid line electrode 41 and the preset second front surface grid line electrode 42, after the diffusion is completed, the masking layer is removed, and the doped conductive layer 2 is obtained, and as shown in fig. 10, the doping concentration of the doped conductive layer 2 is sequentially reduced from the preset first front surface grid line electrode 41 to the symmetrical central region 8 of the preset first front surface grid line electrode 41 and the second front surface grid line electrode 42.
The diffusion treatment can be sequentially performed on each region from the preset second front-surface grid line electrode 42 to the direction of the symmetric central region 8 of the preset first front-surface grid line electrode 41 and the preset second front-surface grid line electrode 42, a masking layer is formed in advance in the non-diffused region, in the diffusion treatment process, the doping concentration is sequentially decreased from the preset second front-surface grid line electrode 42 to the direction of the symmetric central region 8 of the preset first front-surface grid line electrode 41 and the preset second front-surface grid line electrode 42, after the diffusion is finished, the masking layer is removed, and the doped conductive layer 2 is obtained, as shown in fig. 10, the doping concentration of the doped conductive layer 2 is reduced firstly and then increased, that is, the transmission resistance from the first front-surface grid line electrode 41 to the symmetric central region of the second front-surface electrode grid is minimum, and in favor of current transmission to the first front-surface grid line electrode 41 and the second front-surface electrode grid line 42, so that the filling factor is improved, and the battery efficiency is further improved.
Step S202, a front passivation layer 3 and a back passivation layer 5 are formed on the surface of the doped conductive layer 2.
In step S203, the back gate electrode 6 penetrating the back passivation layer 5 to contact the semiconductor substrate 1 and the plurality of gate electrode groups 4 penetrating the surface of the front passivation layer 3 to contact the doped conductive layer 2 are formed.
In a third aspect, a photovoltaic module 1000 includes a string of cells formed by electrically connecting solar cells as described above.
Specifically, referring to fig. 11, the photovoltaic module 1000 includes a first cover plate 200, a first encapsulation adhesive layer 300, a solar cell string, a second encapsulation adhesive layer 400, and a second cover plate 500.
In some embodiments, the solar cell string includes a plurality of solar cells 100 as described above connected by conductive tapes, and the solar cells 100 may be connected by partial lamination or splicing.
In some embodiments, the first and second cover plates 200, 500 may be transparent or opaque cover plates, such as glass cover plates, plastic cover plates.
Two sides of the first encapsulation glue layer 300 are respectively contacted and attached with the first cover plate 200 and the battery string, and two sides of the second encapsulation glue layer 400 are respectively contacted and attached with the second cover plate 500 and the battery string. The first and second encapsulation adhesive layers 300 and 400 may be an ethylene-vinyl acetate copolymer (EVA) adhesive film, a polyethylene octene co-elastomer (POE) adhesive film, or a polyethylene terephthalate (PET) adhesive film, respectively.
The photovoltaic module 1000 may also be packaged with a side edge completely surrounded, that is, the side edge of the photovoltaic module 1000 is completely encapsulated with a packaging adhesive tape, so as to prevent the photovoltaic module 1000 from generating a lamination offset phenomenon in the lamination process.
The photovoltaic module 1000 also includes a sealing member fixedly encapsulated to a portion of the edge of the photovoltaic module 1000. The edge sealing member may be fixedly packaged to an edge of the photovoltaic module 1000 near a corner. The edge sealing member may be a high temperature resistant tape. The high-temperature-resistant adhesive tape has excellent high-temperature resistance, can not be decomposed or fall off in the lamination process, and can ensure reliable packaging of the photovoltaic module 1000. Wherein, both ends of the high temperature resistant tape are fixed to the second cover plate 500 and the first cover plate 200, respectively. The two ends of the high temperature resistant adhesive tape can be respectively adhered to the second cover plate 500 and the first cover plate 200, and the middle part of the high temperature resistant adhesive tape can limit the side edges of the photovoltaic module 1000, so that the photovoltaic module 1000 is prevented from generating lamination offset in the lamination process.
In some embodiments, the photovoltaic module 1000 further includes a frame (the frame is not shown in fig. 11), and the frame may be made of an aluminum alloy material or a stainless steel material, and when the frame is made of an aluminum alloy material, the strength and corrosion resistance of the frame are very good. The frame can play a role in supporting and protecting the whole battery plate. The photovoltaic module can be connected to the photovoltaic support of outside through the frame, and a plurality of photovoltaic modules can interconnect and form photovoltaic power plant jointly.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, alternatives, and improvements that fall within the spirit and scope of the invention.
Claims (10)
1. A solar cell, comprising:
a semiconductor substrate including a front surface and a back surface disposed opposite to each other;
The semiconductor substrate comprises a doped conductive layer, a front passivation layer and a plurality of grid line electrode groups, wherein the doped conductive layer, the front passivation layer and the grid line electrode groups are arranged on the front passivation layer, the grid line electrode groups comprise a first front grid line electrode and a second front grid line electrode which are adjacently arranged, the thickness of the doped conductive layer is gradually decreased from the first front grid line electrode to the symmetrical central area of the first front grid line electrode and the symmetrical central area of the second front grid line electrode, and/or the thickness of the doped conductive layer is gradually decreased from the second front grid line electrode to the symmetrical central area of the first front grid line electrode and the symmetrical central area of the second front grid line electrode;
and the back passivation layer and the back grid line electrode are positioned on the back of the semiconductor substrate.
2. The solar cell of claim 1, wherein the doped conductive layer corresponding to the first front side gate line electrode has the same thickness; and/or the thickness of the doped conductive layer corresponding to the second front gate line electrode is the same.
3. The solar cell according to claim 1, wherein the height of the front passivation layer decreases in sequence from the first front side gate line electrode to a central region of symmetry of the first front side gate line electrode and the second front side gate line electrode, and/or the height of the front passivation layer decreases in sequence from the second front side gate line electrode to a central region of symmetry of the first front side gate line electrode and the second front side gate line electrode.
4. The solar cell of claim 1, wherein the front passivation layer corresponding to the first front gate line electrode has the same thickness; and/or the thickness of the front passivation layer corresponding to the second front gate line electrode is the same.
5. The solar cell of claim 1, wherein the front passivation layer has a thickness in the range of 10nm to 120nm.
6. The solar cell of claim 1, wherein the front side passivation layer comprises at least one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide.
7. The solar cell according to claim 1, wherein the doped conductive layer surface is provided with an emitter.
8. The solar cell of claim 1, wherein the doping element in the doped conductive layer comprises at least one of boron, gallium, phosphorus, and arsenic.
9. The solar cell of claim 1, wherein the first front-side gate line electrode is a metal gate line electrode and the second front-side gate line electrode is a metal gate line electrode.
10. A photovoltaic module, characterized in that it comprises a cover plate, a layer of encapsulating material, a solar cell string comprising a plurality of solar cells according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410064739.2A CN117936600A (en) | 2022-06-28 | 2022-06-28 | Solar cell and photovoltaic module |
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| DE102010024309A1 (en) * | 2010-06-18 | 2011-12-22 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Process for producing a photovoltaic solar cell |
| KR101733055B1 (en) * | 2010-09-06 | 2017-05-24 | 엘지전자 주식회사 | Solar cell module |
| KR101130193B1 (en) * | 2010-12-07 | 2012-03-30 | 엘지전자 주식회사 | Solar cell |
| US9368655B2 (en) * | 2010-12-27 | 2016-06-14 | Lg Electronics Inc. | Solar cell and method for manufacturing the same |
| KR101699309B1 (en) * | 2011-01-14 | 2017-01-24 | 엘지전자 주식회사 | Method for manufacturing solar cell |
| KR20130096822A (en) * | 2012-02-23 | 2013-09-02 | 엘지전자 주식회사 | Solar cell and method for manufacturing the same |
| US9312420B2 (en) * | 2012-04-17 | 2016-04-12 | Lg Electronics Inc. | Solar cell and method for manufacturing the same |
| DE102012107026A1 (en) * | 2012-08-01 | 2014-02-06 | Solarworld Innovations Gmbh | Solar cell and method for producing a solar cell |
| FR3018391B1 (en) * | 2014-03-07 | 2016-04-01 | Commissariat Energie Atomique | METHOD FOR MAKING A SELECTIVE DOPING PHOTOVOLTAIC CELL |
| DE102017102296A1 (en) * | 2017-02-07 | 2018-08-09 | Hanwha Q Cells Gmbh | Solar cell production process, solar cell semifinished product and solar cell |
| CN114203850A (en) * | 2020-09-01 | 2022-03-18 | 嘉兴阿特斯技术研究院有限公司 | Heterojunction solar cell and method for manufacturing same |
| CN113838941B (en) * | 2021-11-23 | 2022-02-11 | 浙江爱旭太阳能科技有限公司 | Selective passivation contact structure of solar cell and double-sided solar cell |
| CN114068729A (en) * | 2021-11-23 | 2022-02-18 | 浙江爱旭太阳能科技有限公司 | Double-sided back contact solar cell and back structure thereof |
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