CN117935749A - Display panel, method and display device - Google Patents
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Abstract
The application discloses a display panel, a method and display equipment, comprising the following steps: a signal source generator generating a video signal; the time sequence controller is connected with the signal source generator and splits the received video signal into a first grid signal and a second grid signal; a gate driving circuit for generating a first scanning signal and a second scanning signal based on the first gate signal and the second gate signal, the gate driving circuit being respectively connected to the timing controller and the plurality of pixel units; the first scanning signal is configured to turn on the pixel units of the first part to display the video signals of the first part; the second scan signal is configured to turn on the pixel unit of the second portion to display the video signal of the second portion. The display panel provided by the application splits a frame of video signal into two frames to display the display frames respectively, so that the display frames are completely displayed without changing a hardware structure, and the display time sequence of the display frames is maintained.
Description
Technical Field
The embodiment of the application relates to the technical field of liquid crystal display, in particular to a display panel, a method and display equipment.
Background
At present, with the development of high refresh rate liquid crystal display technology, a technology of double-row gate open scanning with low cost and frequency doubling is developed under the condition that hardware driving equipment is unchanged in industry. And as most of the pictures displayed by the display screen are gradually approaching in color, the gray scales of the sub-pixels with the same color and close in position are also approaching. Therefore, when the double-row gate turn-on double-frequency timing technology is adopted, because the double-row gate needs to be turned on simultaneously for technical reasons, adjacent sub-pixels on the same data line are charged with the same gray scale, and the double-row gate turned on simultaneously can cause the gray scale of the sub-pixels to be disordered, so that the R (Red), G (Green), B (Blue) color of the display picture is displayed in error.
Disclosure of Invention
The embodiment of the application provides a display panel, a method and display equipment, which are used for solving the technical problem that the frequency multiplication mode of simultaneously opening double rows of gates in the prior art causes the display error of RGB colors of a display picture.
In order to solve the technical problems, the embodiment of the application discloses the following technical scheme:
in a first aspect, there is provided a display panel including:
A signal source generator configured to generate a video signal;
a timing controller connected to the signal source generator, the timing controller configured to split the received video signal into a first gate signal and a second gate signal;
A gate driving circuit connected to the timing controller and the plurality of pixel units, respectively, the gate driving circuit configured to generate a corresponding first scan signal based on the first gate signal and a corresponding second scan signal based on the second gate signal;
the first scanning signal is configured to turn on a first portion of the pixel units to display the video signal of the first portion;
the second scan signal is configured to turn on the pixel unit of a second portion to display the video signal of the second portion.
With reference to the first aspect, the display device further includes a plurality of scan lines and a plurality of data lines, where the plurality of scan lines and the plurality of data lines are insulated from each other and cross each other to define the plurality of pixel units in an array;
one scanning line is respectively connected with a plurality of pixel units, and one data line is connected with a plurality of types of pixel units.
With reference to the first aspect, the timing controller is configured to split the video signal received for each frame into a first frame and a second frame;
Wherein the first gate signal has a high level in the first frame and the second gate signal has a high level in the second frame.
With reference to the first aspect, the first scanning signal is configured to turn on the pixel units of the a n th row;
wherein a n is an arithmetic series, which satisfies the formula:
an＝a1+(n-1)d；
Wherein a 1 epsilon (1, X), X is the type number of the pixel units connected on one data line; n is a positive integer and is greater than or equal to 2; d is a tolerance and satisfies d=2x, where x=2 or x=3.
With reference to the first aspect, the second scan signal is configured to turn on the pixel unit of the b m th row;
wherein b m is an arithmetic series, satisfying the formula:
bm＝b1+(m-1)d；
Wherein b 1 epsilon (X+ 1,2X), X is the type number of the pixel units connected on one data line; m is a positive integer and is greater than or equal to 2; d is a tolerance and satisfies d=2x, x=2 or x=3.
In combination with the first aspect, the types of the pixel units include three types of red, green and blue.
In a second aspect, a display method is provided and applied to a display panel, and the method includes:
Acquiring a video signal;
splitting a frame of the video signal into two frames, namely a first grid signal and a second grid signal;
Converting the first gate signal and the second gate signal into corresponding first scan signal and second scan signal;
the first scanning signal is configured to turn on the pixel units of the first part to display the video signals of the first part;
the second scan signal is configured to turn on the pixel unit of the second portion to display the video signal of the second portion.
With reference to the second aspect, the display panel includes a plurality of data lines, one of the data lines is connected to a plurality of types of the pixel units;
Splitting the video signal into the first scan signal and the second scan signal based on the number of types of the pixel units connected on one of the data lines.
With reference to the second aspect, the first gate signal has a high level in the first frame, and the second gate signal has a high level in the second frame.
In a third aspect, there is provided a display device comprising the display panel according to any one of the first aspects; or the display device displays using the display method according to any one of the second aspects.
One of the above technical solutions has the following advantages or beneficial effects:
compared with the prior art, the display panel of the application comprises: a signal source generator configured to generate a video signal; the time schedule controller is connected with the signal source generator and is configured to split the received video signal into a first grid signal and a second grid signal; the grid driving circuit is respectively connected with the time sequence controller and the pixel units and is configured to generate corresponding first scanning signals based on the first grid signals and generate corresponding second scanning signals based on the second grid signals; the first scanning signal is configured to turn on the pixel units of the first part to display the video signals of the first part; the second scan signal is configured to turn on the pixel unit of the second portion to display the video signal of the second portion. The display panel provided by the application splits a frame of video signal into two frames to display the display frames respectively, so that the display frames are completely displayed without changing a hardware structure, and the display time sequence of the display frames is maintained.
The application discloses a display method, which is applied to a display panel and comprises the following steps: acquiring a video signal; splitting a frame of video signal into two frames, namely a first grid signal and a second grid signal, wherein the first grid signal is positioned in the first frame, and the second grid signal is positioned in the second frame; converting the first gate signal and the second gate signal into corresponding first scanning signals and second scanning signals; the first scanning signal is configured to turn on the pixel units of the first part to display the video signals of the first part; the second scan signal is configured to turn on the pixel unit of the second portion to display the video signal of the second portion. The application provides a display method, which divides a frame of video signal into two frames and respectively displays the two frames of pictures, so that the display picture is completely displayed without changing the hardware structure, and the display time sequence of the display picture is maintained.
Drawings
The technical solution and other advantageous effects of the present application will be made apparent by the following detailed description of the specific embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of a module connection structure of a display panel according to an embodiment of the present application;
FIG. 2 is a timing diagram of a first scan signal and a second scan signal according to a first embodiment of the present application;
FIG. 3 is a timing diagram of a first scan signal and a second scan signal according to a second embodiment of the present application;
FIG. 4 is a schematic diagram of a data line connected to two pixel units according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a data line connected to three pixel units according to another embodiment of the present application;
FIG. 6 is a schematic diagram of a data line connected to a pixel unit according to an embodiment of the present application;
FIG. 7 is a schematic diagram illustrating steps of a display method according to an embodiment of the present application;
Fig. 8 is a schematic diagram of a gate driving circuit according to an embodiment of the application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
The related technicians of the application notice that the electronic competition industry is greatly developed in recent years, and the demands of consumers on large-size high-brush game electronic competition screens are also increasing; at the same time, television manufacturers have also introduced a variety of entertainment high-brush screens to better attract users to the consumer's high-brush needs. Currently 120Hz and 240Hz are the necessary specification requirements of the mainstream high-end high-brush game display panel. In order to cope with market competition and promote the profitability of semiconductor display business, various panel factories are greatly pushing the cost-reducing strategy, and the demand for low-cost high-brush products is also urgent.
For the high-brush driving system in the conventional mode, the scanning signals sequentially scan and turn on the gate port of the TFT from top to bottom to charge the pixel unit with data. For example, 120Hz is reduced by half compared to 60Hz single frame time, and 240Hz is reduced by half compared to 120Hz single frame time.
In the driving system in the conventional mode, taking a TCON-less SoC core board as an example, when data and time sequence processing is performed, the driving system needs to be supported by corresponding specifications such as bandwidth and the like. A drive system such as 4k2k@60hz can process 4k2k@60hz data, but cannot process 4k2k@120hz data; the 4k2k@120hz drive system is capable of processing either 4k2k@120hz data or 4k2k@60hz data, but is incapable of processing 4k2k@240hz data. At the same time, as the refresh rate increases exponentially, the cost of the drive system increases exponentially.
Therefore, a gate voltage turn-on scanning technique for dual-row pixel units without changing the hardware driving device is proposed by those skilled in the art to realize low-cost frequency multiplication. For example, based on a hardware device of a 4K2K@60Hz driving system, the conventional 60Hz time sequence needs to scan and turn on the gate voltage of the pixel unit from top to bottom to perform data charging on the pixel unit. At this time, the data is a 4K2K frame, a gate line charges one line of data, and the gate voltage of the pixel units of 2K lines needs to be turned on to realize scanning of one frame of frame. And under the condition of not changing hardware equipment, the gate voltage of the double-row pixel units is simultaneously turned on to perform data charging, the single-frame time is shortened by half, at the moment, the data is a 4K1K picture, two adjacent gate lines charge the same row of data, and the scanning of one-frame picture can be realized only by the time of turning on the gate voltage of the pixel units of 1K row, so that the 120Hz time sequence with low cost can be realized.
For the low-cost frequency doubling technology, the method is only suitable for 1 gate voltage to scan 1 data, and 1 data line is only connected with pixel units of a single color (as shown in fig. 6), and is not suitable for 1 data line to be connected with pixel units of two colors (as shown in fig. 4) or 1 data line to be connected with pixel units of three colors (as shown in fig. 5), and 1 data line to be connected with more than three colors in an architecture mode and the like.
It will be appreciated that most of the pictures displayed by the display screen are color graded. For the connection architecture of the pixel units shown in fig. 6, the colors or gray scales of the pixel units located close to each other are also close. Therefore, when the frequency doubling time sequence technology is adopted, gate voltages of the double-row pixel units are required to be simultaneously opened for technical reasons, and adjacent pixel units on the same data line are charged by adopting the same gray scale data, so that the display picture approaching to the original time sequence can be realized, and the technology can be adopted for driving.
For the connection architecture of the pixel units in fig. 4, the colors or gray scales of the pixel units located close to each other are also close to each other. However, when the frequency doubling timing technology is adopted, gate voltages of the pixel units in the double rows are simultaneously turned on, and adjacent pixel units on the same data line are charged with the same gray level, so that the gray level of the adjacent pixel units is disordered, and the R, G, B colors in the display picture are wrong.
Similarly, in fig. 5, the gate voltages of the pixel units in the two rows are simultaneously turned on to confuse the gray levels of the adjacent pixel units, and the color R, G, B of the display is wrong. Therefore, the frequency doubling technique is not suitable for the architecture mode of the pixel units with multiple colors on 1 data line. Accordingly, embodiments of the present application address the above-described problems by providing a display panel or display method.
The following examples illustrate embodiments of the application:
as shown in fig. 1, an embodiment of the present application provides a display panel, including: a signal source generator configured to generate a video signal; the time schedule controller is connected with the signal source generator and is configured to split the received video signal into a first grid signal and a second grid signal; the grid driving circuit is respectively connected with the time sequence controller and the pixel units and is configured to generate corresponding first scanning signals based on the first grid signals and generate corresponding second scanning signals based on the second grid signals; the first scanning signal is configured to turn on the pixel units of the first part to display the video signals of the first part; the second scan signal is configured to turn on the pixel unit of the second portion to display the video signal of the second portion. Specifically, the time sequence controller is used for splitting each received frame of video signal into a first grid signal and a second grid signal after processing, and sequentially splicing the first grid signal and the second grid signal to obtain a first grid signal and a second grid signal which are 2 times of the original video signal in number; the gate driving circuit converts the first gate signal and the second gate signal into a first scan signal and a second scan signal, respectively. The grid driving circuit drives the pixel units to display according to the first scanning signal and the second scanning signal. By splitting each frame of video signal, the gray scale confusion of adjacent pixel units in the display panel is avoided, and the display effect of RGB colors in a display picture is improved.
In the embodiment of the application, the double-row gate simultaneous opening frequency multiplication technology is a technology for increasing the refresh rate of the liquid crystal display. The basic principle of the technology is that two rows of grid scanning lines are activated simultaneously at one time, so that two rows of pixel data are transmitted in each refresh period. The scanning mode of the conventional liquid crystal display is a progressive scanning mode, i.e., pixel units of each row are activated in sequence, and then data is transmitted row by row. While double-row gate-on-simultaneously doubling techniques increase refresh rate by activating both rows of gate scan lines simultaneously. This technique is embodied by simultaneously activating two adjacent rows of gate scan lines, and combining the two rows of data into one row of pixels. In this way, twice as much pixel data as in the conventional manner can be transferred in the same refresh period. For example, in one refresh period, the conventional method can only transmit one line of data, while the frequency doubling technology can transmit two lines of data at the same time, so that the refresh rate is improved. Through the double-row gate simultaneous opening frequency doubling technology, the liquid crystal display can achieve higher refresh rate and improve the smoothness and dynamic effect of images. This is very beneficial to scenes such as games, video playing, fast moving pictures, etc., and can reduce motion blur and ghost, providing clearer and smoother image display.
As shown in fig. 1 and fig. 4 to fig. 6, in an embodiment of the present application, the display device further includes a plurality of scan lines and a plurality of data lines, where the plurality of scan lines and the plurality of data lines are insulated from each other and cross each other to define a plurality of pixel units in an array; one scanning line is connected with a plurality of pixel units respectively, and one data line is connected with a plurality of types of pixel units. Specifically, a plurality of scanning lines are sequentially arranged in rows and connect a plurality of pixel units, and a plurality of data lines are arranged in columns and connect one, two, three or more pixel units according to circumstances. The scan line is used for providing a scan signal to open a gate port in the pixel unit, and the data line is used for providing a data signal gate to charge the pixel unit when the gate port of the pixel unit is opened so as to realize a display picture.
As shown in fig. 2 and 3, in an embodiment of the present application, the timing controller is configured to split a received video signal per frame into a first frame and a second frame; wherein the first gate signal has a high level in the first frame and the second gate signal has a high level in the second frame. Specifically, the timing controller splits an original video signal of one frame into two frames of video signals, namely a first grid signal and a second grid signal; the gate driving circuit then converts the first gate signal and the second gate signal into a first scan signal and a second scan signal, respectively, (e.g., CK1-CK8 in fig. 2, or CK1-CK12 in fig. 3); as in the scan signals of fig. 2 and 3, in the first frame, the first scan signal has a high level and the second scan signal has no high level; in the second frame, the second scan signal has a high level, and the first scan signal has no high level; a digital identification is used at each high level to represent which row of pixel cells is to be turned on. It will be appreciated that in the first frame (or the second frame), the first scan signal (or the second scan signal) has a high level only every few rows, such as every other two rows in fig. 2, and the number of rows of the interval is determined by the pixel type connected to one data line, so that when the pixel units connected to one data line have 2,3, and 4 types, the first scan signal (or the second scan signal) has a continuous 2,3, and 4 row level at intervals of 2,3, and 4 rows. The number of rows may be determined according to the number of types of pixel units connected to a specific data line, and embodiments of the present application are not described herein.
As shown in fig. 2 or 3, in the embodiment of the present application, the first scan signal is configured to turn on the pixel units of the a n th row; wherein a n is an arithmetic series, which satisfies the formula:
an＝a1+(n-1)d；
Wherein a 1 epsilon (1, X), X is the type number of pixel units connected on a data line; n is a positive integer and is greater than or equal to 2; d is a tolerance and satisfies d=2x, where x=2 or x=3. Specifically, when the number of types of pixel units connected on one data line is 2, that is, x=2, the optional numbers of a 1 include 1 and 2; thus, when a 1 is 1 and d=4, as calculated by the above formula, the row of pixel cells where the first scan signal is on includes: 1.5, 9, 13, etc.; when a 1 is 2 and d=4, the row of the pixel units turned on by the first scan signal may include 2,6, 10, 14, etc., and the sequence numbers of the rows turned on by the first scan signal of the specific pixel units are shown in fig. 2.
Specifically, when the number of types of pixel units connected on one data line is 3, that is, x=3, the optional numbers of a 1 include 1,2, and 3; thus, when a 1 is 1 and d=6, as calculated by the above formula, the row of pixel cells where the first scan signal is on includes: 1.7, 13, 19, etc.; when a 1 is 2 and d=6, the row of pixel units turned on by the first scan signal includes 2, 8, 14, 20, etc. as calculated by the above formula; when a 1 is 3 and d=6, it is calculated by the above formula that the row of the pixel units turned on by the first scan signal includes 3, 9, 15, 21, etc., and the sequence number of the row of the specific pixel units turned on by the first scan signal is shown in fig. 3.
As shown in fig. 2 or 3, in the embodiment of the present application, the second scan signal is configured to turn on the pixel unit of the b m th row; wherein b m is an arithmetic series, satisfying the formula:
bm＝b1+(m-1)d；
Wherein b 1 epsilon (X+ 1,2X), X is the type number of pixel units connected on one data line; m is a positive integer and is greater than or equal to 2; d is a tolerance and satisfies d=2x, where x=2 or x=3. Specifically, when the number of types of pixel units connected on one data line is 2, that is, x=2, the optional numbers of b 1 include 3 and 4; thus, when b 1 is 3 and d=4, as calculated by the above formula, the row of pixel cells where the first scan signal is on includes: 3. 7, 11, 15, etc.; when b 1 is 4, d=4, the row of the pixel units turned on by the first scan signal may include 4, 8, 12, 16, etc., and the sequence numbers of the rows turned on by the first scan signal of the specific pixel units are shown in fig. 2.
Specifically, when the number of types of pixel units connected on one data line is 3, that is, x=3, the optional numbers of b 1 include 4,5, and 6; thus, when b 1 is 4 and d=6, as calculated by the above formula, the row of pixel cells where the first scan signal is on includes: 4. 10, 16, 22, etc.; further, when b 1 is 5, d=6, as calculated by the above formula, the row of the pixel units turned on by the first scan signal includes 5, 11, 17, 23, etc.; when b 1 is 6, d=6, as calculated by the above formula, the row of the pixel units turned on by the first scan signal includes 6, 12, 18, 24, etc., and the sequence number of the row of the specific pixel units turned on by the first scan signal is shown in fig. 3. The pixel units are opened by separating the rows, so that adjacent pixel units are prevented from displaying similar or same gray scale, errors of the display colors of the RGB three pixel units are avoided, and the display fresh fruits of the display panel are improved.
As shown in fig. 4 to 6, in the embodiment of the present application, the types of the pixel unit include three types of red, green, and blue. Specifically, red, green and blue respectively represent three primary colors, and the display picture can be controlled to display different colors through the numerical control of the three primary colors, so that various colors can be displayed.
As shown in fig. 8, in the gate driving circuit according to the embodiment of the present application, the second clock signal terminal (CLK 2 terminal), the first scan start terminal (STV terminal), and the first scan control terminal (CN terminal) are input with high levels, T1 and T7 are turned on, the pull-up point (pu_cn point) of the gate driving circuit is high level, T6 is turned on, and a dc path is formed between the CLK2 terminal and the dc low level terminal (vgl_g terminal). The second clock signal CLK2 is high, the dc low level vgl_g is low, and a dc current is formed, which increases the circuit power consumption on one hand, and affects the service life of the transistors due to a heating effect on the other hand, wherein T1 represents the first transistor, T2 represents the second transistor, T3 represents the third transistor, T4 represents the fourth transistor, T5 represents the fifth transistor, T6 represents the sixth transistor, T7 represents the seventh transistor, C1 represents the capacitor, RST terminal represents the reset signal terminal, and OUTPUT terminal is the OUTPUT terminal. The gate driving circuit converts the first gate signal and the second gate signal into a first scan signal and a second scan signal, and transmits the first scan signal and the second scan signal into the pixel unit.
As shown in fig. 7, the embodiment of the application further provides a display method, which is applied to a display panel, and the method includes:
S1: a video signal is acquired.
Specifically, the video signal is generated by a signal source generator, which is connected to a timing controller that acquires the video signal from the signal source generator.
S2: a frame of video signal is split into two frames, namely a first grid signal and a second grid signal.
Specifically, the timing controller splits each received video signal into a first frame and a second frame; wherein the first gate signal has a high level in the first frame and the second gate signal has a high level in the second frame. It can be understood that the timing controller splits the video signal of the original frame into two frames of video signals, namely a first gate signal and a second gate signal, and the same splitting operation is adopted for each frame in the video signals;
The splitting basis is to split the video signal into a first scanning signal and a second scanning signal based on the type number of pixel units connected on one data line; the display panel comprises a plurality of scanning lines and a plurality of data lines, and the scanning lines and the data lines are mutually insulated and crossed to define a plurality of pixel units in an array; one scanning line is connected with a plurality of pixel units respectively, and one data line is connected with a plurality of types of pixel units.
S3: the first gate signal and the second gate signal are converted into corresponding first scan signal and second scan signal.
Specifically, the first gate signal has a high level in the first frame, and the second gate signal has a high level in the second frame. The gate driving circuit converts the first gate signal and the second gate signal into a first scan signal and a second scan signal, respectively.
S4: the first scanning signal is configured to turn on the pixel units of the first part to display the video signals of the first part; the second scan signal is configured to turn on the pixel unit of the second portion to display the video signal of the second portion.
Specifically, the gate driving circuit drives the pixel unit to display according to the first scanning signal and the second scanning signal. By splitting each frame of video signal, the gray scale confusion of adjacent pixel units in the display panel is avoided, and the display effect of RGB colors in a display picture is improved.
The embodiment of the application also provides display equipment, which comprises the display panel provided by any one of the above embodiments; or the display device displays using the display method provided in any one of the above.
The display panel, the method and the display device provided by the embodiment of the application are described in detail, and specific examples are applied to illustrate the principle and the implementation of the application, and the description of the above embodiments is only used for helping to understand the technical scheme and the core idea of the application; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.
Claims (10)
1. A display panel, comprising:
A signal source generator configured to generate a video signal;
a timing controller connected to the signal source generator, the timing controller configured to split the received video signal into a first gate signal and a second gate signal;
A gate driving circuit connected to the timing controller and the plurality of pixel units, respectively, the gate driving circuit configured to generate a corresponding first scan signal based on the first gate signal and a corresponding second scan signal based on the second gate signal;
the first scanning signal is configured to turn on a first portion of the pixel units to display the video signal of the first portion;
the second scan signal is configured to turn on the pixel unit of a second portion to display the video signal of the second portion.
2. The display panel of claim 1, further comprising a plurality of scan lines and a plurality of data lines, the plurality of scan lines and the plurality of data lines insulated from each other to cross and define the plurality of pixel cells in an array;
one scanning line is respectively connected with a plurality of pixel units, and one data line is connected with a plurality of types of pixel units.
3. The display panel of claim 2, wherein the timing controller is configured to split the received video signal into a first frame and a second frame for each frame;
Wherein the first gate signal has a high level in the first frame and the second gate signal has a high level in the second frame.
4. The display panel of claim 2, wherein the first scan signal is configured to turn on the pixel cells of row a n;
wherein a n is an arithmetic series, which satisfies the formula:
an＝a1+(n-1)d；
Wherein a 1 epsilon (1, X), X is the type number of the pixel units connected on one data line; n is a positive integer and is greater than or equal to 2; d is a tolerance and satisfies d=2x, where x=2 or x=3.
5. The display panel of claim 2, wherein the second scan signal is configured to turn on the pixel cells of row b m;
wherein b m is an arithmetic series, satisfying the formula:
bm＝b1+(m-1)d；
Wherein b 1 epsilon (X+ 1,2X), X is the type number of the pixel units connected on one data line; m is a positive integer and is greater than or equal to 2; d is a tolerance and satisfies d=2x, x=2 or x=3.
6. The display panel of claim 4 or 5, wherein the types of the pixel units include three types of red, green and blue.
7. A display method applied to a display panel, the method comprising:
Acquiring a video signal;
splitting a frame of the video signal into two frames, namely a first grid signal and a second grid signal;
Converting the first gate signal and the second gate signal into corresponding first scan signal and second scan signal;
the first scanning signal is configured to turn on the pixel units of the first part to display the video signals of the first part;
the second scan signal is configured to turn on the pixel unit of the second portion to display the video signal of the second portion.
8. The display method of claim 7, wherein the display panel includes a plurality of data lines, one of the data lines connecting a plurality of types of the pixel units;
Splitting the video signal into the first scan signal and the second scan signal based on the number of types of the pixel units connected on one of the data lines.
9. The display method of claim 7, wherein the first gate signal has a high level in the first frame and the second gate signal has a high level in the second frame.
10. A display device, characterized in that the display device comprises a display panel according to any one of claims 1-6; or the display device displays using the display method according to any one of claims 7 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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