CN117915659A - Semiconductor structure and memory array structure - Google Patents

Abstract

Embodiments of the present disclosure provide a semiconductor structure and a memory array structure, the semiconductor structure including a read transistor, the read transistor including: the first grid, the first semiconductor layer, second grid and ground layer, wherein, first grid and ground layer interval set up, and the ground layer is located one side of first grid towards first direction, and first semiconductor layer extends to the ground layer lateral wall by first grid lateral wall, and first semiconductor layer includes along first opposite first end and the second end of first direction, and one of first end and second end is located the lateral wall of first grid and deviates from ground layer one side, and another and ground layer electrical contact, and the second grid is located the second end at least and deviates from ground layer one side. Embodiments of the present disclosure are at least beneficial for improving performance of semiconductor structures.

Description

Semiconductor structure and memory array structure

Technical Field

The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a semiconductor structure and a memory array structure.

Background

A common dynamic random access memory (DRAM, dynamic Random Access Memory) is of the 1T1C type, i.e. a transistor source or drain is electrically connected to a capacitor to form a memory cell. The structure stores data by using the capacitor, but the capacitor consumes electric quantity during reading and leaks electricity, so that the electric charge in the capacitor needs to be continuously refreshed, the power consumption of the DRAM is larger, and the electrical property is unstable. Meanwhile, the technology for manufacturing the capacitor occupies a large area, and the size shrinkage is also a difficult problem.

To overcome the difficulty of capacitance, a 2T0C type memory cell is used, i.e., a transistor has a source or drain electrically connected to a gate of another transistor to form a memory cell.

Disclosure of Invention

The embodiment of the disclosure provides a semiconductor structure and a memory array structure, which are at least beneficial to improving the performance of the semiconductor structure.

According to some embodiments of the present disclosure, an aspect of an embodiment of the present disclosure provides a semiconductor structure, including: a read transistor, the read transistor comprising: the semiconductor device comprises a first grid, a first semiconductor layer, a second grid and a grounding layer, wherein the first grid and the grounding layer are arranged at intervals, the grounding layer is located on one side of the first grid facing a first direction, the first semiconductor layer extends from the side wall of the first grid to the side wall of the grounding layer, the first semiconductor layer comprises a first end and a second end which are opposite along the first direction, one of the first end and the second end is located on the side wall of the first grid, which is away from one side of the grounding layer, the other is in electrical contact with the grounding layer, and the second grid is located at least on one side of the second end, which is away from the grounding layer.

In some embodiments, the semiconductor structure further includes a write transistor including a third gate and a second semiconductor layer located on a sidewall of the third gate, the second semiconductor layer being electrically connected to the second gate.

In some embodiments, a surface of the second semiconductor layer facing the second gate electrode is in contact with the second gate electrode, or the second semiconductor layer and the second gate electrode are electrically connected by a connection layer.

In some embodiments, the write transistor is located on a side of the read transistor toward the first direction; the semiconductor structure further includes a bit line; the bit line comprises a first sub bit line and a second sub bit line which are connected, the first sub bit line extends along the first direction, the second sub bit line extends along the second direction, the first direction is intersected with the second direction, the first end is located at one side of the second end, facing the second sub bit line, the first end is in contact with the second sub bit line, and the second semiconductor layer is in contact with the first sub bit line.

In some embodiments, the write transistor is located on a side of the read transistor toward the first direction; the semiconductor structure further includes a bit line; the bit line comprises a first sub bit line, a second sub bit line and a third sub bit line which are sequentially connected, the first sub bit line and the third sub bit line extend along a second direction, the second sub bit line extends along the first direction, the first direction is intersected with the second direction, the first sub bit line is located at one side, far away from the read transistor, of the write transistor and is in contact with the second semiconductor layer, and the third sub bit line is located at one side, far away from the write transistor, of the read transistor and is in contact with the first end.

In some embodiments, the write transistor is located on a side of the read transistor facing a second direction, the second semiconductor layer is located at least on a side wall of the third gate opposite to the first direction and extending to a side wall of the third gate facing away from the read transistor, the first direction intersects the second direction, and the second gate extends from the side of the second end facing away from the ground layer to the surface of the second semiconductor layer.

In some embodiments, the write transistor is located on a side of the read transistor facing a second direction, the first direction intersecting the second direction; the semiconductor structure further includes a bit line extending in a second direction, and the bit line is in contact with the first end and the second semiconductor layer.

In some embodiments, the first end further extends from the bit line surface in the second direction and is connected to the second semiconductor layer, and the first semiconductor layer is of the same material as the second semiconductor layer.

According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a memory array structure, including a plurality of semiconductor structures provided in any one of the previous embodiments, where a plurality of the semiconductor structures are arranged in an array along a first direction, along a second direction, and along a third direction, where the first direction, the second direction, and the third direction intersect in pairs, and adjacent first gates are electrically connected along the third direction to form a read word line.

In some embodiments, the semiconductor structure further comprises: a write transistor and a bit line extending along the second direction, the write transistor including a third gate and a second semiconductor layer; in the memory array structure, the second semiconductor layer of the write transistor is electrically connected with the second gate of the read transistor in a one-to-one correspondence manner so as to form a plurality of memory cells, the bit line is located between two adjacent memory cells arranged along the first direction and is electrically connected with the second semiconductor layer and the first end of the two memory cells, along the third direction, the adjacent third gate is electrically connected to form a write word line, and the adjacent first gate is electrically connected to form a read word line.

The technical scheme provided by the embodiment of the disclosure has at least the following advantages:

the semiconductor structure provided by the embodiment of the disclosure comprises the read transistor, the read transistor comprises the first grid electrode and the second grid electrode, the first grid electrode and the second grid electrode are positioned on two opposite sides of the first semiconductor layer, the control capability of the grid electrode on or off of the read transistor is improved, and the double-grid structure can achieve better electric field distribution, so that the read transistor has higher current density, and the performance of the semiconductor structure is improved.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise; in order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the conventional technology, the drawings required for the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.

Fig. 1 is a schematic structural diagram of a first semiconductor structure according to an embodiment of the disclosure;

fig. 2 is a schematic structural diagram of a second semiconductor structure according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a third semiconductor structure according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a fourth semiconductor structure according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of a fifth semiconductor structure according to an embodiment of the present disclosure;

Fig. 6 is a schematic structural diagram of a sixth semiconductor structure according to an embodiment of the present disclosure;

Fig. 7 is a schematic circuit diagram corresponding to the semiconductor structure provided in fig. 2 to 6;

FIG. 8 is a schematic top view of a first memory array structure according to another embodiment of the present disclosure;

FIG. 9 is a schematic cross-sectional view along the AA1 direction of the first memory array structure shown in FIG. 8;

FIG. 10 is a schematic top view of a second memory array structure according to another embodiment of the present disclosure;

FIG. 11 is a schematic cross-sectional view along BB1 in the second memory array structure shown in FIG. 10;

FIG. 12 is a schematic top view of a third memory array structure according to another embodiment of the present disclosure;

FIG. 13 is a schematic top view of a fourth memory array structure according to another embodiment of the present disclosure;

FIG. 14 is a schematic cross-sectional view of the fourth memory array structure shown in FIG. 13 along the direction CC 1;

Fig. 15 to 24 are schematic structural diagrams corresponding to steps of a method for manufacturing a memory array structure according to another embodiment of the disclosure.

Detailed Description

As known from the background art, the performance of the current semiconductor structure needs to be improved.

The semiconductor structure provided by the embodiment of the disclosure comprises the read transistor, the read transistor comprises the first grid electrode and the second grid electrode which are positioned on two opposite sides of the first semiconductor layer, the control capability of the grid electrode on or off of the read transistor is improved, and the double-grid structure can achieve better electric field distribution, so that the read transistor has higher current density, and the performance of the semiconductor structure is improved.

Embodiments of the present disclosure will be described in detail below with reference to the attached drawings. However, those of ordinary skill in the art will understand that in the various embodiments of the present disclosure, numerous technical details have been set forth in order to provide a better understanding of the present disclosure. The technical solutions claimed in the present disclosure can be implemented without these technical details and with various changes and modifications based on the following embodiments.

Fig. 1 is a schematic structural view of a first semiconductor structure according to an embodiment of the present disclosure, fig. 2 is a schematic structural view of a second semiconductor structure according to an embodiment of the present disclosure, fig. 3 is a schematic structural view of a third semiconductor structure according to an embodiment of the present disclosure, fig. 4 is a schematic structural view of a fourth semiconductor structure according to an embodiment of the present disclosure, fig. 5 is a schematic structural view of a fifth semiconductor structure according to an embodiment of the present disclosure, and fig. 6 is a schematic structural view of a sixth semiconductor structure according to an embodiment of the present disclosure.

Referring to fig. 1, a semiconductor structure includes: the read transistor 10, the read transistor 10 includes: the first gate 100, the first semiconductor layer 101, the second gate 102 and the ground layer 103, wherein the first gate 100 and the ground layer 103 are disposed at intervals, the ground layer 103 is located at one side of the first gate 100 facing the first direction, the first semiconductor layer 101 extends from the sidewall of the first gate 100 to the sidewall of the ground layer 103, the first semiconductor layer 101 includes a first end 201 and a second end 301 opposite to each other along the first direction, one of the first end 201 and the second end 301 is located at the sidewall of the first gate 100 facing away from the ground layer 103, the other is in electrical contact with the ground layer 103, and the second gate 102 is located at least at one side of the second end 301 facing away from the ground layer 103. The semiconductor structure shown in fig. 1 is exemplified by the first end 201 being located at a side wall of the first gate 100 facing away from the ground layer 103.

The second gate 102 may be located only on the side of the second end 301 facing away from the ground layer 103. Or the second gate electrode 102 may be opposite to the sidewall of the first semiconductor layer 101 except the first end 201. The materials of the first gate electrode 100 and the second gate electrode 102 may each include a metal material of copper, aluminum, silver, tin, gold, nickel, lead, titanium, tungsten, or an alloy thereof.

The first semiconductor layer 101 may be integrally disposed around the first gate electrode 100 and the ground layer 103, so that the first semiconductor layer 101 encloses a cavity, which is beneficial to improving the surface area of the first semiconductor layer 101 and the length of the channel formed in the first semiconductor layer 101 while ensuring that the first semiconductor layer 101 occupies a smaller layout space, so as to improve the facing area of the first gate electrode 100 and the first semiconductor layer 101, and improve the facing area of the second gate electrode 102 and the first semiconductor layer 101, so as to improve the control capability of the first gate electrode 100 and the second gate electrode 102 on the first semiconductor layer 101, thereby being beneficial to improving the electrical performance of the read transistor 10.

In some embodiments, the first semiconductor layer 101 may be disposed around three sides of the whole first gate electrode 100 and the ground layer 103, that is, the first semiconductor layer 101 includes a first end 201, a second end 301, and an intermediate portion, where the intermediate portion is located on one sidewall of the first gate electrode 100 and the ground layer 103 extending along the first direction, and two ends of the intermediate portion are respectively in contact with the first end 201 and the second end 301.

In some embodiments, the material of the first semiconductor layer 101 may include a semiconductor material, such as silicon, germanium, or silicon germanium.

In some embodiments, the material of the first semiconductor layer 101 may be an amorphous material, and the amorphous material has a gap therein, so that the material has a higher carrier mobility, which can reduce the thickness of the first semiconductor layer 101, reduce the line width of the semiconductor structure in a limited unit area, and further improve the storage density of the semiconductor structure. The amorphous material may include at least one of IGZO (indium gallium zinc oxide ), IWO (tungsten doped indium oxide, indium Tungsten Oxide), or ITO (indium tin oxide).

In some embodiments, the material of the first semiconductor layer 101 may include IGZO, where the carrier mobility of IGZO is 20-50 times that of polysilicon, which is beneficial to improve the carrier mobility in the first semiconductor layer 101, thereby facilitating to reduce the leakage current when the semiconductor structure is in operation, so as to reduce the power consumption of the semiconductor structure and improve the working efficiency of the semiconductor structure. In addition, the thin film deposition process for preparing the IGZO is simple, the deposition temperature is low, and the problems of thermal damage and thermal defects of the substrate and the active layer can be improved. Due to the characteristics of the IGZO itself, the large-area first semiconductor layer 101 prepared by the IGZO has better uniformity, and the electrical performance and stability of the first semiconductor layer 101 can be improved.

In some embodiments, a first gate dielectric layer 105 may be further disposed between the first semiconductor layer 101 and the first gate electrode 100. In some embodiments, a second gate dielectric layer 106 may be disposed between the first semiconductor layer 101 and the second gate electrode 102. The material of the first gate dielectric layer 105 and the material of the second gate dielectric layer 106 may include silicon oxide, silicon carbide, silicon nitride or other materials with high dielectric constants, which are used to suppress short channel effects, thereby suppressing tunneling leakage current and the like.

An isolation layer 107 may be disposed between the first gate 100 and the ground layer 103. The material of the isolation layer 107 may include a low dielectric constant material such as silicon carbide nitride (SiCN) or silicon oxycarbide (SiCO) to suppress the parasitic capacitance between the first gate 100 and the ground layer 103, thereby improving RC delay and improving performance of the semiconductor structure. The RC delay is a signal delay caused by a charging and discharging process of a capacitor (C) controlled by a resistor (R) in an integrated circuit, and is generally used in a case where a delay time is short. In some embodiments, an Air Gap (Air Gap) is provided between the first gate 100 and the ground layer 103 to reduce parasitic capacitance between the first gate 100 and the ground layer 103. In some embodiments, the first gate dielectric layer 105 may also be located between the ground layer 103 and the first gate 100, for isolating the first gate 100 from the ground layer 103.

Referring to fig. 2, in some embodiments, the semiconductor structure further includes a write transistor 20, the write transistor 20 includes a third gate 104 and a second semiconductor layer 108 located on a sidewall of the third gate 104, and the second semiconductor layer 108 is electrically connected to the second gate 102.

The second semiconductor layer 108 may be disposed around the third gate 104, which is advantageous for increasing the surface area of the second semiconductor layer 108 while ensuring that the second semiconductor layer 108 occupies a smaller layout space, so as to increase the length of a channel formed in the second semiconductor layer 108, thereby advantageously increasing the facing area of the third gate 104 and the second semiconductor layer 108, so as to increase the control capability of the third gate 104 on the second semiconductor layer 108, and thus advantageously increasing the electrical performance of the write transistor 20. In some embodiments, the second semiconductor layer 108 may also be located only on a portion of the surface of the third gate 104.

In some embodiments, a third gate dielectric layer 111 is disposed between the second semiconductor layer 108 and the third gate 104. The material of the third gate dielectric layer 111 may include silicon oxide, silicon carbide, silicon nitride or other materials with high dielectric constant, which are used to suppress short channel effects, thereby suppressing tunneling leakage current and the like.

Referring to fig. 2, in some embodiments, a surface of the second semiconductor layer 108 facing the second gate electrode 102 may be in contact with the second gate electrode 102. Referring to fig. 4, in some embodiments, the second semiconductor layer 108 and the second gate electrode 102 may be electrically connected through a connection layer 109. The material of the connection layer 109 may include polysilicon, copper, aluminum, silver, tin, gold, nickel, lead, titanium, or tungsten, among others.

The read transistor 10 and the write transistor 20 provided in the embodiments of the present disclosure form a 2T0C type memory cell, and a capacitor is not required, which is beneficial to reducing the size of the semiconductor structure itself, so as to improve the integration density of the semiconductor structure.

The semiconductor structure further includes a bit line 110 electrically connected to the second semiconductor layer 108 and the first terminal 201.

A semiconductor structure including the read transistor 10, the write transistor 20, and the bit line provided by the embodiments of the present disclosure will be described in detail below.

Referring to fig. 2, in some embodiments, the write transistor 20 is located on a side of the read transistor 10 facing the first direction; the bit lines may include a first sub bit line 210 and a second sub bit line 310 connected, the first sub bit line 210 extending in a first direction, the second sub bit line 310 extending in a second direction, the first direction intersecting the second direction, and the first end 201 being located on a side of the second end 301 facing the second sub bit line 310, the first end 201 being in contact with the second sub bit line 310, the second semiconductor layer 108 being in contact with the first sub bit line 210.

The surface of the second semiconductor layer 108 facing the second gate 102 is in direct contact with the second gate 102, which is beneficial to further reducing the size of the memory cell formed by the read transistor 10 and the write transistor 20, thereby being beneficial to improving the integration density of the memory array structure. In some embodiments, the second semiconductor layer 108 and the second gate electrode 102 may also be electrically connected through a connection layer.

The material of the first sub-bit line 210 and the material of the second sub-bit line 310 may each include polysilicon, copper, aluminum, silver, tin (Sn), gold, nickel, lead, titanium, tungsten, or titanium nitride. The materials of the first sub-bit line 210 and the second sub-bit line 310 may be the same or different.

Referring to fig. 3, in some embodiments, the write transistor 20 is located on a side of the read transistor 10 facing the first direction; the bit lines may include a first sub bit line 210, a second sub bit line 310, and a third sub bit line 410 connected in sequence, the first sub bit line 210 and the third sub bit line 410 each extending in a second direction, the second sub bit line 310 extending in a first direction, the first direction intersecting the second direction, the first sub bit line 210 being located at a side of the write transistor 20 remote from the read transistor 10 and in contact with the second semiconductor layer 108, and the third sub bit line 410 being located at a side of the read transistor 10 remote from the write transistor 20 and in contact with the first end 201.

The surface of the second semiconductor layer 108 facing the second gate 102 is in direct contact with the second gate 102, which is beneficial to further reducing the size of the memory cell formed by the read transistor 10 and the write transistor 20, thereby being beneficial to improving the integration density of the memory array structure. In some embodiments, the second semiconductor layer 108 and the second gate electrode 102 may be electrically connected through a connection layer.

In some embodiments, the bit line may include two second sub bit lines 310, where the two second sub bit lines are located on two opposite sides of the third gate along the second direction, and each of the two second sub bit lines is connected to the first sub bit line and the third sub bit line.

In some embodiments, the write transistor 20 is located on a side of the read transistor 10 facing the second direction, the second semiconductor layer 108 is located on a side wall of the third gate 104 opposite to the side wall of the third gate 104 facing away from the read transistor 10 along the first direction, the first direction intersects the second direction, and the second gate 102 extends from the side of the second end 301 facing away from the ground layer 103 to the surface of the second semiconductor layer 108.

Specifically, referring to fig. 4, the write transistor 20 is located at a side of the read transistor 10 facing the second direction, the bit line 110 extends in the second direction, and the bit line 110 is in contact with the first terminal 201 and the second semiconductor layer 108. By the arrangement, the read transistor 10 and the write transistor 20 share one bit line, so that the number of bit lines required by the memory cells formed by the read transistor and the write transistor can be reduced, the overall size of the memory cells can be further reduced, the wiring complexity in the memory array structure can be reduced, and the integration density of the memory array structure can be further improved.

Wherein the second semiconductor layer is connected to the second gate electrode 102 through the connection layer 109.

Referring to fig. 5, the write transistor 20 is located at a side of the read transistor 10 facing the second direction, the bit line 110 extends in the second direction, and the bit line 110 is in contact with the first terminal 201 and the second semiconductor layer 108; the first end 201 may further extend from the bit line surface along the second direction and be connected to the second semiconductor layer 108, and the material of the first semiconductor layer 101 and the material of the second semiconductor layer 108 are the same. That is, the first semiconductor layer 101 and the second semiconductor layer 108 together form a semiconductor layer, and the first semiconductor layer 101 and the second semiconductor layer 108 can be manufactured in the same process step, which is beneficial to reducing the process steps for manufacturing the semiconductor structure, thereby improving the efficiency of manufacturing the semiconductor structure. It will be appreciated that referring to fig. 6, in some embodiments, the first semiconductor layer 101 and the second semiconductor layer 108 may not be connected.

Referring to fig. 5 and 6, the first semiconductor layer 101 may be disposed around three sides of the whole first gate electrode 100 and the ground layer 103, that is, the first semiconductor layer 101 includes a first end 201, a second end 301, and a middle portion, where the middle portion is located on a side of the first gate electrode 100 and the ground layer 103 facing away from the second semiconductor layer 108, so as to increase a distance between the first semiconductor layer 101 and the second semiconductor layer 108, reduce generation of parasitic capacitance between the first semiconductor layer 101 and the second semiconductor layer 108, and thus be beneficial to improving electrical performance of the semiconductor structure.

In some embodiments, the first semiconductor layer 101 may be integrally disposed around the first gate 100 and the ground layer 103, so as to increase the facing area of the first semiconductor layer 101 and the first gate 100, to increase the control capability of the third gate 104 on the first semiconductor layer 101, thereby being beneficial to improving the electrical performance of the read transistor 10.

With continued reference to fig. 5, the second gate 102 may be located on a sidewall of the second end 301, and the second gate 102 may further extend to a sidewall of the first semiconductor layer 101 facing away from the first gate 100 and the third gate 104, so that the first semiconductor layer 101, the second semiconductor layer 108, the first gate 100 and the third gate 104 are located between the bit line and the second gate 102, which is beneficial to reducing a size of a memory cell formed by the read transistor 10 and the write transistor 20, so as to increase an integration density of a memory array structure including a plurality of memory cells and bit lines, and the second gate 102 extends from a side of the second end 301 facing away from the ground layer 103 to a surface of the second semiconductor layer 108, and further ensures that a facing area between the second gate 102 and the first semiconductor layer 101 and a facing area between the second gate 102 and the second semiconductor layer 108 are larger.

In some embodiments, the second gate 102 may be located on a sidewall of the second end 301 and extend to a sidewall of the first semiconductor layer 101 opposite to the second direction, and the second gate 102 is spaced from the bit line along the first direction, so that a facing area of the second gate 102 and the first semiconductor layer 101 can be increased to improve a control capability of the second gate 102 on the first semiconductor layer 101, so as to improve an electrical performance of the semiconductor structure.

The second semiconductor layer 108 may be located on a sidewall of the third gate 104 opposite to the third gate 104 along the first direction and extend to a sidewall of the third gate 104 facing away from the read transistor 10 (refer to fig. 5 and 6), so as to increase a distance between the first semiconductor layer 101 and the second semiconductor layer 108, reduce a parasitic capacitance generated between the first semiconductor layer 101 and the second semiconductor layer 108, and thus facilitate improving electrical performance of the semiconductor structure. Or the second semiconductor layer 108 may be disposed around the third gate 104 to increase the facing area of the second semiconductor layer 108 and the third gate 104 to increase the control capability of the third gate 104 on the second semiconductor layer 108, thereby facilitating the improvement of the electrical performance of the write transistor 20.

The write transistor 20 is located at a side of the read transistor 10 facing the second direction, the bit line 110 extends along the second direction, and the bit line 110 contacts the first terminal 201 and the second semiconductor layer 108. In some embodiments, the second gate 102 may be located at a sidewall of the second semiconductor layer facing away from the bit line 110 (refer to fig. 6). In some embodiments, the second gate 102 may be located on a sidewall of the second semiconductor layer facing away from the bit line 110 and on a sidewall of the second semiconductor layer facing away from the first gate (referring to fig. 5), so as to increase a facing area of the second gate 102 and the second semiconductor layer, so as to increase a control capability of the second gate 102 on the second semiconductor layer, so as to increase an electrical performance of the semiconductor structure. In some embodiments, the second semiconductor layer is disposed around the third gate, and the second gate may be located on a sidewall of the second semiconductor layer facing away from the bit line 110, and on sidewalls of opposite sides of the second semiconductor layer along the second direction, and disposed between the second gate 102 and the bit line along the first direction, so that a facing area of the second gate 102 and the second semiconductor layer can be increased, so as to improve a control capability of the second gate 102 on the second semiconductor layer, and improve an electrical performance of the semiconductor structure.

In some embodiments, an insulating layer 112 may be further disposed between the read transistor 10 and the write transistor 20, where the insulating layer is used to isolate the conductive film layers in the read transistor 10 and the write transistor 20, so as to reduce parasitic capacitance, thereby improving performance of the semiconductor structure. For example, the first semiconductor layer 101 may be located on a sidewall of the first gate 100 and the ground layer 103 facing the third gate 104, and the second semiconductor layer 108 may be located on a sidewall of the third gate 104 facing the first gate 100 and the ground layer 103, and by providing the insulating layer 112, parasitic capacitance between the first semiconductor layer 101 and the second semiconductor layer 108 may be reduced, so as to improve electrical performance of the semiconductor structure.

Fig. 7 is a schematic circuit diagram of a semiconductor structure according to an embodiment of the disclosure.

Referring to fig. 2 and 7, in the semiconductor structure provided in the embodiment of the present disclosure, the read transistor 10 and the write transistor 20 form a dual-gate 2T0C memory cell, and a capacitor is not required, which is beneficial to reducing the size of the semiconductor structure itself, so as to improve the integration density of the semiconductor structure. In some embodiments, the first semiconductor layer 101 includes a first source drain region, a first channel region, and a second source drain region that are sequentially connected, and the second semiconductor layer 108 includes a third source drain region, a second channel region, and a fourth source drain region that are sequentially connected, where the first source drain region is electrically connected to the ground layer 103, and the fourth source drain region is electrically connected to the second gate 102.

The second gate electrode 102 may serve as a charge storage electrode layer (i.e., a capacitor electrode layer), and the second gate dielectric layer may serve as a charge storage dielectric layer (i.e., a capacitor dielectric layer) storing signal information, wherein the fourth source drain region and the second gate electrode 102 electrically connected constitute a storage node SN.

The semiconductor structure also includes a write word line WWL, a read word line RWL, and a bit line BL. The third gate 104 of the write transistor 20 is electrically connected to the write word line WWL, the first channel region of the read transistor 10 is electrically connected to the read word line RWL, and the bit line BL is electrically connected to the second source drain region and the third source drain region.

Referring to fig. 7, the step of performing a write operation on the semiconductor structure provided in the embodiment of the present disclosure may include: applying a voltage to write word line WWL to turn on the write transistor and applying a voltage to bit line BL to charge storage node SN to cause the storage node SN to exhibit either a high voltage or a low voltage representing data 1 and 0, respectively; in the writing operation to the storage node SN, a voltage is not applied to the read word line RWL so as not to supply a voltage signal to a gate electrically connected to the read word line RWL in the read transistor.

Referring to fig. 7, the step of performing a read operation of the semiconductor structure provided in the embodiment of the present disclosure may include: applying voltage to the read word line RWL to provide a voltage signal to a gate electrode electrically connected with the read word line RWL, applying voltage to a source/drain region of the read transistor which is not electrically connected with the bit line BL, and judging the potential at the storage structure SN by detecting the magnitude of current in the bit line BL so as to perform a read operation on the storage node SN; during a read operation on the storage node SN, no voltage signal is provided to the gate of the write transistor.

Compared with the read transistor 10 being a single-gate transistor, the read transistor 10 provided in the foregoing embodiment uses the read word line RWL to perform the read operation on the gate electrically connected to the read word line RWL in the read transistor 10, thereby being beneficial to using two gates of the read transistor 10 to respectively complete the data storage and the read/write operation control, and having more flexibility in the read/write operation of the 2T0C type memory cell formed based on the advantage of the gate control read/write operation.

And the memory cell is controlled by two word lines (a first word line WWL and a second word line RWL) and one bit line BL, so that the number of bit lines required by the memory cell is reduced, the overall size of the memory cell is reduced, the wiring complexity in the memory array structure is reduced, and the integration density of the memory array structure is improved.

In addition, when the read word line RWL in the memory array structure is electrically connected to the first gate 100 in the read transistor 10, the magnitude of the current flowing through the read word line RWL is small, and it can be considered that the current flowing through the read word line RWL is 0, the number of the read transistors 10 electrically connected to the same read word line RWL is not limited, so that the memory density of the memory array structure is advantageously improved.

Accordingly, another embodiment of the present disclosure further provides a memory array structure, where the memory array structure provided in another embodiment of the present disclosure includes the semiconductor structure provided in the foregoing embodiment. The semiconductor structure provided in another embodiment of the present disclosure will be described in detail with reference to the accompanying drawings, and the same or corresponding parts as those of the previous embodiment may be referred to for the corresponding description of the previous embodiment, which will not be repeated in detail.

Fig. 8 is a schematic top view of a first memory array structure according to another embodiment of the present disclosure, fig. 9 is a schematic top view of a cross-section along an AA1 direction of the first memory array structure according to another embodiment of the present disclosure, fig. 10 is a schematic top view of a second memory array structure according to another embodiment of the present disclosure, fig. 11 is a schematic top view of a cross-section along a BB1 direction of the second memory array structure according to another embodiment of the present disclosure, fig. 12 is a schematic top view of a third memory array structure according to another embodiment of the present disclosure, fig. 13 is a schematic top view of a fourth memory array structure according to another embodiment of the present disclosure, and fig. 14 is a schematic top view of a cross-section along a CC1 direction of the fourth memory array structure according to another embodiment of the present disclosure.

The memory array structure comprises a plurality of semiconductor structures, the plurality of semiconductor structures are arranged in an array along a first direction, a second direction and a third direction, the first direction, the second direction and the third direction are intersected in pairs, and adjacent first grid electrodes are electrically connected along the third direction to form a read word line. In the embodiment of the disclosure, the first direction, the second direction and the third direction are perpendicular to each other, where the first direction is along the direction of the first end of the first semiconductor layer toward the second end, and the third direction is perpendicular to the extending direction of the bit line.

Referring to fig. 8 and 9, the semiconductor structure provided in the foregoing embodiment may include: the read transistor 10, the write transistor 20 and the bit line 110 extending along the second direction, the write transistor 20 includes a third gate 104 and a second semiconductor layer 108, and the read transistor 10 includes a first semiconductor layer 101, a first gate 100 and a second gate 102; in the memory array structure, the second semiconductor layer 108 of the write transistor 20 is electrically connected to the second gate of the read transistor 10 in a one-to-one correspondence manner to form a plurality of memory cells, the bit line 110 is located between two adjacent memory cells arranged along the first direction and is electrically connected to the second semiconductor layer and the first end of the two memory cells, the adjacent third gate 104 is electrically connected along the third direction to form a write word line, and the adjacent first gate 100 is electrically connected to form a read word line.

In this way, the read transistor 10 and the write transistor 20 in the memory cell share one bit line, which can reduce the number of bit lines required by the memory cell, so as to reduce the overall size of the memory cell and reduce the complexity of the wiring in the memory array structure, thereby improving the integration density of the memory array structure.

In fig. 8 and 9, the write transistor 20 may be located at a side of the read transistor 10 facing the second direction, the bit line 110 extends along the second direction, and the bit line 110 contacts the first end 201 and the second semiconductor layer 108; wherein the first semiconductor layer 101 and the second semiconductor layer 108 are not connected. In some embodiments, the first end 201 may also extend from the bit line surface in the second direction and be connected to the second semiconductor layer 108, and the material of the first semiconductor layer 101 and the material of the second semiconductor layer 108 are the same. That is, the first semiconductor layer 101 and the second semiconductor layer 108 together form a semiconductor layer, and the first semiconductor layer 101 and the second semiconductor layer 108 can be manufactured in the same process step, which is beneficial to reducing the process steps for manufacturing the semiconductor structure, thereby improving the efficiency of manufacturing the semiconductor structure.

It will be appreciated that since the read transistor is a double gate transistor and the write transistor is a single gate transistor, the read transistor may be provided with a larger volume to accommodate more layers of the read transistor, such as the first gate, the second gate, the first semiconductor layer, and the ground layer. Referring to fig. 13 and 14, in some embodiments, the bit line 110 extends along the second direction, two adjacent memory cells arranged along the first direction are located between the two bit lines, one of the two bit lines is electrically connected to the second semiconductor layer and the first end of the memory cell adjacent to the one bit line, and the other bit line is electrically connected to the second semiconductor layer and the first end of the other memory cell, and the read transistor and the write transistor are staggered along the first direction, so as to reduce the size of the memory array structure, thereby being beneficial to improving the integration density of the memory array structure. Wherein the write transistor 20 is located at a side of the read transistor 10 facing the second direction, and the second semiconductor layer of the write transistor is connected to the second gate of the read transistor through the connection layer 109. It should be noted that, reference is made to the foregoing embodiments for detailed description of the read transistor, the write transistor, the bit line and the connection layer in the memory array structure.

Referring to fig. 10 and 11, in some embodiments, the bit line may include a first sub bit line 210, a second sub bit line 310, and a third sub bit line 410 sequentially connected, the first sub bit line 210 and the third sub bit line 410 each extending along a second direction, the second sub bit line 310 extending along a first direction, the first direction intersecting the second direction, the first sub bit line 210 being located on a side of the write transistor 20 away from the read transistor 10 and in contact with the second semiconductor layer 108, and the third sub bit line 410 being located on a side of the read transistor 10 away from the write transistor 20 and in contact with the first end 201.

In the memory array structure, the first sub-bit line 210 is in contact with the second semiconductor layer of the write transistor 20 arranged in the second direction, the third sub-bit line 410 is in contact with the first end of the read transistor 10 arranged in the second direction, and the third sub-bit line 410 is located between adjacent memory cells arranged in the second direction, wherein the memory cells are composed of a write transistor and a read transistor, and the second gate of the read transistor is in contact with the second semiconductor layer of the write transistor. In the third direction, adjacent third gates 104 are electrically connected to constitute a write word line, and adjacent first gates 100 are electrically connected to constitute a read word line.

Referring to fig. 12, each bit line 110 may include a first sub bit line 210, two second sub bit lines 310 and a third sub bit line 410, where the two second sub bit lines 310 are connected to the first sub bit line 210 and the third sub bit line 410; in the memory array structure, the first sub-bit lines are in contact with the second semiconductor layer in the write transistors 20 arranged along the second direction, the third sub-bit lines are in contact with the first ends of the read transistors 10 arranged along the second direction, and the two second sub-bit lines are respectively located at two opposite sides of a column of memory cells arranged along the second direction. In this way, the space occupied by the bit line 110 in the memory array structure can be further reduced, thereby being beneficial to improving the integration density of the memory array structure.

Accordingly, in still another aspect, the embodiments of the present disclosure provide a method for manufacturing a memory array structure, which is the same as or corresponding to the above embodiments, and will not be described in detail herein. Fig. 15 to 24 are schematic structural diagrams corresponding to steps in a method for manufacturing a memory array structure according to another embodiment of the present disclosure.

It should be noted that, fig. 15 to fig. 24 are schematic views of respective steps corresponding to a manufacturing method for forming two semiconductor structures arranged along a third direction, and the memory array structure includes a plurality of semiconductor structures, and a person skilled in the art can reduce the number of corresponding film layers on the basis of the schematic views to form the semiconductor structures; or increasing the number of layers to form an array structure.

Fig. 15 is a schematic cross-sectional view of a stacked structure in a step of forming the stacked structure in a method for manufacturing a memory array structure according to another embodiment of the present disclosure.

Referring to fig. 15, the manufacturing method includes: a laminate structure is provided comprising first film layers 31 and second film layers 32 alternately arranged. In this embodiment of the present disclosure, two memory cells (semiconductor structures) arranged in the third direction are taken as an example, and therefore, the number of second film layers is 2. The first film layers and the second film layers are alternately arranged along the third direction. The embodiment of the disclosure takes the first direction, the second direction and the third direction as examples, which are perpendicular to each other.

In some embodiments, the etching rates of the first film 31 and the second film 32 are different in the same etching process. The material of the first film 31 includes silicon oxide, and the material of the second film 32 includes silicon nitride or polysilicon. The embodiment of the disclosure takes polysilicon as an example of the material of the second film layer.

Fig. 16 is a schematic structural diagram of a second film layer corresponding to a step of forming a first via in a manufacturing method of a memory array structure according to another embodiment of the present disclosure, and fig. 17 is a schematic sectional structural diagram of a DD1 direction in fig. 16.

Referring to fig. 16 and 17, the first film 31 and the second film 32 are patterned to form a first via 33 penetrating the stacked structure; the second film layer 32 is etched along a portion of the width of the first via side to increase the width of the portion of the first via 33 located in the second film layer 32.

Fig. 18 is a schematic structural diagram of a second film layer corresponding to a step of forming a write transistor in a manufacturing method of a memory array structure according to another embodiment of the present disclosure, and fig. 19 is a schematic sectional view along the EE1 direction in fig. 18.

Referring to fig. 18 to 19, a write transistor 20 is formed, the write transistor 20 including a third gate 104, a second semiconductor layer 108 surrounding the third gate, adjacent third gates 108 extending in a third direction and electrically connected to constitute a write word line. The write transistor 20 further includes a third gate dielectric layer 111 between the second semiconductor layer and the third gate.

The step of forming the write transistor 20 may include: a second semiconductor layer 108, a third gate dielectric layer 111 and a write word line are sequentially formed on the surface of the second film layer in the first through hole, the second semiconductor layer 108 and the third gate dielectric layer 111 are located between the adjacent first film layer 31 and the first film layer 31, and the write word line fills the remaining area of the first through hole. The write word line is constituted by the third gate 104 connected in the third direction.

In some embodiments, the material of the second film layer may be polysilicon; before forming the write transistor, a first dielectric layer 34 is further formed, where the first dielectric layer 34 is located on the surface of the second film layer on the sidewall of the first via hole and between adjacent first film layers. The material of the first dielectric layer 34 may include a low dielectric constant material such as silicon carbide nitride or silicon carbide oxide. In some embodiments, the material of the second film layer may be silicon nitride, and the first dielectric layer may not be formed before forming the write transistor.

Fig. 20 is a schematic structural diagram of a second film layer corresponding to a step of forming a second via in a method for manufacturing a memory array structure according to another embodiment of the disclosure.

Referring to fig. 20, the remaining first film layer 31 and the remaining second film layer 32 are patterned to form a second through hole 35 penetrating through the laminated structure, the second through hole 35 being located at a side of the first through hole facing the first direction; the second film 32 is etched partially in width along the second via side direction to increase the width of the portion of the second via 35 located in the second film 32, and the second semiconductor layer 108 in the first via is exposed along the first direction by the second via side wall.

The foregoing embodiment may further remove the first dielectric layer 34 on the side of the second semiconductor layer 108 adjacent to the second via hole in the step of forming the second film layer 32 with the first dielectric layer 34 in the second via hole and etching a portion of the width along the side of the second via hole.

The step of laterally etching a portion of the width of the second film layer 32 along the second via to increase the width of the portion of the second via 35 located in the second film layer 32 includes: etching the second film layer 32 laterally along the second through hole until the surface of the second semiconductor layer facing the second through hole is exposed; and continuing to etch laterally along the second through hole. After the lateral etching is finished, the second through hole comprises a first sub-through hole located in the first film layer and a second sub-through hole located in the second film layer, the length of the first sub-through hole is smaller than that of the second sub-through hole along the first direction, the width of the first sub-through hole is smaller than that of the second sub-through hole along the second direction, and the width of the first film layer exposed on the bottom surface of the second sub-through hole adjacent to one side of the first through hole is smaller than that of the first film layer exposed on the bottom surface of the second sub-through hole far away from one side of the first through hole along the second direction.

Fig. 21 is a schematic structural diagram of a second film layer corresponding to a step of forming a second initial gate, a second initial gate dielectric layer, a first semiconductor layer, a ground layer, an isolation layer, a first gate dielectric layer, and a first gate in a manufacturing method of a memory array structure according to another embodiment of the present disclosure, fig. 22 is a schematic structural diagram of a cross section along a FF1 direction in fig. 21, fig. 23 is a schematic structural diagram of a second film layer corresponding to a step of forming a second gate and a second gate dielectric layer in a manufacturing method of a memory array structure according to another embodiment of the present disclosure, and fig. 24 is a schematic structural diagram of a cross section along a GG1 direction in fig. 23.

Referring to fig. 21 to 24, a read transistor 20 is formed, and the read transistor 20 includes a first gate 100, a ground layer 103, a second gate 102, and a first semiconductor layer 101 integrally disposed around the first gate and the ground layer, the second semiconductor layer being electrically connected to the second gate. Adjacent first gates 100 are electrically connected to constitute a read word line along a third direction, and are electrically connected between adjacent ground layers along the third direction.

The read transistor may further include an isolation layer 107 between the first gate 100 and the ground layer, a first gate dielectric layer 105, and a second gate dielectric layer 106 (refer to fig. 23), the first gate dielectric layer 105 being between the first gate 100 and the first semiconductor layer 101, and the second gate dielectric layer 106 being between the second gate and the first semiconductor layer.

The step of forming the read transistor may include: forming a second initial gate 36, a second initial gate dielectric layer 37 and a first semiconductor layer 101 in the second through hole in sequence, wherein the second initial gate 36, the second initial gate dielectric layer 37 and the first semiconductor layer are positioned between adjacent first film layers, the second initial gate 36, the second initial gate dielectric layer 37 and the first semiconductor layer 101 are positioned between adjacent first film layers, and the second initial gate 36 is in contact with the second semiconductor layer; the ground layer 103, the isolation layer 107, the first gate dielectric layer 105 and the read word line are formed, the ground layer 103 covers a portion of the sidewall of the first film layer in the second via hole, and covers the surface of the first semiconductor layer 101 facing away from the second film layer, the read word line includes a portion located in the first film layer of the second via hole, and the read word line further includes a portion located in the second film layer of the second via hole.

The order of forming the ground layer, the isolation layer, the first gate dielectric layer and the read word line is not limited, for example, the ground layer, the isolation layer, the first gate dielectric layer and the read word line may be sequentially formed in the second via.

In some embodiments, before forming the read transistor, a second dielectric layer 38 is further formed in the second via hole, the second dielectric layer being located between adjacent first film layers, the second dielectric layer covering opposite sidewalls of the second via hole in the second direction and sidewalls of the second via hole remote from the second semiconductor layer, the second dielectric layer also exposing the second semiconductor layer. The material of the second dielectric layer 34 may include a low dielectric constant material such as silicon carbide nitride or silicon carbide oxide.

The step of forming the second dielectric layer 38 may include: forming an initial second dielectric layer filled in the first sub-through holes and the second sub-through holes; removing an initial second dielectric layer in the first sub-through hole, removing an initial second dielectric layer in the second sub-through hole, which is opposite to the first sub-through hole area, and arranging the rest initial second dielectric layers around the side wall of the second sub-through hole and between the adjacent first film layers; wherein, the width of the first film layer exposed on the bottom surface of the second sub-through hole adjacent to the first through hole side is smaller than the width of the first film layer exposed on the bottom surface of the second sub-through hole far away from the first through hole side, and the width of the initial second dielectric layer contacted with the second semiconductor layer in the rest initial second dielectric layers is taken as a first width, and the first width is smaller than the width of the initial second dielectric layer on the opposite side wall of the second sub-through hole along the second direction and smaller than the width of the initial second dielectric layer on the side wall of the second sub-through hole far away from the second semiconductor layer; the initial second dielectric layer in contact with the second semiconductor layer is removed by lateral etching, the remaining initial second dielectric layer serves as a second dielectric layer 38, and it is understood that, since the width of the initial second dielectric layer in contact with the second semiconductor layer is the smallest in the remaining initial second dielectric layer, the thickness of the initial second dielectric layer in which each sidewall of the second sub-via is removed in a certain time is equal in the process of removing the initial second dielectric layer in contact with the second semiconductor layer by lateral etching, and the second semiconductor layer can serve as an etching stop layer for laterally etching the initial second dielectric layer, thereby enabling to ensure that the initial second gate dielectric layer in contact with the second semiconductor layer is removed and form the second dielectric layer with a certain thickness.

In some embodiments, the material of the second film layer may be silicon nitride, and the second dielectric layer may not be formed before forming the read transistor.

Referring to fig. 23 and 24, the second film 32 (refer to fig. 22) of the write transistor 20 on the side far from the first semiconductor layer 101 is removed by lateral etching until the surface of the second semiconductor layer 108 is exposed, and the second film 32, part of the second initial gate dielectric layer 37 and part of the second initial gate 36 of the first gate 100 on the side far from the write transistor are also removed by lateral etching until the first semiconductor layer 101 is exposed; wherein the remaining second initial gate dielectric layer 37 is used as a second gate dielectric layer 106, and the remaining second initial gate electrode 36 is used as a second gate electrode 102; the first sub-bit line 210 and the third sub-bit line 410 are formed, the first sub-bit line 210 is in contact with the second semiconductor layer 108 and is located between adjacent first film layers 31, and the third sub-bit line 410 is in contact with the first semiconductor layer 101 and is located between adjacent first film layers 31.

In some embodiments, the material of the second film 32 may be polysilicon, and the remaining second film 32 is used as the second sub-bit line 310, where the second sub-bit line 310 and the first sub-bit line and the third sub-bit line formed in the subsequent steps together form a bit line. In some embodiments, the material of the second film layer 32 may be silicon nitride, and before forming the first sub-bit line and the third sub-bit line, or after forming the first sub-bit line and the third sub-bit line, a second sub-bit line may be formed on two opposite sides of the second semiconductor layer and the second gate in the second direction, where the second sub-bit line is located between the adjacent first film layers, and the second sub-bit line is separated from the read transistor and the write transistor by the second film layer.

The second gate 102 has a notch at an end facing away from the second semiconductor layer, and the notch is surrounded by the second dielectric layer, the second gate and the second gate dielectric layer 106. Before forming the third sub-bit line 410, a third dielectric layer 39 filled with the notch may also be formed, and the third dielectric layer 39 is used to suppress the generation of parasitic capacitance between the second gate 102 and the third sub-bit line 410. The material of the third dielectric layer may include silicon nitride, silicon carbide nitride, silicon oxide, or silicon oxycarbide.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementing the disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the disclosure, and the scope of the disclosure should therefore be assessed as that of the appended claims.

Claims (10)

1. A semiconductor structure, comprising:

a read transistor, the read transistor comprising: the semiconductor device comprises a first grid, a first semiconductor layer, a second grid and a grounding layer, wherein the first grid and the grounding layer are arranged at intervals, the grounding layer is located on one side of the first grid facing a first direction, the first semiconductor layer extends from the side wall of the first grid to the side wall of the grounding layer, the first semiconductor layer comprises a first end and a second end which are opposite along the first direction, one of the first end and the second end is located on the side wall of the first grid, which is away from one side of the grounding layer, the other is in electrical contact with the grounding layer, and the second grid is located at least on one side of the second end, which is away from the grounding layer.

2. The semiconductor structure of claim 1, further comprising a write transistor comprising a third gate and a second semiconductor layer on a sidewall of the third gate, the second semiconductor layer being electrically connected to the second gate.

3. The semiconductor structure of claim 2, wherein a surface of the second semiconductor layer facing the second gate electrode is in contact with the second gate electrode or is electrically connected to the second gate electrode through a connection layer.

4. A semiconductor structure according to any one of claims 2 or 3, wherein the write transistor is located on a side of the read transistor facing the first direction; the semiconductor structure further includes a bit line;

The bit line comprises a first sub bit line and a second sub bit line which are connected, the first sub bit line extends along the first direction, the second sub bit line extends along the second direction, the first direction is intersected with the second direction, the first end is located at one side of the second end, facing the second sub bit line, the first end is in contact with the second sub bit line, and the second semiconductor layer is in contact with the first sub bit line.

5. A semiconductor structure according to any one of claims 2 or 3, wherein the write transistor is located on a side of the read transistor facing the first direction; the semiconductor structure further includes a bit line;

The bit line comprises a first sub bit line, a second sub bit line and a third sub bit line which are sequentially connected, the first sub bit line and the third sub bit line extend along a second direction, the second sub bit line extends along the first direction, the first direction is intersected with the second direction, the first sub bit line is located at one side, far away from the read transistor, of the write transistor and is in contact with the second semiconductor layer, and the third sub bit line is located at one side, far away from the write transistor, of the read transistor and is in contact with the first end.

6. The semiconductor structure of claim 2, wherein the write transistor is located on a side of the read transistor facing in a second direction, the second semiconductor layer being located at least on a side wall of the third gate opposite in the first direction and extending to a side wall of the third gate facing away from the read transistor, the first direction intersecting the second direction, the second gate extending from the side of the second end facing away from the ground layer to the second semiconductor layer surface.

7. The semiconductor structure of any one of claims 2, 3, or 6, wherein the write transistor is located on a side of the read transistor facing a second direction, the first direction intersecting the second direction; the semiconductor structure further includes a bit line extending in a second direction, and the bit line is in contact with the first end and the second semiconductor layer.

8. The semiconductor structure of claim 7, wherein the first end further extends from the bit line surface in the second direction and is connected to the second semiconductor layer, the first semiconductor layer being of the same material as the second semiconductor layer.

9. A memory array structure comprising a plurality of semiconductor structures according to any one of claims 1-8, wherein a plurality of the semiconductor structures are arranged in an array along a first direction, along a second direction, and along a third direction, the first direction, the second direction, and the third direction intersecting one another, and adjacent ones of the first gates are electrically connected along the third direction to form a read word line.

10. The memory array structure of claim 9, wherein the semiconductor structure further comprises: a write transistor and a bit line extending along the second direction, the write transistor including a third gate and a second semiconductor layer;

In the memory array structure, the second semiconductor layer of the write transistor is electrically connected with the second gate of the read transistor in a one-to-one correspondence manner so as to form a plurality of memory cells, the bit line is located between two adjacent memory cells arranged along the first direction and is electrically connected with the second semiconductor layer and the first end of the two memory cells, along the third direction, the adjacent third gate is electrically connected to form a write word line, and the adjacent first gate is electrically connected to form a read word line.