CN117857772A - Display control system, display control method and display device - Google Patents
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Abstract
The disclosure provides a display control system, a display control method and a display device, belongs to the technical field of display, and can solve the problem that the existing naked eye 3D display product is easy to shake or jam a display picture in the display process. The display control system of the present disclosure includes: a system processing chip and a field programmable gate array; the system processing chip is configured to calculate coordinate information according to the acquired image information, and send the coordinate information when receiving the analog frame interrupt signal; the field programmable gate array is configured to receive the coordinate information, match a corresponding picture to be displayed according to the coordinate information, and generate and transmit an analog frame interrupt signal according to the refresh frequency.
Description
Technical Field
The disclosure belongs to the technical field of display, and particularly relates to a display control system, a display control method and a display device.
Background
With the rise of artificial intelligence, a System on Chip (SoC) and a Field programmable gate array (Field-Programmable Gate Array, FPGA) are increasingly applied to the Field of algorithm hardware acceleration, and particularly for the processing of pictures, the parallel data processing manner of the SoC and the FPGA is adopted to process the pictures, so that the SoC and the FPGA can be applied to the Field of display technology.
In the naked eye 3D display technology, the SoC is responsible for writing data, the FPGA is responsible for reading data, both belong to asynchronous processes, and considering the transmission delay of an Input/Output (I/O) interface, it is possible that the content read by the FPGA is the content of the last frame, so that jitter or katon of the naked eye 3D display will be caused.
Disclosure of Invention
The disclosure aims to at least solve one of the technical problems in the prior art, and provides a display control system, a display control method and a display device.
In a first aspect, embodiments of the present disclosure provide a display control system, including: a system processing chip and a field programmable gate array;
the system processing chip is configured to calculate coordinate information according to the acquired image information, and send the coordinate information when receiving an analog frame interrupt signal;
the field programmable gate array is configured to receive the coordinate information, match a corresponding picture to be displayed according to the coordinate information, and generate and transmit an analog frame interrupt signal according to the refresh frequency.
In some embodiments, the system processing chip is further configured to determine whether the current analog frame interrupt signal is the same as the last analog frame interrupt signal, and cancel the current coordinate information if the current analog frame interrupt signal is the same as the last analog frame interrupt signal.
In some embodiments, the analog frame interrupt signal includes sequence number information, and the sequence number information in the analog frame interrupt signal is different each time.
In some embodiments, the display control system further comprises: an image collector;
the image collector is configured to scan an eye of a user and generate image information.
In some embodiments, the display control system further comprises: an image display;
the image display is configured to display the screen to be displayed.
In some embodiments, the system processing chip and the field programmable gate array are connected by a universal asynchronous receiver-transmitter interface.
In a second aspect, an embodiment of the present disclosure provides a display control method applied to the display control system provided above, where the display control method includes:
the system processing chip calculates coordinate information according to the acquired image information;
the system processing chip receives an analog frame interrupt signal according to the refresh frequency;
the system processing chip sends the coordinate information according to the analog frame interrupt signal;
the on-site logic gate array receives the coordinate information and matches a corresponding picture to be displayed according to the coordinate information;
the field logic gate array generates an analog frame interrupt signal according to the refresh frequency and transmits the analog frame interrupt signal.
In some embodiments, the system processing chip receives an analog frame interrupt signal, and then further comprises:
and the system processing chip judges whether the current analog frame interrupt signal is the same as the last analog frame interrupt signal, and if the current analog frame interrupt signal is the same as the last analog frame interrupt signal, the current coordinate information is canceled.
In some embodiments, the analog frame interrupt signal includes sequence number information, and the sequence number information in the analog frame interrupt signal is different each time.
In some embodiments, the system processing chip calculates coordinate information from the acquired image information, and further includes:
the image collector scans the eyes of the user and generates image information.
In some embodiments, the field logic gate array receives the coordinate information, matches a corresponding picture to be displayed according to the coordinate information, and then further includes:
and the image display displays the picture to be displayed.
In a third aspect, embodiments of the present disclosure provide a display device including a display control system as provided above.
Drawings
Fig. 1 is a schematic structural diagram of a display control system according to an embodiment of the disclosure.
Fig. 2 is a flow chart of a display control method according to an embodiment of the disclosure.
Detailed Description
In order that those skilled in the art will better understand the technical solutions of the present disclosure, the present disclosure will be described in further detail with reference to the accompanying drawings and detailed description.
Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the terms "a," "an," or "the" and similar terms do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.
In the field of naked eye 3D display, a camera is generally used to detect facial information of a user in real time to track eyes of the user. The System on Chip (SoC) is used for deploying an AI algorithm for face recognition and eyeball tracking, acquiring the image information by a camera, analyzing the image information in real time to obtain the coordinate information of the eyes of a user, and transmitting the coordinate information to a Field-programmable gate array (FPGA) through an Input/Output (I/O) interface. A Field programmable gate array (Field-Programmable Gate Array, FPGA) can adjust the display of pictures in a display panel according to the coordinate information of the eyes of a user,
since the frame rate of naked eye 3D display is relatively high, usually 60fps, that is, about 16.7ms, a frame of picture needs to be displayed, so that the coordinate information of eyes of a user needs to be set once about 16.7 ms. The traditional method is that the SoC analyzes the image information of the camera, identifies the face and human eye coordinate information in the camera by using an algorithm, then transmits data to a register of the FPGA through interfaces such as two-wire serial buses (Inter-Integrated Circuit, I2C), serial peripheral interfaces (Serial Peripheral Interface, SPI) and the like, the FPGA reads the information of the register at regular time, and then controls a display panel to display a 3D picture according to the coordinate information of eyes of a user.
An I2C bus is a simple, bi-directional two-wire synchronous serial bus that requires only two wires to transfer information between devices connected to the bus. The master is used to initiate bus transfer of data and generate a clock to open the transferred devices, any addressed device being considered a slave. The relationship of master and slave, transmit and receive on the bus is not constant but depends on the direction of data transfer at this time. If the host computer is to send data to the slave device, the host computer firstly addresses the slave device, then actively sends the data to the slave device, and finally the host computer terminates the data transmission; if the host is to receive data from the slave, the slave is addressed by the master first, then the host receives data sent by the slave, and finally the host terminates the receiving process. In this case, the host is responsible for generating the timing clock and terminating the data transfer. In the high speed mode, it can be received and transmitted at 400kbit/s, however, the transmission process is complicated.
The SPI interface is a synchronous peripheral interface that allows a single-chip microcomputer to communicate with various peripheral devices in a serial fashion to exchange information. The peripheral devices include random access memory (Random Access Memory, RAM), flash memory (flash memory), a network controller, a liquid crystal display driver, an a/D converter, a single chip microcomputer, and the like. Some devices SPI interface transmission rate can reach 50Mbps. The transmission rate of the SPI interface in the product mainly looks at the performance limit of the master-slave device. The SPI interface typically has 4 wires (four wire system) and not all boards have SPI thereon, resulting in a more complex structure.
In the practical application process, the SoC is responsible for writing data, the FPGA is responsible for reading data, the SoC and the FPGA are asynchronous processes, and considering the transmission delay of the I/O interface, it is possible that the content read by the FPGA is still the content of the previous frame, so that jitter or jamming of naked eye 3D display may be caused.
In order to solve at least one of the above technical problems, an embodiment of the present disclosure provides a display control system, a display control method, and a display device, and the display control system, the display control method, and the display device provided by the embodiment of the present disclosure will be described in further detail below with reference to the accompanying drawings and detailed description.
In a first aspect, an embodiment of the present disclosure provides a display control system, fig. 1 is a schematic structural diagram of the display control system provided in the embodiment of the present disclosure, and as shown in fig. 1, the display control system includes: a system processing chip 101 and a field programmable gate array 102. The system processing chip 101 is configured to calculate coordinate information from the acquired image information, and transmit the coordinate information upon receiving the analog frame interrupt signal. The field programmable gate array 102 is configured to receive the coordinate information, match a corresponding picture to be displayed according to the coordinate information, and generate and transmit an analog frame interrupt signal according to the refresh frequency.
An artificial intelligence (Artificial Intelligence, AI) algorithm is integrated in the system processing chip 101, and coordinate information can be calculated through the AI algorithm according to the acquired image information, wherein the image information is specifically image information of eyes of a user, and the coordinate information is specifically coordinate information of eyes of the user.
The field programmable gate array 102 may receive the coordinate information sent by the system processing chip 101, and may be further connected to a signal source, where the signal source may provide a picture to be displayed for the system processing chip 101. The field programmable gate array 102 matches the frame to be displayed provided by the signal source with the coordinate information, so as to realize the naked eye 3D display function.
The field programmable gate array 102 may send a series of data to the system processing chip 101, where the system processing chip 101 processes the data in an interrupt manner, where the series of data is sent at a speed of every 1/60S, and the data specifically sent is 32 bits of data, for example, may be 0x00000001, and the data is used as a frame synchronization signal. The system processing chip 101 receives a 32-bit data every 1/60s, and the system processing chip 101 reads the data in the form of asynchronous I/O as if it simulates a frame interrupt signal, and can send and receive the frame interrupt signal therebetween. A frame interrupt signal indicates that the field programmable gate array 102 has processed the coordinate information that was last transmitted by the system processing chip 101, so that the synchronous transmission of data between the system processing chip 101 and the field programmable gate array 102 can be achieved by simulating a frame interrupt.
In the display control system provided by the embodiment of the disclosure, the data synchronization transmission between the system processing chip 101 and the field programmable gate array 102 can be realized by simulating the frame interruption, so that the data transmission between the system processing chip 101 and the field programmable gate array 102 can be prevented from being delayed, the coordinate information which is transmitted by the system processing chip 101 this time and is processed by the field programmable gate array 102 each time is ensured, the data synchronization transmission between the system processing chip 101 and the field programmable gate array 102 can be realized, the coordinate information is ensured to be completely matched with the picture to be displayed, and the shake or the clamping of naked eye 3D display can be avoided.
In some embodiments, the system processing chip 101 is further configured to determine whether the current analog frame interrupt signal is the same as the last analog frame interrupt signal, and cancel the current coordinate information if the current analog frame interrupt signal is the same as the last analog frame interrupt signal.
The system processing chip 101 sends the serial number information of the present coordinate information while sending the coordinate information to the field programmable gate array 102 each time. The analog frame interrupt signal may contain the sequence number information, and the field programmable gate array 102 may feed back the sequence number information as analog frame interrupt information to the system processing chip 101.
If the current analog frame interrupt signal received by the system processing chip 101 is different from the last analog frame interrupt signal, that is, the current sequence number is greater than the last sequence number, it indicates that the field programmable gate array 102 has completed matching the last sent coordinate information with the picture to be displayed, and the system processing chip 101 can continue to send new coordinate information to realize synchronous transmission between the two.
If the current analog frame interrupt signal received by the system processing chip 101 is the same as the last analog frame interrupt signal, that is, the current sequence number is the last sequence number, it indicates that the field programmable gate array 102 has not completed matching the last sent coordinate information with the frame to be displayed, the system processing chip 101 can cancel the current coordinate information, and the current coordinate information is not sent to the field programmable gate array 102 any more, so that delay of data transmission between the two is avoided, and further jitter or jamming of naked eye 3D display can be avoided.
In some embodiments, as shown in fig. 1, the display control system further comprises: an image collector 103; the image collector 103 is configured to scan the eyes of the user and generate image information.
The image collector 103 may specifically be a camera, and the camera may scan the eyes of the user in real time and generate image information. In some application scenarios, the camera may also scan facial information of the user, for example, identify expression information of the user, to subsequently match the corresponding image to be displayed. The image collector 103 is connected with the system processing chip 101, specifically may be connected with a camera through an input port IN of a high-definition multimedia interface (High Definition Multimedia Interface, HDMI), and through an output port OUT of the HDMI, the image information collected by the camera may be transmitted to the system processing chip 101 through the HDMI interface, so that the system processing chip calculates the above image information, thereby obtaining coordinate information of eyes of a user.
In some embodiments, as shown in fig. 1, the display control system further comprises: an image display 104; the image display 104 is configured to display a screen to be displayed.
The image display 104 may be a display panel, which may be a liquid crystal display panel, an organic electroluminescent diode display panel, a micro light emitting diode display panel, a mini light emitting diode display panel, etc., and is not limited herein. The image display 104 is connected with the system processing chip 101, specifically, can be connected with the field programmable gate array 102 through an input port IN of a high-definition multimedia interface (High Definition Multimedia Interface, HDMI), and can be connected with a display panel through an output port OUT of the HDMI, and a picture to be displayed matched by the field programmable gate array 102 can be transmitted to the display panel and displayed, so that the naked eye 3D display effect is realized.
In some embodiments, as shown in FIG. 1, the system processing chip 101 and the field programmable gate array 102 are interfaced via a universal asynchronous receiver/Transmitter (UART) 105.
UARTs are a universal serial data bus for asynchronous communications that communicates bi-directionally, enabling full duplex transmission and reception. Compared with interfaces such as I2C, SPI, the UART can realize a full duplex mode, can transmit and receive simultaneously, can work at a working frequency of 1.5Mbps or even higher, and is simple in protocol, convenient to wire and more general.
As shown in fig. 1, the UART includes 3 connection lines, one is a ground line GND, one is a receiving line RX, and one is a transmitting line TX, and from the perspective of the SoC, the RX of the UART is responsible for receiving an analog frame interrupt signal sent from the FPGA, and the TX is responsible for sending coordinate information generated by the system processing chip 101 to the FPGA in a synchronous protocol manner. From the perspective of the FPGA, RX of the FPGA is connected with TX of the SoC, TX of the FPGA is connected with RX of the SoC, and GND of the FPGA is connected with GND of the SoC. RX, TX in the embodiments of the present disclosure are described in terms of SoC unless otherwise specified. It can be seen that, because the SoC and the FPGA multiplex the receive line RX and the transmit line TX on the UART, one input/output port is not required to be separately introduced, so that the complexity of logic and circuits is reduced.
In a second aspect, an embodiment of the present disclosure provides a display control method, which is applied to the display control system provided in any one of the embodiments described above, and fig. 2 is a schematic flow chart of the display control method provided in the embodiment of the present disclosure, and as shown in fig. 2, the display control method includes the following steps S201 to S205.
S201, the system processing chip calculates coordinate information according to the acquired image information.
S202, the system processing chip receives an analog frame interrupt signal according to the refresh frequency.
S203, the system processing chip sends the coordinate information according to the analog frame interrupt signal.
S204, the on-site logic gate array receives the coordinate information and matches the corresponding picture to be displayed according to the coordinate information.
S205, the field logic gate array generates an analog frame interrupt signal according to the refresh frequency and transmits the analog frame interrupt signal.
It should be noted that, the connection between the system processing chip 101 and the field programmable gate array 102 may refer to fig. 1, and will not be described in detail herein.
In the display control method provided by the embodiment of the disclosure, the data synchronization transmission between the system processing chip 101 and the field programmable gate array 102 can be realized by simulating the frame interruption, so that the data transmission between the system processing chip 101 and the field programmable gate array 102 can be prevented from being delayed, the coordinate information which is transmitted by the system processing chip 101 this time and is processed by the field programmable gate array 102 each time is ensured, the data synchronization transmission between the system processing chip 101 and the field programmable gate array 102 can be realized, the coordinate information is ensured to be completely matched with the picture to be displayed, and the shake or the clamping of naked eye 3D display can be avoided.
In some embodiments, S202, the system processing chip receives an analog frame interrupt signal according to the refresh frequency, and then further includes:
s202a, the system processing chip judges whether the current analog frame interrupt signal is the same as the last analog frame interrupt signal, and if the current analog frame interrupt signal is the same as the last analog frame interrupt signal, the current coordinate information is cancelled.
The system processing chip 101 sends the serial number information of the present coordinate information while sending the coordinate information to the field programmable gate array 102 each time. The analog frame interrupt signal may contain the sequence number information, and the field programmable gate array 102 may feed back the sequence number information as analog frame interrupt information to the system processing chip 101.
If the current analog frame interrupt signal received by the system processing chip 101 is different from the last analog frame interrupt signal, that is, the current sequence number is greater than the last sequence number, it indicates that the field programmable gate array 102 has completed matching the last sent coordinate information with the picture to be displayed, and the system processing chip 101 can continue to send new coordinate information to realize synchronous transmission between the two.
If the current analog frame interrupt signal received by the system processing chip 101 is the same as the last analog frame interrupt signal, that is, the current sequence number is the last sequence number, it indicates that the field programmable gate array 102 has not completed matching the last sent coordinate information with the frame to be displayed, the system processing chip 101 can cancel the current coordinate information, and the current coordinate information is not sent to the field programmable gate array 102 any more, so that delay of data transmission between the two is avoided, and further jitter or jamming of naked eye 3D display can be avoided.
In some embodiments, as shown in fig. 2, S201, the system processing chip calculates coordinate information according to the acquired image information, and step S201a is further included before.
S201a, the image collector scans the eyes of the user and generates image information.
The image collector 103 may specifically be a camera, and the camera may scan the eyes of the user in real time and generate image information. In some application scenarios, the camera may also scan facial information of the user, for example, identify expression information of the user, to subsequently match the corresponding image to be displayed. The image collector 103 is connected with the system processing chip 101, specifically may be connected with a camera through an input port IN of a high-definition multimedia interface (High Definition Multimedia Interface, HDMI), and through an output port OUT of the HDMI, the image information collected by the camera may be transmitted to the system processing chip 101 through the HDMI interface, so that the system processing chip calculates the above image information, thereby obtaining coordinate information of eyes of a user.
In some embodiments, as shown in fig. 2, S204, the field logic gate array receives the coordinate information, and matches the corresponding frame to be displayed according to the coordinate information, and then further includes step S204a.
S204a, the image display displays the picture to be displayed.
The image display 104 may be a display panel, which may be a liquid crystal display panel, an organic electroluminescent diode display panel, a micro light emitting diode display panel, a mini light emitting diode display panel, etc., and is not limited herein. The image display 104 is connected with the system processing chip 101, specifically, can be connected with the field programmable gate array 102 through an input port IN of a high-definition multimedia interface (High Definition Multimedia Interface, HDMI), and can be connected with a display panel through an output port OUT of the HDMI, and a picture to be displayed matched by the field programmable gate array 102 can be transmitted to the display panel and displayed, so that the naked eye 3D display effect is realized.
In a third aspect, a display device provided by an embodiment of the present disclosure includes a display control system provided by any one of the embodiments, where the display device may be a naked eye 3D display device, and the implementation principle and beneficial effects of the display control system provided by any one of the embodiments are the same as those of the display control system provided by any one of the embodiments, and are not described herein again.
It is to be understood that the above embodiments are merely exemplary embodiments employed to illustrate the principles of the present disclosure, however, the present disclosure is not limited thereto. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the disclosure, and are also considered to be within the scope of the disclosure.
Claims (12)
1. A display control system, the display control system comprising: a system processing chip and a field programmable gate array;
the system processing chip is configured to calculate coordinate information according to the acquired image information, and send the coordinate information when receiving an analog frame interrupt signal;
the field programmable gate array is configured to receive the coordinate information, match a corresponding picture to be displayed according to the coordinate information, and generate and transmit an analog frame interrupt signal according to the refresh frequency.
2. The display control system of claim 1, wherein the system processing chip is further configured to determine whether the current analog frame interrupt signal is identical to a last analog frame interrupt signal, and cancel the current coordinate information if the current analog frame interrupt signal is identical to the last analog frame interrupt signal.
3. The display control system of claim 2, wherein the analog frame interrupt signal includes sequence number information, and the sequence number information in the analog frame interrupt signal is different each time.
4. The display control system of claim 1, wherein the display control system further comprises: an image collector;
the image collector is configured to scan an eye of a user and generate image information.
5. The display control system of claim 1, wherein the display control system further comprises: an image display;
the image display is configured to display the screen to be displayed.
6. The display control system of claim 1, wherein the system processing chip and the field programmable gate array are coupled by a universal asynchronous receiver/transmitter interface.
7. A display control method applied to the display control system according to any one of claims 1 to 6, characterized by comprising:
the system processing chip calculates coordinate information according to the acquired image information;
the system processing chip receives an analog frame interrupt signal according to the refresh frequency;
the system processing chip sends the coordinate information according to the analog frame interrupt signal;
the on-site logic gate array receives the coordinate information and matches a corresponding picture to be displayed according to the coordinate information;
the field logic gate array generates an analog frame interrupt signal according to the refresh frequency and transmits the analog frame interrupt signal.
8. The display control method according to claim 7, wherein the system processing chip receives an analog frame interrupt signal, and further comprising:
and the system processing chip judges whether the current analog frame interrupt signal is the same as the last analog frame interrupt signal, and if the current analog frame interrupt signal is the same as the last analog frame interrupt signal, the current coordinate information is canceled.
9. The display control method according to claim 8, wherein the analog frame interrupt signal contains sequence number information, and the sequence number information in the analog frame interrupt signal is different each time.
10. The display control method according to claim 7, wherein the system processing chip calculates coordinate information from the acquired image information, further comprising:
the image collector scans the eyes of the user and generates image information.
11. The display control method according to claim 7, wherein the field logic gate array receives the coordinate information and matches a corresponding picture to be displayed according to the coordinate information, and further comprising:
and the image display displays the picture to be displayed.
12. A display device, characterized in that the display device comprises the display control system according to any one of claims 1 to 6.
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