CN117856767B - Schmitt trigger - Google Patents
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- CN117856767B CN117856767B CN202410258311.1A CN202410258311A CN117856767B CN 117856767 B CN117856767 B CN 117856767B CN 202410258311 A CN202410258311 A CN 202410258311A CN 117856767 B CN117856767 B CN 117856767B
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Abstract
The invention discloses a Schmitt trigger, which relates to the technical field of electronic circuits and is used for still ensuring that the Schmitt trigger can normally transmit an input signal when the logic high level of an input pulse is different from the power supply voltage of the Schmitt trigger. The Schmitt trigger comprises a biasing circuit, a driving circuit, a shaping circuit and an output circuit which are electrically connected in sequence, wherein: the bias circuit is used for providing a target bias current and a target bias voltage for the drive circuit; the driving circuit is used for driving the shaping circuit to be conducted under the action of the target bias current and the target bias voltage when the logic level voltage of the input signal is larger than or equal to the preset threshold voltage and smaller than the power supply voltage; the shaping circuit is used for outputting a shaping signal after shaping the waveform of the input signal; the output circuit is used for outputting the target shaping signal after the shaping signal is subjected to the reverse phase processing.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a Schmitt trigger.
Background
Schmitt trigger is widely used in digital input ports of chips to shape digital signals (especially rectangular pulse signals) externally input into the chips and to suppress spike noise, and the shaped signals output by the schmitt trigger have the same logic high level as the power supply voltage of the schmitt trigger (i.e., the power supply voltage of the chips).
In a general use scenario, the schmitt trigger can correctly transmit an input signal only by ensuring that the logic high level of the input pulse is the same as the power supply voltage of the schmitt trigger. However, when the logic high level of the input pulse is different from the power supply voltage of the schmitt trigger, the schmitt trigger cannot correctly transmit the input signal in the process of transmitting the logic high level, so that the accuracy and the reliability of the circuit in terms of signal processing are affected.
Based on this, how to ensure that the schmitt trigger can normally transmit the input signal when the logic high level of the input pulse is different from the supply voltage of the schmitt trigger is a problem to be solved.
Disclosure of Invention
The invention aims to provide a Schmitt trigger which is used for ensuring that the Schmitt trigger can normally transmit an input signal when the logic high level of an input pulse is different from the power supply voltage of the Schmitt trigger.
In order to achieve the above object, the present invention provides a schmitt trigger, comprising a bias circuit, a driving circuit, a shaping circuit and an output circuit electrically connected in sequence, wherein: the bias circuit is used for providing a target bias current and a target bias voltage for the drive circuit; the driving circuit is used for driving the shaping circuit to be conducted under the action of the target bias current and the target bias voltage when the logic level voltage of the input signal is larger than or equal to the preset threshold voltage and smaller than the power supply voltage; the shaping circuit is used for outputting a shaping signal after shaping the waveform of the input signal; the output circuit is used for outputting the target shaping signal after the shaping signal is subjected to the reverse phase processing.
Compared with the prior art, in the schmitt trigger provided by the invention, the bias circuit can provide the target bias current and the target bias voltage for the driving circuit, so that the driving circuit can drive the shaping circuit to be conducted when the logic level voltage of the input signal is larger than or equal to the preset threshold voltage and smaller than the power supply voltage, and the shaping signal is output after the waveform of the input signal is shaped, and the target shaping signal is output after the output circuit inverts the shaping signal. Based on the above, in the schmitt trigger provided by the invention, due to the existence of the bias circuit and the driving circuit, when the logic level voltage of the input signal is smaller than the power supply voltage, the schmitt trigger can still accurately identify the input signal and shape the waveform of the input signal, so that the effective information in the input signal can be normally transmitted, and the accuracy and the reliability of the schmitt trigger are improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings:
FIG. 1 is a schematic circuit diagram of a Schmitt trigger according to the prior art;
FIGS. 2 (a) -2 (b) are schematic diagrams of transmission signals of Schmitt triggers in the prior art;
FIG. 3 is a schematic circuit diagram of a Schmitt trigger according to an embodiment of the present invention;
fig. 4 is a schematic diagram of transmission signals of a schmitt trigger according to an embodiment of the invention.
Reference numerals:
a 1-bias circuit, a 2-drive circuit,
A 3-shaping circuit, a 4-output circuit,
31-A first level shaping module, 32-a second level shaping module,
11-Bias current generation module, 12-bias voltage generation module,
21-First drive module, 22-second drive module.
Detailed Description
In order to clearly describe the technical solution of the embodiments of the present invention, in the embodiments of the present invention, the words "first", "second", etc. are used to distinguish the same item or similar items having substantially the same function and effect. For example, the first threshold and the second threshold are merely for distinguishing between different thresholds, and are not limited in order. It will be appreciated by those of skill in the art that the words "first," "second," and the like do not limit the amount and order of execution, and that the words "first," "second," and the like do not necessarily differ.
In the present invention, the words "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.
In the present invention, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a alone, a and B together, and B alone, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b or c may represent: a, b, c, a and b, a and c, b and c, or a, b and c, wherein a, b, c can be single or multiple.
Currently, schmitt triggers are widely used in digital input ports of chips to shape digital signals (especially rectangular pulse signals) externally input into the chip and suppress spike noise. The logic high level V OUTH of the shaped signal output by the prior schmitt trigger is the same as the supply voltage V DD of the schmitt trigger (i.e., the supply voltage of the chip).
The general circuit structure of a conventional schmitt trigger in a complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) process is shown in fig. 1, and the main structure of the schmitt trigger is composed of a transistor PM1', a transistor PM2', a transistor PM3', a transistor NM1', a transistor NM2', and a transistor NM 3'. When the input signal V IN is a trapezoidal pulse and the logic high level V INH of the input signal V IN is equal to the power supply voltage V DD of the schmitt trigger, the output signal V OUT' is a rectangular pulse with the shaped high level V DD and the shaped low level GND.
In a general usage scenario, if the logic high level V INH of the input signal V IN is equal to the power supply voltage V DD of the schmitt trigger, the schmitt trigger can correctly transmit the input signal V IN, as shown in fig. 2 (a). However, in some special usage scenarios, the logic high level V INH of the input signal V IN and the supply voltage V DD of the schmitt trigger may not be equal. Assuming that the threshold V TH=0.7*VDD of the logic high level of the schmitt trigger, when V INH<0.7*VDD, the schmitt trigger will not be able to correctly transmit the input signal V IN, as shown in fig. 2 (b), when the input signal V IN is a trapezoidal impact pulse and the logic high level V INH of the input signal V IN is smaller than the threshold V TH of the logic high level of the schmitt trigger, the schmitt trigger cannot recognize the input signal V IN, so that the output signal V OUT' thereof becomes an error signal with the low level GND, and cannot normally transmit the valid information in the input signal V IN.
In order to solve the above-mentioned problems, as shown in fig. 3, an embodiment of the present invention provides a schmitt trigger, which includes a bias circuit 1, a driving circuit 2, a shaping circuit 3, and an output circuit 4 electrically connected in sequence, wherein: the bias circuit 1 is used for providing a target bias current I 2 and a target bias voltage V 2 to the drive circuit 2; the driving circuit 2 is configured to drive the shaping circuit 3 to be turned on under the action of the target bias current I 2 and the target bias voltage V 2 when the logic level voltage of the input signal V IN is greater than or equal to the preset threshold voltage and less than the supply voltage; the shaping circuit 3 is used for shaping the waveform of the input signal V IN and outputting a shaped signal; the output circuit 4 is configured to output the target shaped signal V OUT after performing an inversion process on the shaped signal.
As can be seen from the specific structure of the schmitt trigger, the bias circuit 1 can provide the target bias current I 2 and the target bias voltage V 2 to the driving circuit 2, so that when the logic level voltage of the input signal V IN is greater than or equal to the preset threshold voltage and less than the supply voltage, the driving circuit 2 can drive the shaping circuit 3 to be turned on, so that the waveform of the input signal V IN is shaped, the shaped signal is output, and the output circuit 4 inverts the shaped signal and outputs the target shaped signal V OUT. Based on this, in the schmitt trigger provided in the embodiment of the present invention, due to the bias circuit 1 and the driving circuit 2, when the logic level voltage of the input signal V IN is smaller than the supply voltage, the schmitt trigger can still accurately identify the input signal V IN and shape the waveform of the input signal V IN, so that the effective information in the input signal V IN can be normally transmitted, and the accuracy and reliability of the schmitt trigger are improved.
In the present application, the output circuit 4 includes an inverter, an input terminal of which is electrically connected to an output terminal of the shaping circuit 3, and an output terminal of which is configured to output the target shaping signal V OUT. Based on this, the output circuit 4 can perform an inversion process on the shaped signal output from the shaping circuit 3, thereby outputting the shaped target shaped signal V OUT.
In a possible implementation, as shown in fig. 3, the shaping circuit 3 comprises a first level shaping module 31 and a second level shaping module 32 electrically connected. The control end of the first level shaping module 31 is electrically connected to the control end of the second level shaping module 32 through the driving circuit 2, and the control end of the second level shaping module 32 is configured to receive the input signal V IN. The first level shaping module 31 is configured to, when the logic level voltage of the input signal V IN is a low level voltage, shape the waveform of the input signal V IN under the action of the driving circuit 2, and output a shaped signal to the output circuit 4. The second level shaping module 32 is configured to, when the logic level of the input signal V IN is greater than or equal to the preset threshold voltage and less than the supply voltage, perform shaping processing on the waveform of the input signal V IN under the action of the driving circuit 2, and output a shaped signal to the output circuit 4.
Based on this, when the logic level of the input signal V IN is low, the first level shaping module 31 is turned on by the driving circuit 2, so that the shaping process is performed on the low-level input signal V IN, and the shaped signal having the level GND can be output to the output circuit 4. When the logic level voltage of the input signal V IN is greater than or equal to the preset threshold voltage and less than the supply voltage, the second level shaping module 32 is turned on under the action of the driving circuit 2, so as to perform shaping processing on the high-level input signal V IN, and can output a shaped signal with a level V DD to the output circuit 4.
In some embodiments, the first level shaping module 31 comprises: the first P-type transistor PM1, the second P-type transistor PM2 and the third P-type transistor PM3. The gate of the first P-type transistor PM1 and the gate of the second P-type transistor PM2 are electrically connected to the driving circuit 2, the source of the first P-type transistor PM1 is electrically connected to the power supply voltage terminal, the drain of the first P-type transistor PM1 and the source of the second P-type transistor PM2 are electrically connected to the source of the third P-type transistor PM3, the drain of the third P-type transistor PM3 is grounded, and the gate of the third P-type transistor PM3 and the drain of the second P-type transistor PM2 are electrically connected to the second level shaping module 32.
In some embodiments, as shown in fig. 3, the second level shaping module 32 includes: the first N-type transistor NM1, the second N-type transistor NM2, the third N-type transistor NM3, the fourth N-type transistor NM4, and the fourth P-type transistor PM4. The gate of the first N-type transistor NM1 and the gate of the second N-type transistor NM2 are both used for receiving the input signal V IN, the drain of the first N-type transistor NM1 and the gate of the third N-type transistor NM3 are both electrically connected to the first level shaping module 31, the source of the first N-type transistor NM1 and the drain of the second N-type transistor NM2 are both electrically connected to the source of the third N-type transistor NM3, and the source of the second N-type transistor NM2 is grounded. The drain of the third N-type transistor NM3 is electrically connected to the source of the fourth N-type transistor NM4, the drain of the fourth N-type transistor NM4 is electrically connected to the drain of the fourth P-type transistor PM4, the source of the fourth P-type transistor PM4 is electrically connected to the power supply voltage terminal, the gate of the fourth N-type transistor NM4 is electrically connected to the voltage output terminal of the bias circuit 1, and the gate of the fourth P-type transistor PM4 is grounded.
Specifically, the first control end of the driving circuit 2 is electrically connected to the input end of the output circuit 4, and the second control end of the driving circuit 2 is configured to receive the target bias voltage V 2.
When the input signal V IN =0 ("0" is only indicated as low level and does not indicate that the actual voltage input is 0V), the node where the driving circuit 2 is connected to the receiving end of the input signal V IN corresponds to the ground, the driving circuit 2 is turned on by the second control end under the effect of the target bias voltage V 2, so that the gate voltage of the first P-type transistor PM1 and the gate voltage of the second P-type transistor PM2 are both pulled down to low level, that is, V 3 =0, and the first P-type transistor PM1 and the second P-type transistor PM2 are both turned on, so that the first level shaping module 31 completes the shaping processing of the input signal V IN and outputs the shaped signal with the level V DD to the output circuit 4.
It should be understood that the above-mentioned predetermined threshold voltage should be at least greater than the threshold voltages V TH ≡0.7V of the first N-type transistor NM1 and the second N-type transistor NM2, and the difference between the target bias voltage V 2 and the input signal V IN should avoid the second control terminal of the driving circuit 2 from being turned on.
In this way, when the logic level voltage of the input signal V IN is greater than or equal to the preset threshold voltage and less than the supply voltage V DD, the logic level of the input signal V IN needs to drive the second level shaping module 32 to be turned on under the condition that the second control terminal of the driving circuit 2 is turned off, so that the second level shaping module 32 can perform shaping processing on the high-level input signal V IN, and output a shaped signal with level 0 to the output circuit 4.
In one possible implementation, as shown in fig. 3, the bias circuit 1 includes a bias current generation module 11 and a bias voltage generation module 12 that are electrically connected. An output terminal of the bias current generating module 11 is electrically connected to a first terminal of the driving circuit 2 for providing a target bias current I 2 to the driving circuit 2. The output end of the bias voltage generating module 12 is electrically connected to the first control end of the driving circuit 2, and is configured to provide the target bias voltage V 2 to the driving circuit 2, so as to control the driving circuit 2 to turn off under the action of the second control end when the logic level voltage of the input signal V IN is greater than or equal to the preset threshold voltage and less than the supply voltage.
In some embodiments, as shown in fig. 3, the bias current generation module 11 includes: fifth P-type transistor PM5, sixth P-type transistor PM6, seventh P-type transistor PM7, and eighth P-type transistor PM8. The source of the fifth P-type transistor PM5, the source of the sixth P-type transistor PM6, the source of the seventh P-type transistor PM7, and the source of the eighth P-type transistor PM8 are all electrically connected to the power supply voltage terminal, the gate of the fifth P-type transistor PM5, the gate of the sixth P-type transistor PM6, the gate of the seventh P-type transistor PM7, and the gate of the eighth P-type transistor PM8 are all electrically connected to the bias voltage generation module 12, and the drain of the fifth P-type transistor PM5, the drain of the sixth P-type transistor PM6, and the drain of the seventh P-type transistor PM7 are each electrically connected to a transistor in the bias voltage generation module 12, respectively, and the drain of the eighth P-type transistor PM8 is electrically connected to the driving circuit 2.
In some embodiments, as shown in fig. 3, the bias voltage generation module 12 includes: a fifth N-type transistor NM5, a sixth N-type transistor NM6, a ninth P-type transistor PM9, a first resistor R1, and a second resistor R2. The drain of the fifth N-type transistor NM5 is electrically connected to the drain of the fifth P-type transistor PM5, the gate of the fifth N-type transistor NM5, the drain of the sixth N-type transistor NM6 and the drain of the ninth P-type transistor PM9 are electrically connected to the drain of the seventh P-type transistor PM7, the source of the fifth N-type transistor NM5 and the gate of the sixth N-type transistor NM6 are both grounded through the first resistor R1, the gate of the ninth P-type transistor PM9 is grounded through the second resistor R2, the source of the ninth P-type transistor PM9 is electrically connected to the power supply voltage terminal V DD, and the source of the sixth N-type transistor NM6 is grounded.
In actual operation, the current mirror module formed by the fifth P-type transistor PM5, the sixth P-type transistor PM6, the seventh P-type transistor PM7 and the eighth P-type transistor PM8 mirrors the generated fixed bias current I 1 to the target bias current I 2. The fifth N-type transistor NM5, the sixth N-type transistor NM6, and the ninth P-type transistor PM9 generate a fixed target bias voltage V 2. It is understood that when the source of the NMOS transistor is grounded, its gate-source voltage V GS is equal to its threshold voltage V TH, for example V GS=VTH =0.7v. In the case where both the source of the sixth transistor NM6 and the source of the fifth transistor NM5 are grounded, the bias voltage V 2 is equal to the sum of the gate-source voltages of the sixth transistor NM6 and the fifth transistor NM5, that is, V 2＝V1+VGS,NM5=VGS,NM5+VGS,NM6, and the gate-source voltages V GS of the sixth transistor NM6 and the fifth transistor NM5 are approximately equal to the threshold voltage V TH ≡0.7V, that is, V 2=VTH,NM5+VTH,NM6 ≡1.4V, when the circuit is operating normally.
In practical application, I 1= V1/R1, where I 1 is a current passing through the first resistor R1, and V 1 is a gate voltage of the sixth N-type transistor NM6, which can also be regarded as a voltage across the first resistor R1. It will be appreciated that the current value of I 1 is only on the order of nA when the resistance value of R1 reaches the order of MΩ. The current mirror formed by the fifth P-type transistor PM5, the sixth P-type transistor PM6, the seventh P-type transistor PM7, and the eighth P-type transistor PM8 mirrors I 1 to the target bias current I 2 in a proportion. When the current value of I 1 is only in the nA order, I 2 is also in the nA order, thereby realizing low power consumption of the schmitt trigger.
As shown in fig. 3, the driving circuit 2 includes a first driving module 21 and a second driving module 22 electrically connected. The control end of the first driving module 21 is electrically connected to the output circuit 4, the first end of the first driving module 21 is electrically connected to the power supply voltage end through the bias circuit 1, the second end of the first driving module 21 is electrically connected to the first end of the second driving module 22 and the control end of the first level shaping module 31, and the first driving module 21 is configured to drive the first level shaping module 31 to shape the waveform of the input signal V IN when the logic level voltage of the input signal V IN is a low level voltage, and output a shaped signal to the output circuit 4. The control end of the second driving module 22 is electrically connected to the voltage output end of the bias circuit 1, the second end of the second driving module 22 is configured to receive the input signal V IN, and the second driving module 22 is configured to drive the second level shaping module 32 to shape the waveform of the input signal V IN when the logic level of the input signal V IN is greater than or equal to the preset threshold voltage and less than the supply voltage, and output the shaped signal to the output circuit 4.
In the above embodiment, the first driving module 21 includes the tenth P-type transistor PM10, and the second driving module 22 includes the seventh N-type transistor NM7.
Based on this, the above-mentioned preset threshold voltage should be satisfied that the first N-type transistor NM1 and the second N-type transistor NM2 can be turned on and the seventh N-type transistor NM7 can be turned off, i.e., the preset threshold voltage should be greater than or equal to the threshold voltage V TH,NM1 Σ0.7V of the first N-type transistor NM1 and the threshold voltage V TH,NM2 Σ0.7V of the second N-type transistor NM2, while the difference between the target bias voltage V 2 and the preset threshold voltage should be at least smaller than the threshold voltage V TH,NM7 Σ0.7V of the seventh N-type transistor NM7, and therefore, the preset threshold voltage should be greater than 0.7V. In practical application, considering factors such as process variation, in order to enable the seventh N-type transistor NM7 to be turned off thoroughly, a margin may be reserved for one time so that the preset threshold voltage is greater than or equal to 1.4V. In this case, the circuit still has a wide application scenario, and in some applications, the supply voltage V DD is usually 3.3V or 5V, and when the logic high level V INH of the input signal V IN is equal to 1.4V, the conventional schmitt trigger cannot correctly transmit the input signal V IN, but the schmitt trigger provided by the embodiment of the present invention can still correctly transmit the input signal V IN.
The shaping process of the input signal V IN by the schmitt trigger according to the embodiment of the present invention will be described in detail with reference to fig. 3 and 4.
When the input signal V IN is at the logic low level V IN =0, the first N-type transistor NM1 and the second N-type transistor NM2 are turned off, the voltage difference between the target bias voltage V 2 and the input signal V IN is approximately equal to 1.4V greater than the threshold voltage V TH,NM7 of the seventh N-type transistor NM7, the seventh N-type transistor NM7 is turned on, the drain voltage of the tenth P-type transistor PM10 and the drain voltage V 3 of the seventh N-type transistor NM7 are pulled down to 0, the first P-type transistor PM1 and the second P-type transistor PM2 are turned on, the drain voltage V 4 of the second P-type transistor PM2 is pulled up to V DD, and the output target shaping signal V OUT =0 is further passed through the subsequent inverter, thereby completing the correct transmission when the input signal V IN is at the low level.
When the logic high level V INH of the input signal V IN satisfies 1.4 v+.v INH≤VDD, the first N-type transistor NM1 and the second N-type transistor NM2 are turned on, the voltage difference between the target bias voltage V 2 and the input signal V IN is approximately equal to 0V and less than the threshold voltage V TH,NM7 of the seventh N-type transistor NM7, the seventh N-type transistor NM7 is turned off, the drain voltage of the tenth P-type transistor PM10 and the drain voltage V 3 of the seventh N-type transistor NM7 are pulled up to V DD, the first P-type transistor PM1 and the second P-type transistor PM2 are turned off, the drain voltage V 4 of the second P-type transistor PM2 is pulled down to 0, and the output target shaping signal V OUT=VDD is passed through the subsequent inverter, thereby completing the shift conversion of the logic high level V INH of the input signal V IN to V DD when the input signal V IN is greater than or equal to the preset threshold voltage and less than the supply voltage V DD.
Therefore, the schmitt trigger provided by the embodiment of the invention can realize the function of voltage conversion, and can realize normal transmission of the input signal V IN without the need that the logic high level V INH of the input signal V IN is equal to the power supply voltage V DD when the logic high level V INH of the input signal V IN is in the interval of 1.4V less than or equal to V INH≤VDD on the basis of keeping the original function of the schmitt trigger at the cost of extremely low additional power consumption, thereby greatly widening the voltage range of the input signal V IN acceptable by the schmitt trigger.
Although the invention is described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
Although the invention has been described in connection with specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made without departing from the spirit and scope of the invention. Accordingly, the specification and drawings are merely exemplary illustrations of the present invention as defined in the appended claims and are considered to cover any and all modifications, variations, combinations, or equivalents that fall within the scope of the invention. It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (4)
1. The Schmitt trigger is characterized by comprising a biasing circuit, a driving circuit, a shaping circuit and an output circuit which are electrically connected in sequence, wherein:
The bias circuit is used for providing a target bias current and a target bias voltage for the drive circuit;
The driving circuit is used for driving the shaping circuit to be conducted under the action of the target bias current and the target bias voltage when the logic level voltage of the input signal is larger than or equal to a preset threshold voltage and smaller than the power supply voltage;
the shaping circuit is used for outputting a shaping signal after shaping the waveform of the input signal;
the output circuit is used for outputting a target shaping signal after carrying out reverse phase processing on the shaping signal;
the bias circuit comprises a bias current generation module and a bias voltage generation module which are electrically connected, wherein:
The output end of the bias current generation module is electrically connected with the first end of the driving circuit and is used for providing the target bias current for the driving circuit;
the output end of the bias voltage generation module is electrically connected with the first control end of the driving circuit and is used for providing the target bias voltage for the driving circuit so as to control the driving circuit to be turned off under the action of the second control end under the condition that the logic level voltage of the input signal is larger than or equal to the preset threshold voltage and smaller than the power supply voltage;
the bias current generation module includes: a fifth P-type transistor, a sixth P-type transistor, a seventh P-type transistor, and an eighth P-type transistor, wherein:
the source electrode of the fifth P-type transistor, the source electrode of the sixth P-type transistor, the source electrode of the seventh P-type transistor and the source electrode of the eighth P-type transistor are all electrically connected with a power supply voltage end, the grid electrode of the fifth P-type transistor, the grid electrode of the sixth P-type transistor, the grid electrode of the seventh P-type transistor and the grid electrode of the eighth P-type transistor are all electrically connected with the bias voltage generation module, and the drain electrode of the fifth P-type transistor, the drain electrode of the sixth P-type transistor and the grid electrode of the ninth P-type transistor are electrically connected; the drain electrode of the seventh P-type transistor is electrically connected with the fifth N-type transistor, and the drain electrode of the eighth P-type transistor is electrically connected with the source electrode of the tenth P-type transistor of the driving circuit;
the bias voltage generation module includes: a fifth N-type transistor, a sixth N-type transistor, a ninth P-type transistor, a first resistor, and a second resistor, wherein:
The drain electrode of the fifth N-type transistor is electrically connected with the drain electrode of the fifth P-type transistor, the grid electrode of the fifth N-type transistor, the drain electrode of the sixth N-type transistor and the drain electrode of the ninth P-type transistor are electrically connected with the grid electrode of the seventh N-type transistor of the driving circuit, the source electrode of the fifth N-type transistor and the grid electrode of the sixth N-type transistor are grounded through the first resistor, the grid electrode of the ninth P-type transistor is grounded through the second resistor, the source electrode of the ninth P-type transistor is electrically connected with the power voltage end, and the source electrode of the sixth N-type transistor is grounded;
the shaping circuit comprises a first level shaping module and a second level shaping module which are electrically connected, wherein:
the control end of the first level shaping module is electrically connected with the control end of the second level shaping module through the driving circuit, and the control end of the second level shaping module is used for receiving the input signal;
The first level shaping module is used for shaping the waveform of the input signal under the action of the driving circuit when the logic level voltage of the input signal is low level voltage, and outputting the shaped signal to the output circuit;
The second level shaping module is configured to, when the logic level of the input signal is greater than or equal to the preset threshold voltage and less than the supply voltage, perform shaping processing on the waveform of the input signal under the action of the driving circuit, and output the shaped signal to the output circuit;
the first level shaping module includes: the first P-type transistor, the second P-type transistor and the third P-type transistor, wherein:
The grid electrode of the first P-type transistor and the grid electrode of the second P-type transistor are electrically connected with the driving circuit, the source electrode of the first P-type transistor is electrically connected with a power supply voltage end, the drain electrode of the first P-type transistor and the source electrode of the second P-type transistor are electrically connected with the source electrode of the third P-type transistor, the drain electrode of the third P-type transistor is grounded, and the grid electrode of the third P-type transistor and the drain electrode of the second P-type transistor are electrically connected with the second level shaping module;
The second level shaping module includes: a first N-type transistor, a second N-type transistor, a third N-type transistor, a fourth N-type transistor, and a fourth P-type transistor, wherein:
the grid electrode of the first N-type transistor and the grid electrode of the second N-type transistor are used for receiving the input signal, the drain electrode of the first N-type transistor and the grid electrode of the third N-type transistor are electrically connected with the first level shaping module, the source electrode of the first N-type transistor and the drain electrode of the second N-type transistor are electrically connected with the source electrode of the third N-type transistor, and the source electrode of the second N-type transistor is grounded;
The drain electrode of the third N-type transistor is electrically connected with the source electrode of the fourth N-type transistor, the drain electrode of the fourth N-type transistor is electrically connected with the drain electrode of the fourth P-type transistor, the source electrode of the fourth P-type transistor is electrically connected with a power supply voltage end, the grid electrode of the fourth N-type transistor is electrically connected with the voltage output end of the bias circuit, and the grid electrode of the fourth P-type transistor is grounded.
2. The schmitt trigger of claim 1, wherein the drive circuit comprises a first drive module and a second drive module electrically connected, wherein:
the control end of the first driving module is electrically connected with the output circuit, the first end of the first driving module is electrically connected with the power supply voltage end through the bias circuit, the second end of the first driving module is respectively electrically connected with the first end of the second driving module and the control end of the first level shaping module, and the first driving module is used for driving the first level shaping module to shape the waveform of the input signal when the logic level voltage of the input signal is low level voltage and outputting the shaped signal to the output circuit;
The control end of the second driving module is electrically connected with the voltage output end of the bias circuit, the second end of the second driving module is used for receiving the input signal, and the second driving module is used for driving the second level shaping module to shape the waveform of the input signal when the logic level of the input signal is greater than or equal to the preset threshold voltage and smaller than the power supply voltage, and outputting the shaped signal to the output circuit.
3. The schmitt trigger of claim 2, wherein the first driving module comprises a tenth P-type transistor and the second driving module comprises a seventh N-type transistor.
4. The schmitt trigger according to claim 1, wherein the output circuit comprises an inverter, an input of the inverter being electrically connected to an output of the shaping circuit, the output of the inverter being for outputting the target shaping signal.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202410258311.1A CN117856767B (en) | 2024-03-07 | 2024-03-07 | Schmitt trigger |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108667440A (en) * | 2017-03-28 | 2018-10-16 | 峰岹科技（深圳）有限公司 | A kind of Schmitt trigger circuit |
| CN111711172A (en) * | 2020-06-22 | 2020-09-25 | 电子科技大学 | Undervoltage protection circuit with ultralow power consumption |
| CN113131905A (en) * | 2019-12-30 | 2021-07-16 | 圣邦微电子（北京）股份有限公司 | Schmitt trigger circuit |
| CN115173692A (en) * | 2022-07-26 | 2022-10-11 | 西安水木芯邦半导体设计有限公司 | Bypass circuit capable of expanding low-voltage input range |
| CN115664384A (en) * | 2022-09-19 | 2023-01-31 | 中国科学院自动化研究所 | Schmitt trigger, chip and electronic equipment |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8203370B2 (en) * | 2009-06-30 | 2012-06-19 | Silicon Laboratories Inc. | Schmitt trigger with gated transition level control |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108667440A (en) * | 2017-03-28 | 2018-10-16 | 峰岹科技（深圳）有限公司 | A kind of Schmitt trigger circuit |
| CN113131905A (en) * | 2019-12-30 | 2021-07-16 | 圣邦微电子（北京）股份有限公司 | Schmitt trigger circuit |
| CN111711172A (en) * | 2020-06-22 | 2020-09-25 | 电子科技大学 | Undervoltage protection circuit with ultralow power consumption |
| CN115173692A (en) * | 2022-07-26 | 2022-10-11 | 西安水木芯邦半导体设计有限公司 | Bypass circuit capable of expanding low-voltage input range |
| CN115664384A (en) * | 2022-09-19 | 2023-01-31 | 中国科学院自动化研究所 | Schmitt trigger, chip and electronic equipment |
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