CN117855223A - Array substrate, manufacturing method thereof, display panel and display device - Google Patents

Abstract

The present disclosure provides an array substrate, a method of manufacturing the same, a display panel, and a display device, wherein the array substrate includes a substrate; the transistor is arranged on the substrate and comprises an active layer, a gate dielectric layer and a grid electrode, wherein the active layer, the gate dielectric layer and the grid electrode are arranged in a stacked mode, the gate dielectric layer is arranged between the grid electrode and the active layer, and the active layer comprises a channel region, and a source electrode region and a drain electrode region which are arranged on two sides of the channel region; and the pixel electrode layer is connected with the drain region through the metal conductive layer. The array substrate can reduce contact resistance between the pixel electrode and the thin film transistor active layer.

Description

Array substrate, manufacturing method thereof, display panel and display device

Technical Field

The disclosure relates to the technical field of display, in particular to an array substrate, a manufacturing method thereof, a display panel and a display device.

Background

Thin film transistors (Thin Film Transistor, TFT) are core devices in flat panel display technology as switching control elements or integrated elements of peripheral drive circuits. However, according to the current array substrate manufacturing process, there is a problem that the on-state current of the thin film transistor is low, which cannot meet the increasing high quality display requirement.

Disclosure of Invention

In view of the above, the present disclosure provides an array substrate, a method of manufacturing the same, a display panel, and a display device capable of reducing contact resistance between a pixel electrode and an active layer of a thin film transistor, thereby improving on-state current of the thin film transistor.

In a first aspect, the present disclosure provides, by way of an embodiment, the following technical solutions:

an array substrate, comprising:

a substrate base;

the transistor is arranged on the substrate and comprises an active layer, a gate dielectric layer and a gate electrode, wherein the active layer, the gate dielectric layer and the gate electrode are arranged in a stacked mode, the gate dielectric layer is arranged between the gate electrode and the active layer, and the active layer comprises a channel region, and a source region and a drain region which are arranged on two sides of the channel region;

and the pixel electrode layer is connected with the drain region through the metal conductive layer.

In some embodiments, the array substrate further includes a first passivation layer, a planarization layer, a common electrode layer, and a second passivation layer sequentially stacked on the transistor; the first passivation layer at least covers the gate arrangement;

the first passivation layer, the flat layer and the second passivation layer are provided with pixel electrode openings, the pixel electrode openings are used for exposing the opening areas of the metal conductive layers, and the pixel electrode layers at least cover the side walls of the pixel electrode openings and the opening areas.

In some embodiments, at the pixel electrode opening, an orthographic projection of the active layer on the substrate covers an orthographic projection of the metal conductive layer on the substrate.

In some embodiments, an orthographic projection of the metal conductive layer on the substrate at the pixel electrode opening covers an orthographic projection of the openings of the first passivation layer and the second passivation layer on the substrate.

In some embodiments, the metal conductive layer and the gate are the same layer of metal.

In some embodiments, the array substrate further comprises a source-drain metal layer disposed on the substrate and a buffer layer disposed to cover the source-drain metal layer; the active layer is stacked on the buffer layer;

the source-drain metal layer comprises a shading layer and a data line; the orthographic projection of the shading layer on the substrate base plate at least covers the orthographic projection of the grid electrode on the substrate base plate.

In some embodiments, the array substrate further includes a metal connection layer for connecting the data line and the source region.

In a second aspect, based on the same inventive concept, the present disclosure provides, through an embodiment, the following technical solutions:

a method of manufacturing an array substrate, comprising:

providing a substrate;

forming an active layer, a gate dielectric layer, a gate electrode and a metal conducting layer which are stacked on the substrate; the gate dielectric layer is positioned between the gate and the active layer, the active layer comprises a channel region, a source region and a drain region, the source region and the drain region are positioned at two sides of the channel region, and the metal conducting layer is laminated on the drain region;

and forming a pixel electrode layer on the metal conductive layer.

In some embodiments, the forming the active layer, the gate dielectric layer, the gate electrode and the metal conductive layer on the substrate includes:

depositing a semiconductor material on the substrate and patterning to form the active layer;

depositing an insulating material on the active layer to form the gate dielectric layer, and forming an opening at the position of the pixel electrode layer to expose the active layer;

depositing a gate metal material on the gate dielectric layer and at the opening and patterning the gate metal material to form the gate and the metal conductive layer; the grid electrode is laminated on the grid dielectric layer, and the metal conducting layer is laminated on the active layer in the opening;

and conducting treatment on the active layer to enable the active layer to form a channel region and source electrode regions and drain electrode regions which are positioned on two sides of the channel region.

In a third aspect, based on the same inventive concept, the present disclosure provides, by an embodiment, the following technical solutions:

a display panel includes an array substrate provided in an embodiment of a first aspect.

According to a fourth aspect, based on the same inventive concept, the present disclosure provides, through an embodiment, the following technical solutions:

a display device comprising a display panel provided by an embodiment of the third aspect.

Through one or more technical schemes of the present disclosure, the present disclosure has the following beneficial effects or advantages:

the present disclosure provides an array substrate, wherein a metal conductive layer is added between a drain region of a thin film transistor and a connection position of a pixel electrode; the metal conducting layer can be used for blocking damage to the active layer in the dry etching process of the insulating layer of the array substrate, and can be used as a good conductor to reduce contact resistance between the pixel electrode layer and the drain electrode region, so that on-state current of the thin film transistor is improved, and display quality of display products is improved.

The foregoing description is merely an overview of the technical solutions of the present disclosure, and may be implemented according to the content of the specification in order to make the technical means of the present disclosure more clearly understood, and in order to make the above and other objects, features and advantages of the present disclosure more clearly understood, the following specific embodiments of the present disclosure are specifically described.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the disclosure. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:

FIG. 1 illustrates a cross-sectional view of an array substrate according to an embodiment of the present disclosure;

FIG. 2 shows a flow diagram of a method of manufacturing an array substrate according to an embodiment of the disclosure;

fig. 3A illustrates a cross-sectional view of forming a source drain metal layer on a substrate base plate according to an embodiment of the present disclosure;

fig. 3B illustrates a top view of forming a source drain metal layer on a substrate base plate according to an embodiment of the present disclosure;

fig. 4 illustrates a cross-sectional view of forming a buffer layer on a source drain metal layer according to an embodiment of the present disclosure;

fig. 5A illustrates a cross-sectional view of depositing semiconductor material to form an active layer in accordance with an embodiment of the present disclosure;

fig. 5B illustrates a top view of depositing semiconductor material to form an active layer in accordance with an embodiment of the present disclosure;

fig. 6A illustrates a cross-sectional view of depositing an insulating material to form a gate dielectric layer in accordance with an embodiment of the present disclosure;

fig. 6B illustrates a top view of depositing an insulating material to form a gate dielectric layer in accordance with an embodiment of the present disclosure;

fig. 7A illustrates a cross-sectional view of depositing a gate metal material to form a gate and a metal conductive layer in accordance with an embodiment of the present disclosure;

fig. 7B illustrates a top view of depositing gate metal material to form a gate and a metal conductive layer in accordance with an embodiment of the present disclosure;

fig. 8 illustrates a cross-sectional view of conducting an active layer in accordance with an embodiment of the present disclosure;

fig. 9 illustrates a cross-sectional view of forming a first passivation layer according to an embodiment of the present disclosure;

fig. 10 illustrates a cross-sectional view of forming a planarization layer on a first passivation layer in accordance with an embodiment of the present disclosure;

fig. 11 illustrates a cross-sectional view of forming a common electrode layer on a planar layer according to an embodiment of the present disclosure;

fig. 12 illustrates a cross-sectional view of forming a second passivation layer on the common electrode layer according to an embodiment of the present disclosure;

fig. 13A shows an ID-VG characteristic curve of a thin film transistor of an array substrate provided according to an embodiment of the present disclosure;

fig. 13B shows an ID-VG characteristic curve of a thin film transistor of a conventional array substrate;

FIG. 14 shows a schematic diagram of a display device according to an embodiment of the disclosure;

reference numerals illustrate:

sub, substrate base plate; BUF, buffer layer; m1, a shading layer; SD, data line; a TFT, a thin film transistor; ACT, active layer; CL, channel region; DA. A drain region; SA, source region; GI. A gate dielectric layer; m2, grid electrode; m3, a metal conducting layer; m4, a metal connecting layer; PVX1, a first passivation layer; PVX2, a second passivation layer; com, common electrode layer; PLN, planar layer; PIX, pixel electrode layer; PH, pixel electrode opening.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned.

The term "film" as used in this disclosure refers to a thin film formed by depositing, coating or other processes on a substrate of a material. The phrase "a and B co-layer arrangement" in this disclosure means that a and B are formed simultaneously by the same patterning process. The term "the front projection of B is within the range of the front projection of a" in this disclosure means that the boundary of the front projection of B falls within the boundary of the front projection of a, or that the boundary of the front projection of a overlaps with the boundary of the front projection of B. In the case where the source and drain of the transistor are symmetrical, the source and drain may be interchanged.

In the context of the present disclosure, the light-emitting side of the display panel is referred to as "top side" or "upper side", and the opposite side is referred to as "bottom side" or "lower side", unless otherwise specified, in order to describe the relative direction. Accordingly, the direction from the bottom side to the top side is the thickness direction of the display panel, and the direction perpendicular to the thickness direction is the "plane direction" or the "extending direction" of the display panel. It should be understood that these directions are relative directions rather than absolute directions.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the terms "a," "an," or "the" and similar terms do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.

The thin film transistors widely used at present mainly include amorphous silicon thin film transistors and polysilicon thin film transistors. Amorphous silicon (a-Si) thin film transistors are widely used in driving circuits in flat panel displays or as switching control devices. But amorphous silicon has low mobility, typically less than 1cm ² And the polysilicon has poor uniformity, complex process and high cost, is sensitive to visible light, can not work under the irradiation of visible light, and is difficult to be used for large-size and high-resolution flat panel display. In recent years, attention has been paid to oxide semiconductor thin film transistors, amorphous Oxide Semiconductors (AOS) such as Indium Tin Oxide (ITO), aluminum zinc oxide (Aluminum zinc oxide, AZO), indium zinc oxide (Indium Zinc Oxide, IZO), indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO), and the like, and many of which are being studied are also relatively potential, have a relatively large mobility, good uniformity, a low process temperature, a high transmittance in the visible light region, and are suitable for flexible display.

Research shows that an important reason for the problem of low on-state current of the thin film transistor is that a high contact resistance exists at the connection part of the pixel electrode and the active layer of the thin film transistor, and the reason for the high contact resistance is that in the process of manufacturing the array substrate, in the dry etching process of an insulating film layer (such as a passivation layer) in the array substrate, the active layer is damaged by over etching time, namely the residual film thickness of the active layer is reduced, so that the impedance of the active layer is increased, the contact resistance between the active layer and the pixel electrode is increased, the on-state current of the thin film transistor is reduced, and meanwhile, the stability is reduced.

In order to solve the above problem, in a first aspect, referring to fig. 1, in an alternative embodiment, an array substrate is provided, including:

a substrate Sub;

a transistor TFT disposed on the substrate Sub, the transistor TFT including an active layer ACT, a gate dielectric layer GI and a gate electrode M2, the gate dielectric layer GI being disposed between the gate electrode M2 and the active layer ACT, the active layer ACT including a channel region CL and source and drain regions SA and DA disposed on both sides of the channel region CL;

the metal conductive layer M3 and the pixel electrode layer PIX are sequentially stacked on the side of the drain region DA away from the substrate Sub, and the pixel electrode layer PIX is connected to the drain region DA through the metal conductive layer M3.

In some embodiments, the substrate base Sub may be a rigid substrate. The rigid substrate may include, for example, a glass substrate, a PMMA (Polymethyl methacrylate ) substrate, a silicon substrate, or the like. In this case, the array substrate may be a rigid array substrate. In other embodiments, the substrate Sub may be a flexible substrate. The flexible substrate may include, for example, a PET (Polyethylene terephthalate ) substrate, a PEN (Polyethylene naphthalate two formic acid glycol ester, polyethylene naphthalate) substrate, a PI (Polyimide) substrate, or the like. The array substrate may be a flexible array substrate.

A plurality of transistor TFTs may be provided on the substrate Sub. In some embodiments, the transistor TFT may be a thin film transistor or other switching devices with the same characteristics, and the thin film transistor will be described below as an example, but not by way of limitation.

The active layer ACT of the transistor TFT in the present disclosure includes a channel region CL and a source region SA at one side of the channel region CL and a drain region DA at the other side. The channel region CL is a semiconductor region of the active layer ACT, and the Source region SA and the Drain region DA are conductor regions formed by conducting the active layer ACT other than the channel region CL, and correspond to a Source (Source) and a Drain (Drain) of the transistor TFT, respectively. The orthographic projections of the channel region CL, the gate dielectric layer GI and the gate electrode M2 on the substrate Sub are at least partially overlapped, so that the channel region CL can be conducted with source and drain regions positioned on two sides of the channel region CL under the action of gate starting voltage to realize the starting of the transistor TFT, or the transistor TFT is turned off after the gate starting voltage is removed. For a transistor TFT, the source and drain thereof may be symmetrical in structure, so the source and drain thereof may be indistinguishable in structure, and thus the positions of the source region SA and the drain region DA on both sides of the channel region CL may be interchanged. In the current TFT display technology, the source, gate and drain of the thin film transistor are connected to the data signal line, the scan line and the pixel electrode, respectively, so that the conductive active layer on one side of the channel region CL near the pixel electrode layer PIX is the drain region DA, and the conductive active layer on the other side of the channel region CL is used as the source region SA to connect to the data signal line.

The drain electrode of the thin film transistor is directly connected to the pixel electrode. In the array substrate provided by the disclosure, a metal conductive layer M3 is added between the connection position of the drain electrode region DA of the thin film transistor and the pixel electrode; the metal conductive layer M3 can prevent the damage to the active layer ACT in the dry etching process of the insulating layer of the array substrate, improves the residual film thickness of the active layer ACT, and can reduce the contact impedance between the pixel electrode layer PIX and the drain electrode region DA as a good conductor, so that the on-state current of the thin film transistor is improved, and the display quality of a display product is improved.

In some embodiments, the metal conductive layer M3 may be formed by separately depositing a layer of good conductor metal material on the active layer ACT, but this requires adding a Mask process, resulting in increased process cost. In order to save cost, in other embodiments, the metal conductive layer M3 and the gate M2 metal of the transistor TFT may be formed in the same Mask process, or may be formed in the same Mask process as the data line SD metal of the array substrate. Next, the metal conductive layer M3 and the gate electrode M2 are further described by using the same mask process, that is, the metal conductive layer M3 and the gate electrode M2 are disposed on the same layer or are made of the same metal.

According to the positional relationship of the gate electrode M2, the gate dielectric layer GI and the active layer ACT in the thickness direction of the array substrate, the thin film transistor in the array substrate may be a bottom gate structure or a top gate structure, wherein the bottom gate is that the gate electrode M2 is deposited below the gate dielectric layer GI and the active layer ACT, and the top gate is that the gate electrode M2 is deposited above the active layer ACT and the gate dielectric layer GI. However, the thin film transistor of the bottom gate structure mainly has two problems: one is control of Back Channel Etching (BCE), which is easy to affect the channel device due to over-etching, and adversely affects the performance of the thin film transistor, and although the problem can be solved by using an etching protection layer (ES), the complexity of the process is increased by using the etching protection layer. Secondly, the bottom gate thin film transistor is not easy to realize self alignment, the back exposure technology has compatibility problem with the existing technology, and the traditional manufacturing method can lead to a larger overlapping area in the bottom gate thin film transistor, generate larger overlapping capacitance, be unfavorable for reducing the channel size, reduce the working speed of a driving circuit and be difficult to be used for driving the Active Matrix Organic Light Emitting Diode (AMOLED) display with high resolution.

The top gate thin film transistor can solve the above-mentioned problems and disadvantages of the bottom gate thin film transistor. First, the top gate thin film transistor has no over-etching damage problem, and the gate dielectric layer GI in the top gate thin film transistor is arranged above the active layer ACT, so that the active layer ACT can be protected. Secondly, the top gate structure has the advantage of realizing self-alignment, the process is relatively simple, the source electrode area SA and the drain electrode area DA are subjected to plasma treatment, hydrogen is doped into the source electrode area SA and the drain electrode area DA to increase the conductivity of the source electrode area SA and the drain electrode area DA, an overlapping area can be avoided by adopting the self-alignment structure, an overlapping capacitor does not exist, the channel size of the thin film transistor can be controlled more accurately, and a shorter channel can be realized.

Thanks to the above advantages of the top gate thin film transistor, the disclosed embodiments employ a transistor TFT structure design of the top gate structure. In some embodiments, referring to fig. 1, the array substrate further includes a first passivation layer PVX1, a planarization layer PLN, a common electrode layer Com, and a second passivation layer PVX2 sequentially stacked on the transistor TFT; the first passivation layer PVX1 is disposed to cover at least the gate electrode M2; therefore, in the thickness direction of the vertical substrate Sub, the active layer ACT, the gate dielectric layer GI, and the gate M2 in the transistor TFT are sequentially stacked from bottom to top to form a top gate structure. Compared with a transistor TFT with a bottom gate structure, the interlayer dielectric layer ILD between the gate electrode M2 and the first passivation layer PVX1 can be omitted, so that a Mask process is reduced, and the manufacturing cost of the array substrate is reduced. This is because in the mass production line, the exposure (Photo) equipment is the most core and expensive equipment, so the production capacity of the mass production line is determined by the exposure equipment, and too many masks or reticles (masks) are used for exposure, which increases the process cost and also increases the production time, so that the production efficiency is significantly reduced. Therefore, in the production process, the exposure times using the photomask are saved, the productivity is improved, and the cost is reduced, which is a requirement for the development of the main advancing technology.

On the other hand, referring to fig. 1, at the drain region DA of the transistor TFT, the first passivation layer PVX1, the planar layer PLN and the second passivation layer PVX2 are provided with a pixel electrode opening PH, where the pixel electrode opening PH is used for exposing an opening region of the metal conductive layer M3, and the pixel electrode layer PIX covers at least a sidewall and the opening region of the pixel electrode opening PH, so that connection between the pixel electrode layer PIX and the drain region DA through the metal conductive layer M3 is achieved, and contact resistance between the pixel electrode layer PIX and the drain region DA is reduced.

In some embodiments, at the pixel electrode opening PH, the orthographic projection of the active layer ACT on the substrate Sub covers the orthographic projection of the metal conductive layer M3 on the substrate Sub. That is, the area of the metal conductive layer M3 is smaller than that of the active layer ACT, and the edge of the metal conductive layer M3 does not exceed the edge of the active layer ACT, so as to avoid that the metal conductive layer M3 affects the conductive treatment of the active layer ACT in the drain region DA.

In some embodiments, at the pixel electrode opening PH, the orthographic projection of the metal conductive layer M3 on the substrate Sub covers the orthographic projection of the openings of the first passivation layer PVX1 and the second passivation layer PVX2 on the substrate Sub. That is, the opening sizes of the first passivation layer PVX1 and the second passivation layer PVX2 in the thickness direction perpendicular to the substrate Sub cannot exceed the area of the metal conductive layer M3, so that when the dry etching of the first passivation layer PVX1 and the second passivation layer PVX2 is performed to expose the metal conductive layer M3, the metal conductive layer M3 can serve as a barrier layer of the drain region DA at the pixel electrode opening PH, and the film damage to the drain region DA active layer that may be caused by the dry etching process is reduced.

In some embodiments, referring to fig. 1, the array substrate further includes a source drain metal layer disposed on the substrate Sub and a buffer layer BUF disposed to cover the source drain metal layer; the active layer ACT is laminated on the buffer layer BUF; the source drain metal layer comprises a shading layer M1 and a data line SD; the orthographic projection of the light shielding layer M1 on the substrate Sub covers at least the orthographic projection of the gate electrode M2 on the substrate Sub. The source-drain metal layer is not used as a source-drain electrode of the transistor TFT but is used to form the data line SD on the array substrate. The buffer layer BUF is used for insulating the source/drain metal layer. Since the transistor TFT has a top gate structure, the light shielding layer M1 provided on the substrate Sub may protect the channel region CL in the active layer ACT.

In some embodiments, referring to fig. 1, the array substrate may further include a metal connection layer M4 for connecting the data line SD and the source region SA. The first passivation layer PVX1 is disposed to cover the metal connection layer M4, i.e., the first passivation layer PVX1 is disposed between the metal connection layer M4 and the planarization layer PLN at the data line SD. The metal connection layer M4, the gate electrode M2 and the metal conductive layer M3 may be the same metal layer, i.e. deposited by the same Mask process.

In a second aspect, referring to fig. 2, in another alternative embodiment, a method for manufacturing an array substrate is provided, which includes steps S21 to S23, and specifically includes:

s21: providing a substrate Sub;

s22: forming an active layer ACT, a gate dielectric layer GI, a gate electrode M2 and a metal conductive layer M3 which are stacked on a substrate Sub; the active layer ACT comprises a channel region CL, a source region SA and a drain region DA which are positioned at two sides of the channel region CL, and a metal conductive layer M3 is laminated in the drain region DA;

s23: a pixel electrode layer PIX is formed on the metal conductive layer M3.

In some embodiments, step S22 specifically includes:

depositing and patterning a semiconductor material on the substrate Sub to form an active layer ACT; depositing an insulating material on the active layer ACT to form a gate dielectric layer GI, and forming an opening at the position of the pixel electrode layer PIX to expose the active layer ACT; depositing a gate metal material on the gate dielectric layer GI and at the opening and patterning to form a gate electrode M2 and a metal conducting layer M3; the grid electrode M2 is laminated on the grid dielectric layer GI, and the metal conductive layer M3 is laminated on the active layer ACT in the opening; the active layer ACT is subjected to a conductive process so that the active layer ACT forms a channel region CL and source and drain regions SA and DA located on both sides of the channel region CL.

In order to more intuitively illustrate the above manufacturing method, further description is made in the following embodiments in conjunction with the manufacturing flow chart and the manufacturing steps:

step 1): a substrate Sub is provided, and a metal material is deposited on the substrate Sub to form a source-drain metal layer, and the source-drain metal layer includes a light shielding layer M1 and a data line SD, as shown in fig. 3A and 3B. The deposited metallic material may be a combination of one or more materials such as titanium (Ti), copper (Cu), molybdenum niobium (MoNb), and a metal mixed Material (MTD) including molybdenum.

Step 2): depositing an insulating material on the source drain metal layer to form a buffer layer BUF, as shown in FIG. 4; the insulating material may be one or more combinations of silicon oxide or silicon nitride.

Step 3): depositing and patterning a layer of semiconductor material to form an active layer ACT, as shown in fig. 5A and 5B; the semiconductor material forming the active layer ACT may be amorphous indium gallium zinc oxide a-IGZO, indium gallium zinc tin oxide IGZTO, or the like.

Step 4): depositing an insulating material to form a gate dielectric layer GI, as shown in FIG. 6A and FIG. 6B; the material of the gate dielectric layer GI may be one or more combinations of silicon oxide or silicon nitride; forming a data opening SDH on the gate dielectric layer GI at a position close to the data line SD to expose the data line SD; openings are formed at the pixel electrodes to prepare for the next step of forming the metal conductive layer M3, and the opening shape of the corresponding metal conductive layer M3 may be square, and the size may be 4 μm×6 μm.

Step 5): continuing to deposit gate metal material and forming a gate electrode M2 and a metal conductive layer M3 by patterning, as shown in fig. 7A and 7B; the gate metal material may be one or more combinations of Ti, cu, moNb, MTD and the like; the size of the metal conductive layer M3 may be 4 μm×4 μm to 6 μm×6 μm corresponding to the opening shape and size of the gate dielectric layer GI, and may not exceed the edge of the active layer ACT, so as to avoid affecting the subsequent conductive treatment of the active layer ACT; then, the gate dielectric layer GI is etched over the entire surface by using the gate electrode M2 as a mask, and the gate dielectric layer GI located between the gate electrode M2 and the active layer ACT is retained.

Step 6): conducting a partial region of the active layer ACT, wherein the process gas may be helium (He) or a mixed gas of helium and argon (he+ar); the conductive active layer ACT is converted into a source region SA or a drain region DA, and the active layer ACT under the gate electrode M2 is maintained in a semiconductor state, forming a channel region CL as shown in fig. 8.

Step 7): the deposition of the insulating material, which may be one or more combinations of silicon oxide or silicon nitride, continues to form a first passivation layer PVX1 covering the gate electrode M2 and the active layer ACT, as shown in fig. 9.

Step 8): a flat layer PLN is formed on the first passivation layer PVX1, and a pixel electrode opening PH is formed at the position of the pixel electrode, as shown in fig. 10; the planar layer PLN material may be an organic material such as a resin.

Step 9): depositing an electrode material on the planar layer PLN to form a common electrode layer Com, as shown in fig. 11; the electrode material may be ITO.

Step 10): depositing an insulating material to form a second passivation layer PVX2; the insulating material may be one or more combinations of silicon oxide or silicon nitride; next, openings are etched on the first passivation layer PVX1 and the second passivation layer PVX2 to expose the metal conductive layer M3, as shown in fig. 12; the opening size may be 3 μm×3 μm to 5 μm×5 μm, and the opening area cannot exceed the area of the metal conductive layer M3.

Step 11): depositing electrode materials in the pixel electrode openings PH to form a pixel electrode layer PIX, so as to obtain an array substrate shown in figure 1; ITO may be used as the electrode material.

In order to analyze the effect of the metal conductive layer M3 on the array substrate manufacturing process and the performance of the thin film transistor, the effect of etching at different stages on the thickness of the active layer ACT was measured for the array substrate of the embodiment of the present disclosure to which the metal conductive layer M3 was added and the array substrate of the conventional comparative example to which the metal conductive layer M3 was not added, respectively, and the measurement results are shown in table 1. It can be seen that after the second passivation layer PVX2 is dry etched, the active layer ACT according to the embodiment of the disclosure has a reduced thickness of the metal conductive layer M3(angstrom) the residual film thickness is +.>While the comparative example has no protection of the metal conductive layer M3, its film reduced thickness is +.>(angstrom) the residual film thickness is +.>The lower the residual film thickness of the active layer ACT, the larger the resistance and the poorer the stability.

Table 1: comparison of active layer ACT residual film thickness of examples of the present disclosure with conventional comparative examples

The contact resistance between the pixel electrode layer PIX and the active layer ACT of the array substrate provided by the present disclosure and the array substrate provided by the conventional scheme and the on-state current of the thin film transistor were measured, respectively, and the results thereof are shown in table 2. It can be seen that after the metal conductive layer M3 is added, the contact resistance between the active layer ACT and the pixel electrode layer PIX can be reduced by one order of magnitude, and the on-state current can be increased by about 30% simultaneously.

Table 2: setting contact resistance before and after the metal conductive layer M3 and on-state current of transistor TFT

Type(s)	Contact resistance	On-state current
			Embodiments of the present disclosure	About 3000 Ω	About 57. Mu.A
Comparative example	About 30000 Ω	About 44. Mu.A

Fig. 13A provides an ID-VG characteristic curve of a thin film transistor of an array substrate according to an embodiment of the present disclosure, fig. 13B provides an ID-VG characteristic curve of a thin film transistor of an array substrate of a conventional comparative example, and in fig. 13A and 13B, an abscissa is a gate M2 voltage VG of the thin film transistor and an ordinate is a drain current ID. It can be seen that the ID-VG curve of the embodiment of the disclosure shows the characteristics of high curve overlap ratio and good stability after being scanned for 2 times; the ID-VG curve of the traditional comparative example shows the characteristics of low curve overlap ratio and poor stability after being scanned for 2 times, which indicates that the thin film transistor on the array substrate provided by the disclosure has better switching performance and stability.

In a third aspect, based on the same inventive concept, in another alternative embodiment, a display panel is provided, including the array substrate provided by the embodiment of the first aspect. The display panel may be a liquid crystal display panel (Liquid Crystal Display, LCD), or an Organic Light-Emitting Diode (OLED) display panel, or the like.

In a third alternative embodiment, referring to fig. 14, a display device is provided, based on the same inventive concept, including the display panel provided in the third embodiment. The display device may be a display module including a display panel, or may be a display apparatus including a display panel. The display module and the display device can be electronic devices with display screens, such as flat televisions, flat computers, smart phones, displays for computers, conference integrated machines, vehicle-mounted display screens and the like.

In general, the embodiments of the present disclosure provide an array substrate, a manufacturing method of the array substrate, and a corresponding display panel and a display device, by adding a metal conductive layer M3 at a position where a pixel electrode layer PIX is connected to a drain region DA of an active layer ACT, and combining with a manufacturing method of a top gate self-aligned oxide thin film transistor, on the premise that TFT characteristics are not affected, a Mask process ILD Mask of an interlayer dielectric layer is omitted, thereby reducing the number of masks, shortening process time, and saving production cost; meanwhile, the newly added metal conductive layer M3 can reduce the damage of the dry etching process to the active layer ACT, so that the contact resistance between the pixel electrode layer PIX and the active layer ACT is reduced, and on-state current and device stability are improved.

While the preferred embodiments of the present disclosure have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the disclosure.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present disclosure without departing from the spirit or scope of the disclosure. Thus, the present disclosure is intended to include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims (11)

1. An array substrate, characterized by comprising:

a substrate base;

the transistor is arranged on the substrate and comprises an active layer, a gate dielectric layer and a gate electrode, wherein the active layer, the gate dielectric layer and the gate electrode are arranged in a stacked mode, the gate dielectric layer is arranged between the gate electrode and the active layer, and the active layer comprises a channel region, and a source region and a drain region which are arranged on two sides of the channel region;

and the pixel electrode layer is connected with the drain region through the metal conductive layer.

2. The array substrate of claim 1, further comprising a first passivation layer, a planarization layer, a common electrode layer, and a second passivation layer sequentially stacked on the transistor; the first passivation layer at least covers the gate arrangement;

the first passivation layer, the flat layer and the second passivation layer are provided with pixel electrode openings, the pixel electrode openings are used for exposing the opening areas of the metal conductive layers, and the pixel electrode layers at least cover the side walls of the pixel electrode openings and the opening areas.

3. The array substrate of claim 2, wherein an orthographic projection of the active layer on the substrate at the pixel electrode opening covers an orthographic projection of the metal conductive layer on the substrate.

4. The array substrate of claim 2, wherein an orthographic projection of the metal conductive layer on the substrate at the pixel electrode opening covers an orthographic projection of the openings of the first passivation layer and the second passivation layer on the substrate.

5. The array substrate of claim 2, wherein the metal conductive layer and the gate are the same layer of metal.

6. The array substrate of claim 1, further comprising a source drain metal layer disposed on the substrate and a buffer layer disposed overlying the source drain metal layer; the active layer is stacked on the buffer layer;

the source-drain metal layer comprises a shading layer and a data line; the orthographic projection of the shading layer on the substrate base plate at least covers the orthographic projection of the grid electrode on the substrate base plate.

7. The array substrate of claim 6, further comprising a metal connection layer for connecting the data line and the source region.

8. A method for manufacturing an array substrate, comprising:

providing a substrate;

forming an active layer, a gate dielectric layer, a gate electrode and a metal conducting layer which are stacked on the substrate; the gate dielectric layer is positioned between the gate and the active layer, the active layer comprises a channel region, a source region and a drain region, the source region and the drain region are positioned at two sides of the channel region, and the metal conducting layer is laminated on the drain region;

and forming a pixel electrode layer on the metal conductive layer.

9. The method of manufacturing of claim 8, wherein forming the active layer, the gate dielectric layer, the gate electrode, and the metal conductive layer on the substrate plate in a stacked arrangement comprises:

depositing a semiconductor material on the substrate and patterning to form the active layer;

depositing an insulating material on the active layer to form the gate dielectric layer, and forming an opening at the position of the pixel electrode layer to expose the active layer;

depositing a gate metal material on the gate dielectric layer and at the opening and patterning the gate metal material to form the gate and the metal conductive layer; the grid electrode is laminated on the grid dielectric layer, and the metal conducting layer is laminated on the active layer in the opening;

and conducting treatment on the active layer to enable the active layer to form a channel region and source electrode regions and drain electrode regions which are positioned on two sides of the channel region.

10. A display panel comprising an array substrate according to any one of claims 1 to 7.

11. A display device comprising the display panel according to claim 10.