CN117854440A

CN117854440A - Display panel and display device

Info

Publication number: CN117854440A
Application number: CN202410179194.XA
Authority: CN
Inventors: 王程
Original assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2024-02-08
Filing date: 2024-02-08
Publication date: 2024-04-09

Abstract

The application discloses a display panel and a display device; the pixel driving circuit comprises a switching transistor, a driving transistor, a compensation transistor and a first capacitor, wherein the switching transistor, the driving transistor, the compensation transistor and the first capacitor are connected, a first electrode of the compensation transistor is connected with a grid electrode of the driving transistor, a compensation grid electrode of the compensation transistor is connected with a first control signal line, a first polar plate of the first capacitor is connected with the first control signal line, and a second polar plate of the first capacitor is connected with a first high potential line; according to the display panel, the first capacitor is arranged between the first control signal line and the first high-potential line, the anti-coupling capacity of the first control signal line is improved by utilizing the high potential of the first high-potential line, and then the stability of a control signal transmitted by the first control signal line is improved, the abnormal opening of the compensation transistor is avoided, the stability of the potential of the grid electrode of the driving transistor is ensured, and the technical problem of abnormal display of the display panel is solved.

Description

Display panel and display device

Technical Field

The application relates to the technical field of display, in particular to a display panel and a display device.

Background

An OLED (Organic Light-Emitting Diode) display technology is a novel display technology, and is gradually paid attention to by unique advantages of low power consumption, high saturation, fast response time, wide viewing angle and the like, and takes a place in the technical field of panel display.

In the related art, a pixel driving circuit of an OLED display panel generally includes a switching transistor, a driving transistor, and a compensation transistor, wherein a drain electrode of the switching transistor is connected to a data line, a gate electrode of the compensation transistor is connected to a control signal line, and an overlapping area exists between the data line and the control signal line.

Disclosure of Invention

The application provides a display panel and a display device, which are used for improving the technical problem of abnormal display of the existing display panel.

In order to solve the above problems, the technical scheme provided by the application is as follows:

the application provides a display panel, it includes a plurality of sub-pixel unit, every sub-pixel unit include light emitting device and with the pixel drive circuit that light emitting device is connected, pixel drive circuit includes:

a switching transistor having a first electrode connected to the first data signal line and a second electrode connected to the first node;

A driving transistor, a first electrode of the driving transistor is connected to the first node, a second electrode of the driving transistor is connected to the second node, and a driving gate of the driving transistor is connected to the third node;

a compensation transistor, a first electrode of which is connected to the third node, a second electrode of which is connected to the second node, and a compensation gate of which is connected to a first control signal line; and

the first polar plate of the first capacitor is connected to the first control signal line, and the second polar plate of the first capacitor is connected to the first high potential line.

The application also provides a display device which comprises the display panel.

The beneficial effects are that: according to the display panel, the first capacitor is arranged between the first control signal line and the first high-potential line, the anti-coupling capacity of the first control signal line is improved by utilizing the high potential of the first high-potential line, and then the stability of a control signal transmitted by the first control signal line is improved, the abnormal opening of the compensation transistor is avoided, the stability of the potential of the grid electrode of the driving transistor is ensured, and the technical problem of abnormal display of the display panel is solved.

Drawings

Technical solutions and other advantageous effects of the present application will be made apparent from the following detailed description of specific embodiments of the present application with reference to the accompanying drawings.

FIG. 1 is a schematic diagram of a display panel of the present application;

FIG. 2 is an equivalent circuit diagram of a pixel driving circuit in a display panel of the present application;

FIG. 3 is a schematic view of a film layer in a display panel according to the present application;

FIG. 4 is a film layer diagram of a first gate layer of the display panel of the present application;

FIG. 5 is a film layer diagram of a first active layer in a display panel of the present application;

fig. 6 is a film lamination layer diagram of a first gate layer and a first active layer in the display panel of the present application;

FIG. 7 is a film layer diagram of a second gate layer of the display panel of the present application;

FIG. 8 is a film stack layer diagram of a first gate layer and a second gate layer in a display panel of the present application;

FIG. 9 is a film layer diagram of a second active layer in the display panel of the present application;

FIG. 10 is a film layer diagram of a third gate layer of the display panel of the present application;

FIG. 11 is a film layer diagram of a first active layer, a second gate layer and a third gate layer of the display panel of the present application;

FIG. 12 is a film layer diagram of a first source/drain layer in a display panel of the present application;

FIG. 13 is a film layer diagram of a first gate layer, a third gate layer, a first active layer, a second active layer, and a first source/drain layer in the display panel of the present application;

FIG. 14 is a film layer diagram of a second active layer, a second gate layer and a first source/drain layer in the display panel of the present application;

FIG. 15 is a film layer diagram of a first gate layer, a second gate layer, a third gate layer, a first active layer, a second active layer, and a first source/drain layer of the display panel of the present application;

FIG. 16 is a first film layer diagram of a second source/drain layer of the display panel of the present application;

FIG. 17 is a first film stack diagram of a first active layer, a second active layer, a third gate layer, a first source drain layer, and a second source drain layer in a display panel of the present application;

FIG. 18 is a first film stack diagram of a pixel drive circuit of the present application;

FIG. 19 is a diagram showing the connection between different sub-pixel units and different data lines of the display panel of the present application;

FIG. 20 is a second film layer diagram of a second source/drain layer of the display panel of the present application;

fig. 21 is a second film stack diagram of a first active layer, a second active layer, a third gate layer, a first source drain layer, and a second source drain layer in the display panel of the present application;

fig. 22 is a second film stack diagram of the pixel driving circuit of the present application;

FIG. 23 is a third film layer diagram of a second source/drain layer in the display panel of the present application;

fig. 24 is a third film stack diagram of a first active layer, a second active layer, a third gate layer, a first source drain layer, and a second source drain layer in the display panel of the present application;

Fig. 25 is a third film stack diagram of the pixel driving circuit of the present application;

FIG. 26 is a film layer diagram of a third source/drain layer in the display panel of the present application;

FIG. 27 is a film layer diagram of a second source/drain layer and a third source/drain layer of the display panel of the present application;

fig. 28 is a fourth film stack diagram of the pixel driving circuit of the present application;

FIG. 29 is a diagram of a third source/drain layer in a display panel of the present application in a plurality of sub-pixel units;

FIG. 30 is a diagram showing the connection relationship among the first reset signal line, the second reset signal line, the third reset signal line and the fourth reset signal line in the display panel of the present application;

fig. 31 is a film stack diagram of the third source/drain layer, the data signal line, and the anode of the light emitting device in the display panel of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application. Furthermore, it should be understood that the detailed description is presented herein for purposes of illustration and explanation only and is not intended to limit the present application. In this application, unless otherwise indicated, terms of orientation such as "upper" and "lower" are used to generally refer to the upper and lower positions of the device in actual use or operation, and specifically the orientation of the drawing figures; while "inner" and "outer" are for the outline of the device.

Referring to fig. 1 to 30, the present application provides a display panel 100, and the display panel 100 may include a display portion 200 and a gate driving circuit 300 located at one side of the display portion 200, wherein the gate driving circuit 300 is used for inputting a control signal to the display portion 200.

In this embodiment, referring to fig. 1, the display portion 200 includes a plurality of sub-pixel rows 210, each sub-pixel row 210 includes a plurality of sub-pixel units 211, a light emitting device 211b and a pixel driving circuit 211a connected to the light emitting device 211b are disposed in each sub-pixel unit 211, and the gate driving circuit 300 is used for inputting a gate control signal to a transistor in the pixel driving circuit 211 a.

In the present embodiment, the pixel driving circuit 211a may include a switching transistor T2, a driving transistor T1, and a compensation transistor T3 connected. The first electrode of the switching transistor T2 is connected to the first Data signal line Data1, the second electrode of the switching transistor T2 is connected to the first node a, the first electrode of the driving transistor T1 is connected to the first node a, the second electrode of the driving transistor T1 is connected to the second node B, the driving gate T1G of the driving transistor T1 is connected to the third node Q, the first electrode of the compensating transistor T3 is connected to the third node Q, the second electrode of the compensating transistor T3 is connected to the second node B, and the compensating gate T3G of the compensating transistor T3 is connected to the first control signal line Nscan1.

In this embodiment, the pixel driving circuit 211a further includes a first capacitor C1, a first plate of the first capacitor C1 is connected to the first control signal line Nscan1, and a second plate of the first capacitor C1 is connected to the first high potential line VDD1.

According to the display panel 100, the first capacitor C1 is arranged between the first control signal line Nscan1 and the first high potential line VDD1, the anti-coupling capacity of the first control signal line Nscan1 is improved by utilizing the high potential of the first high potential line VDD1, so that the stability of a control signal transmitted by the first control signal line Nscan1 is improved, the abnormal starting of the compensation transistor T3 is avoided, the stability of the potential of the grid electrode of the driving transistor T1 is ensured, and the technical problem of abnormal display of the display panel 100 is solved.

It should be noted that the light emitting device 211b of the present application may be an organic light emitting diode, a Mini LED, a Micro LED, a conventional size LED, or other light emitting source.

The technical solutions of the present application will now be described with reference to specific embodiments.

Referring to fig. 1, the display panel 100 includes a display area AA and a non-display area NA disposed adjacent to the display area AA, and a display portion 200 is disposed in the display area AA. Optionally, the non-display area NA surrounds the display area AA, so that the display area AA is surrounded by the non-display area NA. The display area AA is an area for performing a display function in the display panel 100, and a plurality of sub-pixel units 211 for realizing the display function are provided therein. The non-display area NA may be a frame area of the display panel 100, and functional components for assisting the sub-pixel unit 211 in the display area AA to display may be disposed therein.

Referring to fig. 1, a binding terminal 400 is disposed at the lower side of the display area AA, the binding terminal 400 can be connected to an external circuit, and the binding terminal 400 transmits signals input by the external circuit to the data trace, so as to drive the display panel 100 to display a picture. For example, the bonding terminal 400 may be bonded to a chip or a flip chip film, etc. for providing power and driving signals to the display panel 100, etc.

In the present embodiment, the gate driving circuit 300 is disposed in the non-display area NA, and the gate driving circuit 300 may be disposed at both sides of the display area AA; the gate driving circuit 300 may include a plurality of gate driving units in cascade, and the plurality of gate driving units may be arranged along the first direction X, and the structure of the gate driving units is not particularly limited herein.

In this embodiment, a plurality of light emitting devices 211b and a pixel driving circuit 211a for driving the light emitting devices 211b may be disposed in an array in the display area AA, and the pixel driving circuit 211a may be a pixel driving circuit 211a such as 7T1C, 7T2C, 8T3C, 8T4C, etc., and the following embodiment will be described taking the 8T3C pixel driving circuit 211a as an example.

Referring to fig. 2, the pixel driving circuit 211a may include a switching transistor T2, a driving transistor T1, a compensation transistor T3, a first reset transistor T4, a second reset transistor T7, a third reset transistor T8, a first light emitting transistor T5, a second light emitting transistor T6, a first capacitor C1, a boosting capacitor Cboost, and a storage capacitor Cst, wherein the first capacitor C1 includes a first plate and a second plate, the storage capacitor Cst includes a third plate Cst1 and a fourth plate Cst2, and the boosting capacitor Cboost includes a fifth plate and a sixth plate.

Referring to fig. 2, a first electrode of the switching transistor T2 is connected to the first Data signal line Data1, a second electrode of the switching transistor T2 is connected to the first node a, and a switching gate T2G of the switching transistor T2 is connected to the second control signal line Pscan1; a first electrode of the driving transistor T1 is connected to the first node a, a second electrode of the driving transistor T1 is connected to the second node B, and a driving gate T1G of the driving transistor T1 is connected to the third node Q; the first electrode of the compensation transistor T3 is connected to the third node Q, the second electrode of the compensation transistor T3 is connected to the second node B, and the compensation gate T3G of the compensation transistor T3 is connected to the first control signal line Nscan1; a first electrode of the first reset transistor T4 is connected to the first reset signal line Vi1, a second electrode of the first reset transistor T4 is connected to the third node Q, and a first reset gate T4G of the first reset transistor T4 is connected to the third control signal line Nscan2; a first electrode of the second reset transistor T7 is connected to the second reset signal line Vi2, a second electrode of the second reset transistor T7 is connected to the anode of the light emitting device 211b, and a second reset gate T7G of the second reset transistor T7 is connected to the fourth control signal line Pscan2; a first electrode of the third reset transistor T8 is connected to the third reset signal line Vi3, a second electrode of the third reset transistor T8 is connected to the first node a, and a third reset gate T8G of the third reset transistor T8 is connected to the fourth control signal line Pscan2; the first electrode of the first light emitting transistor T5 is connected to the first high potential line VDD1, the second electrode of the first light emitting transistor T5 is connected to the first node A, and the first light emitting grating T5G of the first light emitting transistor T5 is connected to the light emitting signal line EM; the first electrode of the second light emitting transistor T6 is connected to the second node B, the second electrode of the second light emitting transistor T6 is connected to the anode of the light emitting device 211B, and the second light emitting gate T6G of the second light emitting transistor T6 is connected to the light emitting signal line EM; the fifth polar plate of the boost capacitor Cboost is connected to the third node Q, and the sixth polar plate of the boost capacitor Cboost is connected to the second control signal line Pscan1; the third electrode Cst1 of the storage capacitor Cst is connected to the third node Q, and the fourth electrode Cst2 of the storage capacitor Cst is connected to the first high potential line VDD1; the first polar plate of the first capacitor C1 is connected to the first control signal line Nscan1, and the second polar plate of the first capacitor C1 is connected to the first high potential line VDD1; the cathode of the light emitting device 211b is connected to the first low potential line VSS.

Note that, the switching transistor T2 in the different sub-pixel units 211 is different from one data signal line to which it is connected, and only one of them is described as an example in the present application.

In the present embodiment, the first high potential line VDD1 is used to supply a constant voltage high level to the pixel driving circuit 211a, and the first low potential line VSS is used to supply a constant voltage low level to the pixel driving circuit 211 a.

In this embodiment, the switching transistor T2, the driving transistor T1, the second reset transistor T7, the third reset transistor T8, the first light emitting transistor T5, and the second light emitting transistor T6 may be one of a P-type transistor and an N-type transistor, and the compensation transistor T3 and the first reset transistor T4 may be the other one of a P-type transistor and an N-type transistor; the present application describes, as examples, a switching transistor T2, a driving transistor T1, a second reset transistor T7, a third reset transistor T8, a first light emitting transistor T5, and a second light emitting transistor T6 as P-type transistors, and a compensation transistor T3 and a first reset transistor T4N-type transistor.

In this embodiment, the capacitance value of the first capacitor C1 is smaller than the capacitance value of the storage capacitor Cst, and the capacitance value of the boost capacitor Cboost is smaller than the capacitance value of the storage capacitor Cst. In this embodiment, the storage capacitor Cst is mainly used for maintaining the stability of the potential of the third node Q, so the capacitance of the storage capacitor Cst is relatively large, for example, the capacitance range of the storage capacitor Cst may be 45fF to 55fF, and the capacitance range of the boost capacitor Cboost and the first capacitor C1 may be 5fF to 15fF.

In this embodiment, the first electrode may be one of the source or the drain, and the second electrode may be the other of the source or the drain.

In the following embodiments, the included angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 °, for example, the first direction X is transverse, and the second direction Y is longitudinal.

Next, a film structure of the pixel driving circuit 211a of the present application will be described with respect to the structure of fig. 2.

Referring to fig. 3, a display area AA and a non-display area NA of the display panel 100 may be provided with a substrate 110 and an array driving layer 120 disposed on the substrate 110; in the display area AA, the display panel 100 may further be provided with a pixel definition layer (not shown) disposed on the array driving layer 120, a light emitting device layer (not shown) disposed on the same layer as the pixel definition layer, and an encapsulation layer (not shown) disposed on the pixel definition layer. The following mainly describes the film structure in the display area AA.

In the present embodiment, the base substrate 110 supports the respective layers provided on the base substrate 110. When the display panel 100 is a bottom emission light emitting display device or a double-sided emission light emitting display device, a transparent substrate is used. When the display panel 100 is a top emission light emitting display device, a translucent or opaque substrate and a transparent substrate may be used.

In the present embodiment, the substrate 110 is used to support the respective film layers provided on the substrate 110, and the substrate 110 may be made of an insulating material such as glass, quartz, or polymer resin. The substrate base 110 may be a rigid substrate or a flexible substrate that may be bent, folded, rolled, etc. Examples of flexible materials for the flexible substrate include, but are not limited to, polyimide (PI).

In the present embodiment, the substrate base 110 may include a first flexible base 111, a first barrier layer 112, a second flexible base 113, and a second barrier layer 114 that are stacked, the first flexible base 111 and the second flexible base 113 may be formed of the same material such as polyimide, and the first barrier layer 112 and the second barrier layer 114 may be formed of an inorganic material including at least one of SiOx and SiNx, for example.

In the present embodiment, the first flexible substrate 111 is formed by coating a polymeric material on a support substrate (not shown) and then curing the polymeric material, the second flexible substrate 113 is formed by coating the same material as that of the first flexible substrate 111 and curing the material, and the second flexible substrate 113 is formed by the same method as that of forming the first flexible substrate 111. Each of the first and second flexible substrates 111 and 113 may be formed to have a thickness of about 8 μm to about 12 μm. Further, when the substrate base 110 is formed of the first flexible base 111 and the second flexible base 113, pinholes, cracks, and the like formed during the manufacture of the first flexible base 111 are covered by the second flexible base 113, so that the above-described defects can be removed.

Referring to fig. 3, the array driving layer 120 may include a plurality of thin film transistors, and the thin film transistors may be of an etching-stop type, a back channel etching type, or be divided into a bottom gate thin film transistor, a top gate thin film transistor, or the like according to the positions of the gate and the active layer, or be divided into an N-type thin film transistor and a P-type thin film transistor according to the performance of the thin film transistors; the tft in fig. 3 is not a schematic diagram of any of the transistors in fig. 2, but is a schematic diagram of each layer of the display panel 100.

Referring to fig. 3, the array driving layer 120 may include a light shielding layer 121 disposed on the substrate 110, a buffer layer 122 disposed on the light shielding layer 121, a first active layer 123 disposed on the buffer layer 122, a first gate insulating layer 124 disposed on the first active layer 123, a first gate layer 125 disposed on the first gate insulating layer 124, a second gate insulating layer 126 disposed on the first gate layer 125, a second gate layer 127 disposed on the second gate insulating layer 126, a third gate insulating layer 128 disposed on the second gate layer 127, a second active layer 129 disposed on the third gate insulating layer 128, a fourth gate insulating layer 130 disposed on the second active layer 129, a third gate layer 131 disposed on the fourth gate insulating layer 130, a first inter-gate insulating layer 132 disposed on the third gate layer 131, a first source-drain layer 133 disposed on the first inter-gate insulating layer 132, a second inter-gate insulating layer 134 disposed on the first source-drain layer 133, a second inter-gate insulating layer 135 disposed on the second inter-gate insulating layer 135, a third drain insulating layer 137 disposed on the third inter-gate insulating layer 136, and a third drain insulating layer 137 disposed on the third inter-gate insulating layer 136.

Referring to fig. 3, the light shielding layer 121 is disposed on the second blocking layer 114, and the light shielding layer 121 is used for shielding external light from entering the thin film transistor from the bottom, and the material of the light shielding layer 121 may be made of black light shielding material, such as black light shielding metal or black organic material.

Referring to fig. 3, a buffer layer 122 is disposed on the light shielding layer 121, the buffer layer 122 is used for isolating the light shielding layer 121 from the upper metal material, and the material of the buffer layer 122 may include a compound composed of nitrogen element, silicon element and oxygen element, such as a single silicon oxide film layer or a stacked structure of silicon oxide and silicon nitride.

Referring to fig. 3, the first active layer 123 is disposed on the buffer layer 122, the second active layer 129 may be disposed on the third gate insulating layer 128, and the materials of the first active layer 123 and the second active layer 129 may be an ingazn oxide semiconductor, amorphous silicon or low-temperature polysilicon, for example, the material of the first active layer 123 may be low-temperature polysilicon, and the material of the second active layer 129 may be an ingazn oxide semiconductor.

Referring to fig. 3, the first gate insulating layer 124, the second gate insulating layer 126, the third gate insulating layer 128, the fourth gate insulating layer 130, the first inter-insulating layer 132, the second inter-insulating layer 134, and the third inter-insulating layer 136 are respectively disposed on the corresponding metal layers or semiconductor layers, and are separated by the metal layers or semiconductor layers of different layers; the materials of the first gate insulating layer 124, the second gate insulating layer 126, the first inter-gate insulating layer 132, the third gate insulating layer 128, the fourth gate insulating layer 130, the second inter-gate insulating layer 134, and the third inter-gate insulating layer 136 may be inorganic materials combined with silicon oxynitride or organic materials having flatness.

Referring to fig. 3, the first gate layer 125, the second gate layer 127 and the third gate layer 131 are respectively disposed on the corresponding insulating layers, and the materials of the first gate layer 125, the second gate layer 127 and the third gate layer 131 may be copper, molybdenum or molybdenum-titanium alloy.

Referring to fig. 3, the first source/drain layer 133 is disposed on the first insulating layer 132, the second source/drain layer 135 is disposed on the second insulating layer 134, the third source/drain layer 137 is disposed on the third insulating layer 136, and the materials of the first source/drain layer 133, the second source/drain layer 135 and the third source/drain layer 137 may be copper, molybdenum-titanium alloy or titanium-aluminum-titanium three-layer metal.

Referring to fig. 3, the planarization layer 138 is laid on the whole layer to ensure the flatness of the film layer of the array driving layer 120, and the material of the planarization layer 138 may be an inorganic material or an organic material with flatness.

Referring to fig. 4, the first gate layer 125 includes a light emitting signal line EM, a first reset signal line Vi1, a third reset signal line Vi3, and a fourth control signal line Pscan2, wherein the light emitting signal line EM, the first reset signal line Vi1, the third reset signal line Vi3, and the fourth control signal line Pscan2 extend along a first direction X, and the third reset signal line Vi3, the fourth control signal line Pscan2, the light emitting signal line EM, and the first reset signal line Vi1 are arranged at intervals along a second direction Y.

Referring to fig. 4, the first gate layer 125 further includes a switching gate T2G and a third plate Cst1 disposed between the light emitting signal line EM and the first reset signal line Vi1, the switching gate T2G and the third plate Cst1 are arranged at intervals in the second direction Y, and the third plate Cst1 is close to the light emitting signal line EM, and the switching gate T2G is far away from the light emitting signal line EM.

In the present embodiment, the light emitting signal line EM may directly serve as the first light emitting gate T5G and the second light emitting gate T6G, and the fourth control signal line Pscan2 may directly serve as the second reset gate T7G and the third reset gate T8G.

Referring to fig. 4, the switch gate T2G and the third pole Cst1 may have rectangular shapes, and four corners of the third pole Cst1 may be chamfered.

Referring to fig. 5, the first active layer 123 includes a switching active portion T2A of the switching transistor T2, a driving active portion T1A of the driving transistor T1, a second reset active portion T7A of the second reset transistor T7, a third reset active portion T8A of the third reset transistor T8, a first light emitting active portion T5A of the first light emitting transistor T5, and a second light emitting active portion T6A of the second light emitting transistor T6.

Referring to fig. 5, the switch active portion T2A, the driving active portion T1A, the second reset active portion T7A, the first light emitting active portion T5A, and the second light emitting active portion T6A are connected to each other, the third reset active portion T8A is disposed separately from the other active portions, the switch active portion T2A, the second reset active portion T7A, the third reset active portion T8A, the first light emitting active portion T5A, and the second light emitting active portion T6A are elongated and extend along the second direction Y, the driving active portion T1A is in a shape of a letter and is disposed between the first light emitting active portion T5A and the second light emitting active portion T6A, a first end of the switch active portion T2A, a first end of the first light emitting active portion T5A is connected to the first connection point P1, a second end of the driving active portion T1A and a first end of the second light emitting active portion T6A are connected to the second connection point P2A, and a first end of the second light emitting active portion T6A are connected to the first end P3 a of the second light emitting active portion.

In this embodiment, the first connection point P1 is the first node a, the second connection point P2 is the second node B, and the third connection point P3 is the point where the anode of the light emitting device 211B is located.

Referring to fig. 6, the light emitting signal line EM overlaps the first light emitting active portion T5A partially, and the overlapping portion is a channel of the first light emitting active portion T5A; the light emitting signal line EM and the second light emitting active portion T6A partially overlap, and the overlapping portion is a channel of the second light emitting active portion T6A; the switch grid electrode T2G and the switch active part T2A are partially overlapped, and the overlapped part is a channel of the switch active part T2A; the fourth control signal line Pscan2 and the second reset active portion T7A are partially overlapped, and the overlapped portion is a channel of the second reset active portion T7A; the fourth control signal line Pscan2 and the third reset active portion T8A are partially overlapped, and the overlapped portion is a channel of the third reset active portion T8A; the driving active portion T1A and the third pole plate Cst1 are partially overlapped, and the overlapped portion is a channel of the driving active portion T1A, and the third pole plate Cst1 of the present application is multiplexed to a driving gate T1G of the driving transistor T1.

Referring to fig. 7 and 8, the second gate layer 127 includes a fourth electrode Cst2 of the storage capacitor Cst disposed along the second direction Y, a first light shielding unit T3S of the compensation transistor T3, and a second light shielding unit T4S of the first reset transistor T4, wherein the fourth electrode Cst2, the first light shielding unit T3S, and the second light shielding unit T4S are located between the light emitting signal line EM and the first reset signal line Vi1, the third electrode Cst1 is disposed near the light emitting signal line EM, the second light shielding unit T4S is disposed near the first reset signal line Vi1, and the first light shielding unit T3S is located between the second light shielding unit T4S and the fourth electrode Cst 2.

Referring to fig. 7 and 8, the area of the fourth pole plate Cst2 is larger than the area of the third pole plate Cst1, and the orthographic projection of the third pole plate Cst1 on the fourth pole plate Cst2 is located in the fourth pole plate Cst2, and a first through hole HL0 is formed in the fourth pole plate Cst2 to expose a portion of the third pole plate Cst1.

Referring to fig. 8, the first light shielding unit T3S, the second light shielding unit T4S, and the fourth electrode Cst2 may have rectangular shapes, and at least some of the top corners of the three may be chamfered.

Referring to fig. 8, the second gate layer 127 further includes first electrical connection sections 311 disposed on two sides of the fourth electrode Cst2, wherein the two first electrical connection sections 311 extend along a first direction X, and the fourth electrode Cst2 in two adjacent sub-pixel units 211 disposed along the first direction X is electrically connected through the first electrical connection section 311; the fourth electrode Cst2 of the present embodiment is connected to the first high potential line VDD1, and in order to reduce the impedance on the fourth electrode Cst2, the present application may connect the fourth electrode Cst2 in the sub-pixel unit 211 disposed along the first direction X to each other and be disposed in parallel with the first high potential line VDD1 of the upper layer, reducing the impedance of the first high potential line VDD1 and the fourth electrode Cst 2.

Referring to fig. 9 and 11, the second active layer 129 includes a compensation active portion T3A of the compensation transistor T3 and a first reset active portion T4A of the first reset transistor T4, wherein the compensation active portion T3A and the first reset active portion T4A extend along the second direction Y, a first end of the compensation active portion T3A and a first end of the first reset active portion T4A are connected to the fourth connection point P4, a second end of the compensation active portion T3A extends toward the second connection point P2 and is separated from the second connection point P2, and a second end of the first reset active portion T4A extends toward the first reset signal line Vi1 and overlaps the first reset signal line Vi 1.

In this embodiment, the fourth connection point P4 may be the third node Q.

Referring to fig. 9 and 11, the second active layer 129 further includes a first extension 321 connected to the fourth connection point P4 and a second extension 322 connected to the second end of the first reset active portion T4A; the first extension section 321 extends along the second direction Y and extends to the position of the storage capacitor Cst, and the first extension section 321 is separated from the storage capacitor Cst; the second extension section 322 extends in the first direction X, and the second extension section 322 and the first reset signal line Vi1 at least partially overlap.

Referring to fig. 10 and 11, the third gate layer 131 includes a compensation gate T3G and a first reset gate T4G of the first reset transistor T4, an area of the compensation gate T3G is smaller than an area of the first light shielding unit T3S, an orthographic projection of the compensation gate T3G on the first light shielding unit T3S is located in the first light shielding unit T3S, an area of the first reset gate T4G is smaller than an area of the second light shielding unit T4S, and an orthographic projection of the first reset gate T4G on the second light shielding unit T4S is located in the second light shielding unit T4S.

Referring to fig. 10 and 11, the first reset gate T4G and the first reset active portion T4A are partially overlapped, and the overlapped portion is a channel of the first reset active portion T4A; the compensation active portion T3A and the compensation active portion T3A partially overlap, and the overlapping portion is a channel of the compensation active portion T3A.

Referring to fig. 10 and 11, the first reset gate T4G and the compensation gate T3G may be rectangular, and part of top corners of the first reset gate T4G and the compensation gate T3G may be chamfered.

Referring to fig. 10 and 11, the third gate layer 131 further includes a first conductive segment 331 connected to the compensation gate T3G, and a second conductive segment 332 connected to the first reset gate T4G, wherein the first conductive segment 331 extends along the second direction Y and toward a side away from the compensation gate T3G, and the second conductive segments 332 each extend along the second direction Y and toward a side away from the first reset gate T4G.

Referring to fig. 7 and 11, the second gate layer 127 further includes a third conductive segment 333 connected to the first light shielding unit T3S, and a fourth conductive segment 334 connected to the second light shielding unit T4S. The third conductive segment 333 extends along the second direction Y and toward a side away from the compensation gate T3G, a line width of the first conductive segment 331 may be less than or equal to a line width of the third conductive segment 333, and an orthographic projection of the first conductive segment 331 on the third conductive segment 333 may be located within the third conductive segment 333; the fourth conductive segment 334 may extend first along the second direction Y and toward a side away from the first reset gate T4G, and second may extend along the first direction X and toward a side away from the compensation transistor T3, and one ends of the second conductive segment 332 and the fourth conductive segment 334 away from the first reset gate T4G may be located on the same horizontal line.

Referring to fig. 12, the first source-drain layer 133 includes a second reset signal line Vi2, a fifth control signal line Nscan3, a second high potential line VDD2, a second control signal line Pscan1, a first control signal line Nscan1, a third control signal line Nscan2, a second reset signal line Vi2, a fifth control signal line Nscan3, a second high potential line VDD2, a second control signal line Pscan1, a first control signal line Nscan1, and a third control signal line Nscan2, all of which may extend in the first direction X.

Referring to fig. 12 to 15, the second reset signal line Vi2 is disposed between the third reset signal line Vi3 and the first control signal line Nscan1, the fifth control signal line Nscan3 and the fourth control signal line Pscan2 are partially overlapped, the second high potential line VDD2 is disposed between the light emitting signal line EM and the first electrical connection section 311, the second control signal line Pscan1, the first control signal line Nscan1 and the third control signal line Nscan2 are disposed between the first electrical connection section 311 and the first reset signal line Vi1, and the second control signal line Pscan1 is disposed near the first electrical connection section 311, the third control signal line Nscan2 is disposed near the first reset signal line Vi1, and the first control signal line Nscan1 is disposed between the second control signal line Pscan1 and the third control signal line Nscan 2.

Referring to fig. 12 to 15, the first source-drain layer 133 further includes a second electrical connection section 312 disposed between the second reset signal line Vi2 and the third reset signal line Vi3, a first end of the second electrical connection section 312 passes through the first via HL1 and the third reset signal line Vi3 to be electrically connected, a second end of the second electrical connection section 312 passes through the second via HL2 and the first end of the third reset active portion T8A to be electrically connected, and the third reset signal line Vi3 transmits the reference voltage to the third reset transistor T8 through the second electrical connection section 312.

In the present embodiment, the first via HL1 penetrates the second gate insulating layer 126, the third gate insulating layer 128, the fourth gate insulating layer 130, and the first inter-insulating layer 132, and the second via HL2 penetrates the first gate insulating layer 124, the second gate insulating layer 126, the third gate insulating layer 128, the fourth gate insulating layer 130, and the first inter-insulating layer 132.

In this embodiment, in order to avoid interference between the second electrical connection section 312 and the second reset signal line Vi2, the second reset signal line Vi2 is designed to sink at a position corresponding to the second electrical connection section 312, that is, the signal line of the region is offset toward the side away from the third reset signal line Vi 3; meanwhile, in order to secure a line distance between the fifth control signal line Nscan3 and the second reset signal line Vi2, the fifth control signal line Nscan3 is also designed to sink.

Referring to fig. 12 to 15, the first source/drain layer 133 further includes a third extension segment 323, a third electrical connection segment 313 and a fourth electrical connection segment 314 disposed between the second high potential line VDD2 and the fifth control signal line Nscan3, wherein the third extension segment 323 and the third electrical connection segment 313 extend along the second direction Y, and the fourth electrical connection segment 314 extends along the first direction X.

In the present embodiment, the first end of the third extension 323 is electrically connected to the second high potential line VDD2, the second end of the third extension 323 extends to a side far away from the second high potential line VDD2, and the third extension 323 overlaps a portion of the first light emitting active portion T5A, and the second end of the third extension 323 is electrically connected to the second end of the first light emitting active portion T5A through the third via HL 3; the first end of the third electrical connection section 313 is electrically connected through the fourth via HL4 and the second end of the third reset active portion T8A, the first active layer 123 further includes a fourth extension section 324 connected to the first light emitting active portion T5A, the fourth extension section 324 extends along the first direction X, the second end of the third electrical connection section 313 is electrically connected through the fifth via HL5 and the fourth extension section 324, and the third reset signal line Vi3 transmits a reference voltage to the first connection point P1 through the second electrical connection section 312, the third electrical connection section 313 and the fourth extension section 324 to reset the potential of the first node a; one end of the fourth electrical connection section 314 is electrically connected to the third connection point P3 in the first active layer 123 through one via hole, and the other end of the fourth electrical connection section 314 is electrically connected to the conductive layer in the second source-drain layer 135 through the other via hole.

In the present embodiment, the third via HL3 penetrates the first gate insulating layer 124, the second gate insulating layer 126, the third gate insulating layer 128, the fourth gate insulating layer 130, the first inter-insulating layer 132, and the fourth via HL4 and the fifth via HL5 each penetrate the first gate insulating layer 124, the second gate insulating layer 126, the third gate insulating layer 128, the fourth gate insulating layer 130, the first inter-insulating layer 132.

Referring to fig. 12 to 15, the first source/drain layer 133 further includes a fifth electrical connection section 315 and a sixth electrical connection section 316 disposed between the second high potential line VDD2 and the second control signal line Pscan1, and the fifth electrical connection section 315 and the sixth electrical connection section 316 each extend along the second direction Y.

In the present embodiment, the first end of the fifth electrical connection section 315 is electrically connected through the sixth via HL6 and one end of the first extension section 321 far away from the second control signal line Pscan1, the second end of the fifth electrical connection section 315 extends into the storage capacitor Cst and is electrically connected with the third electrode Cst1 of the storage capacitor Cst through the seventh via HL7, in the structure of fig. 14, the seventh via HL7 passes through the first via HL0 on the fourth electrode Cst2, and the center of the first via HL0 and the center of the seventh via HL7 may be located on the same straight line perpendicular to the light emitting surface of the display panel 100; a first end of the sixth electrical connection section 316 is electrically connected through the eighth via HL8 and the second connection point P2 in the first active layer 123, and a second end of the sixth electrical connection section 316 is electrically connected through the ninth via HL9 and the second end in the compensation active portion T3A.

In the present embodiment, the sixth via HL6 and the ninth via HL9 penetrate through the fourth gate insulating layer 130, the first inter-insulating layer 132, and the seventh via HL7 and the eighth via HL8 penetrate through the first gate insulating layer 124, the second gate insulating layer 126, the third gate insulating layer 128, the fourth gate insulating layer 130, the first inter-insulating layer 132.

Referring to fig. 12 to 15, the first source/drain layer 133 further includes a fifth extension 325, one end of the fifth extension 325 is electrically connected to the first control signal line Nscan1, and the fifth extension 325 extends along the second direction Y and towards a side far away from the first control signal line Nscan 1; one end of the fifth extension segment 325 away from the first control signal line Nscan1 is electrically connected through the tenth via HL10 and the first conductive segment 331, and the first control signal line Nscan1 transmits a control signal to the compensation gate T3G of the compensation transistor T3 through the fifth extension segment 325 and the first conductive segment 331; meanwhile, an end of the second conductive segment 332 remote from the first reset gate T4G overlaps the third control signal line Nscan2 and is electrically connected to the third control signal line Nscan2 through the eleventh via HL11, and the third control signal line Nscan2 transmits a control signal to the first reset gate T4G of the first reset transistor T4 through the second conductive segment 332.

In the present embodiment, the tenth via HL10 and the eleventh via HL11 each penetrate through the first inter-insulating layer 132.

Referring to fig. 12 to 15, the third conductive segment 333 overlaps the first conductive segment 331 and the third conductive segment 333, and the third conductive segment 333 is electrically connected to the first control signal line Nscan1 through the twelfth via HL12, the first control signal line Nscan1 transmits a control signal to the first light shielding unit T3S through the third conductive segment 333, that is, the first light shielding unit T3S may be multiplexed as the bottom gate of the compensation transistor T3, the compensation gate T3G is the top gate of the compensation transistor T3, and the arrangement of the first light shielding unit T3S and the compensation gate T3G may increase the turn-on rate of the compensation transistor T3, so as to improve the device effect of the compensation transistor T3; the fourth conductive segment 334 overlaps a portion of the third control signal line Nscan2, and is electrically connected to the third control signal line Nscan2 through the thirteenth through hole HL13, the third control signal line Nscan2 transmits a control signal to the second light shielding unit T4S through the fourth conductive segment 334, that is, the second light shielding unit T4S may be multiplexed as the bottom gate of the first reset transistor T4, the first reset gate T4G is the top gate of the first reset transistor T4, and the arrangement of the second light shielding unit T4S and the first reset gate T4G may increase the turn-on rate of the first reset transistor T4, thereby improving the device effect of the first reset transistor T4.

In the present embodiment, the twelfth via HL12 and the thirteenth via HL13 each penetrate through the third gate insulating layer 128, the fourth gate insulating layer 130, and the first inter-insulating layer 132.

Note that the third conductive segment 333 may be disposed insulated from the first control signal line Nscan1, and the fourth conductive segment 334 may be disposed insulated from the third control signal line Nscan 2.

Referring to fig. 12 to 15, the fifth control signal line Nscan3 may be connected in parallel through the fourteenth via HL14 and the fourth control signal line Pscan2, i.e., the fifth control signal and the fourth control signal line Pscan2 are arranged in parallel, reducing the impedance of the fifth control signal line Nscan3 and the fourth control signal line Pscan 2.

In the present embodiment, the fourteenth via HL14 penetrates the second gate insulating layer 126, the third gate insulating layer 128, the fourth gate insulating layer 130, and the first inter-insulating layer 132.

Referring to fig. 12 to 15, the first control signal line Nscan1 and the first reset active portion T4A are partially overlapped, the second control signal line Pscan1 and the first extension portion 321 are partially overlapped, the second control signal line Pscan1 and the compensation active portion T3A are partially overlapped, the third control signal line Nscan2 and the first reset active portion T4A are partially overlapped, the overlapping regions are all overlapping of the material of the second active layer 129 and the material of the first source drain layer 133, the fourth gate insulating layer 130 and the first inter-insulating layer 132 are spaced between the first source drain layer 133 and the second active layer 129, and the material of the third gate layer 131 is not disposed in the middle, so that the technical problem that the third gate layer 131 is easy to be shorted with the first source drain layer 133 is avoided.

Referring to fig. 12 to 15, the portion where the second control signal line Pscan1 overlaps the first extension 321 is a boost capacitor Cboost of the present application, a fifth plate of the boost capacitor Cboost may be a portion of the first extension 321 overlapping the second control signal line Pscan1, and a sixth plate of the boost capacitor Cboost may be a portion of the second control signal line Pscan1 overlapping the first extension 321.

Referring to fig. 12 to 15, the first source-drain layer 133 further includes a seventh electrical connection segment 317 disposed between the second reset signal line Vi2 and the third control signal line Nscan2, the seventh electrical connection segment 317 extending along the second direction Y and toward a side away from the second reset signal line Vi 2; the seventh electrical connection section 317 and the second extension section 322 are overlapped, i.e., the capacitance is formed between the first reset signal line Vi1 and the second reset signal line Vi2, so as to ensure the stability of the voltages on the first reset signal line Vi1 and the second reset signal line Vi 2.

Referring to fig. 16, the second source/drain layer 135 includes a first Data signal line Data1, a second Data signal line Data2, and a first high potential line VDD1, wherein the second Data signal line Data2, the first Data signal line Data1, and the first high potential line VDD1 are arranged along a first direction X and extend along a second direction Y, and the first Data signal line Data1 is disposed between the second Data signal line Data2 and the first high potential line VDD 1.

Referring to fig. 17 to 19, the first source/drain layer 133 includes an eighth electrical connection section 318 disposed between the first control signal line Nscan1 and the second control signal line Pscan1, one end of the eighth electrical connection section 318 is electrically connected to the second end of the switching active portion T2A, the other end of the eighth electrical connection section 318 is electrically connected to the first Data signal line Data1, and the first Data signal line Data1 transmits a Data signal to the switching transistor T2 through the eighth electrical connection section 318.

In the structure of fig. 19, the present application enumerates 6 sub-pixel units 211, the sub-pixel units 211 located in the first row are all connected to the first Data signal line Data1, the sub-pixel units 211 located in the second row are all connected to the second Data signal line Data2, and the sub-pixel units 211 enumerated in fig. 17 and 18 herein are the sub-pixel units 211 of the first row in fig. 19.

In this embodiment, the structure of each pixel driving circuit 211a is the same, that is, the input ends of the switch active portions T2A corresponding to the switch transistors T2 are all disposed on the same side, if the first Data signal line Data1 and the second Data signal line Data2 are disposed on two sides of the pixel driving circuit 211a, for example, when the first Data signal line Data1 is disposed on the left side of the pixel driving circuit 211a and the second Data signal line Data2 is disposed on the right side of the pixel driving circuit 211a, the input ends of the switch active portions T2A of the sub-pixel units 211 of the first row are disposed adjacent to the first Data signal line Data1, and the pitch between the switch active portions T2A of the sub-pixel units 211 of the second row and the second Data signal line Data2 is the width of one sub-pixel unit 211, that is, a connecting line crossing the sub-pixel units 211 is required to electrically connect the second Data signal line Data2 and the switch active portions T2A of the sub-pixel units 211 of the second row, and the connecting line overlap with the plurality of structures in the pixel driving circuit 211a, so that the capacitance coupling stability of the pixel driving circuit 211a is deteriorated; for example, in the structure of fig. 19, by disposing two data signal lines on the same side of the pixel driving circuit 211a, the connection distance between the data signal lines and the switching active portion T2A in the sub-pixel unit 211 is reduced, the coupling capacitance inside the pixel driving circuit 211a is reduced, and the stability of the pixel driving circuit 211a is improved.

Referring to fig. 16 to 18, the first high-potential line VDD1 includes a first sub-board 341, a second sub-board 342, a third sub-board 343, a fourth sub-board 344 and a fifth sub-board 345, wherein the third sub-board 343, the first sub-board 341, the fourth sub-board 344, the second sub-board 342 and the fifth sub-board 345 are arranged along the second direction Y, the first sub-board 341 is arranged between the third sub-board 343 and the fourth sub-board 344, and the second sub-board 342 is arranged between the fourth sub-board 344 and the fifth sub-board 345; in the first direction X, the width of the first sub-board 341 is smaller than the width of the second sub-board 342, the width of the first sub-board 341 may be greater than the width of the fourth sub-board 344, and the width of the fourth sub-board 344 may be greater than or equal to the widths of the third sub-board 343 and the fifth sub-board 345.

In the present embodiment, since the potential of the driving gate T1G is the potential of the third node Q, the potential change of the third node Q directly affects the operating current of the light emitting device 211b, so the present application needs to ensure the stability of the potential of the third node Q; the orthographic projection of the driving gate T1G on the first high-potential line VDD1 can be located in the first sub-board 341, that is, the first sub-board 341 is used as a shielding layer to maintain the stability of the third node Q potential, so that the application needs to increase the lateral width of the first sub-board 341, so that the first sub-board 341 fully covers the driving gate T1G, and the third sub-board Cst1 of the storage capacitor Cst is multiplexed to the driving gate T1G, that is, the orthographic projection of the third sub-board Cst1 on the first high-potential line VDD1 can be located in the first sub-board 341, so that the width of the first sub-board 341 in the application can be larger than the widths of the third sub-board 343, the fourth sub-board 344 and the fifth sub-board 345.

In this embodiment, the fifth electrical connection section 315 and the first extension section 321 are electrically connected to the driving gate T1G, so the electric potential variation on the fifth electrical connection section 315 and the first extension section 321 also affects the electric potential of the driving gate T1G, so the width of the fourth sub-board 344 can be increased to fully cover the fifth electrical connection section 315 and the first extension section 321, and thus the lateral width of the fourth sub-board 344 can be larger than the lateral width of the third sub-board 343 and the fifth sub-board 345.

Referring to fig. 16 and 17, the compensation gate T3G is a first sub-portion of the first plate, and the orthographic projection of the compensation gate T3G on the first high-potential line VDD1 is located in the second sub-plate 342, and the second sub-plate 342 may be a second plate of the first capacitor C1.

According to the display panel, the part of the first high potential line VDD1 is overlapped with the compensation grid T3G, the compensation grid T3G is used as a first polar plate, the second sub-plate 342 is used as a second polar plate, the first polar plate and the second polar plate form the first capacitor C1, the constant high potential on the second polar plate improves the anti-coupling capacity of the first control signal line Nscan1, and further improves the stability of a control signal transmitted by the first control signal line Nscan1, so that the abnormal starting of the compensation transistor T3 is avoided, the stability of the potential of the grid of the driving transistor T1 is ensured, and the technical problem of abnormal display of the display panel 100 is solved.

It should be noted that, since the second sub-board 342 needs to fully cover the compensation gate T3G and a portion of the first extension section 321, the lateral width of the second sub-board 342 of the present application is greater than the lateral width of the first sub-board 341.

Referring to fig. 20 to 22, the second sub-board 342 has an increased longitudinal width compared to the structures of fig. 16 and 17, and the orthographic projection of the first conductive segment 331 on the first high-potential line VDD1 may be located in the second sub-board 342; that is, the first conductive segment 331 may be used as a second sub-portion of the first electrode plate, and an orthographic projection of the second sub-portion on the second source-drain layer 135 is located in the first high-potential line VDD 1.

According to the display panel, the longitudinal width of the second subplate 342 is increased, so that the second subplate 342 simultaneously covers the compensation grid T3G and the first conductive section 331, the compensation grid T3G and the first conductive section 331 serve as first polar plates, the second subplate 342 serves as second polar plates, the first polar plates and the second polar plates form the first capacitor C1, the relative area between the first polar plates and the second polar plates is increased, the capacitance value of the first capacitor C1 is increased, the stability of control signals transmitted by the first control signal line Nscan1 is further improved, abnormal opening of the compensation transistor T3 is avoided, the stability of the potential of the grid electrode of the driving transistor T1 is guaranteed, and the technical problem that the display panel 100 displays abnormal is solved.

Referring to fig. 23 to 25, compared with fig. 20 to 22, the longitudinal width of the second sub-board 342 is further increased, and part of the first control signal line Nscan1 and the second sub-board 342 overlap, the first control signal line Nscan1 overlapping the second sub-board 342 is a third sub-portion of the first electrode plate, and the orthographic projection of the third sub-portion on the second source/drain layer 135 is located in the first high potential line VDD 1.

According to the display panel 100, the longitudinal width of the second sub-board 342 is increased, so that the second sub-board 342 simultaneously covers the compensation grid T3G, the first conductive section 331 and part of the first control signal line Nscan1, the compensation grid T3G, the first conductive section 331 and part of the first control signal line Nscan1 serve as first polar plates, the second sub-board 342 serves as second polar plates, the first polar plates and the second polar plates form the first capacitor C1, the relative area between the first polar plates and the second polar plates is increased, the capacitance value of the first capacitor C1 is increased, the stability of a control signal transmitted by the first control signal line Nscan1 is further improved, abnormal starting of the compensation transistor T3 is avoided, the stability of the potential of the grid of the driving transistor T1 is guaranteed, and the technical problem of abnormal display of the display panel 100 is improved.

Accordingly, the first plate may be disposed in the third gate layer 131, or the first plate may be disposed in the first source drain layer 133, or the first plate may be disposed in both the third gate layer 131 and the first source drain layer 133, while the second plate is disposed only in the second source drain layer 135.

In fig. 16 to 25, since the fifth extension 325 is connected to the first control signal line Nscan1 and the fifth extension 325 overlaps the second sub-board 342, the fifth extension 325 of the present application may also be used as the fourth sub-portion of the first electrode plate, i.e. the orthographic projection of the fourth sub-portion on the first high potential line VDD1 is located in the second sub-board 342.

Note that, in fig. 16 to 25, since the area of the first light shielding unit T3S is larger than the area of the compensation gate T3G, and the first light shielding unit T3S may be electrically connected to the first control signal line Nscan1, a capacitance is also formed between a portion of the first light shielding unit T3S that exceeds the compensation gate T3G and the second sub-board 342, and a portion of the first light shielding unit T3S that exceeds the compensation gate T3G may be a portion of the first sub-board 341.

In fig. 16 to 22, a part of the third sub-portion and the first control signal line Nscan1 are overlapped, and the overlapped part may be a part of the first electrode plate and the second electrode plate, respectively.

It should be noted that, when the first high-potential line VDD1 does not cover the compensation gate T3G and the first conductive segment 331, there is a smaller area of overlap between the first control signal line Nscan1 and the first high-potential line VDD1, the first capacitance C1 therebetween may be 7.3fF, and the second capacitance between the data line and the first control signal line Nscan1 is 1.05fF; taking the second source-drain layer 135 in fig. 22 and 23 as an example, when the first high-potential line VDD1 does not cover the compensation gate T3G, the first conductive segment 331, and part of the first control signal line Nscan1, the area of the first electrode plate increases, the first capacitance C1 between the first high-potential line VDD1 and the first control signal line Nscan1 increases to 14.2fF, and the second capacitance between the data line and the first control signal line Nscan1 is still 1.05fF; therefore, compared with the prior art, the quotient of the second capacitance value and the first capacitance C1 value is reduced from 14.38% to 7.4%, the anti-coupling capacity of the first control signal line Nscan1 is improved, and the stability of the control signal transmitted by the first control signal line Nscan1 is further improved.

Referring to fig. 26 and 28, the third source/drain layer 137 may include a third high potential line VDD3 extending along the second direction Y, the third high potential line VDD3 is electrically connected to the second high potential line VDD2, and the third high potential line VDD3 is mainly configured to reduce the impedance of a conductive line transmitting a constant voltage high level.

It should be noted that, in fig. 16 to 26, the first high-potential line VDD1 of the present application may be electrically connected to the second high-potential line VDD2, and then the second high-potential line VDD2 is electrically connected to the fourth electrode Cst2 of the storage capacitor Cst, and the fourth electrode Cst2 located in the same row is electrically connected through the first electrical connection section 311; therefore, the wire for transmitting the constant voltage high level has four layers of metals, namely the fourth electrode Cst2 and the first electric connection section 311 which are positioned in the second gate layer 127, the second high potential line VDD2 which is positioned in the first source drain layer 133, the first high potential line VDD1 which is positioned in the second source drain layer 135, the third high potential line VDD3 which is positioned in the third source drain layer 137, the fourth electrode Cst2, the first electric connection section 311 and the second high potential line VDD2 all extend along the first direction X, and the first high potential line VDD1 and the third high potential line VDD3 all extend along the second direction Y, so the wire uses four layers of metals for transmitting the constant voltage high level to form a metal net which is in a net shape in a transverse-longitudinal staggered manner, thereby reducing the impedance of the wire and reducing the loss of the constant voltage high level on the transmission wire.

Referring to fig. 29, the third source-drain layer 137 of the present application includes a plurality of repeating units 137a, each repeating unit 137a corresponds to three adjacent sub-pixel units 211 arranged along the first direction X, for example, the three sub-pixel units 211 are respectively a first sub-pixel unit 212, a second sub-pixel unit 213 and a third sub-pixel unit 214, each repeating unit 137a may include a 1 st third high potential line VDD3 corresponding to the first sub-pixel unit 212, a 3 rd third high potential line VDD3 corresponding to the third sub-pixel unit 214, a 2 nd high potential line corresponding to the second sub-pixel unit 213 and a fourth reset signal line Vi4, the structures of the 1 st third high potential line VDD3 and the 3 rd third high potential line VDD3 may be the same, the structures of the 2 nd third high potential line VDD3 and the 3 rd third high potential line VDD3 are different, and the lateral width of the 2 nd third high potential line VDD3 is smaller than the lateral width of the 3 rd third high potential line VDD 3.

Referring to fig. 29, a longitudinal reset signal line and three transverse reset signal lines are disposed in each repeating unit 137a, and in order to reduce the impedance of the reset signal lines, the reset signal lines disposed longitudinally may be electrically connected to one of the three transverse reset signal lines; for example, in fig. 30, 3 rows of repeating units 137a are provided, each row of repeating units 137a includes 3 repeating units 137a, 1 fourth reset signal line Vi4 is provided in each repeating unit 137a, the fourth reset signal line Vi4 in the 1 st repeating unit 137a may be electrically connected to the first reset signal line Vi1 of each row, the fourth reset signal line Vi4 in the 2 nd repeating unit 137a may be electrically connected to the second reset signal line Vi2 of each row, and the fourth reset signal line Vi4 in the 3 rd repeating unit 137a may be electrically connected to the third reset signal line Vi3 of each row, so that each reset signal line and the fourth reset signal line Vi4 which are transversely arranged are electrically connected to form a metal mesh which is horizontally and longitudinally staggered, thereby reducing the impedance of the reset signal lines.

It should be noted that, in fig. 29, the first sub-pixel unit 212, the second sub-pixel unit 213, and the third sub-pixel unit 214 only represent the positions of the pixel driving circuits 211a of the corresponding sub-pixel units 211, and the positions of the anodes in the sub-pixel units 211 may not be in the corresponding areas; for example, referring to fig. 31, the pixel driving circuit 211a in the first sub-pixel unit 212 is electrically connected to the first anode 211b1, the pixel driving circuit 211a in the second sub-pixel unit 213 is electrically connected to the second anode 211b2, the first anode 211b1 and the second anode 211b2 are arranged along the second direction Y, and the first anode 211b1 and the second anode 211b2 span across the first sub-pixel unit 212 and the second sub-pixel unit 213.

In fig. 31, the third source-drain layer 137 may further include a ninth electrical connection section 319 and a tenth electrical connection section 320, the ninth electrical connection section 319 is disposed between the fourth reset signal line Vi4 and the 2 nd third high potential line VDD3, the tenth electrical connection section 320 is disposed at one side of the 1 st third high potential line VDD3 and the 3 rd third high potential line VDD3, and the tenth electrical connection section 320 corresponds to the fourth electrical connection section 314; the second source-drain layer 135 may further include an eleventh electrical connection section 321, and the second anode electrode 211b2 may be electrically connected through third connection points P3 of the first active layer 123 in the ninth electrical connection section 319, the eleventh electrical connection section 321, the fourth electrical connection section 314 of the second sub-pixel unit 213 and the pixel driving circuit 211a of the second sub-pixel unit 213; similarly, the first anode electrode 211b1 may be electrically connected to the third connection point P3 of the first active layer 123 in the pixel driving circuit 211a of the first sub-pixel unit 212 through the tenth electrical connection section 320, the eleventh electrical connection section 321, the fourth electrical connection section 314 of the first sub-pixel unit 212; similarly, the connection of the anode electrode in the third sub-pixel unit 314 is the same as that of the first anode electrode 211b 1.

The application also provides a display device, which comprises the display panel. The display device may be: any product or component with display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.

The foregoing has described in detail a display panel provided by embodiments of the present application, and specific examples have been applied herein to illustrate the principles and embodiments of the present application, where the foregoing examples are only for aiding in understanding of the technical solutions and core ideas of the present application; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel comprising a plurality of sub-pixel units, each of the sub-pixel units comprising a light emitting device and a pixel driving circuit connected to the light emitting device, the pixel driving circuit comprising:

2. The display panel of claim 1, wherein the display panel comprises:

a substrate base;

the first grid electrode layer is arranged on one side of the substrate base plate;

the second grid electrode layer is arranged on one side, far away from the substrate, of the first grid electrode layer;

the third grid electrode layer is arranged on one side, far away from the first grid electrode layer, of the second grid electrode layer;

The first source-drain electrode layer is arranged on one side of the third grid electrode layer far away from the second grid electrode layer;

the second source-drain electrode layer is arranged on one side of the first source-drain electrode layer, which is far away from the third grid electrode layer;

the first polar plate is arranged on at least one of the third gate layer and the first source drain layer, and the second polar plate is arranged on the second source drain layer.

3. The display panel according to claim 2, wherein the second source-drain layer includes a plurality of the first high potential lines arranged in a first direction and extending in a second direction, the third gate layer includes the compensation gate and a first conductive segment, one end of the first conductive segment is electrically connected to the compensation gate, and the other end of the first conductive segment is electrically connected to the first control signal line;

the compensation gate is a first sub-portion of the first polar plate, orthographic projection of the first sub-portion on the second source-drain electrode layer is located in the first high potential line, and an included angle between the first direction and the second direction is larger than 0 and smaller than or equal to 90 degrees.

4. The display panel of claim 3, wherein the first conductive segment is a second sub-portion of the first plate, and an orthographic projection of the second sub-portion on the second source-drain layer is located within the first high-potential line.

5. The display panel according to claim 4, wherein the first source-drain layer includes the first control signal line and a second control signal line extending in the first direction, the first control signal line and the second control signal line being arranged at intervals in the second direction, the second control signal line being connected to a switching gate of the switching transistor;

the compensation grid and the first conductive segment are both arranged between the first control signal line and the second control signal line, the compensation grid extends along the first direction, and the first conductive segment extends along the second direction.

6. The display panel of claim 5, wherein the first control signal line comprises a third sub-portion of the first plate, an orthographic projection of the third sub-portion on the second source-drain layer being located within the first high potential line.

7. The display panel according to claim 6, wherein the first source-drain layer further includes a fourth sub-portion of the first electrode plate extending in the second direction, one end of the fourth sub-portion being electrically connected to the first control signal line, the other end of the fourth sub-portion being electrically connected to the second sub-portion;

And the orthographic projection of the fourth sub-part on the second source-drain electrode layer is positioned in the first high-potential line.

8. The display panel of claim 1, wherein the first high-potential line includes a first sub-board and a second sub-board arranged along the second direction, an orthographic projection of the driving gate on the first high-potential line is located in the first sub-board, and an orthographic projection of the first plate on the first high-potential line is located in the second sub-board;

wherein, in the second direction, the width of the second sub-board is larger than the width of the first sub-board.

9. The display panel according to any one of claims 1 to 8, wherein the pixel driving circuit further comprises a storage capacitor including a third electrode plate and a fourth electrode plate, the third electrode plate being connected to the third node, the fourth electrode plate being connected to the first high potential line;

the capacitance value of the first capacitor is smaller than that of the storage capacitor.

10. The display panel of claim 9, wherein the pixel driving circuit further comprises:

a first reset transistor, a first electrode of which is connected to a first reset signal line, and a second electrode of which is connected to the third node;

A second reset transistor, a first electrode of which is connected to a second reset signal line, and a second electrode of which is connected to an anode of the light emitting device;

a third reset transistor, a first electrode of which is connected to a third reset signal line, and a second electrode of which is connected to the first node;

a first electrode of the first light-emitting transistor is connected to the first high potential line, a second electrode of the first light-emitting transistor is connected to the first node, and a gate of the first light-emitting transistor is connected to a light-emitting signal line;

the first electrode of the second light-emitting transistor is connected to the second node, the second electrode of the second light-emitting transistor is connected to the anode of the light-emitting device, and the grid electrode of the second light-emitting transistor is connected to the light-emitting signal line;

the boost capacitor comprises a fifth polar plate and a sixth polar plate, the fifth polar plate is connected with the third node, and the sixth polar plate is connected with the second control signal line;

the capacitance value of the boost capacitor is smaller than that of the storage capacitor.

11. A display device comprising a display panel according to any one of claims 1 to 10.