CN117850520A

CN117850520A - Electronic device with voltage linear regulator and method of operating the same

Info

Publication number: CN117850520A
Application number: CN202311251226.4A
Authority: CN
Inventors: A·庞斯
Original assignee: STMicroelectronics Alps SAS
Current assignee: STMicroelectronics Alps SAS
Priority date: 2022-10-05
Filing date: 2023-09-26
Publication date: 2024-04-09

Abstract

The present disclosure relates to an electronic device having a voltage linear regulator and a method of operating the same. The present disclosure relates to an apparatus having: a power supply input terminal that receives a power supply voltage; a switched mode power supply comprising an output at which a supply voltage is generated; and a voltage linear regulator for supplying power to the load, the regulator receiving the supply voltage, the regulator comprising two transistors coupled between the supply input, the output of the power supply, and an output node of the regulator, respectively. The output current delivered to the load is equal to the current through the transistor when the current drawn by the load is below the threshold, and therefore equal to the current through the transistor plus the current through the transistor when the current drawn by the load is above the threshold.

Description

Electronic device with voltage linear regulator and method of operating the same

Cross Reference to Related Applications

The present application claims the benefit of priority from french patent application No.2210179 entitled "Dispositif lectronique" filed 10 at 2022, 10, which is incorporated herein by reference to the maximum extent allowed by law.

Technical Field

The present disclosure relates generally to electronic devices and methods, and more particularly to devices including voltage linear regulators and methods of operating the same.

Background

In electronics, a linear regulator is a voltage regulator based on active components operating in its linear region or passive components (such as zener diodes) operating in its reverse region.

A Low Dropout (LDO) voltage regulator is a type of voltage linear regulator that regulates an output voltage even when a supply voltage is near the output voltage.

Disclosure of Invention

One embodiment addresses all or some of the shortcomings of known electronic devices.

One embodiment provides an electronic device comprising:

a first supply input configured to receive a first supply voltage;

a first switched mode power supply comprising a first output, the first switched mode power supply being configured to generate a second supply voltage at the first output; and

a voltage linear regulator configured to supply power to a load included in a device, the regulator configured to receive first and second supply voltages, the regulator comprising:

A first transistor coupled between the first supply input and an output node of the regulator; and

a second transistor coupled between the output of the first switch mode power supply and an output node of the regulator,

the regulator is configured such that a first output current delivered to the load by the output node of the regulator is equal to a third current flowing through the second transistor when a current drawn by the load is below a threshold, and such that the first output current is equal to a sum of a fourth current flowing through the first transistor and the third current flowing through the second transistor when the current is above the threshold, the fourth current being non-zero.

Another embodiment provides a method for controlling an electronic device, the electronic device comprising:

a first power supply input terminal receiving a first power supply voltage;

a first switched mode power supply comprising a first output, the first switched mode power supply generating a second supply voltage at the first output; and

a voltage linear regulator for supplying power to a load included in a device, the regulator receiving first and second supply voltages, the regulator comprising:

when the current drawn by the load is below the threshold, the first output current delivered to the load by the output node of the regulator is equal to the third current flowing through the second transistor, and when the current is above the threshold, the first output current is equal to the sum of the fourth current flowing through the first transistor and the third current flowing through the second transistor, the fourth current being non-zero.

According to an embodiment, the regulator is configured such that when the current drawn by the load is above the threshold, the larger the current drawn, the larger the fourth current flowing through the first transistor.

According to an embodiment, a regulator includes:

an error amplifier configured to receive as inputs the set point voltage and a voltage representative of an output voltage of the regulator, and configured to generate an error voltage;

a voltage-to-current converter comprising an input configured to receive the error voltage and generate a fifth current at a second output of the converter and a sixth current at a third output of the converter; and

a first gate drive circuit driving the first transistor, and a second gate drive circuit driving the second transistor, the converter being configured to deliver a fifth current to the first drive circuit and a sixth current to the second drive circuit.

According to an embodiment, the regulator comprises a voltage dividing bridge, an input of which is coupled to the output node of the regulator, and an output of which is coupled to the input of the amplifier in such a way that a voltage representative of the output voltage is delivered.

According to an embodiment, the converter comprises a third transistor coupled between the first node and a node for applying the reference voltage, the third transistor being configured to be controlled by the error voltage, the converter comprising a fourth transistor coupling the first node with the second output terminal and at least one fifth transistor coupling the first node with the third output terminal.

According to an embodiment, the first node and the third output are coupled via a set of at least two fifth transistors connected in parallel.

According to an embodiment, the second gate drive circuit comprises a sixth transistor diode coupled between the second output of the converter and the output of the first switched-mode power supply, the drive terminal of the sixth transistor being coupled to the output of the second drive circuit.

According to an embodiment, the second driving circuit includes:

a seventh transistor diode coupled between an input configured to receive the setpoint current and an output of the first switch mode power supply; and

An eighth transistor coupled between the second output terminal of the converter and the output terminal of the first switch mode power supply, the drive terminal of the eighth transistor being coupled with the drive terminal of the seventh transistor.

According to an embodiment, the first gate drive circuit comprises a diode connected ninth transistor, the ninth transistor and the resistor being coupled between the first output of the converter and the first input of the device, the drive terminal of the ninth transistor being coupled to the output of the first drive circuit.

According to an embodiment, a first gate driving circuit includes:

a tenth transistor diode connected between the input terminal configured to receive the set point current and the first input terminal of the device, and

an eleventh transistor coupled between the first output of the converter and the first input of the device, the drive terminal of the tenth transistor being coupled to the drive terminal of the eleventh transistor.

According to an embodiment, a first driving circuit includes:

a twelfth transistor coupled between the first output of the converter and the first input of the device;

a first switch coupled between the drive terminal of the twelfth transistor and an input configured to receive the setpoint current; and

A second switch is coupled between the drive terminal of the twelfth transistor and the first input of the device.

According to an embodiment, the device comprises at least one second switched-mode power supply, and for each second switched-mode power supply comprises a second transistor coupled between the output of the corresponding second switched-mode power supply and the output node, the regulator being configured such that the current flowing through only one of the second transistors at a time is non-zero.

Drawings

The foregoing features and advantages and other embodiments will be described in detail in the following description of particular embodiments, given by way of illustration and not limitation, with reference to the accompanying drawings, in which:

FIG. 1 illustrates an embodiment of an electronic device including a voltage linear regulator;

FIG. 2 illustrates an embodiment of a voltage linear regulator;

FIG. 3 illustrates a portion of the embodiment of FIG. 2 in more detail;

FIG. 4 illustrates another portion of the embodiment of FIG. 2 in more detail; and

fig. 5 illustrates another portion of the embodiment of fig. 2 in more detail.

Detailed Description

Like features are denoted by like reference numerals throughout the various figures. In particular, structural and/or functional features common between the various embodiments may have the same reference numerals and may be provided with exactly the same structural, dimensional, and material characteristics.

For clarity, only the operations and elements useful for understanding the embodiments described herein are illustrated and described in detail.

Unless otherwise indicated, when two elements are referred to as being connected together, this means that there is no direct connection of any intermediate elements other than conductors, and when two elements are referred to as being coupled together, this means that the two elements may be connected or they may be coupled via one or more other elements.

In the following disclosure, unless otherwise indicated, when absolute positional qualifiers (such as the terms "front", "rear", "top", "bottom", "left", "right", etc.) or relative positional qualifiers (such as the terms "above", "below", "higher", "lower", etc.) or orientation qualifiers (such as "horizontal", "vertical", etc.) are referred to, reference is made to the orientation shown in the figures.

Unless otherwise indicated, the expressions "about", "approximately", "substantially" and "about" mean within 10%, and preferably within 5%.

Fig. 1 illustrates an embodiment of an electronic device 10 that includes a voltage linear regulator 12. The voltage regulator 12 is a low dropout voltage regulator or LDO regulator.

The regulator 12 is configured to energize a load 14. The load 14 is, for example, an analog circuit. The load 14 is, for example, a logic circuit. The load 14 is an analog circuit that controls a Switched Mode Power Supply (SMPS), for example.

Regulator 12 includes an output terminal at which an output voltage VOUT is generated. The voltage VOUT is the supply voltage for the circuit 14. The output is coupled to (preferably connected to) a supply input of the circuit 14.

The device 10 may operate in a low power mode, for example. To ensure low power, regulator 12 may be powered by at least two voltage sources, at least one of which has a value less than the supply voltage of device 10. The voltage sources deliver different supply voltages. Regulator 12 generates an output voltage VOUT from one of the supply voltages. The regulator generates a current IOUT at the output.

In the example of fig. 1, regulator 12 is coupled to three power supplies. The regulator 12 may be powered by one or more of these voltage sources. Depending on the load 14 and on the power used by the load 14, the supply voltage of the regulator may come from one of these sources, or from several of these sources.

Regulator 12 is powered, for example, by a supply voltage VDD of device 10. The voltage VDD is for example higher than 3V, for example equal to 5V. In other words, regulator 12 includes a supply input coupled to node 16 for applying voltage VDD (preferably connected to node 16). Thus, the regulator receives the current IBAT at the input.

The regulator 12 is powered, for example, by at least one voltage generated by a switched mode power supply. In the example of fig. 1, the device comprises two switched mode power supplies 18 and 20. Thus, each of the power sources 18 and 20 includes an output coupled to the supply input of the regulator 12 (preferably connected to the supply input of the regulator 12). For example, the power supplies 18 and 20 are buck (low-converting) power supplies (buck).

The power supply 18 generates a supply voltage VBUCK at an output coupled to the regulator 12 (preferably connected to the regulator 12) ₁ . Regulator 12 thus receives voltage VBUCK at the supply input ₁ . Similarly, the power supply 18 generates a current IBUCK at the output ₁ . The regulator 12 thus receives a current IBUCK at the supply input ₁ . Similarly, the power supply 20 generates a supply voltage VBUCK at an output coupled to the regulator 12 (preferably connected to the regulator 12) ₂ . Regulator 12 thus receives voltage VBUCK at the supply input ₂ . Similarly, the power supply 20 generates a current IBUCK at the output ₂ . The regulator 12 thus receives a current IBUCK at the supply input ₂ . Voltage VBUCK ₁ And VBUCK ₂ For example below the supply voltage VDD, for example below 3.3V.

The power sources 18 and 20 are preferably different. The power supplies 18 and 20 are, for example, configured to supply different ranges of voltages or currents.

The device 10 is preferably configured such that only one of the power sources 18 and 20 may be active at the same time. In other words, if regulator 12 is powered by power supply 18, then the regulator is not powered by power supply 20. Similarly, if regulator 12 is powered by power supply 20, then the regulator is not powered by power supply 18. Thus, the device 10 is configured such that the regulator 12 does not receive the non-zero current IBUCK at the same time ₁ And IBUCK ₂ 。

The device 10 is configured such that the current IOUT is equal to the sum of the current IBAT and the current IBUCK, which are dependent on whether the power source 18 or 20 is powering the regulator ₁ Or current IBUCK ₂ Corresponding to the above.

The current IBAT is configured to be determined by the following equation: ibat=β×ibuck-IOS, IOS is a constant value, and β is, for example, a variable that depends, for example, on the current used by the load. Preferably, the larger the current requested by the load, the higher the value β.

During operation of the regulator, for example in a low power mode, when the value β is such that the value of the β -IBUCK term is lower than the value of the constant IOS, the value of the current IBAT is zero and the value of the current IBAT cannot be negative. The current IOUT is therefore equal to the current IBUCK.

During operation of the regulator, for example in a low power mode, when the value β is such that the value of the β -IBUCK term is higher than the value of the constant IOS, the value of the current IBAT is non-zero. Thus, the current IOUT depends on the values of the current IBAT and the current IBUCK. The value VOUT depends on the values of the voltage VDD and the voltage VBUCK. Thus, the regulator is powered by the supply voltage VDD and the power supply 18 or 20 delivering the voltage VBUCK.

Thus, when the current used by the load is below the threshold, the regulator is powered by the switch mode power supply, and when the current used by the load is above the threshold, the regulator is powered by the switch mode power supply and by the supply voltage source VDD. Preferably, the larger the current used by the load, the larger the portion of current IOUT that is made up of current IBAT.

Fig. 2 illustrates an embodiment of the voltage linear regulator 12.

Regulator 12 includes an error amplifier 22. The amplifier 22 is, for example, an operational amplifier. Amplifier 22 includes a first input, such as a positive input (+) at which a set point voltage VREF and a current IREF are delivered. Thus, the first input is coupled to (preferably connected to) a node for applying the voltage VREF. The amplifier 22 includes a second input, e.g., a negative input (-), at which the loop voltage VFB is applied. The loop voltage depends on, e.g., is proportional to, the output voltage VOUT.

The regulator 12 includes a voltage-to-current converter (V-I converter) 24. The converter 24 comprises an input coupled to the output of the amplifier 22, preferably connected to the output of the amplifier 22. The converter 24 includes at least two outputs, each delivering a current representative of the voltage received as input by the converter 24.

Regulator 12 includes gate drive circuits 26, 28, 30. Regulator 12 includes as many gate drive circuits as there are power supplies for regulator 12. In other words, in the example of fig. 1, regulator 12 includes a gate drive circuit 30 associated with a source of voltage VDD and gate drive circuits 26 and 28 associated with power supplies 18 and 20, respectively.

The drive circuits 26, 28, and 30 are configured to each receive the current generated by the converter 24. Thus, each circuit 26, 28, 30 includes an input coupled to the output of the converter 24 (preferably connected to the output of the converter 24).

Preferably, the converter 24 is configured such that the current supplied to the gate drive circuits 26 and 28 (i.e., the gate drive circuits associated with the switch mode power supplies 18 and 20) is n times higher than the current supplied to the gate drive circuit 30 (i.e., the drive circuit associated with the source of the supply voltage VDD). The value n is preferably an integer value, e.g. a positive number, e.g. greater than two.

Each gate drive circuit is configured to receive a supply voltage associated therewith. Thus, circuits 26 and 28 respectively receive voltage VBUCK ₁ And VBUCK ₂ And circuit 30 receives voltage VDD. In other words, the circuit 26 includes and is used to apply the voltage VBUCK ₁ Is coupled to (preferably connected to) a power supply input of a node (e.g., an output of power supply 18) of the plurality of nodes. The circuit 28 includes and is used to apply a voltage VBUCK ₂ Is coupled (preferably connected) to a power supply input of a node (e.g., an output of power supply 20) of the node. The circuit 30 comprises a supply input coupled to (preferably connected to) a node for applying a voltage VDD.

Each gate drive circuit 26, 28, 30 generates a drive voltage for the gate of the transistor. Circuit 26 generates the gate of transistor 32Driving voltage VGBUCK ₁ . Circuit 28 generates a gate drive voltage VGBUCK for transistor 34 ₂ . The circuit 30 generates a gate drive voltage VGAT of the transistor 36.

Transistor 32 is connected in series with transistor 38 for applying voltage VBUCK ₁ And output node 40, the output voltage VOUT of regulator 12 is generated at output node 40. Transistor 34 is connected in series with transistor 42 for applying voltage VBUCK ₂ And output node 40. Transistor 36 is connected between a node for applying a voltage VDD and an output node 40.

The transistors 32, 34, 36, 38, 42 are, for example, insulated gate field effect transistors (MOSFETs). For example, transistors 32, 34, 36, 38, 42 are P-channel transistors.

One conductive terminal (e.g., source) of transistor 32 and a voltage VBUCK for application ₁ Preferably connected to the node, and the other conductive terminal (e.g., drain) of transistor 32 is coupled to node 44, preferably connected to node 44. One conductive terminal (e.g., source) of transistor 38 is coupled to node 40, preferably connected to node 40, and the other conductive terminal (e.g., drain) of transistor 38 is coupled to node 44, preferably connected to node 44. The body of the transistor 32 is for example connected to a voltage VBUCK ₁ Is preferably connected to the node. The body of transistor 38 is coupled, for example, to node 40, preferably connected to node 40.

One conductive terminal (e.g., source) of transistor 34 and a voltage VBUCK for application ₂ Preferably connected to the node, and the other conductive terminal (e.g., drain) of transistor 34 is coupled to node 46, preferably connected to node 46. One conductive terminal (e.g., source) of transistor 42 is coupled to node 40, preferably connected to node 40, and the other conductive terminal (e.g., drain) of transistor 42 is coupled to node 44, preferably connected to node 44. The body of the transistor 34 is for example connected to a voltage VBUCK ₂ Is preferably connected to the node. The body of transistor 42 is coupled, for example, to node 40, preferably connected to node 40.

One conductive terminal (e.g., source) of transistor 36 is coupled to, preferably connected to, a node for applying voltage VDD, and the other conductive terminal (e.g., drain) of transistor 36 is coupled to, preferably connected to, node 40.

The current flowing through transistor 36 (i.e., the current reaching node 40 from the node for applying voltage VDD) is current IBAT. The current flowing through transistor 34 and transistor 42 (i.e., from the voltage VBUCK for application ₂ Current from node 40) is current IBUCK ₂ . The current flowing through transistor 32 and transistor 44 (i.e., from the voltage VBUCK for application ₁ Current from node 40) is current IBUCK ₁ 。

The output current IOUT (i.e., the current delivered at the output of regulator 12) is related to the current IBAT, IBUCK ₁ And IBUCK ₂ The sum corresponds to the current IBUCK ₁ And IBUCK ₂ And cannot be non-zero at the same time.

Regulator 12 includes control circuitry not shown. The control circuit is configured to generate control voltages for transistors 38 and 42.

Regulator 12 includes, for example, a capacitor 48 coupled between node 40 and a node (e.g., ground) for applying a reference voltage GND. In other words, one terminal of the capacitor 48 is coupled with the node 40, preferably connected to the node 40, and the other terminal of the capacitor 48 is coupled with the node for applying the voltage GND, preferably connected to the node.

The regulator includes two resistors 50 and 52. Resistors 50 and 52 form a voltage divider bridge that generates voltage VFB. Resistors 50 and 52 are connected in series between node 40 and the node for applying voltage GND. One terminal of resistor 50 is coupled to node 40, preferably to node 40, and the other terminal of resistor 50 is coupled to node 54, preferably to node 54, generating voltage VFB at node 54. One terminal of resistor 52 is coupled to node 54, preferably to node 54, and the other terminal of resistor 52 is coupled to, preferably to, the node for applying voltage GND. Node 54 is coupled to a second input of amplifier 22 and is preferably connected to a second input of amplifier 22. Thus, node 40 corresponds to the input node of the voltage divider bridge and node 54 corresponds to the output node of the voltage divider bridge.

Fig. 3 illustrates a portion of the embodiment of fig. 2 in more detail. More precisely, fig. 3 illustrates an embodiment of the V-I converter 24 of fig. 2.

The converter 24 includes an input 56 coupled to the output of the amplifier 22 (preferably connected to the output of the amplifier 22).

The converter includes a transistor 58. Transistor 58 is, for example, a MOSFET transistor, such as an N-channel transistor. Transistor 58 is controlled by the input voltage (i.e., the voltage delivered by amplifier 22 at node 56). The drive terminal of transistor 58 is coupled to node 56, preferably connected to node 56.

The converter comprises a resistor 60. Between the node 62 and the node for applying the reference voltage GND, a resistor 60 is connected in series to the transistor 58. In other words, one conductive terminal (e.g., drain) of transistor 58 is coupled to node 62, preferably connected to node 62, and the other conductive terminal (e.g., source) of transistor 58 is coupled to node 64, preferably connected to node 64. Current IG flows through transistor 58 and resistor 60.

Node 62 is coupled to an output node 66 of converter 24. Converter 24 delivers current IMBAT via output 66. The current IMBAT is a current supplied to the driving circuit 30 of fig. 2.

Converter 24 includes a transistor 68 and a transistor 70. Transistors 68 and 70 are preferably MOSFET transistors, such as N-channel transistors. Transistors 68 and 70 are connected in series between node 62 and output 66. In other words, one conductive terminal (e.g., drain) of transistor 68 is coupled to output 66, preferably to output 66, and the other conductive terminal (e.g., source) of transistor 68 is coupled to node 72, preferably to node 72. One conductive terminal (e.g., drain) of transistor 70 is coupled to node 72, preferably connected to node 72, and the other conductive terminal (e.g., source) of transistor 70 is coupled to node 62, preferably connected to node 62.

Node 62 and the output node of converter 2474 are coupled. Converter 24 delivers current IMBUCK via output 74 ₁ . Current imBUCK ₁ Is the current supplied to the drive circuit 26 of fig. 2.

Converter 24 includes a transistor 76 and a set 78 of transistors. The transistors 76 and 78 are, for example, MOSFET transistors, such as N-channel transistors. The set 78 of transistors includes n transistors connected in parallel. In other words, the drains of the transistors of the set 78 are coupled to each other, preferably connected to each other, and the sources of the transistors of the set 78 are coupled to each other, preferably connected to each other. In addition, the drive terminals of the transistors of the set 78 are coupled to each other, preferably connected to each other.

Transistors 76 and 78 are connected in series between node 62 and output 74. In other words, one conductive terminal (e.g., drain) of transistor 76 is coupled to output 74, preferably to output 74, and the other conductive terminal (e.g., source) of transistor 76 is coupled to node 80, preferably to node 80. One conductive terminal of set 78 (e.g., the drain, i.e., the drain of the transistor of set 78) is coupled to node 80, preferably connected to node 80, and the other conductive terminal of set 78 (e.g., source 78) is coupled to node 62, preferably connected to node 62.

Node 62 is coupled to output node 82 of converter 24. Converter 24 delivers a current IMBUCK via output 82 ₂ . Current imBUCK ₂ Is the current supplied to the drive circuit 28 of fig. 2.

Converter 24 includes a transistor 84 and a set of transistors 86. The transistors 84 and 86 are, for example, MOSFET transistors, such as N-channel transistors. The set 86 of transistors includes several transistors, preferably as many as the set 78, preferably n transistors, connected in parallel. In other words, the drains of the transistors of set 86 are coupled to each other, preferably connected to each other, and the sources of the transistors of set 86 are coupled to each other, preferably connected to each other. In addition, the drive terminals of the transistors of set 86 are coupled to each other, preferably connected to each other.

Transistors 84 and collection 86 are connected in series between node 62 and output 82. In other words, one conductive terminal (e.g., source) of transistor 84 is coupled to output 82, preferably to output 82, and the other conductive terminal (e.g., drain) of transistor 84 is coupled to node 88, preferably to node 88. One conductive terminal of set 86 (e.g., the source, i.e., the source of the transistor of set 86) is coupled to node 88, preferably connected to node 88, and the other conductive terminal of set 86 (e.g., the drain, i.e., the drain of the transistor of set 86) is coupled to node 62, preferably connected to node 62.

The drive terminals of transistors 68, 76 and 84 are coupled to each other, preferably connected to each other. Transistors 68, 76, and 84 are controlled by voltage VCAS. The voltage VCAS is a cascode voltage configured such that the source voltages of transistors 68, 76, and 84 are identical.

Transistor 70 and sets 78 and 86 are controlled by a voltage generated by a control circuit, not shown, of regulator 12. During operation of converter 24, the drive voltage of transistor 70 causes transistor 70 to turn on, e.g., equal to voltage VDD. During operation of converter 24, the drive voltage of the set 78 or 86 corresponding to the switch-mode power supply supplying power to regulator 12 causes the set to turn on, e.g., equal to voltage VDD. The drive voltage of the other set is such that the set is turned off, for example substantially equal to 0V.

Preferably, the transistors of the set 78 are identical to each other. Preferably, the transistors of the set 86 are identical to each other. Preferably, the transistors of set 78 are identical to the transistors of set 86. Preferably, transistor 70 is identical to the transistors of sets 78 and 86.

Thus, the current IMBUCK ₁ And IMBUCK ₂ Is n times higher than the current IBAT. The control voltages of sets 78 and 86 cause a current imBUCK ₁ And IMBUCK ₂ And cannot be non-zero during the same period of operation.

During operation of device 10, current IG is equal to current IMBAT and current IMBUCK ₁ And IMBUCK ₂ The sum of the currents IMBUCK ₁ And IMBUCK ₂ One of which is zero. Thus, the current IMBUCK ₁ And IMBUCK ₂ Wherein the non-zero current is equal to n/(n+1) IG and the current IMBAT is equal to 1/(n+1)IG。

Fig. 4 illustrates another portion of the embodiment of fig. 2 in more detail. More precisely, fig. 4 illustrates an embodiment of the circuit 89. Circuit 89 is coupled to circuits 26 and 28 (i.e., the gate drive circuits of transistors 32 and 34, in other words, to supply voltage VBUCK ₁ And VBUCK ₂ Associated gate drive circuitry). Regulator 12 thus includes two circuits 89. More generally, regulator 12 includes as much circuitry 89 as possible, for example, of the supply voltage from the switch mode power supply.

The circuit 89 includes an input 90, a supply voltage VBUCK is applied at the input 90, the supply voltage VBUCK and the supply voltage VBUCK corresponding to the circuit 26 or 28, depending on whether the circuit 89 corresponds to the circuit 26 or 28 ₁ Or VBUCK ₂ Corresponding to the above. The circuit 89 includes an input 92, a current imBUCK being supplied at the input 92, the current imBUCK being equal to the current imBUCK ₁ Or current IMBUCK ₂ Corresponding to the above. In other words, input 92 is coupled to, and preferably connected to, the output of circuit 24 associated with supply voltage VBUCK. The circuit 89 includes an input 94, and a set point current IREF is supplied at the input 94. The current IREF is generated by, for example, a control circuit, not shown, described with respect to fig. 2. The current IREF is approximately constant, for example, during operation of the circuit 89. The circuit 89 includes an output 96, a voltage VGBUCK is generated at the output 96, the voltage VGBUCK and the voltage VGBUCK ₁ Or voltage VGBUCK ₂ Corresponding to the above.

Circuit 89 includes a transistor 98. Transistor 98 is, for example, a MOSFET transistor, such as a P-channel transistor. A transistor 98 is coupled between input 90 and input 94. In other words, one conductive terminal (e.g., drain) of transistor 98 is coupled to input 94, preferably to input 94, and the other conductive terminal (e.g., source) of transistor 98 is coupled to input 90, preferably to input 90. The drive terminal of transistor 98 is coupled to node 100, preferably connected to node 100. The transistor 98 is diode-connected, for example. Node 100 is coupled to input 94, for example, and is preferably connected to input 94.

The circuit 89 includes a transistor 102. Transistor 102 is, for example, a MOSFET transistor, such as a P-channel transistor. Transistor 102 is coupled between input 90 and input 92. In other words, one conductive terminal (e.g., drain) of transistor 102 is coupled to input 92, preferably to input 92, and the other conductive terminal (e.g., source) of transistor 102 is coupled to input 90, preferably to input 90. The drive terminal of transistor 102 is coupled to node 100, preferably connected to node 100.

Circuit 89 includes a transistor 104. Transistor 104 is, for example, a MOSFET transistor, such as a P-channel transistor. Transistor 104 is coupled between input 90 and input 92. Transistor 104 is coupled in parallel to transistor 102. In other words, one conductive terminal (e.g., drain) of transistor 104 is coupled to input 92, preferably to input 92, and the other conductive terminal (e.g., source) of transistor 104 is coupled to input 90, preferably to input 90. The drive terminal of transistor 104 is coupled to input 96 and is preferably connected to input 96.

Preferably, the surface area of transistor 32 or 34 corresponding to circuit 89 is equal to m times the surface area of transistor 104, m being a constant value, preferably a positive integer value.

The current IBUCK is equal to a times the current IC flowing through transistor 104. When the transistor 32 or 34 is in saturation, the value α is equal to m.

Transistors 98 and 102 are preferably identical. Thus, current imBUCK is equal to the sum of current IC and current IREF.

Fig. 5 illustrates another portion of the embodiment of fig. 2 in more detail. More precisely, fig. 5 illustrates an embodiment of the circuit 30 (i.e. the gate drive circuit of the transistor 36, in other words, the gate drive circuit associated with the supply voltage VDD).

The circuit 30 includes an input 106, and a supply voltage VDD is applied at the input 106. The circuit 30 includes an input 108, with a current IMBAT supplied at the input 108. In other words, the input 108 is coupled to, and preferably connected to, the output of the circuit 24 associated with the supply voltage VDD. Circuit 30 includes an input 110, with a set point current IREF supplied at input 110. The current IREF is generated by, for example, a control circuit, not shown, described with respect to fig. 2. The current IREF is approximately constant, for example, during operation of the circuit 30. The circuit 30 includes an output 112, and a voltage VGBAT is generated at the output 112.

The circuit 30 includes a transistor 114. Transistor 114 is, for example, a MOSFET transistor, such as a P-channel transistor. A transistor 114 is coupled between input 106 and input 110. In other words, one conductive terminal (e.g., drain) of transistor 114 is coupled to input 110, preferably to input 110, and the other conductive terminal (e.g., source) of transistor 114 is coupled to input 106, preferably to input 106. The drive terminal of transistor 114 is coupled to node 116, preferably connected to node 116. The transistor 114 is diode-connected, for example. Node 116 is coupled to input 110, for example, and is preferably connected to input 110.

The circuit 30 includes a transistor 118. Transistor 118 is, for example, a MOSFET transistor, such as a P-channel transistor. Transistor 118 is coupled between input 106 and input 108. In other words, one conductive terminal (e.g., drain) of transistor 118 is coupled to input 108, preferably to input 108, and the other conductive terminal (e.g., source) of transistor 118 is coupled to input 106, preferably to input 106. The drive terminal of transistor 118 is coupled to node 116 and is preferably connected to node 116.

Circuit 30 includes a transistor 120. Transistor 120 is, for example, a MOSFET transistor, such as a P-channel transistor. Transistor 120 is coupled between input 106 and input 108. Transistor 120 is connected in parallel with transistor 118. In other words, one conductive terminal (e.g., drain) of transistor 120 is coupled to input 108, preferably to input 108, and the other conductive terminal (e.g., source) of transistor 120 is coupled to input 106, preferably to input 106. The drive terminal of transistor 120 is coupled to input 110 via switch 122. In addition, the drive terminal of transistor 120 is coupled to input 106 via switch 124. In other words, one terminal of switch 122 is coupled to the drive terminal of transistor 120, preferably to the drive terminal of transistor 120, and the other terminal of switch 122 is coupled to node 116, preferably to node 116. Similarly, one terminal of switch 124 is coupled to the drive terminal of transistor 120, preferably to the drive terminal of transistor 120, and the other terminal of switch 124 is coupled to input 106, preferably to input 106. The switches 122 and 124 are controlled, for example, by a control circuit not shown, described with respect to fig. 2.

Circuit 30 includes, for example, a transistor 126 and a resistor 128 connected in series between input 106 and input 108. Transistor 128 is, for example, a MOSFET transistor, such as a P-channel transistor. One terminal of resistor 128 is coupled, for example, to input 106, preferably connected to input 106, and the other terminal of resistor 128 is coupled, for example, to node 130, preferably connected to node 130. One conductive terminal (e.g., source) of transistor 126 is coupled to node 130, preferably connected to node 130, and the other conductive terminal (e.g., drain) of transistor 126 is coupled to input 108, preferably connected to input 108. The drive terminal of transistor 126 is coupled to output 112, preferably to output 112, and a voltage VGBAT is applied at output 112. Output 112 is further coupled to input 108 (preferably connected to input 108) such that transistor 126 is diode connected.

Preferably, the surface area of transistor 36 is equal to m times the surface area of transistor 126. Transistor 36 is always in saturation. Thus, current IBAT is equal to m times the value of current ICB, which is the current flowing through transistor 126. In addition, current IMBAT is equal to the sum of current ICB and p times current IREF, p being a constant value defined by circuit 24.

Thus, the current IBAT is configured to be determined by the following equation: ibat=β×ibuck-IOS, β being equal toAnd IOS is equal to->

When the load uses a low current, the current IOUT is therefore equal to the current IBUCK, and the IBAT portion of the current IOUT is zero.

When the voltage drop is high, i.e. when the voltage difference between VBUCK and the regulated voltage is high, the value α becomes equal to the value m and the current IOUT is equal to the sum of the current IBAT and the current IBUCK, the current IBAT is non-zero and the current IBUCK is equal to n times the current IBAT. Thus, the current IOUT is mostly delivered by a switched mode power supply that generates IBUCK.

As the voltage drop decreases, the transistor 32 or 34 corresponding to the switch mode power supply generating the non-zero current enters the triode region. The value α becomes smaller than the value m. Thus, the current IBUCK becomes less than n times the current IBAT.

The more the voltage drop decreases, the more transistors enter the transistor region and the value α becomes increasingly lower than the value m. Thus, the ratio of the value of the current IBUCK to the value of the current IBAT decreases until it becomes less than 1. The current IBUCK becomes smaller than the current IBAT. Thus, a majority of current IOUT comes from current IBAT.

Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of the embodiments may be combined and that other variations will readily occur to those skilled in the art. In particular, while the described embodiments include two switch mode power supplies, it should be understood that the device may include a single switch mode power supply, or a greater number of switch mode power supplies.

Additionally, although the depicted embodiment includes transistor 70 and sets 78 and 86, transistor 70 may be replaced with a set of parallel-connected (preferably identical) transistors, such as sets 78 and 86. Thus sets 78 and 86 include n times more transistors than set 70.

Finally, based on the functional description provided above, the actual implementation of the embodiments and variants described herein is within the ability of those skilled in the art.

Claims

1. An electronic device, comprising:

a first supply input configured to receive a first supply voltage;

a first switched mode power supply comprising a first output, wherein the first switched mode power supply is configured to generate a second supply voltage at the first output; and

a voltage linear regulator configured to supply power to a load included in a device, the voltage linear regulator configured to receive a first supply voltage and a second supply voltage, the voltage linear regulator comprising:

a first transistor coupled between the first supply input and an output node of the voltage linear regulator; and

a second transistor coupled between an output of the first switch mode power supply and an output node of the voltage linear regulator;

Wherein the voltage linear regulator is configured to:

delivering, by an output node of the voltage linear regulator, a first output current to the load in response to the second current drawn by the load being below a threshold, the first output current being equal to a third current flowing through the second transistor; and

in response to the second current being above the threshold, the first output current is set equal to a sum of a fourth current flowing through the first transistor and a third current flowing through the second transistor, wherein the fourth current is non-zero.

2. The apparatus of claim 1, wherein the voltage linear regulator is further configured to increase the fourth current flowing through the first transistor in accordance with an increase in the current drawn in response to the second current drawn by the load being above a threshold.

3. The apparatus of claim 1, wherein the voltage linear regulator comprises:

an error amplifier configured to receive as inputs the set point voltage and a voltage representative of an output node of the voltage linear regulator and configured to generate an error voltage;

The first gate driving circuit driving the first transistor, and the second gate driving circuit driving the second transistor, the converter being configured to deliver a fifth current to the first gate driving circuit and a sixth current to the second gate driving circuit.

4. The apparatus of claim 3, wherein the voltage linear regulator comprises a voltage divider bridge having an input coupled to an output node of the voltage linear regulator and an output coupled to an input of the amplifier in a manner to deliver a voltage representative of the output node.

5. The apparatus of claim 3, wherein the converter comprises a third transistor coupled between the first node and a node for applying the reference voltage, the third transistor configured to be controlled by the error voltage, the converter comprising a fourth transistor coupling the first node to the second output and at least one fifth transistor coupling the first node to the third output.

6. The apparatus of claim 5, wherein the first node and the third output are coupled via a set of at least two fifth transistors connected in parallel.

7. The apparatus of claim 5, wherein the second gate drive circuit comprises a sixth transistor diode connected between the second output of the converter and the output of the first switch mode power supply, a drive terminal of the sixth transistor coupled to the output of the second gate drive circuit.

8. The apparatus of claim 7, wherein the second gate drive circuit comprises:

a seventh transistor diode connected between an input configured to receive the setpoint current and an output of the first switch mode power supply; and

an eighth transistor coupled between the second output of the converter and the output of the first switch mode power supply, the drive terminal of the eighth transistor being coupled to the drive terminal of the seventh transistor.

9. A device as claimed in claim 3, wherein the first gate drive circuit comprises a diode-connected ninth transistor, the ninth transistor and the resistor being coupled between the first output of the converter and the first supply input of the device, the drive terminal of the ninth transistor being coupled to the output of the first gate drive circuit.

10. The apparatus of claim 9, wherein the first gate drive circuit comprises:

a tenth transistor diode connected between the input configured to receive the set point current and the first power supply input of the device, and

an eleventh transistor coupled between the first output of the converter and the first supply input of the device, the drive terminal of the tenth transistor being coupled to the drive terminal of the eleventh transistor.

11. The apparatus of claim 10, wherein the first gate drive circuit comprises:

a twelfth transistor coupled between the first output of the converter and the first power supply input of the device;

a second switch is coupled between the drive terminal of the twelfth transistor and the first supply input of the device.

12. The device of claim 1, wherein the device comprises at least one second switched-mode power supply, and for each second switched-mode power supply comprises a further second transistor coupled between the output of the corresponding second switched-mode power supply and the output node, the voltage linearity adjuster being configured such that the current flowing through only one of the second transistors at a time is non-zero.

13. A method for controlling an electronic device, the method comprising:

receiving a first supply voltage by a first supply input;

generating, by the first switch mode power supply, a second supply voltage at a first output of the first switch mode power supply;

supplying power to a load included in the device by the voltage linear regulator;

Receiving, by a voltage linear regulator, a first supply voltage and a second supply voltage, the voltage linear regulator including a first transistor coupled between a first supply input and an output node of the voltage linear regulator and a second transistor coupled between a first output of a first switch mode power supply and the output node of the voltage linear regulator; and

delivering, by an output node of the voltage linear regulator, a first output current to the load in response to the second current drawn by the load being below a threshold, the first output current being equal to a third current flowing through the second transistor; or alternatively

In response to the second current being above the threshold, the first output current is set equal to a sum of a fourth current flowing through the first transistor and a third current flowing through the second transistor, the fourth current being non-zero.

14. The method of claim 13, further comprising, responsive to the second current drawn by the load being above a threshold, increasing, by the voltage linear regulator, a fourth current through the first transistor in accordance with an increase in the drawn current.

15. The method of claim 13, further comprising:

receiving as inputs a set point voltage and a voltage representative of an output node of the voltage linear regulator by an error amplifier of the voltage linear regulator;

Generating an error voltage by an error amplifier;

receiving an error voltage from an input of the voltage-to-current converter;

generating a fifth current at a second output of the converter;

generating a sixth current at a third output of the converter;

driving the first transistor by a first gate driving circuit;

driving the second transistor by a second gate driving circuit; and

the fifth current is delivered to the first gate driving circuit by the converter and the sixth current is delivered to the second gate driving circuit.

16. The method of claim 15, further comprising delivering the voltage representative of the output node by an output of a voltage divider bridge of the voltage linear regulator, an input of the voltage divider bridge coupled to the output node of the voltage linear regulator, and an output of the voltage divider bridge coupled to an input of the amplifier.

17. The method of claim 15, further comprising:

coupling the first node with a node for applying a reference voltage by a third transistor of the converter, the third transistor being controlled by an error voltage;

coupling the first node to the second output by a fourth transistor of the converter; and

the first node is coupled to the third output by at least one fifth transistor of the converter.

18. The method of claim 17, further comprising coupling the first node and the third output via a set of at least two fifth transistors connected in parallel.

19. The method of claim 15, further comprising coupling the second output of the converter and the first output of the first switch mode power supply by a sixth transistor connected by a diode of the second gate drive circuit, a drive terminal of the sixth transistor being coupled to the output of the second gate drive circuit.

20. The method of claim 19, further comprising:

a seventh transistor connected by a diode of the second gate drive circuit couples the input terminal receiving the setpoint current and the output terminal of the first switch mode power supply; and

the second output of the converter and the output of the first switch mode power supply are coupled by an eighth transistor of the second gate drive circuit, the drive terminal of the eighth transistor being coupled to the drive terminal of the seventh transistor.

21. The method of claim 15, further comprising coupling a first output of the converter and a first power input of the device by a ninth transistor and a resistor connected by a diode of the first gate drive circuit, a drive terminal of the ninth transistor coupled to an output of the first gate drive circuit.

22. The method of claim 21, further comprising:

a tenth transistor connected by a diode of the first gate drive circuit is coupled to an input configured to receive the setpoint current and to a first supply input of the device; and

the first output of the converter and the first power supply input of the device are coupled by an eleventh transistor of the first gate drive circuit, the drive terminal of the tenth transistor being coupled to the drive terminal of the eleventh transistor.

23. The method of claim 22, further comprising:

coupling a first output of the converter and a first power supply input of the device by a twelfth transistor of the first gate drive circuit;

coupling, by a first switch of a first gate drive circuit, a drive terminal of a twelfth transistor and an input configured to receive the setpoint current; and

the drive terminal of the twelfth transistor and the first supply input of the device are coupled by the second switch of the first gate drive circuit.