CN117833655A

CN117833655A - Current bias circuit for switching converter and switching converter

Info

Publication number: CN117833655A
Application number: CN202311699262.7A
Authority: CN
Inventors: 李露露; 武子建; 于翔
Original assignee: Shengbang Microelectronics Suzhou Co ltd
Current assignee: Shengbang Microelectronics Suzhou Co ltd
Priority date: 2023-12-12
Filing date: 2023-12-12
Publication date: 2024-04-05

Abstract

The invention discloses a current bias circuit for a switching converter and the switching converter. A current bias circuit for providing a bias current to an operational amplifier in a switching converter, comprising: the ramp voltage generation module comprises a capacitor and is used for charging or discharging the capacitor according to the level state of the current-saving mode signal so as to generate a ramp voltage; and the current output module is used for generating a first voltage following the ramp voltage and generating a bias current according to the first voltage, wherein the bias current rises to the set current with a first slope when the current-saving mode signal changes from a high level to a low level, and the bias current falls from the set current with a second slope when the current-saving mode signal changes from the low level to the high level. The bias current of the invention can realize smooth change when the mode of the switching converter is switched, thereby avoiding the fluctuation of the input signal of the error amplifier caused by parasitic coupling and improving the stability of the system.

Description

Current bias circuit for switching converter and switching converter

Technical Field

The present invention relates to the technical field of switching power supplies, and more particularly, to a current bias circuit for a switching converter and a switching converter.

Background

In recent years, with the rise of various battery-powered wearable devices and IoT devices, there is also a further demand for power chips that have higher efficiency and can achieve longer endurance. In wearable equipment, the time that the sensor equipment is in work is less, and the system is more in light load and even no load, so that the efficiency of the equipment under extremely light load is particularly important, and the endurance of the equipment is directly influenced.

DCDC converters are commonly used as power supply devices in such electronic products. The DCDC product has higher conversion efficiency and is controlled by adopting a PWM (Pulse Width Modulation ) control mode. The PWM control mode has the advantages of fixed working frequency, small output voltage ripple, good stability, mature control and the like. However, the power tube in the converter needs to be turned on and off in each switching period, so that the switching loss of the power tube is large, and the overall efficiency of the converter is low in light load or standby, which severely limits the application range of the PWM control mode.

In the prior art, a PFM (Pulse Frequency Modulation ) control method, a PSM (Pulse PSM Modulation, pulse cross period modulation) control method, and the like are generally adopted to prevent the reduction of the operating efficiency of the DCDC converter from heavy load to light load. The essence of the PFM control mode and the PSM control mode is to reduce the substantial switching frequency, thereby improving the light load working efficiency.

Under the PSM control mode, the DCDC converter enters the PSM mode when in light load, and the decision criterion for entering the PSM mode is to control the low setting time of pulse width modulation waves of a DCDC product to be prolonged. After entering PSM mode, the output PWM wave may skip some clock cycles, thereby reducing the switching frequency. The converter operating in the PSM mode has the advantages of high response speed, high efficiency, strong anti-interference capability, good electromagnetic compatibility, strong robustness, etc. under light load, but its performance is degraded under heavy load.

In the prior art, DCDC products with PWM/PSM hybrid operation modes are used in power management techniques for systems and electronics that are widely operated and continuously change between light and heavy loads in order to improve efficiency and circuit performance under light and heavy loads. However, there are still many problems with the current PSM control approach. For example, for a DCDC converter with low quiescent current, when the converter is operated in a light load state, in order to improve efficiency and reduce standby loss, the internal circuit is generally converted into a small current mode, and when the system is switched from a current-saving mode to a normal mode, the operating current of an error amplifier inside the DCDC converter is suddenly changed and then coupled to the input end of the comparator through a parasitic capacitor, so that an output logic of the error amplifier is wrong, and the ripple of the output voltage of the DCDC converter is increased, which has adverse effects on the stability, efficiency, electromagnetic compatibility and the like of a power supply system.

Disclosure of Invention

In view of the foregoing, an object of the present invention is to provide a current bias circuit for a switching converter and a switching converter, which can supply a smoothly varying bias current to an error amplifier at the time of mode switching of the switching converter, can avoid fluctuation of an input voltage of the error amplifier due to parasitic coupling caused by abrupt change of the bias current, and can help maintain the operation of the error amplifier in its optimum operating range, and improve the stability and efficiency of a system.

According to an aspect of the present invention, there is provided a current bias circuit for a switching converter for providing a bias current to an operational amplifier in the switching converter, comprising: the ramp voltage generation module comprises a capacitor and is used for charging or discharging the capacitor according to the level state of the current-saving mode signal so as to generate a ramp voltage; and a current output module for generating a first voltage following the ramp voltage and generating the bias current according to the first voltage, wherein the bias current rises to a set current with a first slope when the current saving mode signal changes from a high level to a low level, and the bias current falls from the set current with a second slope when the current saving mode signal changes from a low level to a high level.

Optionally, the method further comprises: and the feedback clamping module is used for clamping the first voltage to be smaller than/equal to a set bias voltage through negative feedback when the current-saving mode signal is changed from a high level to a low level so that the bias current is equal to the set current.

Optionally, the method further comprises: and the tail current source module is used for providing working current following the bias current for the feedback clamping module according to the first voltage.

Optionally, the ramp voltage generating module further includes: a first current source having a first end connected to a power supply voltage; a first end of the first transistor is connected with a second end of the first current source, and a control end of the first transistor is connected with the current-saving mode signal; a third transistor having a first terminal and a control terminal connected to a second terminal of the first transistor, and a second terminal connected to a first terminal of the capacitor; a second transistor, a first end of which is connected with a first end of the capacitor, and a control end of which is connected with the current-saving mode signal; and a second current source having a first terminal connected to a second terminal of the second transistor and a second terminal connected to the second terminal of the capacitor and ground, wherein the first transistor is adapted to charge the capacitor according to a first current of the first current source when turned on, and the second transistor is adapted to discharge the capacitor according to a second current of the second current source when turned on.

Optionally, the current output module includes: a fourth transistor having a first terminal as an output terminal of the bias current, a control terminal connected to the control terminal and the first terminal of the third transistor; and a first resistor having a first terminal connected to a second terminal of the fourth transistor, and a second terminal connected to ground.

Optionally, the feedback clamp module includes: an input pair, an active load adaptively connected to the input pair, and a source follower transistor, wherein the input pair includes fifth and sixth transistors, first ends of the fifth and sixth transistors are connected to an output of the tail current source module, a control end of the fifth transistor is connected to a second end of the fourth transistor to receive the first voltage, a control end of the sixth transistor is used to receive the bias voltage, the active load includes seventh and eighth transistors, a first end of the seventh transistor is connected to a second end of the fifth transistor, a control end of the seventh transistor, a control end of the eighth transistor, and a first end of the eighth transistor are connected to a second end of the sixth transistor, second ends of the seventh and eighth transistors are connected to ground, the source follower transistor includes a ninth transistor, a first end of the ninth transistor is connected to an output of the tail current source module and a fourth end of the fourth transistor, a fifth end of the seventh transistor is connected to a fifth end of the seventh transistor, and a fifth end of the seventh transistor is connected to a fourth end of the seventh transistor, and a fifth end of the seventh transistor is connected to a node.

Optionally, the tail current source module includes: a tail current unit for generating a second voltage varying with the first voltage and converting the second voltage into a first current; and a current mirror adapted to be connected to the tail current unit, the tail current unit being connected to an input pair of transistors and a source follower transistor in the feedback clamp module through the current mirror, wherein the tail current unit includes a tenth transistor and a second resistor, a control terminal of the tenth transistor being connected to a control terminal of the fourth transistor, a second terminal of the tenth transistor being connected to a first terminal of the second resistor, a second terminal of the second resistor being connected to ground, a first terminal of the tenth transistor being an output terminal of the first current, the current mirror including eleventh to thirteenth transistors, a first terminal of the eleventh to thirteenth transistors being connected to a power supply voltage, a control terminal of the eleventh to thirteenth transistors and a second terminal of the eleventh transistor being connected to the first current, a second terminal of the twelfth transistor being connected to a first terminal of the source follower transistor to output a second current, a first terminal of the thirteenth transistor being connected to a third input of the third pair of transistors.

According to another aspect of the present invention, there is provided a switching converter including: the power circuit adopts at least one switching tube and an inductor to control the transmission of electric energy from an input end to an output end, so that output voltage is generated according to input voltage; an error amplifier for comparing the feedback voltage of the output voltage with a set reference voltage to generate an error signal; a comparator circuit for comparing the error signal with the feedback voltage to generate a pulse width modulated signal; the logic and driving circuit is used for controlling the on and off of at least one switching tube in the power circuit according to the pulse width modulation signal; and the current bias circuit is used for providing bias current for the error amplifier.

Optionally, the switching converter is switchable between a normal mode and a current saving mode, wherein the operational amplifier enters a low current mode when the switching converter is operated in the current saving mode and enters a high current mode when the switching converter is operated in the normal mode.

Optionally, the logic and driving circuit is further configured to compare a time interval between adjacent pulses of the pulse width modulation signal with a set threshold value, and determine a time when the switching converter enters the current saving mode according to a comparison result.

In summary, the current bias circuit for a switching converter according to the embodiments of the present invention includes a ramp voltage generating module and a current output module, where the ramp voltage generating module is configured to charge or discharge a capacitor according to a level state of a current-saving mode signal to generate a ramp voltage, and the current output module follows the ramp voltage to generate a bias current to be provided to an error amplifier, so that a smoothly varying bias current can be provided to the error amplifier when the mode of the switching converter is switched, which not only can avoid fluctuations in an input voltage of the error amplifier due to parasitic coupling caused by abrupt change of the bias current, but also can help to maintain the operation of the error amplifier in an optimal operating range thereof, and improve stability of a system. In addition, the smooth change of the bias current can reduce transient response during mode switching, so that fluctuation of output voltage is avoided, and the noise level of the system is reduced.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1 shows a schematic circuit diagram of a switching converter according to the prior art.

Fig. 2 shows a schematic circuit diagram of an error amplifier for a switching converter according to the prior art.

Fig. 3 shows a schematic circuit diagram of a switching converter according to an embodiment of the invention.

Fig. 4 shows a schematic circuit diagram of a current bias circuit according to an embodiment of the invention.

Fig. 5 shows a waveform comparison diagram of an error amplifier of the related art and an error amplifier of an embodiment of the present invention at the time of mode switching.

Detailed Description

Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

In the description, it should be noted that like reference numerals have been used to denote like parts in other figures as far as possible for these elements. In the following description, when functions and configurations known to those skilled in the art are irrelevant to the basic configuration of the present disclosure, their detailed description will be omitted. The terms described in the specification should be understood as follows.

Advantages and features of the present disclosure and methods of accomplishing the same will be described below by way of embodiments described with reference to the accompanying drawings. This disclosure may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Furthermore, the disclosure is limited only by the scope of the claims.

The shapes, dimensions, ratios, angles, and numbers disclosed in the drawings for describing embodiments of the present disclosure are merely examples, and thus the present disclosure is not limited to the details illustrated. Like numbers refer to like elements throughout. In the following description, a detailed description will be omitted when it is determined that the detailed description of related known functions or constructions will inevitably obscure the gist of the present disclosure.

In the case where the terms "including", "having" and "comprising" described in this specification are used, another part may be added unless "only" is used. Unless otherwise indicated to the contrary, singular terms may include the plural.

In describing the positional relationship, for example, when the positional relationship between two portions is described as such as "on", "above", "under" or "under" unless "only" or "direct" is used, one or more other portions may be disposed between the two portions. In describing the temporal relationship, for example, when the temporal sequence is described as "after", "following after", "next", or "before", a discontinuous case may be included unless "just" or "direct" is used.

It will be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first component could be termed a second component, and, similarly, a second component could be termed a first component, without departing from the scope of the present disclosure.

The term "at least one" should be understood to include any and all combinations of one or more of the corresponding listed items. For example, the meaning of "at least one of the first, second, and third items" means a combination of all items proposed from two or more of the first, second, and third items, as well as the first, second, or third items.

As those skilled in the art will fully appreciate, the features of the various embodiments of the disclosure may be combined or combined, in part or in whole, with one another and may be interoperable and technically driven in various ways with one another. Embodiments of the present disclosure may be performed independently of each other or may be performed together in mutual dependency.

Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

Fig. 1 shows a schematic circuit diagram of a switching converter according to the prior art. The switching converter 100 adopts a Buck topology, and includes a power circuit and a control circuit 110, where the power circuit includes switching transistors S1 and S2 connected in series between an input terminal and a ground terminal, the switching transistor S1 is also referred to as a main switching transistor, the switching transistor S2 is also referred to as a synchronous switching transistor, an inductor Lx is connected between an intermediate node of the switching transistors S1 and S2 and an output terminal, an output capacitor Cout is connected between the output terminal and the ground terminal, a resistor Resr is an equivalent series resistance of the output capacitor Cout, and a load RL is connected in parallel between two ends of the output capacitor Cout.

The input of the switching converter 100 receives an input voltage Vin and the output provides an output voltage Vout. The voltage divider network of resistors Ra and Rb is used to obtain the feedback voltage Vfb of the output voltage Vout.

The control circuit 110 is used to provide switching control signals to the switching transistors S1 and S2. By way of example, the control circuit 110 includes an error amplifier 101, a comparator circuit 102, and a logic and drive circuit 103. The error amplifier 101 is configured to compare a feedback voltage Vfb provided by the feedback resistor network with a reference voltage Vref, and amplify an error therebetween to obtain an error signal Vea. The comparator circuit 102 is configured to compare the error signal Vea with the feedback voltage Vfb, generate a pulse width modulation signal PWM according to the comparison result, and the logic and driving circuit 103 converts the pulse width modulation signal PWM into a switch driving signal to drive the on states of the switching transistors S1 and S2.

For low quiescent current switching converters, when the switching converter is operating in a light load or no load condition, the internal circuitry is typically turned into a low current mode of operation in order to increase light load efficiency and reduce standby losses. When the external load is changed from no load to heavy load, the current-saving mode signal SKIP is turned from high level "1" to low level "0", and the system needs to be switched from the current-saving mode to the normal operation mode.

Fig. 2 shows a schematic circuit diagram of an error amplifier for a switching converter according to the prior art. As shown in fig. 2, the error amplifier 101 of the related art includes a current source Iref and transistors M1 to M4. The transistors M1 and M2 are input to the error amplifier 101, the gate of the transistor M1 is used for receiving the reference voltage Vref, the gate of the transistor M2 is used for receiving the feedback voltage Vfb, and the sources of the transistors M1 and M2 are connected to each other and to the power supply voltage VDD through the current source Iref. Transistors M3 and M4 serve as load cells for the input pair transistors M1 and M2, wherein the gate and drain of transistor M3 are connected to the drain of transistor M1, the drain of transistor M4 is connected to the drain of transistor M2, the gate of transistor M4 is connected to the gate of transistor M3, the sources of transistors M3 and M4 are connected to ground, and the common node of transistors M2 and M4 is used to output the error signal Vea. The current source Iref is used to connect with the sources of the input pair of tubes M1 and M2 to provide the input pair of tubes M1 and M2 with an operating current.

In the error amplifier 101 of the related art, when the current-saving mode signal SKIP is changed from the high level "1" to the low level "0", the output current of the current source Iref will suddenly increase, corresponding to an increase in the pull-up current for the input pair of transistors M1 and M2, so the source terminal voltages VS of the transistors M1 and M2 will also increase, and the increased voltages are then coupled to the input signals Vref and Vfb at the gate terminals of the transistors M1 and M2 through parasitic capacitances Cgs (not shown in the drawing) of both, resulting in an increase in both the signals Vref and Vfb. When the current-saving mode signal SKIP is changed from low level "0" to high level "1", the output current of the current source Iref will become 0, which corresponds to a decrease in the pull-up current for the input pair of transistors M1 and M2, so that the source voltages VS of the transistors M1 and M2 will decrease, and the decreased voltages will couple to the gate terminals through parasitic capacitances of both to cause the input signals Vref and Vfb to decrease, which easily causes an output error of the error amplifier 101.

Fig. 3 shows a schematic circuit diagram of a switching converter according to an embodiment of the invention. As shown in fig. 3, the switching converter 200 includes a power circuit and a control circuit 210. The power circuit is an output circuit of a buck switching regulator of a general synchronous rectification system, which steps down an input voltage Vin applied to an input terminal and supplies an output voltage Vout from the output terminal. The invention is not limited in this regard and the various concepts disclosed herein may be used in connection with any type of DC-DC converter architecture, including Buck-Boost (Buck) converters, boost-Boost (Boost) converters, flyback (Flyback) converters, buck-Boost (Buck-Boost) converters, etc., depending on the topology classification of the power circuit, for example. Furthermore, while complementary PWM control of the high-side switching device and the low-side switching device is utilized in the illustration of the embodiments of the present invention, the concepts described herein can be implemented in power converters that use only a single switching device and/or in power converters that employ more than two pulse width modulations.

As shown in fig. 3, the power circuit includes a switching tube S1 (also referred to as a high-side switching tube), a switching tube S2 (also referred to as a low-side switching tube), and an inductor Lx. The drains of the high-side switching tube S1 and the low-side switching tube S2 are connected to each other, a common end of the two forms a switching node SW, a source of the high-side switching tube S1 is connected to the input voltage Vin, and a source of the low-side switching tube S2 is connected to the ground. The first terminal of the inductor Lx is connected to the switching node SW, and the second terminal is connected to the output terminal of the power circuit. It should be understood that in the present embodiment, the switching transistor S1 is a main power transistor, the switching transistor S2 is a rectifying transistor, the switching transistors S1 and S2 may be any type of field effect transistor, such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), and the switching transistor S1 is, for example, a field effect transistor having a P channel (abbreviated as PMOS transistor), and the switching transistor S2 is, for example, a field effect transistor having an N channel (abbreviated as NMOS transistor). Other types of field effect transistors and/or other types of transistors within the purview of those skilled in the art are also possible without departing from the teachings of the present invention.

The switching converter 200 further comprises an output capacitor Cout arranged between the output terminal of the switching converter 200 and the ground terminal to generate an output voltage Vout across the output capacitor Cout, a resistor Resr being an equivalent series resistance of the output capacitor Cout, and a load RL being connected in parallel between the two terminals of the output capacitor Cout. The voltage divider network of resistors Ra and Rb is used to obtain the feedback voltage VFB of the output voltage Vout.

The control circuit 210 is used to generate a driving signal applied to the gates of the switching transistors S1 and S2, and to control the switching states of the switching transistors S1 and S2 to supply energy to the load. In the present embodiment, the control circuit 210 alternately turns on/off the switching transistors S1 and S2, and performs energy conversion by the inductor Lx, thereby reducing the input voltage Vin, smoothing the reduced voltage by the inductor Lx and the output capacitor Cout, and outputting the smoothed voltage as the output voltage Vout.

In which the control circuit 210 of the switching converter 200 may be integrated into an LSI chip on a semiconductor substrate. In the present embodiment, the switching transistors S1 and S2 may be provided outside the control circuit 210, but may be provided inside the control circuit.

In the present embodiment, the control circuit 210 further includes an error amplifier 201, a comparator circuit 202, a logic and drive circuit 203, and a current bias circuit 204.

Wherein the inverting input of the error amplifier 201 is configured to receive the feedback voltage Vfb, the non-inverting input of the error amplifier 201 is configured to set a reference voltage Vref, and the error amplifier 201 is configured to compare the feedback voltage Vfb with the reference voltage Vref to generate an error signal Vea, the signal Vea representing a difference between the feedback voltage Vfb and the reference voltage Vref.

A non-inverting input of the comparator circuit 202 is arranged to receive the error signal Vea and an inverting input of the comparator circuit 202 is arranged to receive the feedback voltage Vfb, the comparator circuit 202 being arranged to compare the feedback voltage Vfb with the error signal Vea to generate a pulse width modulated signal PWM.

The logic and drive circuit 203 is used to implement the logic control function of the system, which is connected to the output of the comparator circuit 202, the output of the logic and drive circuit 203 being connected to the gates of the high side switch transistor S1 and the low side switch S2, and these transistors being operated so that the power circuit outputs electrical energy to the load. Illustratively, the logic and drive circuit 203 receives the output from the comparator circuit 202 and generates a gate drive signal to drive the gates of the high-side switching tube S1 and the low-side switching tube S2.

Depending on the output of the logic and drive circuit 203, current will flow from the input voltage Vin through the high-side switching tube S1, and through either the inductor Lx (during a portion of the cycle where no power is delivered) or the low-side switching tube S2 (during a portion of the cycle where power is delivered). When the high-side switching tube S1 is turned on (thus during a part of the period in which no power is supplied), the input voltage Vin charges the inductor Lx, and thus the current of the inductor Lx rises; when the low-side switching tube S2 is turned on (thus during a part of the period of delivering electric power), the current stored in the inductor Lx flows to the load, and thus the current of the inductor Lx decreases.

The logic and driving circuit 203 is further configured to detect a time interval between adjacent pulses of the pulse width modulation signal PWM, and switch the current-saving mode signal SKIP from low level "0" to high level "1" when the time interval is greater than a set threshold value, so as to control each circuit including the error amplifier 201 in the system to operate in a low current mode, and reduce static power consumption of the circuit. And the logic and driving circuit 203 is further configured to switch the current-saving mode signal SKIP from a high level "1" to a low level "0" when receiving the active pulse of the pulse width modulation signal PWM again in the current-saving mode, so as to control each circuit including the error amplifier 201 in the system to exit the low current mode.

As described above, when the system is switched between the current saving mode and the normal mode, the conventional error amplifier is susceptible to an output logic error due to abrupt change of the bias current, which in turn increases ripple of the output voltage. To solve this problem, the control circuit 210 according to the embodiment of the present invention further includes a current bias circuit 204, wherein the current bias circuit 204 is configured to provide a bias current Iref to the error amplifier 201 according to the current saving mode signal SKIP, and the current bias circuit 204 may further enable the bias current Iref to smoothly rise or fall according to a set slope when the current saving mode signal SKIP level is switched. As shown in fig. 4, a schematic circuit diagram of a current bias circuit for a switching converter according to an embodiment of the invention is shown. The current bias circuit 204 includes a ramp voltage generation module 241, a current output module 242, a feedback clamp module 243, and a tail current source module 244.

Wherein the ramp voltage generating module 241 includes a capacitor C1, the ramp voltage generating module 241 is configured to perform a charging or discharging operation on the capacitor C1 according to a level state of the current saving mode signal SKIP to generate the ramp voltage Vss. The ramp voltage generating module 241 includes a current source I1, a current source I2, a PMOS transistor M1, an NMOS transistor M2, and an NMOS transistor M3. The first end of the current source I1 is connected to the power supply voltage VDD, the second end of the current source I1 is connected to the source of the PMOS transistor M1, the gate of the PMOS transistor M1 is connected to the current-saving mode signal SKIP, the drain of the PMOS transistor M1 is connected to the gate and drain of the NMOS transistor M3, the source of the NMOS transistor M3 is connected to the first end of the capacitor C1, and the second end of the capacitor C1 is connected to ground. The drain of the NMOS transistor M2 is connected to the first end of the capacitor C1, the gate of the NMOS transistor M2 is connected to the current-saving mode signal SKIP, and the source of the NMOS transistor M2 is connected to ground through the current source I2.

When the switching converter 200 exits the current-saving mode, the current-saving mode signal SKIP is switched from the high level "1" to the low level "0", the PMOS transistor M1 is turned on, the NMOS transistor M2 is turned off, and the current source I1 charges the capacitor C1 through the PMOS transistor M1 and the NMOS transistor M3, so that the smoothly rising ramp voltage Vss is obtained at the first end of the capacitor C1, and the rising slope of the ramp voltage Vss is I1/C1. When the switching converter 200 enters the current-saving mode, the current-saving mode signal SKIP is switched from low level "0" to high level "1", the NMOS transistor M2 is turned on, the PMOS transistor M1 is turned off, the capacitor C1 discharges to the ground through the NMOS transistor M2, the ramp voltage Vss slowly drops, and the falling slope is I2/C1.

In an exemplary embodiment, the rising and falling slopes of the ramp voltage Vss may be set by setting the current magnitudes of the current sources I1 and I2 and the capacitance value of the capacitor C1.

The current output module 242 is configured to generate a first voltage V1 that follows the ramp voltage Vss, and generate the bias current Iref according to the first voltage V1. The current output module 242 includes an NMOS transistor M4 and a resistor R1, where the gate of the NMOS transistor M4 is connected to the gate and the drain of the NMOS transistor M3, the source of the NMOS transistor M4 is connected to the first terminal of the resistor R1, the second terminal of the resistor R1 is connected to ground, and the drain of the NMOS transistor M4 is used as the output terminal of the bias current Iref. When the switching converter 200 exits/enters the current saving mode, the source voltages of the NMOS transistors M3 and M4 are approximately clamped, so the first voltage V1 rises slowly following the ramp voltage Vss, at which time the bias current iref=v1/r1=vss/R1. Since the ramp voltage Vss can smoothly rise/fall when the switching converter 200 exits/enters the current saving mode, the bias current Iref can also smoothly change, the rising slope of the bias current Iref is I1/C1, and the falling slope of the bias current Iref is I2/C2. Therefore, compared with the prior art, the current bias circuit of the embodiment can avoid fluctuation of the input signal of the error amplifier caused by parasitic coupling during mode switching, and improve the stability of the system.

The feedback clamping module 243 is configured to negative feedback clamp the first voltage V1 when the switching converter 200 is out of the current saving mode, such that the first voltage V1 is less than or equal to a preset bias voltage Vbias. The feedback clamp module 243 includes a buffer formed by PMOS transistors M5 and M6 and NMOS transistors M7 and M8, and a source follower transistor formed by PMOS transistor M9, for example. The PMOS transistors M5 and M6 form an input pair of transistors of the buffer, the sources of the PMOS transistors M5 and M6 are connected to the output of the tail current source module 244 to receive a tail current or an operating current, the gate of the PMOS transistor M5 is connected to the source of the NMOS transistor M4 to receive the first voltage V1, and the gate of the PMOS transistor M6 is configured to receive the preset bias voltage Vbias. The NMOS transistors M7 and M8 constitute an active load of the input pair transistors M5 and M6, wherein the drain of the NMOS transistor M7 is connected to the drain of the PMOS transistor M5, the gate of the NMOS transistor M7, the gate of the NMOS transistor M8, and the drain of the NMOS transistor M8 are connected to the drain of the PMOS transistor M6, and the sources of the NMOS transistors M7 and M8 are connected to ground. The gate of the PMOS transistor M9 is connected to the drain of the PMOS transistor M5 and the drain of the NMOS transistor M7, the source of the PMOS transistor M9 is connected to the output of the tail current source module 244, and the drain of the PMOS transistor M9 is connected to ground.

The tail current source module 244 is configured to provide an operating current that varies with the bias current Iref to the feedback clamp module 243. The tail current source module 244 comprises, for example, a tail current unit 2401 and a current mirror adapted for connection, the tail current unit 2401 being adapted for connection via said current mirror to the source of the input pair tube and the source follower transistor in the feedback clamp module 243. In detail, the tail current unit 2401 is configured to generate a second voltage V2 that varies following the first voltage V1, and convert the second voltage V2 into a current I5. In more detail, the tail current unit 2401 includes an NMOS transistor M10 and a resistor R2, the gate of the NMOS transistor M10 is connected to the gate of the NMOS transistor M4, the source of the NMOS transistor M10 is connected to the first terminal of the resistor R2, the second terminal of the resistor R2 is connected to ground, and the drain of the NMOS transistor M10 is used to output the current I5. The current mirror includes PMOS transistors M11, M12, and M13. The sources of the PMOS transistors M11, M12 and M13 are connected to the power supply voltage VDD, the gates of the PMOS transistors M11 to M13 are connected to the drain of the PMOS transistor M11, the drain of the PMOS transistor M11 is connected to the drain of the NMOS transistor M10 as a current input terminal of the current mirror, the drain of the PMOS transistor M12 is connected to the source of the source follower transistor M9 as one current output terminal of the current mirror, and the drain of the PMOS transistor M13 is connected to the sources of the input pair transistors M5 and M6 as the other current output terminal of the current mirror.

Fig. 5 shows a waveform comparison diagram of an error amplifier of the related art and an error amplifier of an embodiment of the present invention at the time of mode switching. Fig. 5 shows waveforms of the current-saving mode signal SKIP, the bias current Iref, and the reference voltage Vref or the feedback voltage Vfb, respectively, wherein a solid line indicates a waveform of the bias current and the reference voltage or the feedback voltage at the time of mode switching in an embodiment of the present invention, and a dotted line indicates a schematic of the bias current and the reference voltage or the feedback voltage at the time of mode switching in the prior art. The principle of the current bias circuit according to the embodiment of the present invention will be described in detail with reference to fig. 5 and 4.

As shown in fig. 5, at time t3, when the system exits the current-saving mode, the current-saving mode signal SKIP changes from high to low, the capacitor C1 in the ramp voltage generating module 241 is charged, and then a slowly rising ramp voltage Vss is generated, the current output module 242 generates a slowly rising bias current Iref following the ramp voltage Vss, and at the same time, the second voltage V2 slowly rises following the first voltage V1 (the first voltage V1 rises following the ramp voltage Vss), and at this time, the current i5=v2/r2=vss/R2. Assuming that the area ratios of the PMOS transistors M11, M12 and M13 are K1 and K2, respectively, the current i3=k1×i5, and the current i4=k2×i5. As the ramp voltage Vss increases, the operating current of the feedback clamp module 243 gradually increases, and when the operating current of the feedback clamp module 243 is greater than the quiescent operating point, the negative feedback effect of buffer increases, thereby clamping the first voltage V1 to a level equal to the bias voltage Vbias at time t4, at which time the bias current Iref no longer changes, i.e., the bias current iref=vbias/R1. Therefore, compared with the scheme in the prior art, when the switching converter exits the current-saving mode, the scheme of the embodiment of the invention can obviously reduce the upward coupling amplitude of the input voltage Vref/Vfb of the error amplifier and improve the stability of the circuit.

At time t1, when the switching converter 200 enters the current-saving mode, the current-saving mode signal SKIP changes from low level to high level, the capacitor C1 in the ramp voltage generating module 241 discharges to ground, and then a slowly decreasing ramp voltage Vss is generated, and the current output module 242 generates a slowly decreasing bias current Iref following the ramp voltage Vss. After a period of time, at time t2, the capacitor C1 discharges, at which time the ramp voltage vss=0, i.e. the bias current iref=0. In addition, since the output current of the tail current source module 244 also varies along with the bias current Iref, the output currents I3 and I4 of the tail current source module 244 also become 0, so that the static power consumption of the circuit in the current saving mode can be reduced. Therefore, compared with the scheme in the prior art, when the switching converter enters the current-saving mode, the embodiment of the invention not only can reduce the downward coupling of the input voltage Vref/Vfb of the error amplifier, but also can reduce the static power consumption of the circuit in the current-saving mode and improve the efficiency of the circuit.

In the above description, well-known structural elements and steps have not been described in detail. Those of ordinary skill in the art will understand that the corresponding structural elements and steps may be implemented by various technical means. In addition, in order to form the same structural elements, those skilled in the art can also devise methods which are not exactly the same as the methods described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.

Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The scope of the invention should be determined by the following claims.

Claims

1. A current bias circuit for a switching converter for providing a bias current to an operational amplifier in the switching converter, comprising:

the ramp voltage generation module comprises a capacitor and is used for charging or discharging the capacitor according to the level state of the current-saving mode signal so as to generate a ramp voltage;

a current output module for generating a first voltage following the ramp voltage and generating the bias current according to the first voltage,

wherein the bias current rises to a set current with a first slope when the current saving mode signal changes from a high level to a low level, and falls from the set current with a second slope when the current saving mode signal changes from a low level to a high level.

2. The current bias circuit of claim 1 further comprising:

and the feedback clamping module is used for clamping the first voltage to be smaller than/equal to a set bias voltage through negative feedback when the current-saving mode signal is changed from a high level to a low level so that the bias current is equal to the set current.

3. The current bias circuit of claim 2, further comprising:

and the tail current source module is used for providing working current following the bias current for the feedback clamping module according to the first voltage.

4. The current bias circuit of claim 3 wherein said ramp voltage generating module further comprises:

a first current source having a first end connected to a power supply voltage;

a first end of the first transistor is connected with a second end of the first current source, and a control end of the first transistor is connected with the current-saving mode signal;

a third transistor having a first terminal and a control terminal connected to a second terminal of the first transistor, and a second terminal connected to a first terminal of the capacitor;

a second transistor, a first end of which is connected with a first end of the capacitor, and a control end of which is connected with the current-saving mode signal; and

a second current source having a first terminal connected to a second terminal of the second transistor, a second terminal connected to the second terminal of the capacitor and ground,

wherein the first transistor is adapted to charge the capacitor when turned on according to a first current of the first current source and the second transistor is adapted to discharge the capacitor when turned on according to a second current of the second current source.

5. The current biasing circuit of claim 4, wherein the current output module comprises:

a fourth transistor having a first terminal as an output terminal of the bias current, a control terminal connected to the control terminal and the first terminal of the third transistor; and

a first resistor having a first terminal connected to a second terminal of the fourth transistor and a second terminal connected to ground.

6. The current bias circuit of claim 5 wherein said feedback clamp module comprises:

an input pair of transistors, an active load adaptively connected to the input pair of transistors and a source follower transistor,

wherein the input pair transistor comprises a fifth and a sixth transistor, a first end of the fifth and sixth transistor is connected with the output of the tail current source module,

a control terminal of a fifth transistor is connected to the second terminal of the fourth transistor for receiving the first voltage, a control terminal of the sixth transistor is for receiving the bias voltage,

the active load comprises a seventh and an eighth transistor, a first terminal of the seventh transistor being connected to the second terminal of the fifth transistor, a control terminal of the seventh transistor, a control terminal of the eighth transistor and a first terminal of the eighth transistor being connected to the second terminal of the sixth transistor, a second terminal of the seventh and eighth transistors being connected to ground,

the source follower transistor includes a ninth transistor, a first end of the ninth transistor is connected to an output of the tail current source module and a second end of the fourth transistor, a control end of the ninth transistor is connected to a common node of the fifth transistor and the seventh transistor, and a second end of the ninth transistor is connected to ground.

7. The current bias circuit of claim 6 wherein said tail current source module comprises:

a tail current unit for generating a second voltage varying with the first voltage and converting the second voltage into a first current; and

a current mirror adapted to connect with the tail current unit, the tail current unit being connected with an input pair of transistors and a source follower transistor in the feedback clamp module through the current mirror,

wherein the tail current unit comprises a tenth transistor and a second resistor, the control end of the tenth transistor is connected with the control end of the fourth transistor, the second end of the tenth transistor is connected with the first end of the second resistor, the second end of the second resistor is connected with the ground, the first end of the tenth transistor is used as the output end of the first current,

the current mirror includes eleventh to thirteenth transistors, first terminals of the eleventh to thirteenth transistors being connected to a power supply voltage,

the control terminal of the eleventh to thirteenth transistors and the second terminal of the eleventh transistor are connected to the first current,

a second terminal of the twelfth transistor is connected to the first terminal of the source follower transistor to output a second current,

a second terminal of the thirteenth transistor is connected to the first terminal of the input pair of transistors to output a third current.

8. A switching converter, comprising:

the power circuit adopts at least one switching tube and an inductor to control the transmission of electric energy from an input end to an output end, so that output voltage is generated according to input voltage;

an error amplifier for comparing the feedback voltage of the output voltage with a set reference voltage to generate an error signal;

a comparator circuit for comparing the error signal with the feedback voltage to generate a pulse width modulated signal;

the logic and driving circuit is used for controlling the on and off of at least one switching tube in the power circuit according to the pulse width modulation signal; and

a current biasing circuit as claimed in any one of claims 1 to 7, for providing a bias current to the error amplifier.

9. The switching converter of claim 8, wherein the switching converter is switchable between a normal mode and a current-saving mode, wherein,

the operational amplifier enters a small current mode when the switching converter works in a current-saving mode, and enters a large current mode when the switching converter works in a normal mode.

10. The switching converter of claim 9, wherein the logic and driver circuit is further configured to compare a time interval of adjacent pulses of the pulse width modulated signal with a set threshold value, and determine a time when the switching converter enters the current saving mode based on the comparison result.