CN117832085A - Super-junction IGBT device and manufacturing method thereof - Google Patents
Super-junction IGBT device and manufacturing method thereof Download PDFInfo
- Publication number
- CN117832085A CN117832085A CN202311860768.1A CN202311860768A CN117832085A CN 117832085 A CN117832085 A CN 117832085A CN 202311860768 A CN202311860768 A CN 202311860768A CN 117832085 A CN117832085 A CN 117832085A
- Authority
- CN
- China
- Prior art keywords
- layer
- super
- region
- epitaxial layer
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000002347 injection Methods 0.000 claims abstract description 15
- 239000007924 injection Substances 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 claims description 107
- 239000002184 metal Substances 0.000 claims description 34
- 239000002019 doping agent Substances 0.000 claims description 22
- 238000000151 deposition Methods 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 14
- 239000011229 interlayer Substances 0.000 claims description 11
- 230000000873 masking effect Effects 0.000 claims description 11
- 238000000137 annealing Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 239000007943 implant Substances 0.000 claims description 7
- 238000003860 storage Methods 0.000 claims description 6
- 238000002161 passivation Methods 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 229910000789 Aluminium-silicon alloy Inorganic materials 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 claims description 3
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 3
- 238000000407 epitaxy Methods 0.000 claims description 3
- 238000005224 laser annealing Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 2
- 210000003850 cellular structure Anatomy 0.000 claims description 2
- 238000000605 extraction Methods 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 13
- 230000008901 benefit Effects 0.000 description 5
- 238000002513 implantation Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
Abstract
The invention provides a super-junction IGBT device and a manufacturing method thereof, and the specific technical scheme is as follows: the positive current path of the super-junction IGBT is connected with the positive current path of the super-junction IGBT and the positive hole extraction path is disconnected from the positive current path of the super-junction IGBT through the P column region, and the positive P-type region is connected with the second P column region, so that a longitudinal PNP structure is formed, the super-junction IGBT is started under the strong collector emitter voltage of a short circuit device of the device, and a short circuit current discharge channel of the super-junction IGBT structure can be formed through a bipolar transistor. The invention provides the super-junction IGBT with innovation and practicability, and the compromises of the conduction performance, the switching characteristic and the short circuit capability of the super-junction IGBT are obviously improved by optimizing the electron injection enhancement structure and the turn-off hole extraction path.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a super-junction IGBT device and a manufacturing method thereof.
Background
The IGBT device is developed on the basis of a VDMOS structure, and the back side N+ drain electrode of the VDMOS device is changed into P+, so that the basic structure of the IGBT device is obtained. Therefore, it can be said that the IGBT device is a voltage controlled device composed of a front side MOS structure and a back side bipolar BJT structure. By controlling the gate voltage, the IGBT device can regulate the current flowing through the MOS channel and the backside collector-emitter.
IGBT devices combine the main advantages of bipolar junction power transistors and power MOSFETs, such as high input impedance, easy driving, large current capacity, and reduced saturation voltage. This makes IGBTs one of the important switching components for power control and conversion of high power section power electronics systems. Its performance directly affects the conversion efficiency of the power electronics system. In addition, the superjunction IGBT device has an important characteristic of a conductance modulation effect. When the super-junction IGBT is conducted, the collector P-type doped region of the super-junction IGBT can inject minority carrier holes into the N-drift region, so that conductivity modulation of the N-drift region is realized. The on-state voltage drop of the super-junction IGBT can be reduced, and the on-state current density of the super-junction IGBT can be improved.
Compared with the mode that the conventional single doping type drift region structure can only be longitudinally depleted, the super junction structure introduces the concept of lateral electric field depletion, so that the electric field distribution of the drift region is changed from conventional triangular or trapezoid-like distribution to nearly rectangular distribution, and the reverse voltage withstand capability of the device is improved under the same thickness of the drift region. In addition, as the super junction structure introduces the concept of lateral depletion, the on-resistance of the device can be reduced by increasing the doping concentration of the N column region of the drift region.
And introducing the structure with alternating superjunction N, P columns into the IGBT drift region to replace the original single doping type drift region, thus obtaining the superjunction IGBT structure. The super-junction IGBT has more excellent electrical performance than the traditional IGBT, has smaller chip area and larger on-current density,
FIG. 1 is a schematic diagram of a structure of a conventional super-junction IGBT device, which comprises an X100-P column region, an X101-N column region, an X200-carrier storage layer, an X201-P well region, an X300-polysilicon (Poly) gate, an X301-gate oxide layer, an X400-N+ emission region, an X401-P+ emission region, an X500-interlayer dielectric (ILD) layer, an X600-contact hole, an X601-front metal, an X700-collector, an X701-back field stop layer, an X800-back metal and other components. The current super-junction IGBT device has remarkable improvement on the aspect of forward current density, but the channel density of the front MOS structure is larger, so that the short-circuit current is large, the power born by the short-circuit device is large, and the short-circuit tolerance time length is limited. In power electronics systems, devices may be subject to short circuit conditions for various reasons (e.g., sudden load changes, line faults, etc.). At this time, if the short-circuit withstand time of the superjunction IGBT is insufficient, it may cause damage to the device and even cause a safety accident. In addition, compared with the traditional IGBT, the super-junction IGBT device has smaller chip area conduction, so that the super-junction IGBT device has smaller gate input capacitance Cies, and the grid driving current can cause the condition that the super-junction IGBT device generates current oscillation in the starting process, thereby generating an EMI problem and greatly influencing the reliability of the super-junction IGBT device. On the other hand, if the P column region in the super-junction IGBT structure is connected to the Body region, holes flow from the P column region to the emitter during the on period, which negatively affects the conductance modulation effect of the drift region, increases the on-voltage drop of the device, and weakens the advantageous characteristics of the bipolar device. Therefore, how to improve the short-circuit tolerance time of the superjunction IGBT and reduce the switching oscillation thereof and maintain a strong conductance modulation effect remains an important challenge and a problem that must be solved in a compromise.
Disclosure of Invention
In view of this, the present invention provides a superjunction IGBT device and a method of fabricating the same, and in particular, a superjunction IGBT device having an electron injection enhancement structure and a turn-off/short hole extraction path.
The specific technical scheme of the invention is as follows.
The manufacturing method of the super-junction IGBT device specifically comprises the following steps:
step one, preparing an N-type doped substrate 100;
step two, epitaxially growing a first N epitaxial layer 101 on the front surface of the N-type doped substrate 100, and then masking the first P-type injection region Mask to selectively inject P-type dopants to form a first P-pillar region 200;
step three, sequentially extending a second layer to a seventh layer of epitaxy on the first layer of P column region 200 and sequentially implanting second to seventh P-type dopants by using a Mask of a first P-implantation region to form second to seventh P column regions; thereafter growing an eighth epitaxial layer 207, forming an eighth P-pillar region 200' using a second P-implant Mask implant of P-type dopants over the eighth epitaxial layer 207, and growing a ninth epitaxial layer 208 over the eighth epitaxial layer 207; then, performing thermal annealing on each P column region to form a drift region structure with P column regions 200 and N column regions 201 alternately arranged with each other;
step four, masking and implanting the p+ region 300 on the ninth epitaxial layer 208 by using a first p+ Mask and thermally annealing;
depositing TEOS on the ninth epitaxial layer 208 to form a hard Mask, selectively etching the hard Mask by using the first TR Mask, and etching the ninth epitaxial layer 208 to form a front trench 301;
in the fifth step, the front trench 301 is located at the two sides of the p+ region 300 and the center of the cellular structure, the depth of the trench is greater than the height of the ninth epitaxial layer 208, and the bottom is the seventh epitaxial layer.
Step six, thermally growing a sacrificial oxide layer on the ninth epitaxial layer 208 and the front side groove 301, and etching, and then thermally growing a gate oxide layer 302; polysilicon Poly is deposited on the gate oxide layer 302 in the trench and etched back to form a central Poly gate 301a, a side Poly gate 301b and a side Poly gate 301c;
step seven, high-energy injecting N-type dopant between the central poly gate 301a and the side poly gate 301b of the ninth epitaxial layer 208 and pushing the junction to form a carrier storage layer 304, and then injecting P-type dopant at the same position and thermally annealing to form a P-well region 303; thereafter implanting N-type dopants on both side upper surfaces of the central poly gate 301a using an n+ Mask and annealing to form an emitter n+ 400;
step eight, depositing USG and BPSG on the ninth epitaxial layer 208 to form an interlayer dielectric layer 500; using a CT Mask to Mask and etch the ILD on the interlayer dielectric layer, and then etching a second groove on the ninth epitaxial layer 208 to form an emitter contact hole 501;
step nine, depositing barrier metal Ti/TiN on the interlayer dielectric layer 500, then depositing AlSi to form a front metal layer 600, and masking and etching the metal layer 600 by using a metal Mask to form emitter metal, gate metal and termination region stop ring metal; depositing a silicon-rich oxynitride over the metal layer 600 to form a front passivation protection layer 601;
step ten, turning over the structure, thinning the surface of the N-type doped substrate 100, which is far away from the first N epitaxial layer 101, and then forming a field stop layer 701 and a collector 702 by respectively implanting N-type and P-type dopants and laser annealing; a metal Al/Ti/Ni/Ag is deposited on top of the collector 702 to form a backside collector metal layer 800.
In the second step, the first P-pillar regions 200 are distributed on the upper portion of the first N-epi layer 101.
In step four, the p+ region 300 is biased to a position above the P pillar region 200 at the eighth P pillar region 200 'and above the center of the eighth P pillar region 200'.
In step six, the central polycrystalline gate 301a is an active gate, and is connected to the gate PAD; the side one poly gate 301b is set as an active gate or a co-gate or a floating gate, and the side two poly gate 301c is a co-gate connected with the emitter.
In step eight, the emitter contact hole 501 is located at the center of the emitter n+400 and directly above the center of the eighth P pillar region 200'.
The super-junction IGBT structure is obtained by the preparation method.
Compared with the prior art, the invention has the following beneficial effects:
the invention relates to a super-junction IGBT with an electron injection enhancement structure and a turn-off hole extraction path. Compared with the conventional super-junction IGBT device, the method has the advantages that the electron injection enhancement structures are introduced at the two sides of the front active grid, so that the saturation voltage drop of the super-junction IGBT is obviously reduced, and the forward conduction current density of the super-junction IGBT is improved. The innovative design benefits from the electron injection enhancement region formed by the deep P+ injection region, the Pbody region and the groove, and further optimizes the conduction performance of the super-junction IGBT.
In addition, the invention also introduces a hole release path, and forms a structure that the P-type region is connected with the emitter through a P+ injection region which is narrower than the electron injection enhancement region and a P column region connected with the P+ injection region. The design innovation accelerates the extraction capability of carrier holes in the IGBT turn-off process, and remarkably improves the turn-off speed of the super-junction IGBT. Compared with the existing super-junction IGBT, the super-junction IGBT has the advantages that the channel density of the front MOS structure of the existing super-junction IGBT is reduced by introducing the electron injection enhancement structure into the front of the super-junction IGBT.
Furthermore, the positive current path and the positive hole extraction path of the super-junction IGBT are connected and separated through the P column region, and the positive P-type region is connected with the second P column region, so that a longitudinal PNP structure is formed, the device is started under the strong collector emitter voltage of the device short-circuit device, and a short-circuit current discharge channel of the super-junction IGBT structure can be formed through the bipolar transistor. The innovations not only improve the short-circuit tolerance time of the super-junction IGBT, but also make the super-junction IGBT more stable and reliable when facing extreme conditions such as short circuit and the like; meanwhile, the turn-off speed is improved, and powerful support is provided for quick response and control of the power electronic system; and the main current paths of the IGBT in the switching-on and short-circuit and switching process are divided, so that the characteristics and the robustness of the super-junction IGBT device are further improved.
In addition, the side one grid electrode can be connected with the grid electrode and provided with a channel to form an active grid, and can also be connected with the emitter to form an accompanying grid, or neither of the side one grid electrode and the emitter is connected with the emitter to form a floating grid, so that the super-junction IGBT device also has the characteristics of adjusting the input capacitance and the grid charge Qg of the device, and can optimize the EMI performance of the super-junction IGBT.
In summary, the super-junction IGBT with innovation and practicability is provided, and the compromises of the conduction performance, the switching characteristic and the short circuit capability of the super-junction IGBT are remarkably improved by optimizing the electron injection enhancement structure and turning off the hole extraction path. The invention has important significance and value for promoting the development and application of the power electronic technology, especially in the field of power control and conversion in a high-power section.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 is a diagram showing a conventional super junction IGBT structure.
Fig. 2 is a schematic diagram of the final super-junction IGBT structure of the invention.
FIG. 3 is a schematic diagram of the structure after the completion of the first step of the present invention.
FIG. 4 is a schematic diagram of the structure after the completion of step two of the present invention.
Fig. 5 is a schematic structural diagram of the third embodiment of the present invention.
FIG. 6 is a schematic diagram of the structure after the completion of step four of the present invention.
Fig. 7 is a schematic structural diagram of the present invention after the completion of step five.
Fig. 8 is a schematic structural diagram of the present invention after the completion of step six.
Fig. 9 is a schematic structural diagram of the present invention after the completion of step seven.
FIG. 10 is a schematic diagram of the structure of the present invention after the completion of step eight.
FIG. 11 is a schematic diagram of the structure of the present invention after the step nine is completed.
Reference numerals illustrate:
100-a first N-type doped substrate; 101-a first N-type epitaxial layer; 200-a first P column region; 200' -eighth P column region; 201-N column regions; 207-eighth epitaxial layer; 208-a ninth epitaxial layer; 301-front side grooves; 302-gate oxide; 301 a-a central poly gate; 301 b-a side poly gate; 301 c-side two poly gate; 303-P well region; 304-a carrier storage layer; 400-emitter n+; 500-interlayer dielectric layers; 501-an emitter contact hole; 502-emitter p+; 600-front side metal layer; 601-passivation protection layer; 701-field cut layer; 702-collector and 800-collector metal layer.
Detailed Description
The present invention is described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth in detail. The present invention will be fully understood by those skilled in the art without the details described herein. Well-known methods, procedures, flows, components and circuits have not been described in detail so as not to obscure the nature of the invention.
Moreover, those of ordinary skill in the art will appreciate that the drawings are provided herein for illustrative purposes and that the drawings are not necessarily drawn to scale.
Unless the context clearly requires otherwise, the words "comprise," "comprising," and the like throughout the application are to be construed as including but not being exclusive or exhaustive; that is, it is the meaning of "including but not limited to".
In the description of the present invention, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Furthermore, in the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.
In order to solve the problems in the prior art, the invention provides a super-junction IGBT device and a manufacturing method thereof, and referring to fig. 2, the diagram is a final embodiment drawing of the super-junction IGBT device and the manufacturing method thereof.
In the embodiment, the saturation voltage drop of the super-junction IGBT is reduced through the electron injection enhancement structure on the front surface; by introducing a hole release path, hole extraction at turn-off is accelerated.
Referring to fig. 2-11, the manufacturing method of the super-junction IGBT device comprises the following specific steps:
1. an N-doped substrate 100 is prepared.
2. Epitaxially growing a first N epitaxial layer 101 on the front surface of the N-doped substrate 100, and then masking the first P-doped region Mask to selectively implant P-type dopants to form a first P-pillar region 200
3. Sequentially extending a second layer to a seventh layer of epitaxy on the first layer of P column region 200 and sequentially implanting second to seventh P type dopants by using a Mask of a first P implantation region to form second to seventh P column regions; thereafter growing an eighth epitaxial layer 207, forming an eighth P-pillar region 200' using a second P-implant Mask implant of P-type dopants over the eighth epitaxial layer 207, and growing a ninth epitaxial layer 208 over the eighth epitaxial layer 207; and then performing thermal annealing on the P column regions to form a drift region structure with the P column regions 200 and the N column regions 201 alternately arranged.
4. A first P + Mask is used to Mask the implanted P + region 300 and thermally annealed over the ninth epitaxial layer 208.
5. A TEOS forming hard Mask (HardMask) is deposited over the ninth epitaxial layer 208, etched using the first TR Mask masking, the hard Mask, and the ninth epitaxial layer 208 is etched to form a front side Trench (Trench) 301.
6. Thermally growing a sacrificial oxide layer (SAC, sacrificial Oxide) over the ninth epitaxial layer 208 and the front side trench 301 and etching, followed by thermally growing a gate oxide layer 302; polysilicon (Poly) is deposited over the gate oxide layer 302 and selectively etched back to the wafer surface using a Poly Mask to form Poly gates 301a,301b,301c; wherein 301a is an active Gate, connected to a Gate (Gate) PAD; 301b may be provided as an active Gate or a Dummy Gate (Dummy Gate) or a Floating Gate (Floating Gate), 301c being a Dummy Gate (Dummy Gate) to emitter.
7. High-energy implantation of N-type dopants and junction pushing in the ninth epitaxial layer 208 to form a carrier storage layer (Carrier Storage Layer) 304, followed by implantation of P-type dopants and thermal annealing to form a P-well region (PWell) 304; an N-type dopant is then implanted using an N + Mask and annealed to form emitter N + 400.
8. Depositing USG and BPSG over the ninth epitaxial layer 208 to form an interlayer dielectric layer (ILD) 500; and (3) using a CT Mask to Mask and etch the ILD on the interlayer dielectric layer, etching a second groove on the ninth epitaxial layer 208 to form an emitter contact hole 501, and then injecting a P-type doping agent and annealing to form an emitter P+502.
9. Depositing barrier metal Ti/TiN on the interlayer dielectric layer 500, then depositing AlSi to form a front metal layer 600, and masking and etching the metal layer 600 by using a metal Mask to form emitter metal, gate metal and termination region stop ring metal; a Silicon Rich Nitride (SRN) is deposited over the metal layer 600 to form a front passivation protection layer 601.
10. A vertical flip structure for thinning the surface of the N-type doped substrate 100 far from the first N epitaxial layer 101, and then forming a field stop layer (FS) 701 and a collector 702 by respectively implanting N-type and P-type dopants and laser annealing; a metal Al/Ti/Ni/Ag is deposited on top of the collector 702 to form a backside collector metal layer 800.
Claims (6)
1. The manufacturing method of the super-junction IGBT device is characterized by comprising the following steps of:
step one, preparing an N-type doped substrate (100);
step two, epitaxially growing a first N epitaxial layer (101) on the front surface of the N-type doped substrate (100), and then masking and selectively implanting a P-type dopant into a first P-type injection region Mask to form a first P-type column region (200);
step three, sequentially extending a second layer to a seventh layer of epitaxy on the first layer of P column region (200) and sequentially implanting second to seventh P type dopants by using a Mask of a first P injection region to form second to seventh P column regions; thereafter growing an eighth epitaxial layer (207), forming an eighth P-pillar region (200') using a second P-implant Mask implant of P-type dopants over the eighth epitaxial layer (207), and growing a ninth epitaxial layer (208) over the eighth epitaxial layer (207); then, carrying out thermal annealing on each P column region to form a drift region structure with P column regions (200) and N column regions (201) alternately arranged;
masking the implanted p+ region (300) above the ninth epitaxial layer (208) using a first p+ Mask and thermally annealing;
depositing TEOS on the ninth epitaxial layer (208) to form a hard Mask, masking and etching the hard Mask by using a first TR Mask, and etching the ninth epitaxial layer (208) to form a front surface groove (301);
in the fifth step, the front side grooves (301) are arranged at the two sides of the P+ region (300) and the central position of the cellular structure, the depth of the grooves is larger than the height of the ninth epitaxial layer (208), and the bottom is a seventh epitaxial layer;
thermally growing a sacrificial oxide layer on the ninth epitaxial layer (208) and the front side groove (301) and etching, and then thermally growing a gate oxide layer (302); depositing polysilicon Poly on the gate oxide layer (302) in the trench and etching back to form a central polycrystalline gate (301 a), a side one polycrystalline gate (301 b) and a side two polycrystalline gate (301 c);
step seven, high-energy N-type dopants are injected between the central polycrystalline grid electrode (301 a) and the side polycrystalline grid electrode (301 b) of the ninth epitaxial layer (208) and pushed to form a carrier storage layer (304), and then P-type dopants are injected at the same position and thermally annealed to form a P well region (303); thereafter implanting N-type dopants on both side upper surfaces of the central poly gate (301 a) using n+ Mask masking and annealing to form an emitter n+ (400);
depositing USG and BPSG on the ninth epitaxial layer (208) to form an interlayer dielectric layer (500); using a CT Mask to Mask and etch the ILD on the interlayer dielectric layer, and then etching a second groove on the ninth epitaxial layer (208) to form an emitter contact hole (501);
step nine, depositing barrier metal Ti/TiN on the interlayer dielectric layer (500), then depositing AlSi to form a front metal layer (600), and masking and etching the metal layer (600) by using a metal Mask to form emitter metal, gate metal and termination region cut-off ring metal; depositing a silicon-rich oxynitride over the metal layer (600) to form a front passivation protection layer (601);
step ten, turning over the structure, thinning the surface of one side of the N-type doped substrate (100) far away from the first N epitaxial layer (101), and then forming a field stop layer (701) and a collector (702) by respectively implanting N-type and P-type dopants and laser annealing; and depositing metal Al/Ti/Ni/Ag on the collector (702) to form a back collector metal layer (800).
2. The method for manufacturing the super-junction IGBT device according to claim 1, wherein: in the second step, the first P column regions (200) are distributed on the upper portion of the first N epitaxial layer (101) in a dispersed manner.
3. The method for manufacturing the super-junction IGBT device according to claim 1, wherein: in the fourth step, the p+ region (300) is biased to a position above the P pillar region (200) and above the center of the eighth P pillar region (200').
4. The method for manufacturing the super-junction IGBT device according to claim 1, wherein: in the sixth step, the central polycrystalline grid (301 a) is an active grid and is connected with the grid PAD; the side one polycrystalline grid (301 b) is arranged as an active grid or a coside grid (connected with an emitter) or a floating grid, and the side two polycrystalline grid (301 c) is connected with the emitter.
5. The method for manufacturing the super-junction IGBT device according to claim 1, wherein: in the eighth step, the emitter contact hole (501) is located at the center of the emitter N+ (400) and directly above the center of the eighth P column region (200').
6. A superjunction IGBT device obtainable by the method of manufacturing of claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311860768.1A CN117832085A (en) | 2023-12-31 | 2023-12-31 | Super-junction IGBT device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311860768.1A CN117832085A (en) | 2023-12-31 | 2023-12-31 | Super-junction IGBT device and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117832085A true CN117832085A (en) | 2024-04-05 |
Family
ID=90503794
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311860768.1A Pending CN117832085A (en) | 2023-12-31 | 2023-12-31 | Super-junction IGBT device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117832085A (en) |
-
2023
- 2023-12-31 CN CN202311860768.1A patent/CN117832085A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11133407B2 (en) | Super-junction IGBT device and method for manufacturing same | |
| US9087893B2 (en) | Superjunction semiconductor device with reduced switching loss | |
| TWI534902B (en) | Method of forming a power semiconductor device and power semiconductor device | |
| CN109713037B (en) | Insulated gate bipolar transistor device and preparation method thereof | |
| US20210057556A1 (en) | Igbt devices with 3d backside structures for field stop and reverse conduction | |
| KR20120135121A (en) | Semiconductor structure integrated superjunction mosfet and diode, and method of forming the same | |
| JPWO2011136272A1 (en) | Semiconductor device | |
| CN110600537B (en) | Separation gate CSTBT with PMOS current clamping and manufacturing method thereof | |
| CN113838916B (en) | Separation gate CSTBT with PMOS current clamping function and manufacturing method thereof | |
| CN107731898B (en) | CSTBT device and manufacturing method thereof | |
| CN114005877A (en) | Ultrathin super-junction IGBT device and preparation method | |
| CN110137250B (en) | High-speed IGBT device with ultralow conduction voltage drop | |
| CN110419111B (en) | Self-aligned and robust insulated gate bipolar transistor device | |
| US10692995B2 (en) | Insulated-gate bipolar transistor structure and method for manufacturing the same | |
| CN108155230B (en) | Transverse RC-IGBT device and preparation method thereof | |
| US11195942B2 (en) | Semiconductor device including electrode trench structure and isolation trench structure and manufacturing method therefore | |
| CN103117309A (en) | Horizontal power device structure and preparation method thereof | |
| CN107634094B (en) | Insulated gate bipolar transistor structure and manufacturing method thereof | |
| CN116936626A (en) | IGBT device and manufacturing method thereof | |
| CN110473905B (en) | TIGBT (tungsten inert gas) with self-biased PMOS (P-channel metal oxide semiconductor) separation gate and manufacturing method thereof | |
| CN117832085A (en) | Super-junction IGBT device and manufacturing method thereof | |
| US11004839B1 (en) | Trench power MOSFET with integrated-schottky in non-active area | |
| CN112018162B (en) | 4H-SiC side gate integrated SBD MOSFET device and preparation method thereof | |
| CN111129134B (en) | IGBT chip and manufacturing method thereof | |
| CN115295612B (en) | Single-side channel RC-IGBT device, preparation method thereof and chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |