CN1178285C - Method for assembling integrated circuit in printing mode - Google Patents
Method for assembling integrated circuit in printing mode Download PDFInfo
- Publication number
- CN1178285C CN1178285C CNB021468583A CN02146858A CN1178285C CN 1178285 C CN1178285 C CN 1178285C CN B021468583 A CNB021468583 A CN B021468583A CN 02146858 A CN02146858 A CN 02146858A CN 1178285 C CN1178285 C CN 1178285C
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- chip
- zone
- integrated circuit
- sealing
- substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
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- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
The present invention relates to a method for assembling an integrated circuit in a printing way. After a chip comprising a welding projection is placed on a base plate, sealing compounds are filled into a gap between the chip and the base plate in a printing way by using a stencil of the present invention to fix the chip to the base plate. The different distribution density and the different style design of sieve numbers of the stencil of the present invention are used for controlling the mode and the speed of the sealing compounds to flow into the gap between the chip and the base plate, voids are avoided generating in the sealing compounds between the chip and the base plate after the assembly structure of the integrated circuit is formed, and the efficiency and the quality for assembling the integrated circuit can not be reduced.
Description
Technical field
The present invention relates to a kind of method, to avoid behind the assembling structure of formation integrated circuit inner usefulness and the quality that produces pore and reduce structure dress integrated circuit of the sealing between chip and the substrate with mode of printing structure dress integrated circuit.
Background technology
Integrated circuit generally needs framework within the structure package material, and the flat structure dress in four for example traditional limits (Quad Flat Package, QFP).Smooth assembling structure comprises a pin frame, and many lead-in wires that are contacted with integrated circuit (IC) chip (Chip) are arranged on pin frame.Chip is contained in one by structure has mechanical support to reach in the firm plastics that insulate with circuit, and lead-in wire mainly is to be welded on the printed circuit board (PCB).
In the past, the integrated circuit structure packing technique that integrated circuit manufacturer develops has out attempted to satisfy the requirement of microminiaturization.For the integrated circuit modification method of microminiaturization, be to make it on silicon base material, combination comprise millions of transistor circuit assemblies such as circuit, chip.The method of these improvement causes the method for structure dress circuit unit in limited space more to come into one's own.
Integrated circuit, is created in integrated device electronics through complicated technology such as etching, doping, deposition and cutting by a Silicon Wafer.One Silicon Wafer comprises an integrated circuit (IC) chip at least, and each chip is represented an independent integrated circuit.At last, this chip can be adorned by being enclosed in chip mould of plastics structure all around, and has diversified stitch to expose and interconnected design.For example: M type dual inline type packaging housing (the M Dual-In-Line-Package that a quite smooth structure dress is provided; M-Dip), it has the parallel pin of two row to extend out from the reach through hole of bottom, contacts and is fixed on below the surface-mounted integrated circuit.The printed circuit board (PCB) of allowing the higher density integrated circuit is single-column type packaging housing (Single-In-Line-Package; SIP) and little external form pin structure dress (Small Outline J-leaded; SOJ), it is for adopting the structure dress of model.
According to the integrated circuit (IC) chip number of combination in the structure dress, the kind of structure dress integrated circuit is broadly divided into single-chip structure dress (Single Chip Package; SCP) with many chip packaging (MultichipPackage; MCP) two big classes, many chip packagings also comprise multi-chip module structure dress (MultichipModule; MCM).If according to the juncture of assembly and circuit board, structure dress integrated circuit can be divided into pin insert type (Pin-Through-Hole; PTH) with SMD LED surface-mount device LED (Surface MountTechnology; SMT) two big classes.The pin of pin insert type assembly is fine acicular or lamellar metal, and is fixing for welding in the guide hole (Via) that inserts runners (Socket) or circuit board.After then sticking on the circuit board earlier, fixes in the mode of welding again by the assembly of SMD LED surface-mount device LED.Currently used advanced structure packing technique is that chip directly coheres (Direct Chip Attach; DCA) structure dress is adorned the size of the volume of integrated circuit to reduce structure, and increases the integration of the circuit of structure dress IC interior.The technology that chip directly coheres is fixed on the substrate (Substrate) for direct chip (Integrated Circuit Chip) with integrated circuit, carries out the binding of circuit again.
The most general structure dress mode that adopts is that routing engages the mode of (wire-bonding) at present; be elder generation chip is fixed on the pin frame (lead-frame), next utilize lead connection pin frame and chip and utilize adhesive filling mould mixture (Molding Compound) to cover the pin frame of chip and part to form structure dress integrated circuit.Structure dress integrated circuit can utilize the pin frame that exposes to be fixed on the substrate with the circuit in circuit on the connection substrate and the structure dress integrated circuit.Because the structure packing technique that utilizes routing to engage can't dwindle the volume of structure dress integrated circuit, therefore developed the structure packing technique that a chip bonding (Flip-Chip) at present and adorned the more and more littler demand of volume of integrated circuit to meet structure.The characteristics of the structure packing technique of chip bonding are at first borrowing the soldering projection of being installed on the chip active surface to be directly fixed on the substrate chip.Next utilize cover brilliant mode of filling (Underfill) with sealing insert between chip and the substrate the gap be fixed in chip on the substrate and protect chip and substrate between the binding interface.Owing to need not use pin frame, therefore utilize the volume of the structure dress integrated circuit of chip bonding technology can dwindle fully to meet the demand of product.
With reference to shown in Figure 1, this covers brilliant schematic diagram of filling (Underfill) structure process for tradition.Shown in Fig. 2 A to Fig. 2 C, when this fills structure process for utilizing traditional approach to cover crystalline substance, the schematic diagram of the fill pattern of sealing and the defective that is produced.When tradition is covered crystalline substance filling structure process, at first chip 10 can be connected on the substrate 20 by the soldering projection on the chip 10.Next utilize filler device 25 that gap between chip 10 and the substrate 20 is inserted in sealing 30, with the contact point between protection chip 10 and the substrate 20.In traditional filler process, route that filler device 25 moved is most of to adopt " one " font, " L " font or " ㄇ " font sealing 30 to be inserted gap between chip 10 and the substrate 20 with the external form that cooperates chip 10.Utilization is covered the structure dress integrated circuit that brilliant mode of filling structure process produces and is chip bonding structure dress (Flip Chip Package; FC) integrated circuit.
In Fig. 2 A, the mobile alignment that the filler device adopts " one " font is inserted gap between chip and the substrate with sealing, so sealing 30 enters between chip and the substrate with single direction, and can not form pore in structure dress integrated circuit.Though can not contain pore when the inside that the filler device is adorned integrated circuit with the formed structure of the mobile alignment of " one " font, the mobile alignment of this " one " font will spend the more processing procedure time and influence the operational paradigm that structure is adorned the processing procedure of integrated circuit.In the 2nd B figure and Fig. 2 C, the filler device adopts " L " font or the mobile alignment of " ㄇ " font that gap between chip and the substrate is inserted in sealing, so sealing 30 can enter between chip and the substrate operational paradigm with the processing procedure that improves structure dress integrated circuit simultaneously with two kinds of directions.Because the speed of sealing 30 on this two direction is also inequality, therefore in structure dress integrated circuit, tend to form pore 35 and the quality of reduction structure dress integrated circuit.When structure dress integrated circuit contains pore 35, represent the gap that sealing 30 is not filled between chip and the substrate up hill and dale, and reduce the reliability of structure dress integrated circuit.Structure when formed pore will become running in structure process is adorned the distinguished point of integrated circuit and is formed the phenomenon that stress is concentrated, and then causes structure dress integrated circuit structure to produce the defective that crumbles.
Owing to utilizing the formed structure dress of traditional processing procedure integrated circuit is not to need the more processing procedure time of cost to influence the processing procedure efficiency of operating, can adorn IC interior generation pore and influence the quality that structure is adorned integrated circuit at structure exactly, therefore be necessary to propose preferable manufacturing method thereof and improve the quality that structure is adorned integrated circuit with operational paradigm and the one side that one side improves the processing procedure of structure dress integrated circuit.
Summary of the invention
In above-mentioned background technology, using traditional structure dress integrated circuit manufacture process is not to influence the quality that the processing procedure efficiency of operating is exactly a meeting reduction structure dress integrated circuit.The invention provides a kind of method of structure dress integrated circuit, utilize distribution density and pattern are different on the web plate of the present invention mesh enters the gap between chip and substrate with the control sealing pattern and speed and sealing is inserted gap between chip and the substrate in the mode of printing, to avoid defective at structure dress IC interior generation pore.
Second purpose of the present invention is to utilize distribution density and pattern are different on the web plate of the present invention mesh enters the gap between chip and substrate with the control sealing pattern and speed and sealing is inserted gap between chip and the substrate in the mode of printing, with the operational paradigm of the structure process of raising integrated circuit.
The 3rd purpose of the present invention is to utilize distribution density and pattern are different on the web plate of the present invention mesh enters the gap between chip and substrate with the control sealing pattern and speed and sealing is inserted gap between chip and the substrate in the mode of printing, adorns the production cost of integrated circuit to reduce structure.
The 4th purpose of the present invention is to utilize distribution density and pattern are different on the web plate of the present invention mesh enters the gap between chip and substrate with the control sealing pattern and speed and sealing is inserted gap between chip and the substrate in the mode of printing, adorns yield (yield) reliability (Reliability) of integrated circuit to improve structure.
A further object of the present invention is to utilize distribution density and pattern are different on the web plate of the present invention mesh enters the gap between chip and substrate with the control sealing pattern and speed and sealing is inserted gap between chip and the substrate in the mode of printing, adorns the scope of application of integrated circuit to improve structure.
According to above-described purpose, the invention provides a kind of method of structure dress integrated circuit, utilize distribution density and pattern are different on the web plate of the present invention mesh enters the gap between chip and substrate with the control sealing pattern and speed and sealing is inserted gap between chip and the substrate in the mode of printing, to avoid defective at structure dress IC interior generation pore.On web plate of the present invention, comprise a first area, a second area, one the 3rd zone, one the 4th zone and one the 5th zone.Second area is in inside, first area, and the screen frequency on the first area is low than the screen frequency on the second area.The 3rd zone, the 4th zone with the 5th zone all at second area inner and the 4th zone between the 3rd regional and the 5th zone.There is no the distribution of mesh on the 5th zone and the 3rd zone all is lower than screen frequency on the second area with screen frequency on the 4th zone.The present invention at first utilizes the soldering projection on the chip to combine with substrate.The substrate that next will comprise chip is positioned on the platform and installation web plate of the present invention above chip.The last surface of on the web plate of part, coating a sealing and utilizing a scraper to cross this web plate so that sealing can be gathered in via the mesh that is distributed on the web plate substrate around and make the sealing porous go into gap between chip and the substrate.After the sealing dry forming, chip promptly is fixed on the substrate, and the structure of the integrated circuit finished of structure dress can be coated on segment chip in the sealing according to the demand of product and the back side of exposed chip, to improve the radiating efficiency of chip.Flow in the process in gap of chip and substrate in sealing, because sealing flows into the control that chip and the speed in the gap of substrate have been passed through the different screen frequencies distributed areas on the web plate, so sealing is with the gap of unidirectional form inflow chip and substrate and can avoid pore to result from the gap of chip and substrate.Utilize method of the present invention also can improve integrated circuit structure process operational paradigm and reduce the production cost of structure dress integrated circuit.Method of the present invention more can improve the yield and the scope of application that improves structure dress integrated circuit of structure dress integrated circuit.
Description of drawings
Fig. 1 covers brilliant schematic diagram of filling structure process for tradition;
When Fig. 2 A to Fig. 2 C fills structure process for utilizing traditional approach to cover crystalline substance, the schematic diagram of the fill pattern of sealing and the defective that is produced;
Fig. 3 is the schematic diagram of web plate of the present invention;
Fig. 4 utilizes method of the present invention that sealing is inserted schematic diagram between chip and the substrate in the mode of printing;
Fig. 5 A and Fig. 5 B are that integrated circuit is through the schematic diagram behind the structure process of the present invention;
Fig. 6 A and Fig. 6 B are the schematic diagram that a fin is installed on structure dress integrated circuit.
Symbol description among the figure
10 chips
20 substrates
25 filler devices
30 sealings
35 pores
100 web plates
110 first areas
120 second areas
130 the 3rd zones
140 the 4th zones
150 the 5th zones
200 platforms
210 chips
220 soldering projections
230 substrates
240 sealings
250 scrapers
310 first directions
320 second directions
400 fin
Embodiment
Some embodiments of the present invention can be described in detail as follows.Yet except describing in detail, the present invention can also be widely implements at other embodiment, and scope of the present invention is not subjected to the qualification of embodiment, and its scope with claims is as the criterion.
The invention provides a kind of method of structure dress integrated circuit, utilize distribution density is different with pattern on the web plate of the present invention mesh enters the gap between chip and substrate with the control sealing pattern and speed and sealing is inserted gap between chip and the substrate in the mode of printing, to avoid defective at structure dress IC interior generation pore.With reference to shown in Figure 3, this is the schematic diagram of web plate of the present invention.On comprising several meshes and its, web plate 100 of the present invention comprises a first area 110, a second area 120, one the 3rd zone 130,140 and 1 the 5th zone 150, one the 4th zone.The screen frequency of second area 120 on 110 inside, first area and first area 110 is low than the screen frequency on the second area 120.The 3rd zone 130, the 140 and the 5th zone 150, the 4th zone all at second area 120 inner and the 4th zone 140 between the 3rd regional the 130 and the 5th zone 150.There is no perforate on the 5th zone 150, and the 3rd screen frequency of zone on the 130 and the 4th zone 140 all is lower than screen frequency on the second area 120 and the screen frequency on the first area 110.The 3rd zone 130 more can be an opened state, can pass through the 3rd zone at faster speed to make sealing in successive process.On the surface of a first direction 310 of web plate 100, putting in order of each zone is first area 110, second area 120 and the 3rd zone 130, the 4th zone 140, the 5th zone 150, and first area 110, and wherein this first direction 310 is scraper is advanced in successive process direction.
With reference to shown in Figure 4, this is to utilize method of the present invention that sealing is inserted schematic diagram between chip and the substrate in the mode of printing.The present invention at first utilizes the soldering projection of being installed on chip 210 first surfaces (being active surface) 212 220 that chip 210 is combined with substrate 230.The substrate 230 that next will comprise chip 210 is positioned on the platform 200 and web plate 100 of the present invention is installed above chip 210.The 5th zone 150 on the web plate 100 of the present invention is corresponding to chip 210, and therefore the size in the 5th zone increases along with the surface area of the second surface 214 of chip or dwindles, and the first surface of its chips and a second surface are parallel to each other.The last surface of on the web plate 100 of part, coating a sealing 240 and utilizing a scraper (Squeegee) 250 to cross this web plate 100, so that sealing 240 can be gathered in via the mesh that is distributed on the web plate 100 on the substrate 230 and chip 210 around, and making sealing 240 porous go into gap between chip 210 and the substrate 230, the sealing of wherein being adopted is most of to be resin (Resin).
When scraper crosses web plate 100 surperficial with a first direction 310, in the sealing on the web plate 100 240 at first through the zone of the 1 on the web plate 100 and through the mesh of this first area 110 and be gathered on the substrate 230.Next sealing 240 simultaneously through the zone of the 2 120 on the web plate 100 and the 3rd zone 130 and through this second area 120 be gathered in the mesh in the 3rd zone 130 reach on the substrate 230 chip around.When sealing 240 entered first area 110 on the web plate 100, because the screen frequency on the first area 110 is less, so sealing 240 can be gathered on the substrate 230 by the mesh on the first area 110 rapidly.To pass through the 2 120 on the web plate 100 zone simultaneously regional 130 the time with the 3rd when sealing, because the screen frequency on the web plate 100 on the second area 120 is higher than the screen frequency on the 3rd zone 130, therefore the seepage velocity of sealing 240 on the 3rd zone 130 is higher than the seepage velocity on second area 120, and sealing 240 can form the shape in the 3rd zone 130 on substrate 230.Because the 3rd zone 130 also can be an open no shielding status, so sealing 240 can be at faster speed by the 3rd zone 130 on the web plate 100.Next sealing 240 is gathered on the substrate 230 and around chip through the zone of the 2 120 on the web plate 100 and the 4th zone 140 and through the mesh in this second area 120 and the 4th zone 140 simultaneously.To pass through the 2 120 on the web plate 100 zone simultaneously regional 140 the time with the 4th when sealing 240, because the screen frequency on the web plate 100 on the second area 120 is higher than the screen frequency on the 4th zone 140, therefore the seepage velocity of sealing 240 on the 4th zone 140 is higher than the seepage velocity on second area 120, and sealing 240 can form the shape in the 4th zone 140 on substrate 230.When sealing 240 via the second area on the web plate 100 120, the 130 and the 4th zone 140, the 3rd zone be gathered on the substrate 230 and chip 210 all around the time, because sealing 240 is fast in the flowing velocity in the 130 and the 4th zone 140, the 3rd zone than the flowing velocity of sealing on second area 120, therefore sealing 240 can diffuse to the gap of chip 210 and substrate 230 with fast speeds and can be gone out by diffusion in the gap of chip 210 and substrate 230 by a second direction 320 (with reference to shown in Figure 3) on first direction 310, and wherein first direction 310 is perpendicular to second direction 320.Though sealing 240 also can be flowed to the gap of chip 210 and substrate 230 via the second area 120 of web plate 100 by second direction 320, but the gap that the speed that is gone out by the interstitial diffusion of chip 210 and substrate 230 on first direction 310 owing to sealing 240 flows to chip 210 and substrate 230 by first direction 310 than sealing 240 is for fast, thus sealing can Fig. 2 A in shown flow pattern enter chip 210 can not produce pore with the gap of substrate 230 defective.When the mode of utilizing printing of the present invention with sealing 240 with Fig. 2 A in shown flow pattern insert the generation that the space more can be avoided in gap between chip 210 and the substrate 230.Next sealing 240 is gathered on the substrate 230 through the zone of the 2 120 on the web plate 100 and the 5th zone 150 and through the mesh of this second area 120 simultaneously.Owing to there is no the state that the distribution mesh is a complete closed on the 5th zone 150 of web plate 100, so sealing 240 can not be formed on the second surface of chip.Last sealing 240 is also passed through the mesh of this first area 110 through the first area on the web plates 100 110 and is gathered on the substrate 230.
Shown in Fig. 5 A and Fig. 5 B, this for integrated circuit through the schematic diagram behind the structure process of the present invention.Shown in Fig. 6 A and Fig. 6 B, this is the schematic diagram that a fin is installed on structure dress integrated circuit.After sealing 240 dryings of being inserted in the mode of printing and shaping, chip 210 promptly is fixed on the substrate 230 and finishes the processing procedure of structure dress integrated circuit of the present invention.Utilize the structure of the integrated circuit that method of the present invention institute structure dress finishes to form different shapes according to the demand of product.But utilize the chip 210 and the substrate 230 of part and the second surface 314 of exposed chip 210 of sealing 240 formed protective covered sections, to improve the radiating efficiency of chip 210.Along with the difference of product demand, the present invention more can adorn integrated circuit to form difform structure by the distribution of the screen frequency on the first area of control web plate.Fig. 5 A is the external form of the first area formed structure dress integrated circuit when the width of first direction is narrower on the web plate.Fig. 5 B is the external form of the first area formed structure dress integrated circuit when the wider width of first direction on the web plate.Finish behind the processing procedure of structure dress integrated circuit and can on structure is adorned the second surface of chip of integrated circuit, a fin 400 be installed, avoid structure dress integrated circuit that overheated defective takes place to increase the radiating efficiency of structure dress integrated circuit.The length of this fin and shape can be with the demand of product and processing procedure difference.
Utilize method of the present invention the gap of chip and substrate to be inserted in sealing, can form the interface of protective protection chip and substrate binding around the chip with on the substrate under the state that does not use mould in the mode of printing.Need use the adhesive filling mould mixture structure process of mould compared to tradition, mode of the present invention can improve the efficient of structure process and reduce the cost of structure process.Utilize different screen frequencies on the web plate of the present invention to distribute and sealing is inserted the gap of chip and substrate, can reach tradition and utilize the filler device, more can under the prerequisite that improves structure dress usefulness, avoid forming pore at structure dress IC interior with the resulting sealing flow pattern of the course of " one " font.Therefore utilize method of the present invention also can improve the quality of structure dress integrated circuit.Traditional brilliant filling in (Underfill) structure process and adhesive filling mould mixture (Molding Compound) structure process of covering, the external form of structure dress integrated circuit is a fixed shape.Utilize the structure of the formed structure of method of the present invention dress integrated circuit, the demand of visual processing procedure and product and form difform structure dress integrated circuit.Therefore utilize method of the present invention more can improve the utilization scope of structure dress integrated circuit.
In sum, the invention provides a kind of structure dress integrated circuit and its method, utilize distribution density and style design are different on the web plate of the present invention mesh enters the gap between chip and substrate with the control sealing pattern and speed and sealing is inserted gap between chip and the substrate in the mode of printing, to avoid defective at structure dress IC interior generation pore.On web plate of the present invention, comprise a first area, a second area, one the 3rd zone, one the 4th zone and one the 5th zone.The screen frequency of second area on inside, first area and first area is low than the screen frequency on the second area.The 3rd zone, the 4th zone with the 5th zone all at second area inner and the 4th zone between the 3rd regional and the 5th zone.There is no the distribution of mesh on the 5th zone and the 3rd zone all is lower than screen frequency on the second area with screen frequency on the 4th zone.The present invention at first utilizes the soldering projection on the chip to combine with substrate.The substrate that next will comprise chip is positioned on the platform and installation web plate of the present invention above chip.The last surface of on the web plate of part, coating a sealing and utilizing a scraper to cross this web plate so that sealing can be gathered on the substrate via the mesh that is distributed on the web plate and chip around, and make the sealing porous go into gap between chip and the substrate.After the sealing dry forming, chip promptly is fixed on the substrate and the structure of the integrated circuit that the structure dress is finished can be coated on segment chip in the sealing according to the demand of product and the back side of exposed chip, to improve the radiating efficiency of chip.Flow in the process in gap of chip and substrate in sealing, because sealing flows into the control that chip and the speed in the gap of substrate have been passed through the different screen frequencies distributed areas on the web plate, so sealing is with the gap of unidirectional form inflow chip and substrate and can avoid pore to result from the gap of chip and substrate.Utilize structure of the present invention and method also can improve integrated circuit structure process efficient and reduce the production cost of structure dress integrated circuit.Structure of the present invention and method more can improve the yield and the scope of application that improves structure dress integrated circuit of structure dress integrated circuit, not only have practical effect, and are design not seen before, have the enhancement of effect and progressive.
The above is preferred embodiment of the present invention only, is not in order to limit protection scope of the present invention; All other do not break away from the equivalence of being finished under the disclosed spirit and changes or modification, all should be included in the scope of claims.
Claims (8)
1. the construction method of an integrated circuit is characterized in that, this method comprises at least:
(a) provide an integrated circuit that comprises a chip and a substrate, wherein the active surface of this chip is combined to cover crystal type by several soldering projections with this substrate;
(b) place this integrated circuit on a platform, and above this chip of this integrated circuit, a web plate is installed, comprise several meshes and the different zone of several screen frequencies on this web plate;
(c) coat a sealing at the upper surface of the part of this web plate;
(d) on this web plate, move a scraper, this sealing be uniformly coated on All Ranges on this web plate, and flow into this web plate below by these several meshes with first direction, with this substrate surface of cover part and fill this chip and this substrate between the zone; And
(e) dry this sealing.
2. the construction method of integrated circuit as claimed in claim 1 is characterized in that, this scraper before can be through the wide-open web plate zone of a no mesh directly over moving to this chip.
3. the construction method of integrated circuit as claimed in claim 1 is characterized in that, the zone that this web plate is positioned at directly over this chip surface is the closed area of a no mesh.
4. the construction method of integrated circuit as claimed in claim 1 is characterized in that, this sealing is a resin.
5. the construction method of integrated circuit as claimed in claim 1 is characterized in that, should more comprise installation one fin after (e) step.
6. the construction method of integrated circuit as claimed in claim 1, it is characterized in that, wherein a second direction is perpendicular to this first direction in (d) step, and this sealing is flowed to the speed in the gap between this chip and this substrate by this second direction greater than this sealing in the speed that is gone out by the interstitial diffusion between this chip and this substrate on this first direction.
7. the construction method of integrated circuit as claimed in claim 1, it is characterized in that, this web plate can comprise: the first area, second area, the 3rd zone, the 4th zone, with the 5th zone, wherein this first area be distributed in this second, the 3rd, outside the 4th and the 5th zone, this second area is distributed in the 3rd, outside the 4th and the 5th zone, the 4th zone is between the 3rd and the 5th zone, the 5th zone is the closed area of a no mesh directly over being positioned at this chip, and screen frequency by big and little is in regular turn: this second area, this first area, the 4th zone, and the 3rd zone.
8. the construction method of integrated circuit as claimed in claim 7 is characterized in that, the 3rd zone can be the wide-open zone of a no mesh.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021468583A CN1178285C (en) | 2002-10-15 | 2002-10-15 | Method for assembling integrated circuit in printing mode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021468583A CN1178285C (en) | 2002-10-15 | 2002-10-15 | Method for assembling integrated circuit in printing mode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1405870A CN1405870A (en) | 2003-03-26 |
| CN1178285C true CN1178285C (en) | 2004-12-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021468583A Expired - Lifetime CN1178285C (en) | 2002-10-15 | 2002-10-15 | Method for assembling integrated circuit in printing mode |
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| Country | Link |
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| CN (1) | CN1178285C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4542059B2 (en) * | 2006-03-31 | 2010-09-08 | 日東電工株式会社 | Printing apparatus and printing method |
| CN105138138A (en) * | 2015-07-30 | 2015-12-09 | 山东超越数控电子有限公司 | Adhesive brushing screen plate and packaging method for reinforcing computer silicon keyboard |
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2002
- 2002-10-15 CN CNB021468583A patent/CN1178285C/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| CN1405870A (en) | 2003-03-26 |
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