CN117811385A - Active rectifying circuit based on self-adaptive adjustable capacitance delay compensation - Google Patents
Active rectifying circuit based on self-adaptive adjustable capacitance delay compensation Download PDFInfo
- Publication number
- CN117811385A CN117811385A CN202311848193.1A CN202311848193A CN117811385A CN 117811385 A CN117811385 A CN 117811385A CN 202311848193 A CN202311848193 A CN 202311848193A CN 117811385 A CN117811385 A CN 117811385A
- Authority
- CN
- China
- Prior art keywords
- coupled
- comparator
- unit
- detection circuit
- edge detection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 107
- 238000003708 edge detection Methods 0.000 claims description 87
- 230000000630 rising effect Effects 0.000 claims description 45
- 230000003044 adaptive effect Effects 0.000 claims description 33
- 230000002441 reversible effect Effects 0.000 claims description 15
- 230000001960 triggered effect Effects 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 11
- 238000005516 engineering process Methods 0.000 description 9
- 238000000034 method Methods 0.000 description 8
- 230000008569 process Effects 0.000 description 5
- 238000004804 winding Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Landscapes
- Networks Using Active Elements (AREA)
Abstract
The invention belongs to the field of power electronics and integrated circuits, and particularly provides an active rectifying circuit based on self-adaptive adjustable capacitance delay compensation. The invention can realize accurate delay compensation under different alternating current input voltages, thereby realizing lower power loss and larger output power and improving the overall performance of the rectifying circuit.
Description
Technical Field
The invention belongs to the field of power electronics and integrated circuits, and particularly provides an active rectifying circuit based on self-adaptive adjustable capacitance delay compensation.
Background
Along with the continuous development of science and technology, electronic products provide irreplaceable convenience in life of people, and as an important part in ensuring normal work of the electronic products, a power supply is required to be adapted and promoted in various ways under the current wider and wider application scenes. For example, in the biomedical field, part of human body implanted chips need to adopt an integrated isolation power supply to avoid external electrical interference, so that the safety of human bodies and equipment is ensured; in this type of power supply, an input source is an ac power supply, a dc power supply required for supplying power to other components in the chip is output, and a structure for performing an ac-dc conversion function is called a rectifier circuit.
Rectifying circuits are widely used in the fields of analog, radio frequency, and other circuits. For example, in the design of an integrated isolated power supply or a wireless power transmission system, alternating current transfers energy from a primary winding to a secondary winding through magnetic coupling of a transformer, and the energy obtained by the secondary winding is still in an alternating current form, so that a rectifying circuit is usually connected to the secondary winding to convert alternating current electric energy into direct current electric energy, so that direct current voltage is provided for other components. In order to meet the requirements of different application scenes, the current integrated isolation power supply is developed towards miniaturization, high efficiency, high power density, high reliability and the like. In the optimization of efficiency and power density, each part of the system needs to be subjected to targeted design consideration, and the rectifying circuit is taken as an important ring of the system structure, so that the influence on output power and system efficiency is not negligible.
At present, rectifying technologies can be mainly classified into active and passive technologies. The passive rectification technology realizes rectification based on the diode, has the advantages of simple structure, has the defects that the diode is conducted to have an opening voltage, and has great influence on the output power and conversion efficiency of the passive rectification in low-voltage application; the existing passive rectification technology usually adopts a schottky diode with lower starting voltage to improve efficiency, but the process requirement is higher, the process cost is increased, and the temperature characteristic is poor. The active rectifying technology adopts an active device such as an MOS tube to replace a diode, and controls the on and off of the MOS tube according to the rectifying function requirement; the problem caused by the starting voltage of the diode can be well solved because the conducting voltage between the drain electrode and the source electrode in the conducting state of the MOS tube is very low. As shown in fig. 1, in the conventional active rectification technology, a comparator compares drain voltage and source voltage of an MOS transistor to generate a gate driving voltage to control on and off of the MOS transistor; because delay exists in the processes of voltage comparison and grid driving, a MOS tube in the traditional active technology cannot be timely conducted or cut off according to drain-source voltage, so that parasitic diode conducting states and reverse conducting states exist in the working process of the MOS tube, system efficiency and output power are reduced, and particularly as the working frequency of a chip is higher, the duty ratio of the delay in a working period is larger, and negative effects are larger. Therefore, solving the delay problem becomes a key to implementing active rectification techniques.
Disclosure of Invention
The invention aims to provide an active rectifying circuit based on self-adaptive adjustable capacitance delay compensation, which compares drain voltage and source voltage at the switching time of an MOS tube in each working period between an on state and an off state, adjusts the size of an adjustable capacitor in a delay line according to a comparison result to change the charging time of the adjustable capacitor, so that the opening time of the MOS tube in the next working period from the off state to the on state and the switching time from the on state to the off state are advanced or delayed by one unit capacitor charging time step, and finally the delay in the stable working state is smaller than the unit capacitor charging time step through the iteration of a plurality of working periods. The invention can realize accurate delay compensation under different alternating current input voltages, thereby realizing lower power loss and larger output power and improving the overall performance of the rectifying circuit.
In order to achieve the above purpose, the invention adopts the following technical scheme:
an active rectifier circuit based on adaptive adjustable capacitance delay compensation, comprising: the device comprises a MOS tube, an edge detection circuit, a first adjustable delay unit, a second adjustable delay unit, a first SR latch and a driving circuit; wherein:
the first input port of the edge detection circuit is coupled to the drain electrode of the MOS tube, and the second input port of the edge detection circuit is coupled to the source electrode of the MOS tube; a first output port of an edge detection circuit is coupled to an input port of the first adjustable delay unit, and a second output port of the edge detection circuit is coupled to an input port of the second adjustable delay unit; an output port of the first adjustable delay unit is coupled to a set terminal (S) of the first SR latch, and an output port of the second adjustable delay unit is coupled to a reset terminal (R) of the first SR latch; a non-inverting output of the first SR latch is coupled to an input of the drive circuit; the output end of the driving circuit is coupled to the grid electrode of the MOS tube; the first output port of the edge detection circuit provides a first clock signal, the second output port of the edge detection circuit provides a second clock signal, and the output end of the driving circuit provides a gate control signal CTRL of the MOS tube;
the first adjustable delay unit includes: the self-adaptive adjustable capacitor comprises a first self-adaptive adjustable capacitor unit, a first switch, a first current source, a first reference voltage, a first comparator and a first rising edge detection circuit, wherein the first switch is connected with the first self-adaptive adjustable capacitor unit in parallel, and the first switch is controlled to be turned on or off through a first clock signal; one end of the current source is coupled to the direct current output voltage of the active rectifying circuit, the other end of the current source is coupled to the positive voltage end of the first self-adaptive adjustable capacitor unit, the negative voltage end of the first self-adaptive adjustable capacitor unit is coupled to the grounding end of the active rectifying circuit, the positive voltage end of the first self-adaptive adjustable capacitor unit is coupled to the positive input end of the first comparator, the first reference voltage is coupled to the reverse input end of the first comparator, the output end of the first comparator is coupled to the input end of the first rising edge detection circuit, and the output end of the first rising edge detection circuit is coupled to the output end of the first adjustable delay unit;
the first adaptively tunable capacitance unit includes: the third comparator is a discrete time comparator, the clock end of the third comparator is coupled to the grid electrode of the MOS tube, the positive input end of the third comparator is coupled to the drain electrode of the MOS tube, the negative input end of the third comparator is coupled to the source electrode of the MOS tube, and the positive input end of the third comparator is coupled to the positive input end of the MOS tubeAn output terminal is coupled to a set terminal of the second SR latch, an inverted output terminal of the third comparator and the first clock signal are respectively input to the first or gate, and the first or gate output terminal is coupled to a reset terminal of the second SR latch; the first switch capacitor group consists of n 1 The first switch capacitor units are connected in parallel, each first switch capacitor unit is composed of a controllable switch S1 i And a capacitor C1 i Series configuration (i=1, 2,., n 1 ) Controllable switch S1 i One end of the first self-adaptive adjustable capacitance unit is coupled to the positive voltage end of the first self-adaptive adjustable capacitance unit, and the other end is coupled to the capacitor C1 i Capacitor C1 i The other end of the first self-adaptive adjustable capacitance unit is coupled to the negative voltage end of the first self-adaptive adjustable capacitance unit; the counting direction signal end of the first counting unit is coupled to the non-inverting output end of the second SR latch, and the clock end of the first counting unit is coupled to the grid electrode of the MOS tube; the third comparator and the first counting unit work simultaneously, and the first counting unit counts the value N (N is more than or equal to 1 and less than or equal to N) 1 ) Generating a multipath output signal to control the conduction of corresponding N controllable switches in the first switch capacitor group, so as to realize the self-adaptive adjustment of the effective capacitance value of the first switch capacitor group;
the second adjustable delay unit includes: the second self-adaptive adjustable capacitance unit, a second switch, a second current source, a second reference voltage, a second comparator and a second rising edge detection circuit are connected in parallel, and the second switch is controlled to be turned on or turned off through a second clock signal; one end of the current source is coupled to the direct current output voltage of the active rectifying circuit, the other end of the current source is coupled to the positive voltage end of the second self-adaptive adjustable capacitor unit, the negative voltage end of the second self-adaptive adjustable capacitor unit is coupled to the grounding end of the active rectifying circuit, the positive voltage end of the second self-adaptive adjustable capacitor unit is coupled to the positive input end of the second comparator, the second reference voltage is coupled to the reverse input end of the second comparator, the output end of the second comparator is coupled to the input end of the second rising edge detection circuit, and the output end of the second rising edge detection circuit is coupled to the output end of the second adjustable delay unit;
the second adaptively tunable capacitance unit includes: a fourth comparator, a third SR latch, a second counting unit, a second switched capacitor group and a second or gate, wherein the fourth comparator is a discrete time comparator, a clock end of the fourth comparator is coupled to the gate of the MOS transistor, a positive input end of the fourth comparator is coupled to the source of the MOS transistor, a negative input end of the fourth comparator is coupled to the drain of the MOS transistor, a positive output end of the fourth comparator is coupled to the set end of the third SR latch, a negative output end of the fourth comparator and the first clock signal are respectively input to the second or gate, an output end of the second or gate is coupled to the reset end of the third SR latch, and the second switched capacitor group is formed by n 2 The second switch capacitor units are connected in parallel, each second switch capacitor unit is composed of a controllable switch S2 i And a capacitor C2 i Series configuration (i=1, 2,., n 2 ) Controllable switch S2 i One end of the second self-adaptive adjustable capacitance unit is coupled to the positive voltage end of the second self-adaptive adjustable capacitance unit, and the other end is coupled to the capacitor C2 i Capacitance C2 i The other end of the second self-adaptive adjustable capacitance unit is coupled to the negative voltage end of the second self-adaptive adjustable capacitance unit; the counting direction signal end of the second counting unit is coupled to the non-inverting output end of the third SR latch, and the clock end of the second counting unit is coupled to the grid electrode of the MOS tube; the fourth comparator and the second counting unit work simultaneously, and the second counting unit counts the data according to the count value M (M is more than or equal to 1 and less than or equal to n) 2 ) Generating a multipath output signal to control the conduction of corresponding M controllable switches in the second switch capacitor group, so as to realize the self-adaptive adjustment of the effective capacitance value of the second switch capacitor group;
the edge detection circuit includes: the fifth comparator, the third rising edge detection circuit and the first falling edge detection circuit are provided with a first input port, a second input port, a first output port and a second output port; a positive input end of the fifth comparator is coupled to a first input port of the edge detection circuit, a negative input end of the fifth comparator is coupled to the first input port of the edge detection circuit and a second input port of the edge detection circuit, a single-ended output end of the fifth comparator is coupled to the input ends of the third rising edge detection circuit and the first falling edge detection circuit, when the MOS transistor is of a PMOS type, an output end of the third rising edge detection circuit is coupled to a first output port of the edge detection circuit, and an output end of the first falling edge detection circuit is coupled to a second output port of the edge detection circuit; when the MOS tube is NMOS, the output end of the first falling edge detection circuit is coupled to the first output port of the edge detection circuit, and the output end of the third rising edge detection circuit is coupled to the second output port of the edge detection circuit.
Further, when the MOS tube is NMOS, the third comparator and the first counting unit are triggered by the clock falling edge, and the fourth comparator and the second counting unit are triggered by the clock rising edge;
when the MOS tube is of a PMOS type, the third comparator and the first counting unit are triggered by the rising edge of the clock, and the fourth comparator and the second counting unit are triggered by the falling edge of the clock.
Further, in the first adjustable delay unit:
wherein C is 1 Representing the capacitance of the capacitors in the first switched capacitor group (each capacitor C1 i The capacitance values of (a) are the same), I 1 Representing the current value, T, of the first current source max Representing the maximum period, T, of the alternating input voltage of the active rectifying circuit min Representing a minimum period of an ac input voltage of the active rectifying circuit;
in the second adjustable delay unit:
wherein C is 2 Representing the capacitance of the capacitors in the second switched capacitor group (each capacitor C2 i The capacitance values of (a) are the same), I 2 Representing the current value of the second current source.
Furthermore, the first counting unit and the second counting unit respectively comprise a reversible counter and a decoder, the clock signal end and the counting direction signal end are respectively input into the reversible counter, and the output of the reversible counter generates a signal for controlling a controllable switch in the self-adaptive adjustable capacitance unit in a multipath manner through the decoder.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides an active rectifying circuit based on self-adaptive adjustable capacitance delay compensation, which can realize self-adaptive adjustment of the on time and the off time of an MOS (metal oxide semiconductor) tube, so that in a stable working state, the delay between the on time of the MOS tube and the falling edge zero crossing time (when the MOS tube is an NMOS tube) or the rising edge zero crossing time (when the MOS tube is a PMOS tube) of drain-source voltage VDS is smaller than or equal to the capacitance charging time of a single group of switch capacitance units, the delay between the off time of the MOS tube and the rising edge zero crossing time (when the MOS tube is an NMOS tube) or the falling edge zero crossing time (when the MOS tube is a PMOS tube) of the drain-source voltage VDS is smaller than or equal to the capacitance charging time of the single group of switch capacitance units, and accurate delay compensation is realized, parasitic diode on loss caused by untimely on of the MOS tube and reverse current caused by untimely turn-off of the MOS tube are eliminated, and rectifying efficiency and output power are improved. The self-adaptive adjustment method for the on time and the off time of the MOS tube can be suitable for various different alternating current input voltages and different temperature working conditions, and is used for realizing lower power loss and higher conversion efficiency.
Drawings
Fig. 1 is a schematic diagram of an active rectifying circuit based on the conventional technology.
Fig. 2 is a schematic structural diagram of a PMOS transistor in the active rectifying circuit based on adaptive adjustable capacitance delay compensation according to the present invention.
Fig. 3 is a schematic structural diagram of an NMOS transistor in the active rectifying circuit based on adaptive adjustable capacitance delay compensation according to the present invention.
Fig. 4 is a schematic circuit diagram of a first adaptive tunable capacitor unit in an active rectifier circuit based on adaptive tunable capacitor delay compensation according to the present invention.
Fig. 5 is a schematic circuit diagram of a second adaptive capacitance unit in an active rectifying circuit based on adaptive capacitance delay compensation according to the present invention.
Fig. 6 is a schematic circuit diagram of an active rectifier circuit based on adaptive adjustable capacitive delay compensation according to the present invention.
Fig. 7 is a waveform schematic diagram of an on-time adaptive delay adjustment of an NMOS transistor for a MOS transistor in an active rectifying circuit based on adaptive capacitance delay compensation according to the present invention.
Fig. 8 is a schematic waveform diagram of the off-time adaptive delay adjustment of the MOS transistor to the NMOS transistor in the active rectifying circuit based on the adaptive capacitance delay compensation according to the present invention.
Fig. 9 is a voltage-current waveform comparison chart before and after delay compensation in an active rectifying circuit based on adaptive adjustable capacitance delay compensation according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantageous effects of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings and examples.
Example 1
As shown in fig. 2, the present embodiment provides an active rectifying circuit based on adaptive adjustable capacitance delay compensation, wherein the MOS transistor is PMOS type, a first input port of the edge detection circuit is coupled to a drain electrode of the MOS transistor, and a first output port of the edge detection circuit is coupled to a source electrode of the MOS transistor; a first output port of the edge detection circuit is coupled to an input port of the first adjustable delay unit, and a second output port of the edge detection circuit is coupled to an input port of the second adjustable delay unit; an output port of the first adjustable delay unit is coupled to a set end of the first SR latch, and an output port of the second adjustable delay unit is coupled to a reset end of the first SR latch; the non-inverting output of the first SR latch is coupled to the input of the drive circuit; the output end of the driving circuit is coupled to the grid electrode of the MOS tube, and the output end of the driving circuit provides a grid electrode control signal CTRL of the MOS tube.
Example 2
As shown in fig. 3, the present embodiment provides another active rectifying circuit based on adaptive adjustable capacitance delay compensation, in which the MOS transistor is NMOS, a first input port of the edge detection circuit is coupled to a drain of the MOS transistor, and a first output port of the edge detection circuit is coupled to a source of the MOS transistor; a first output port of the edge detection circuit is coupled to an input port of the first adjustable delay unit, and a second output port of the edge detection circuit is coupled to an input port of the second adjustable delay unit; an output port of the first adjustable delay unit is coupled to a set end of the first SR latch, and an output port of the second adjustable delay unit is coupled to a reset end of the first SR latch; the non-inverting output of the first SR latch is coupled to the input of the drive circuit; the output end of the driving circuit is coupled to the grid electrode of the MOS tube, and the output end of the driving circuit provides a grid electrode control signal CTRL of the MOS tube.
As shown in fig. 4 and 5, the circuit schematic diagrams of the first adaptive adjustable capacitance unit and the second adaptive adjustable capacitance unit are respectively corresponding; wherein:
the first adaptively tunable capacitance unit includes: the third comparator is a discrete time comparator, a clock end of the third comparator is coupled to the grid electrode of the MOS tube, a positive input end of the third comparator is coupled to the drain electrode of the MOS tube, a negative input end of the third comparator is coupled to the source electrode of the MOS tube, a positive output end of the third comparator is coupled to the set end of the second SR latch, a negative output end of the third comparator and the first clock signal are respectively input to the first OR gate, and an output end of the first OR gate is coupled to the reset end of the second SR latch; the first switch capacitor group consists of n 1 The first switch capacitor units are connected in parallel, each first switch capacitor unit is composed of a controllable switch S1 i And a capacitor C1 i Series configuration (i=1, 2,., n 1 ) Controllable switch S1 i Is coupled to the positive voltage terminal of the first adaptive adjustable capacitance unit, anotherEnd-coupled to capacitor C1 i Capacitor C1 i The other end of the first self-adaptive adjustable capacitance unit is coupled to the negative voltage end of the first self-adaptive adjustable capacitance unit; the counting direction signal end of the first counting unit is coupled to the non-inverting output end of the second SR latch, and the clock end of the first counting unit is coupled to the grid electrode of the MOS tube; the third comparator and the first counting unit work simultaneously, and the first counting unit counts the value N (N is more than or equal to 1 and less than or equal to N) 1 ) Generating a multipath output signal to control the conduction of corresponding N controllable switches in the first switch capacitor group, so as to realize the self-adaptive adjustment of the effective capacitance value of the first switch capacitor group;
the second adaptively tunable capacitance unit includes: a fourth comparator, a third SR latch, a second counting unit, a second switched capacitor group and a second or gate, wherein the fourth comparator is a discrete time comparator, a clock end of the fourth comparator is coupled to the gate of the MOS transistor, a positive input end of the fourth comparator is coupled to the source of the MOS transistor, a negative input end of the fourth comparator is coupled to the drain of the MOS transistor, a positive output end of the fourth comparator is coupled to the set end of the third SR latch, a negative output end of the fourth comparator and the first clock signal are respectively input to the second or gate, an output end of the second or gate is coupled to the reset end of the third SR latch, and the second switched capacitor group is formed by n 2 The second switch capacitor units are connected in parallel, each second switch capacitor unit is composed of a controllable switch S2 i And a capacitor C2 i Series configuration (i=1, 2,., n 2 ) Controllable switch S2 i One end of the second self-adaptive adjustable capacitance unit is coupled to the positive voltage end of the second self-adaptive adjustable capacitance unit, and the other end is coupled to the capacitor C2 i Capacitance C2 i The other end of the second self-adaptive adjustable capacitance unit is coupled to the negative voltage end of the second self-adaptive adjustable capacitance unit; the counting direction signal end of the second counting unit is coupled to the non-inverting output end of the third SR latch, and the clock end of the second counting unit is coupled to the grid electrode of the MOS tube; the fourth comparator and the second counting unit work simultaneously, and the second counting unit counts the data according to the count value M (M is more than or equal to 1 and less than or equal to n) 2 ) Generating a multiplexed output signal to control the firstCorresponding M controllable switches in the two switch capacitor groups are conducted, so that the effective capacitance value of the second switch capacitor group is adaptively adjusted;
FIG. 6 is a schematic circuit diagram of the edge detection circuit, the first adjustable delay unit, the second adjustable delay unit, the first SR latch, and the driving circuit according to embodiment 2; wherein:
the edge detection circuit comprises a fifth comparator, a third rising edge detection circuit and a first falling edge detection circuit, wherein the first input port and the second input port of the edge detection circuit are coupled to the input end of the fifth comparator, the single-ended output end of the fifth comparator is coupled to the input end of the third rising edge detection circuit and the first falling edge detection circuit, the output end of the first falling edge detection circuit is coupled to the first output port of the edge detection circuit, and the output end of the third rising edge detection circuit is coupled to the second output port of the edge detection circuit;
the first adjustable delay unit comprises a first self-adaptive adjustable capacitance unit, a first switch, a first current source, a first reference voltage, a first comparator and a first rising edge detection circuit, wherein the first switch is connected with the first self-adaptive adjustable capacitance unit in parallel, one end of the current source is coupled to the direct current output voltage of the active rectifying circuit, the other end of the current source is coupled to the positive voltage end of the first self-adaptive adjustable capacitance unit, the negative voltage end of the first self-adaptive adjustable capacitance unit is coupled to the grounding end of the active rectifying circuit, the positive voltage end of the first self-adaptive adjustable capacitance unit is coupled to the positive input end of the first comparator, the first reference voltage is coupled to the reverse input end of the first comparator, the output end of the first comparator is coupled to the input end of the first rising edge detection circuit, and the output end of the first rising edge detection circuit is coupled to the output end of the first adjustable delay unit;
the second adjustable delay unit comprises a second self-adaptive adjustable capacitance unit, a second switch, a second current source, a second reference voltage, a second comparator and a second rising edge detection circuit, wherein the second switch is connected with the second self-adaptive adjustable capacitance unit in parallel, one end of the current source is coupled to the direct current output voltage of the active rectifying circuit, the other end of the current source is coupled to the positive voltage end of the second self-adaptive adjustable capacitance unit, the negative voltage end of the second self-adaptive adjustable capacitance unit is coupled to the grounding end of the active rectifying circuit, the positive voltage end of the second self-adaptive adjustable capacitance unit is coupled to the positive input end of the second comparator, the second reference voltage is coupled to the reverse input end of the second comparator, the output end of the second comparator is coupled to the input end of the second rising edge detection circuit, and the output end of the second rising edge detection circuit is coupled to the output end of the second adjustable delay unit.
In embodiment 2, when the drain voltage of the MOS transistor (hereinafter abbreviated as VD) is smaller than the source voltage of the MOS transistor (hereinafter abbreviated as VS), that is, when VDs falls to zero, the first falling edge detection circuit detects the falling edge of the output voltage of the fifth comparator, and sends a first clock signal of a high level short pulse, the first switch is closed when the first clock signal is at a high level, so that the capacitor at the positive voltage end of the first adaptive adjustable capacitor unit discharges, the voltage VC1charge at the positive voltage end is reduced to the ground bit, then the first clock signal is low, the first switch is opened, the capacitor at the positive voltage end of the first adaptive adjustable capacitor unit starts to charge, after the first reference voltage is multiplied by the delay tcarge1 of the effective capacitance value in the first adaptive adjustable capacitor unit divided by the current value of the first current source, the first comparator outputs a low transition high voltage, the first rising edge detection circuit detects the rising edge of the output signal of the first comparator, and generates the high level signal of the short pulse, and sends the high level signal of the short pulse to the set end of the first SR, and the first SR is forward to the output end (the output end is controlled by the low transition voltage to drive the high output transistor to turn on; when VD is greater than VS, that is, when the rising edge of VDs crosses zero, the third rising edge detection circuit detects the rising edge of the output voltage of the third comparator, and sends a short pulse of high-level second clock signal, the second switch is closed when the second clock signal is high, so that the capacitor at the positive voltage end of the second adaptive adjustable capacitance unit discharges, the voltage VC2charge at the positive voltage end is reduced to the ground point, then the second clock signal is low, the second switch is opened, the capacitor at the positive voltage end of the second adaptive adjustable capacitance unit starts to charge, after the second reference voltage is multiplied by the delay Tcharge2 of the effective capacitance value in the second adaptive adjustable capacitance unit divided by the current value of the second current source, the output of the second comparator changes from low to high, the second rising edge detection circuit detects the output rising edge of the fifth comparator, the high-level signal for generating the short pulse is sent to the reset end of the first SR latch, and the output at the positive output end (Q) of the first SR latch changes from high to low, so that the driving circuit outputs a low level control transistor to cut off.
Fig. 7 and fig. 8 are schematic waveforms of the on-time and off-time adaptive delay adjustment in embodiment 2, where the first adaptive adjustable capacitor unit has the following working modes: when a grid signal CTRL of the MOS tube is changed from low level to high level, a third comparator compares VD with VS once, if VD is larger than VS, which means that the opening time of the MOS tube is earlier than the falling edge zero crossing time of VDS, then the positive output end of the third comparator outputs high level to the setting end of the second SR latch, the negative output end of the third comparator outputs low level to the reset end of the second SR latch, the positive output end Q of the second SR latch outputs high level, the counting mark input of the first counting unit is high, the first counting unit COUNT is incremented at the falling edge of the next period of the CTRL signal, a switch is controlled to be closed for multiple times, the effective capacitance value of the positive voltage end is increased by one C1i capacitance delta C1, and the capacitance charging time of the positive voltage end of the first self-adaptive adjustable capacitance unit in the first adjustable delay circuit is correspondingly increased by one C1i capacitance delta C1 charging time, namely, the step of increasing the unit capacitance charging time step is completed once; if VD is smaller than VS, after the turn-on time of the MOS transistor is delayed compared with the zero crossing time of the falling edge of VDs, the positive output end of the third comparator outputs a low level to the set end of the second SR latch, the negative output end of the third comparator outputs a high level to the reset end of the second SR latch, the positive output end Q of the second SR latch outputs a low level, the COUNT flag of the first counting unit is input to be low, the COUNT value of the first counting unit is decremented by one at the falling edge of the next period of the CTRL signal, the first switch capacitor group is controlled to close one switch, the effective value capacitance of the positive voltage end is reduced by one C1i capacitor size Δc1, the capacitance charging time of the positive voltage end of the first adaptive adjustable capacitor unit in the first adjustable delay circuit is reduced by one C1i capacitor size Δc1 in correspondence to the next working period, and one unit capacitor charging time step is reduced by one unit. After a plurality of period iterations, the effective capacitance value of the first self-adaptive adjustable capacitance unit is finally kept in a cycle of reducing delta C1 and increasing delta C1, so that the delay of the turn-on time of the MOS tube and the zero crossing time of the falling edge of the drain-source voltage VDS is smaller than or equal to the capacitance charging time of a single group of switch capacitance units in the first self-adaptive adjustable capacitance unit, and the turn-on time delay compensation is considered to be completed.
The working mode of the second self-adaptive adjustable capacitor unit is as follows: when a grid signal CTRL of the MOS tube is changed from high level to low level, a fourth comparator compares VD with VS once, if VD is smaller than VS, the turn-off time of the MOS tube is earlier than the rising edge zero crossing time of VDS, the positive output end of the fourth comparator outputs high level to the setting end of a third SR latch, the negative output end of the fourth comparator outputs low level to the reset end of the third SR latch, the positive output end Q of the third SR latch outputs high level, the counting mark input of a second counting unit is high, the COUNT of the second counting unit is increased by one along the rising edge of the CTRL signal, the second switching capacitor group is controlled to be closed by one more, the effective capacitance value of the positive voltage end is increased by one C2i capacitor size delta C2, and the capacitance charging time of the positive voltage end of the second self-adaptive adjustable capacitor unit in the first adjustable delay circuit in the next working period is correspondingly increased by one C2i capacitor size delta C2, namely the step of increasing the unit capacitor charging time step of one turn-off time is completed; if VD is greater than VS, it indicates that the turn-off time of the MOS transistor is delayed compared with the zero crossing time of the falling edge of VDs, the positive output end of the fourth comparator outputs a low level to the set end of the third SR latch, the negative output end of the fourth comparator outputs a high level to the reset end of the third SR latch, the positive output end Q of the third SR latch outputs a low level, the COUNT flag of the second counting unit is input to be low, the COUNT value of the second counting unit is decremented by one at the rising edge of the next period of the CTRL signal, the second switch capacitor group is controlled to close one switch less, the effective value capacitance of the positive voltage end is reduced by one C2i capacitor size Δc2, and the capacitor charging time of the positive voltage end of the second adaptive adjustable capacitor unit in the first adjustable delay circuit of the next working period is reduced by one C2i capacitor size Δc2 charging time, i is completed, and the turn-off time is reduced by one unit capacitor charging time step. After a plurality of period iterations, the effective capacitance value of the second self-adaptive adjustable capacitance unit is finally kept in a cycle of reducing delta C2 and increasing delta C2, so that the delay of the turn-off time of the MOS tube and the zero crossing time of the falling edge of the drain-source voltage VDS is smaller than or equal to the capacitance charging time of a single group of switch capacitance units in the second self-adaptive adjustable capacitance unit, and the turn-off time delay compensation is considered to be completed.
In addition, the third comparator and the fourth comparator output low level at the positive output end and the negative output end in the working period without clock edge triggering; the first or gate and the second or gate are respectively used for initializing the output of the first SR latch and the second SR latch when the circuit is powered on, and avoiding the condition that the MOS tube cannot be normally opened due to overlong capacitor charging delay at the initial moment.
Fig. 9 is a voltage-current waveform comparison diagram of the active rectifying circuit in embodiment 2 and the conventional active rectifying circuit in a stable working state, where VDS represents a drain-source voltage of the MOS transistor, CTRL represents a gate-source voltage of the MOS transistor, and IDS represents a drain-source current of the MOS transistor; when delay compensation is not performed, the VDS is reduced to a voltage negative value with the same magnitude as the diode conduction voltage in the corresponding time tdiode because the MOS tube is not started in time after the VDS is reduced to zero, and the parasitic diode of the MOS tube provides a current path until the MOS tube is conducted to provide the current path; after VDS rises to zero, as the MOS tube is not turned off in time, reverse current of IDS is generated, and the existence of corresponding time trc, trc and tdiode greatly influences the performance of the rectifying circuit; after delay compensation, the MOS tube is timely turned on after the VDS descends and crosses zero, and the MOS tube is timely turned off after the VDS ascends and crosses zero, so that the time of trc and tdiode is greatly shortened, and the rectification efficiency and the output power are improved.
While the invention has been described in terms of specific embodiments, any feature disclosed in this specification may be replaced by alternative features serving the equivalent or similar purpose, unless expressly stated otherwise; all of the features disclosed, or all of the steps in a method or process, except for mutually exclusive features and/or steps, may be combined in any manner.
Claims (4)
1. An active rectifying circuit based on adaptive adjustable capacitance delay compensation, comprising: the device comprises a MOS tube, an edge detection circuit, a first adjustable delay unit, a second adjustable delay unit, a first SR latch and a driving circuit; wherein:
the first input port of the edge detection circuit is coupled to the drain electrode of the MOS tube, and the second input port of the edge detection circuit is coupled to the source electrode of the MOS tube; a first output port of an edge detection circuit is coupled to an input port of the first adjustable delay unit, and a second output port of the edge detection circuit is coupled to an input port of the second adjustable delay unit; an output port of the first adjustable delay unit is coupled to a set terminal (S) of the first SR latch, and an output port of the second adjustable delay unit is coupled to a reset terminal (R) of the first SR latch; a non-inverting output of the first SR latch is coupled to an input of the drive circuit; the output end of the driving circuit is coupled to the grid electrode of the MOS tube; the first output port of the edge detection circuit provides a first clock signal, the second output port of the edge detection circuit provides a second clock signal, and the output end of the driving circuit provides a gate control signal CTRL of the MOS tube;
the first adjustable delay unit includes: the self-adaptive adjustable capacitor comprises a first self-adaptive adjustable capacitor unit, a first switch, a first current source, a first reference voltage, a first comparator and a first rising edge detection circuit, wherein the first switch is connected with the first self-adaptive adjustable capacitor unit in parallel, and the first switch is controlled to be turned on or off through a first clock signal; one end of the current source is coupled to the direct current output voltage of the active rectifying circuit, the other end of the current source is coupled to the positive voltage end of the first self-adaptive adjustable capacitor unit, the negative voltage end of the first self-adaptive adjustable capacitor unit is coupled to the grounding end of the active rectifying circuit, the positive voltage end of the first self-adaptive adjustable capacitor unit is coupled to the positive input end of the first comparator, the first reference voltage is coupled to the reverse input end of the first comparator, the output end of the first comparator is coupled to the input end of the first rising edge detection circuit, and the output end of the first rising edge detection circuit is coupled to the output end of the first adjustable delay unit;
the first adaptively tunable capacitance unit includes: the third comparator is a discrete time comparator, a clock end of the third comparator is coupled to the grid electrode of the MOS tube, a positive input end of the third comparator is coupled to the drain electrode of the MOS tube, a negative input end of the third comparator is coupled to the source electrode of the MOS tube, a positive output end of the third comparator is coupled to the set end of the second SR latch, a negative output end of the third comparator and the first clock signal are respectively input to the first OR gate, and an output end of the first OR gate is coupled to the reset end of the second SR latch; the first switch capacitor group consists of n 1 The first switch capacitor units are connected in parallel, each first switch capacitor unit is composed of a controllable switch S1 i And a capacitor C1 i Series configuration (i=1, 2,., n 1 ) Controllable switch S1 i One end of the first self-adaptive adjustable capacitance unit is coupled to the positive voltage end of the first self-adaptive adjustable capacitance unit, and the other end is coupled to the capacitor C1 i Capacitor C1 i The other end of the first self-adaptive adjustable capacitance unit is coupled to the negative voltage end of the first self-adaptive adjustable capacitance unit; the counting direction signal end of the first counting unit is coupled to the non-inverting output end of the second SR latch, and the clock end of the first counting unit is coupled to the grid electrode of the MOS tube; the third comparator and the first counting unit work simultaneously, and the first counting unit counts the value N (N is more than or equal to 1 and less than or equal to N) 1 ) Generating a multipath output signal to control the conduction of corresponding N controllable switches in the first switch capacitor group;
the second adjustable delay unit includes: the second self-adaptive adjustable capacitance unit, a second switch, a second current source, a second reference voltage, a second comparator and a second rising edge detection circuit are connected in parallel, and the second switch is controlled to be turned on or turned off through a second clock signal; one end of the current source is coupled to the direct current output voltage of the active rectifying circuit, the other end of the current source is coupled to the positive voltage end of the second self-adaptive adjustable capacitor unit, the negative voltage end of the second self-adaptive adjustable capacitor unit is coupled to the grounding end of the active rectifying circuit, the positive voltage end of the second self-adaptive adjustable capacitor unit is coupled to the positive input end of the second comparator, the second reference voltage is coupled to the reverse input end of the second comparator, the output end of the second comparator is coupled to the input end of the second rising edge detection circuit, and the output end of the second rising edge detection circuit is coupled to the output end of the second adjustable delay unit;
the second adaptively tunable capacitance unit includes: a fourth comparator, a third SR latch, a second counting unit, a second switched capacitor group and a second or gate, wherein the fourth comparator is a discrete time comparator, a clock end of the fourth comparator is coupled to the gate of the MOS transistor, a positive input end of the fourth comparator is coupled to the source of the MOS transistor, a negative input end of the fourth comparator is coupled to the drain of the MOS transistor, a positive output end of the fourth comparator is coupled to the set end of the third SR latch, a negative output end of the fourth comparator and the first clock signal are respectively input to the second or gate, an output end of the second or gate is coupled to the reset end of the third SR latch, and the second switched capacitor group is formed by n 2 The second switch capacitor units are connected in parallel, each second switch capacitor unit is composed of a controllable switch S2 i And a capacitor C2 i Series configuration (i=1, 2,., n 2 ) Controllable switch S2 i One end of the second self-adaptive adjustable capacitance unit is coupled to the positive voltage end of the second self-adaptive adjustable capacitance unit, and the other end is coupled to the capacitor C2 i Capacitance C2 i Is coupled to the second adaptively adjustable capacitance unitIs connected with the negative voltage end of the capacitor; the counting direction signal end of the second counting unit is coupled to the non-inverting output end of the third SR latch, and the clock end of the second counting unit is coupled to the grid electrode of the MOS tube; the fourth comparator and the second counting unit work simultaneously, and the second counting unit counts the data according to the count value M (M is more than or equal to 1 and less than or equal to n) 2 ) Generating a multipath output signal to control the conduction of corresponding M controllable switches in the second switch capacitor group;
the edge detection circuit includes: the fifth comparator, the third rising edge detection circuit and the first falling edge detection circuit are provided with a first input port, a second input port, a first output port and a second output port; a positive input end of the fifth comparator is coupled to a first input port of the edge detection circuit, a negative input end of the fifth comparator is coupled to the first input port of the edge detection circuit and a second input port of the edge detection circuit, a single-ended output end of the fifth comparator is coupled to the input ends of the third rising edge detection circuit and the first falling edge detection circuit, when the MOS transistor is of a PMOS type, an output end of the third rising edge detection circuit is coupled to a first output port of the edge detection circuit, and an output end of the first falling edge detection circuit is coupled to a second output port of the edge detection circuit; when the MOS tube is NMOS, the output end of the first falling edge detection circuit is coupled to the first output port of the edge detection circuit, and the output end of the third rising edge detection circuit is coupled to the second output port of the edge detection circuit.
2. The active rectifying circuit based on adaptive adjustable capacitance delay compensation according to claim 1, wherein when the MOS transistor is NMOS, the third comparator and the first counting unit are triggered by a clock falling edge, and the fourth comparator and the second counting unit are triggered by a clock rising edge;
when the MOS tube is of a PMOS type, the third comparator and the first counting unit are triggered by the rising edge of the clock, and the fourth comparator and the second counting unit are triggered by the falling edge of the clock.
3. The active rectifier circuit based on adaptive tunable capacitive delay compensation of claim 1, wherein in the first tunable delay unit:
wherein C is 1 Representing the capacitance of the capacitors in the first switched capacitor group, I 1 Representing the current value, T, of the first current source max Representing the maximum period, T, of the alternating input voltage of the active rectifying circuit min Representing a minimum period of an ac input voltage of the active rectifying circuit;
in the second adjustable delay unit:
wherein C is 2 Representing the capacitance of the capacitors in the second switched capacitor group, I 2 Representing the current value of the second current source.
4. The active rectifier circuit based on adaptive capacitance delay compensation according to claim 1, wherein the first counting unit and the second counting unit respectively comprise a reversible counter and a decoder, the clock signal end and the counting direction signal end are respectively input into the reversible counter, and the output of the reversible counter generates a signal for controlling controllable switches in the adaptive capacitance unit in a multipath manner through the decoder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311848193.1A CN117811385A (en) | 2023-12-28 | 2023-12-28 | Active rectifying circuit based on self-adaptive adjustable capacitance delay compensation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311848193.1A CN117811385A (en) | 2023-12-28 | 2023-12-28 | Active rectifying circuit based on self-adaptive adjustable capacitance delay compensation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117811385A true CN117811385A (en) | 2024-04-02 |
Family
ID=90429443
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311848193.1A Pending CN117811385A (en) | 2023-12-28 | 2023-12-28 | Active rectifying circuit based on self-adaptive adjustable capacitance delay compensation |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117811385A (en) |
-
2023
- 2023-12-28 CN CN202311848193.1A patent/CN117811385A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9118255B2 (en) | Flyback power converter and electronic apparatus | |
| US10116222B2 (en) | Soft switching flyback converter with primary control | |
| US9954455B2 (en) | Constant on time COT control in isolated converter | |
| US20130063985A1 (en) | Adaptive Dead Time Control Apparatus and Method for Switching Power Converters | |
| CN110098735B (en) | Control method of switch circuit | |
| US10651750B2 (en) | Constant on-time (COT) control in isolated converter | |
| CN103066855A (en) | System and method used for no-voltage switch in power source transformation system | |
| CN106992670B (en) | Adaptive turn-on time control circuit for PFM mode boost type DC-DC converter | |
| WO2023065789A1 (en) | Drive circuit and related product | |
| CN115347799B (en) | Synchronous rectification drive control method and system applied to flyback converter | |
| US20040140791A1 (en) | High efficiency electrical switch and DC-DC converter incorporating same | |
| CN101834527A (en) | Two-stage switching power supply conversion circuit | |
| EP3934074B1 (en) | Power supply device without ringing effect | |
| CN107040152A (en) | Active rectifier based on delay controller | |
| WO2024021695A1 (en) | Power management integrated circuit | |
| CN108667304A (en) | Synchronous rectification inverse-excitation type DC-DC power conversion equipment and control method | |
| CN105991028A (en) | Self-comparison self-oscillation DC-DC circuit | |
| US9698666B2 (en) | Power supply and gate driver therein | |
| Zhang et al. | Comparison of continuous and discontinuous current source drivers for high frequency applications | |
| CN117811385A (en) | Active rectifying circuit based on self-adaptive adjustable capacitance delay compensation | |
| WO2019140215A1 (en) | Circuits for three-level buck regulators | |
| CN111245225B (en) | Power supply conversion system and control circuit and current regulation method thereof | |
| CN204334375U (en) | Two end rectifying devices and there is the circuit of two end rectifying devices | |
| CN113783402A (en) | Self-adaptive control circuit and control method | |
| CN117811386A (en) | Active rectifying circuit with self-adaptive delay compensation function |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |