CN117792344A - UART sampling pulse generation circuit and method with decimal frequency division function - Google Patents

Abstract

The invention discloses a UART sampling pulse generating circuit with a decimal frequency dividing function and a UART sampling pulse generating method. The circuit comprises a decimal lookup table module, an adder, a comparator, a frequency division counter, a sampling point counter and a start bit synchronization module; the decimal lookup table module outputs corresponding decimal part clock numbers according to the fractional frequency value decimal signal and the sampling point position signal; the adder adds the decimal part clock number and the integral part clock number of each sampling point to be used as the total clock number output of the sampling point; the comparator compares the total number of clocks of each sampling point with the clock count value of the system clock, and outputs a sampling pulse signal when the clock count value of the system clock is equal to the total number of clocks of the sampling points. The circuit adopts the decimal lookup table module to carry out average distribution on the decimal part clock number generated during the calculation of the baud rate frequency division value, so that the accuracy of sampling pulse on asynchronous data is improved while the baud rate deviation rate is obviously reduced.

Description

UART sampling pulse generation circuit and method with decimal frequency division function

Technical Field

The invention relates to a UART sampling pulse generating circuit with a decimal frequency dividing function, and also relates to a UART sampling pulse generating method with the decimal frequency dividing function, belonging to the technical field of digital circuits.

Background

In UART (asynchronous serial) communication, it is generally necessary to sample an intermediate point of one bit of asynchronously received data to acquire a logical value of the bit data. Therefore, accurate positioning of the bisection point of one bit data is required first, and then sampling pulse is generated for sampling.

In the prior art, as shown in fig. 1, UART frequency division design generally divides one bit data into 16 sampling points, and samples at three intermediate sampling points of 7, 8, and 9 of the bit data. Wherein the time of each sampling point is 1/16 of the bit time length, i.e. each of the aliquots has the same number of clocks. The baud rate frequency division values of different baud rates are according to the formula: UART clock frequency/(UART baud rate 16), when the calculation result is not an integer but has a fractional part, the fractional part is rounded off, and then the baud rate register is configured with the resulting integer. Therefore, when the clock number obtained by the frequency division method is used for controlling the generated sampling pulse, a large error is generated between the clock number and the communication baud rate, and if the clock signals of the crystal oscillators of the receiving and transmitting parties have certain deviation, the error is accumulated, so that the problem of sampling error in UART communication is caused.

In the chinese patent application of application number 202111485076.4, a method for generating sampling pulses in a digital asynchronous communication system is disclosed. The method realizes fractional frequency division by using an error integrator, and under the condition that the time of each sampling period cannot be completely distributed evenly, the sampling error of each frame of data is controlled in a lower range by adjusting the numerical value of the error integrator.

Disclosure of Invention

The primary technical problem to be solved by the invention is to provide a UART sampling pulse generating circuit with a decimal frequency dividing function.

Another technical problem to be solved by the present invention is to provide a UART sampling pulse generating method with a fractional frequency division function.

In order to achieve the above purpose, the present invention adopts the following technical scheme:

according to a first aspect of an embodiment of the present invention, there is provided a UART sampling pulse generating circuit having a fractional frequency division function, including a fractional lookup table module, an adder, a comparator, a frequency division counter, a sampling point counter, and a start bit synchronization module; wherein,

the decimal lookup table module is used for outputting corresponding decimal part clock numbers to the adder according to the fractional frequency value decimal signal and the sampling point position signal;

the adder is used for adding the decimal part clock number and the integer part clock number of each sampling point and then outputting the sum of the clocks as the sampling point to the comparator;

the frequency division counter is used for accumulating and counting the clock number of the UART system clock and outputting the clock number to the comparator;

the comparator is used for comparing the clock total number of each sampling point with the clock count value of the system clock, and when the clock count value of the system clock is equal to the clock total number of the sampling points, the comparator outputs a sampling pulse signal to the sampling point counter;

the sampling point counter is used for accumulating and counting the sampling pulses generated by the comparator and outputting the counting result to the decimal lookup table module;

the start bit synchronous module is used for detecting asynchronous data signals, and when a start bit low-level signal of a frame data signal is detected, a reset signal is output to reset the frequency division counter and the sampling point counter to zero so that each frame of data is resynchronized from the start bit to start sampling.

Wherein preferably, the UART sampling pulse generating circuit further comprises an or gate and an inverter; and the sampling pulse signal output by the comparator provides a reset signal for the frequency division counter through the inverter and the OR gate.

Preferably, the frequency division value decimal signal end is connected with the second selection control end of the decimal lookup table module, the first selection control end of the decimal lookup table module is connected with the output end of the sampling point counter, and the output end of the decimal lookup table module is connected with the first input end of the adder; the second input end of the adder is connected with the integer signal end of the frequency division value, and the output end of the adder is connected with the first input end of the comparator; the system clock end is connected with the input end of the frequency division counter, the output end of the frequency division counter is connected with the second input end of the comparator, and the output end of the comparator is connected with the input end of the sampling point counter on one hand and the first input end of the OR gate through the inverter on the other hand; the asynchronous data signal end is connected with the input end of the initial bit synchronization module, the first output end of the initial bit synchronization module is connected with the second input end of the OR gate, and the second output end of the initial bit synchronization module is connected with the reset end of the sampling point counter; and the output end of the OR gate is connected with the reset end of the frequency division counter.

Wherein preferably the sample point counter recounts from 0 when the count value of the sample point counter exceeds the last sample point number of bits.

Preferably, the sampling pulse signal generated by the comparator is used for sampling and judging asynchronous data at one or more middle sampling points of each bit of data.

Wherein preferably the fractional lookup table module comprises a first selector and a second selector; wherein,

the first selector is used for selecting a corresponding first digital signal according to the sampling point position signal and outputting the first digital signal to the second selector; the number of input ends of the first selector is the same as the number of sampling points;

the second selector is used for selecting a corresponding fractional part clock number to output to the adder according to the fractional value fractional signal; the number of input ends of the second selector is the same as the number of bits of the first digital signal.

Preferably, each input end of the first selector is connected with one first digital signal end, the selection control end is connected with the output end of the sampling point counter, and the output end is connected with the input end of the second selector; the selection control end of the second selector is connected with the frequency division value decimal signal end, and the output end of the second selector is connected with the first input end of the adder.

Preferably, for each sampling point, each bit value from low order to high order of the first digital signal is the same as the fractional part clock number corresponding to the remainder clock from low order to high order of the sampling point.

According to a second aspect of the embodiment of the present invention, there is provided a UART sampling pulse generating method having a fractional frequency division function, including the steps of:

(1) Calculating the integer clock number of each sampling point and the remainder clock number of one bit data according to the system clock frequency, the baud rate of UART communication and the sampling point bit number of one bit data;

(2) The remainder clock number is evenly distributed from two sides to the middle in all sampling points of one bit data, so that the decimal clock number of each sampling point is obtained;

(3) Calculating the total number of clocks (Ti) of each sampling point, ti=i+di; wherein I is an integer clock number, di is a decimal clock number, and I is a sampling point position serial number;

(4) Pulse sampling is sequentially carried out on each bit data in one frame of received data;

(5) And generating a reset signal by using a low-level signal of a start bit of each frame of data in the asynchronous data, so that each frame of data is sampled from the start bit in a resynchronization mode.

Wherein preferably, in step (4):

each sampling point in each bit data is counted from zero by adopting a system clock pulse, and when the count value of the system clock pulse is equal to the total number of clocks of the sampling point, a sampling pulse signal is generated;

and at one or more middle sampling points of each bit of data, sampling and judging the asynchronous data by using the sampling pulse signals.

Compared with the prior art, the UART sampling pulse generating circuit with the decimal frequency dividing function provided by the invention has the advantages that the technical scheme that the decimal lookup table module is adopted to carry out average distribution on the decimal part clock number generated during the calculation of the baud rate frequency dividing value is adopted, so that the accuracy of sampling pulse on asynchronous data is improved while the baud rate deviation rate is obviously reduced. Therefore, the UART sampling pulse generating circuit with the decimal frequency dividing function has the advantages of ingenious and reasonable structural design, lower design cost, low deviation rate, high pulse sampling accuracy and the like.

Drawings

FIG. 1 is a diagram showing a bit data divided into 16 sampling points according to the prior art;

FIG. 2 is a schematic diagram of a UART sampling pulse generating circuit with fractional frequency division according to an embodiment of the present invention;

FIG. 3 is a schematic circuit diagram of a decimal lookup table module in an embodiment of the present invention;

FIG. 4 is a flowchart of a UART sampling pulse generating method with fractional frequency division function according to an embodiment of the present invention.

Detailed Description

The technical contents of the present invention will be described in detail with reference to the accompanying drawings and specific examples.

In the prior art, taking UART clock frequency of 32MHz as an example, UART frequency division adopts one bit data to divide into 16 sampling points, and under different UART baud rates, baud rate frequency division values, baud rate register configuration values and baud rate deviation rates are shown in table 1.

TABLE 1

In table 1, a positive deviation rate indicates a positive deviation, and a negative deviation indicates a negative deviation.

As can be seen from table 1, the baud rate frequency division value adopts the calculation formula: UART clock frequency/(UART baud rate 16) is calculated, and integer frequency division value is obtained after rounding carry is adopted to decimal part in calculation result. Since the error of the decimal part causes the deviation of the actual baud rate, when the UART baud rate adopts 115200bit/s, the deviation rate of 2.08% is generated; when the UART baud rate is 43000 bits/s, a deviation of-1.05% will result. The larger deviation, plus the deviation of the clocks of the transmitting and receiving parties, is accumulated, so that UART communication is likely to generate data error, and therefore, the problem of fractional frequency division needs to be solved.

The invention provides a UART sampling pulse generating circuit with a decimal frequency dividing function, which firstly performs the following distribution processing on a clock remainder corresponding to a decimal part generated during the calculation of a baud rate frequency dividing value.

The UART divide design divides a bit of data into 16 sampling points and samples at three intermediate sampling points of 7, 8, 9 of the bit of data. The integer part and the fractional part are generated when the baud rate frequency division value is calculated, wherein the fractional part is multiplied by 16 and rounded, the obtained clock remainder is in the range of 1-15, and the clock remainder is evenly distributed from the sampling points at two sides to the middle sampling point in 16 sampling points, namely, 1 clock pulse is added from two sides to each sampling point in the middle until the clock remainder is distributed. The result of this allocation is shown in table 2, where a clock remainder of 0 indicates no fractional part. As can be seen from table 2, the three intermediate sampling points 7, 8 and 9 can be always kept at the intermediate position of one bit data, which is favorable for the accuracy of asynchronous data sampling, so the invention adopts the mode of searching the distribution table to carry out decimal frequency division processing.

TABLE 2

As shown in FIG. 2, the UART sampling pulse generating circuit with the decimal frequency dividing function provided by the embodiment of the invention comprises a decimal lookup table module, an adder, a comparator, a frequency dividing counter, a sampling point counter, a start bit synchronizing module, an OR gate and an inverter. Wherein the fractional-value signal BRP [3: the 0 end is connected with the second selection control end of the decimal lookup table module, the first selection control end of the decimal lookup table module is connected with the output end of the sampling point counter, and the output end of the decimal lookup table module is connected with the first input end of the adder; a second input of the adder is coupled to the divide value integer signal BRP [15: the end 4 is connected with the output end of the adder, and the output end of the adder is connected with the first input end of the comparator; the system clock end is connected with the input end of the frequency division counter, the output end of the frequency division counter is connected with the second input end of the comparator, the output end of the comparator is connected with the input end of the sampling point counter on one hand, and the output end of the comparator is connected with the first input end of the OR gate through the inverter on the other hand; the asynchronous data signal RXD end is connected with the input end of the initial bit synchronization module, the first output end of the initial bit synchronization module is connected with the second input end of the OR gate, and the second output end of the initial bit synchronization module is connected with the reset end of the sampling point counter; the output end of the OR gate is connected with the reset end of the frequency division counter.

The decimal lookup table module is used for calculating a decimal signal BRP [3 ] according to the frequency division value: 0] and sampling point position signals output by the sampling point counter, and outputting corresponding fractional part clock numbers to the adder; the relationship between the input value and the output value corresponds to the relationship between the clock remainder and the sampling point and the fractional part clock number shown in table 2, for example, the input fractional value fractional signal BRP [3:0 is 7, i.e., zhong Yushu is 7, and when the sampling point is 3, the number of fractional clocks to be output is 1 as can be seen from table 2.

Wherein the fractional-value signal BRP [3:0 is a low-order 4-bit digital signal of BRP (Baud rate frequency division value signal), wherein decimal values of the low-order 4-bit digital signal are respectively represented by clock remainder 0-15 generated by fractional calculation fractional parts from small to large, and 0 represents no fractional part.

The adder is used for adding the fractional part clock number and the integer part clock number of each sampling point and outputting the added fractional part clock number and the integer part clock number to the comparator as the total number of clocks of the sampling point. The integer part clock number is represented by the divide value integer signal BRP [15:4] is provided.

Wherein the divided value integer signal BRP [15:4 is the high order 12bit digital signal of BRP, and the decimal value is the integer part clock number after multiplying by 16.

The frequency division counter is used for carrying out accumulated count on the clock number of the UART system clock and outputting the accumulated count to the comparator. When the total number of clocks of each sampling point is counted, the frequency division counter is reset and cleared once. Since the baud rate register is configured to be 16 bits, the counter is a maximum of 16 bits to prevent overflow of counts, and the count range is 0 to 65535.

The comparator is used for comparing the clock total number of each sampling point with the clock count value of the system clock, and when the clock count value of the system clock is equal to the clock total number of the sampling points, the comparator outputs a sampling pulse signal to the sampling point counter. Meanwhile, the sampling pulse signal output by the comparator provides a reset signal for the frequency division counter through the inverter and the OR gate. And the subsequent circuit module samples and judges the asynchronous data by using the sampling pulse signals at one or more middle sampling points of each bit data. For example, sampling pulses of three sampling points of 7, 8 and 9 are used for sampling asynchronous data.

The sampling point counter is used for accumulating and counting sampling pulses generated by the comparator and outputting the counting result (namely the current sampling point position) to the decimal lookup table module. When each bit data adopts 16 times of oversampling, the counting range of the sampling point counter is 0-15, and when the counting value exceeds 15, the sampling point counter starts to count again from 0.

The start bit synchronous module is used for detecting an asynchronous data signal RXD, and when a start bit low-level signal of a frame data signal is detected, a reset signal is output to reset and clear the frequency division counter and the sampling point counter, so that each frame of data is synchronized again from the start bit to start sampling.

As shown in fig. 3, in one embodiment of the present invention, the fractional lookup table module includes a first selector MUX1 and a second selector MUX2. Each input end of the first selector MUX1 is connected with a first digital signal end respectively, the selection control end is connected with the output end of the sampling point counter, and the output end is connected with the input end of the second selector MUX 2; the selection control terminal of the second selector MUX2 and the fractional-value fractional signal terminal BRP [3:0] and the output end is connected with the first input end of the adder.

The first selector MUX1 is configured to select a corresponding first digital signal according to the sampling point signals, and output the first digital signal to the second selector MUX2, where the number of input ends of the first selector MUX1 is the same as the number of sampling points. The second selector MUX2 is configured to, based on the fractional-value fractional signal BRP [3:0], selecting a corresponding fractional part clock number to output to the adder, wherein the number of input ends of the second selector MUX2 is the same as the bit number of the first digital signal.

In the present embodiment, the number of sampling point bits is 16, and therefore, the first selector MUX1 has 16 inputs; the bit number of the first digital signal is the same as the clock remainder 16, and therefore,

the second selector MUX2 also has 16 inputs. It should be noted that the first digital signal input by each input terminal of the first selector MUX1 is not in phase.

The 16 input ends of the first selector MUX1, from the input end 0 to the input end 15, represent sampling points from 0 point to 15 point respectively; the 16bit first digital signals respectively input from the input terminal 0 to the input terminal 15 respectively represent fractional part clock numbers corresponding to 16 clock residues from 0 point to 15 point in the sampling point, namely a row of numbers respectively corresponding to 0 point to 15 point in table 2. For example, the 16-bit first digital signal input at the first input terminal (0 terminal) of the first selector MUX1 is 0 xfffe= 1111 1111 1111

1110, the digital signal from low order to high order respectively represents the fractional part clock number of the clock remainder from 0 to 15. The first selector MUX1 first selects the fractional part clock number corresponding to the 16 clock remainder according to the sampling point.

The second selector MUX2 is configured to, based on the fractional-value fractional signal BRP [3: and 0], selecting the fractional part clock number corresponding to the clock remainder, and outputting the fractional part clock number to the adder. The 16 inputs of the second selector MUX2 from input 0 to input 15 represent clock remainder from 0 to 15, respectively. The 1bit digital signal input by each input terminal is from the input terminal 0 to the input terminal 15, and is respectively a 1bi digital signal from low bit to high bit, i.e. a decimal part clock number 1 or 0, of a 16bit first digital signal output by the first selector. For example, the sampling point output by the sampling point counter is 0 point, and the fractional value fractional signal BRP [3: when the clock remainder represented by 0 is 3, the output signal of the first selector MUX1 is 0 xfffe= 1111 1111 1111 1110; at this time, the order of the 1bi digital signals respectively input from the input terminal 0 to the input terminal 15 of the second selector MUX2 is 0111

1111 1111 1111, the second selector MUX2 is based on the fractional-value signal BRP [3:0] and the input signal 1 of the selection input terminal 3 is output to the adder, namely the output decimal part clock number is 1.

It should be noted that, the decimal lookup table module may be implemented by adopting other technical schemes of circuit structures, as long as the functions of the decimal lookup table shown in table 2 can be implemented, which is not limited in this embodiment.

The following describes in detail the working principle and working procedure of the UART sampling pulse generating circuit with fractional frequency division function provided by the embodiment of the invention, taking the example of calculating the fractional frequency value of the baud rate to generate 3 clock remainder by taking the figure 2 as an example. The number of clocks of the integer part in the baud rate division value calculation is 32, assuming that 8-bit data is contained in one frame of the received data.

Firstly, in the sampling process of the 1 st bit data, the values of a frequency division counter and a sampling point counter are 0 in the initial state; wherein, the value of the sampling point counter is 0, which means that the current sampling point is 0 point; fractional frequency signal BRP [3: the value of 0 is 3, which means that the fractional part of the divide calculation produces 3 clock remainder. The decimal lookup table module outputs decimal part clock number 1 according to the sampling point position value 0 and the clock remainder 3; frequency-divided value integer signal BRP [15:4] is 32, and the adder outputs the total number of clocks of the sampling point 0, i.e. the total number of clocks of the sampling point 0, which is obtained by adding the fractional part clock number 1 and the integer part clock number 32, to the comparator, i.e. the total number of clocks of the sampling point 0 is 33. When the number of the system clocks accumulated by the frequency division counter is less than 33, the comparator outputs a low level signal; when the number of the system clocks accumulated by the frequency division counter is equal to 33, the comparator outputs a high-level pulse signal to the sampling point counter, and the value of the sampling point counter is increased by 1, namely 0+1=1, which means that the current sampling point is changed to 1 point. Meanwhile, the high level signal output by the comparator provides a low level reset signal to the frequency division counter through the inverter and the OR gate, and the frequency division counter is cleared to prepare for clock counting of the next point.

When the value of the sampling point counter is changed into 1 point, the decimal lookup table module outputs the decimal part clock number still being 1 according to the sampling point value 1 and the clock remainder 3, and the adder adds the decimal part clock number 1 and the integer part clock number 32 and then outputs the decimal part clock number 1 and the integer part clock number 32 as the total number of clocks of the sampling point 1 to the comparator, namely the total number of clocks of the 1 point is 33. When the number of the system clocks accumulated by the frequency division counter is equal to 33, the comparator outputs a high-level pulse signal to the sampling point counter, and the value of the sampling point counter is increased by 1, namely 1+1=2, which means that the current sampling point is changed to 2 points. Meanwhile, the high-level signal output by the comparator provides a low-level reset signal for the frequency division counter through the inverter and the OR gate, and the frequency division counter is cleared again.

When the value of the sampling point counter is changed into 2 points, the decimal lookup table module outputs decimal part clock number 0 according to the sampling point value 2 and clock remainder 3, and the adder adds decimal part clock number 0 and integer part clock number 32 and then outputs the sum of the decimal part clock number 0 and the integer part clock number 32 as the sum of the clocks of the sampling point 2 to the comparator, namely the sum of the clocks of the 2 points is 32. When the number of the system clocks accumulated by the frequency division counter is equal to 32, the comparator outputs a high-level pulse signal to the sampling point counter, and the value of the sampling point counter is increased by 1, namely 2+1=3, which means that the current sampling point is changed to 3 points. Meanwhile, the high-level signal output by the comparator provides a low-level reset signal for the frequency division counter through the inverter and the OR gate, and the frequency division counter is cleared again.

The working conditions of sampling points from 3 points to 14 points are the same as those of the sampling points from 2 points, the number of the decimal part clocks output by the decimal lookup table module is 0, and the total number of the clocks from 3 points to 14 points is 32. And at the three sampling points of 7, 8 and 9, the subsequent circuit module performs three sampling judgment on the received asynchronous data according to the sampling pulse output by comparison. When two or three sampling results of the three sampling points are 1, judging that the logic value of the bit data is 1; if two or three sampling results are 0, the logic value of the bit data is judged to be 0. Because the three middle sampling points 7, 8 and 9 can be always kept at the middle position of one bit of data, partial signal noise can be filtered while the data sampling accuracy is ensured. After the 14-bit comparator outputs a high-level pulse signal, the value of the sampling point counter is changed to 15, which means that the current sampling point is changed to 15, namely the last sampling point of the 1 st bit data. The working process of the point location is basically the same as that of the 1 point location, and the difference is that the inside is automatically cleared after the numerical value of the sampling point counter reaches 15, so that the first sampling point location of the 2 nd bit data is restarted to count.

The sampling process of the 8bit data in one frame of data is the same as the sampling process of the 1 st bit data, when the next frame of data starts after the sampling process of the one frame of data is finished, the start bit synchronization module outputs a reset signal of a low level to reset the frequency division counter and the sampling point counter after detecting a start bit low level signal of one frame of data signal, so that each frame of data is sampled from the start bit in a resynchronization mode.

After the UART sampling pulse generating circuit with the fractional frequency division function provided by the embodiment of the invention performs frequency division sampling, taking the UART clock frequency as an example of 32MHz, UART frequency division adopts one bit data to divide into 16 sampling points, and under different UART baud rates, baud rate frequency division values, baud rate register configuration values and baud rate deviation rates are shown in table 3.

TABLE 3 Table 3

As can be seen from Table 3, the deviation from the ideal baud rate is significantly reduced at different UART baud rates compared to Table 1 of the prior art. For example, when the UART baud rate adopts 115200bit/s, the deviation rate is reduced to 0.08% from the original 2.08%; when 43000bit/s is adopted by UART baud rate, the deviation rate is reduced to 0.02% from the original 1.05%. Therefore, the technical scheme of the invention has very obvious effect of improving the baud rate deviation generated by frequency division.

The working principle and the working process of the UART sampling pulse generating circuit with the decimal frequency dividing function provided by the embodiment of the invention are described in detail. Based on the UART sampling pulse generating circuit, the embodiment of the invention further provides a UART sampling pulse generating method with a fractional frequency division function, the workflow of which is shown in fig. 4, comprising the following steps:

s1: and calculating the integer clock number I of each sampling point and the remainder clock number D of one bit data according to the baud rate B of the system clock frequency F and UART communication and the sampling point bit number N of one bit data.

The integer clock number I is the integer part of the calculation result of formula F/(b×n). The fractional part of the result calculated by the formula F/(b×n) is multiplied by the number N of sampling points and rounded to obtain the remainder clock number D, which is conceivable to be less than N. For example, assuming that the system clock frequency is 32MHz, the baud rate is 9600 bits/s, and the number of sampling point bits of one bit of data is 16, F/(b×n) = 208.3333, the integer clock number i=208; 0.3333×16= 5.3328, taking the remainder clock number d=5 (rounding).

S2: and evenly distributing the remainder clock number D from two sides to the middle in N sampling points to obtain the decimal clock number Di of each sampling point, wherein i is sampling point sequence numbers 0 to (N-1).

The allocation principle is that 1 clock pulse is allocated to each sampling point position from two sides of the sampling point position, namely a 0 point position and an N-1 point position, to the middle point position, namely an N/2 point position, until the remainder clock number D is allocated. Therefore, the value of the fractional clock number Di is only 1 or 0. The allocation principle ensures that the middle sampling point can be always kept at the middle position of one bit of data, thereby being beneficial to the accuracy of sampling.

S3: the total number of clocks per sampling point Ti, ti=i+di, is calculated. Wherein I is an integer clock number, di is a decimal clock number, and I is a sampling point position sequence number.

S4: and pulse sampling is sequentially carried out on each bit data in one frame of received data.

Typically, one frame of data includes 8bit data. And counting each sampling point position in each bit data by adopting a system clock pulse from zero, and generating a sampling pulse signal when the count value of the system clock pulse is equal to the total number Ti of clocks of the sampling point positions. And at one or more middle sampling points of each bit of data, sampling and judging the asynchronous data by using the sampling pulse signals.

S5: and generating a reset signal by using a low-level signal of a start bit of each frame of data in the asynchronous data, so that each frame of data is sampled from the start bit in a resynchronization mode.

In summary, compared with the prior art, the UART sampling pulse generating circuit with the decimal frequency dividing function provided by the invention adopts the technical scheme that the decimal lookup table module is used for carrying out average distribution on the decimal part clock number generated during the calculation of the baud rate frequency dividing value, so that the accuracy of sampling pulse to asynchronous data is improved while the baud rate deviation rate is obviously reduced. Therefore, the UART sampling pulse generating circuit with the decimal frequency dividing function has the advantages of ingenious and reasonable structural design, lower design cost, low deviation rate, high pulse sampling accuracy and the like.

It should be noted that the terms "first," "second," and "second" are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implying a number of technical features being indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

The UART sampling pulse generating circuit and method with the decimal frequency dividing function provided by the invention are described in detail. Any obvious modifications to the present invention, without departing from the spirit thereof, would constitute an infringement of the patent rights of the invention and would take on corresponding legal liabilities.

Claims (10)

1. The UART sampling pulse generating circuit with the decimal frequency dividing function is characterized by comprising a decimal lookup table module, an adder, a comparator, a frequency dividing counter, a sampling point counter and a start bit synchronization module; wherein,

the decimal lookup table module is used for outputting corresponding decimal part clock numbers to the adder according to the fractional frequency value decimal signal and the sampling point position signal;

the adder is used for adding the decimal part clock number and the integer part clock number of each sampling point and then outputting the sum of the clocks as the sampling point to the comparator;

the frequency division counter is used for accumulating and counting the clock number of the UART system clock and outputting the clock number to the comparator;

the comparator is used for comparing the clock total number of each sampling point with the clock count value of the system clock, and when the clock count value of the system clock is equal to the clock total number of the sampling points, the comparator outputs a sampling pulse signal to the sampling point counter;

the sampling point counter is used for accumulating and counting the sampling pulses generated by the comparator and outputting the counting result to the decimal lookup table module;

the start bit synchronous module is used for detecting asynchronous data signals, and when a start bit low-level signal of a frame data signal is detected, a reset signal is output to reset the frequency division counter and the sampling point counter to zero so that each frame of data is resynchronized from the start bit to start sampling.

2. The UART sampling pulse generating circuit with fractional frequency division function as recited in claim 1, wherein:

the UART sampling pulse generation circuit further comprises an OR gate and an inverter; and the sampling pulse signal output by the comparator provides a reset signal for the frequency division counter through the inverter and the OR gate.

3. The UART sampling pulse generating circuit with fractional frequency division function as recited in claim 2, wherein:

the frequency division value decimal signal end is connected with the second selection control end of the decimal lookup table module, the first selection control end of the decimal lookup table module is connected with the output end of the sampling point counter, and the output end of the decimal lookup table module is connected with the first input end of the adder; the second input end of the adder is connected with the integer signal end of the frequency division value, and the output end of the adder is connected with the first input end of the comparator; the system clock end is connected with the input end of the frequency division counter, the output end of the frequency division counter is connected with the second input end of the comparator, and the output end of the comparator is connected with the input end of the sampling point counter on one hand and the first input end of the OR gate through the inverter on the other hand; the asynchronous data signal end is connected with the input end of the initial bit synchronization module, the first output end of the initial bit synchronization module is connected with the second input end of the OR gate, and the second output end of the initial bit synchronization module is connected with the reset end of the sampling point counter; and the output end of the OR gate is connected with the reset end of the frequency division counter.

4. The UART sampling pulse generating circuit with fractional frequency division function as recited in claim 1, wherein:

when the count value of the sampling point counter exceeds the last sampling point digit, the sampling point counter starts to count again from 0.

5. The UART sampling pulse generating circuit with fractional frequency division function as recited in claim 1, wherein:

and at one or more middle sampling points of each bit of data, sampling and judging the asynchronous data by using the sampling pulse signals generated by the comparator.

6. The UART sampling pulse generating circuit with fractional frequency division function as recited in claim 1, wherein:

the decimal lookup table module comprises a first selector and a second selector; wherein,

the first selector is used for selecting a corresponding first digital signal according to the sampling point position signal and outputting the first digital signal to the second selector; the number of input ends of the first selector is the same as the number of sampling points;

the second selector is used for selecting a corresponding fractional part clock number to output to the adder according to the fractional value fractional signal; the number of input ends of the second selector is the same as the number of bits of the first digital signal.

7. The UART sampling pulse generating circuit with fractional frequency division function as recited in claim 6, wherein:

each input end of the first selector is connected with one first digital signal end respectively, the selection control end is connected with the output end of the sampling point counter, and the output end is connected with the input end of the second selector; the selection control end of the second selector is connected with the frequency division value decimal signal end, and the output end of the second selector is connected with the first input end of the adder.

8. The UART sampling pulse generating circuit with fractional frequency division function as recited in claim 6, wherein:

for each sampling point, each bit value from low order to high order of the first digital signal is the same as the fractional part clock number corresponding to the remainder clock from low order to high order of the sampling point.

9. A UART sampling pulse generation method with a decimal frequency dividing function is characterized by comprising the following steps:

(1) Calculating the integer clock number of each sampling point and the remainder clock number of one bit data according to the system clock frequency, the baud rate of UART communication and the sampling point bit number of one bit data;

(2) The remainder clock number is evenly distributed from two sides to the middle in all sampling points of one bit data, so that the decimal clock number of each sampling point is obtained;

(3) Calculating the total number of clocks (Ti) of each sampling point, ti=i+di; wherein I is an integer clock number, di is a decimal clock number, and I is a sampling point position serial number;

(4) Pulse sampling is sequentially carried out on each bit data in one frame of received data;

(5) And generating a reset signal by using a low-level signal of a start bit of each frame of data in the asynchronous data, so that each frame of data is sampled from the start bit in a resynchronization mode.

10. The UART sampling pulse generating method with fractional frequency division function as recited in claim 9, wherein in step (4):

each sampling point in each bit data is counted from zero by adopting a system clock pulse, and when the count value of the system clock pulse is equal to the total number of clocks of the sampling point, a sampling pulse signal is generated;

and at one or more middle sampling points of each bit of data, sampling and judging the asynchronous data by using the sampling pulse signals.