CN117785061A

CN117785061A - Hardware data management system, related device and write command processing method

Info

Publication number: CN117785061A
Application number: CN202311852293.1A
Authority: CN
Inventors: 黄朋; 孟鹏涛
Original assignee: Shenzhen Dapu Microelectronics Co Ltd
Current assignee: Shenzhen Dapu Microelectronics Co Ltd
Priority date: 2023-12-28
Filing date: 2023-12-28
Publication date: 2024-03-29

Abstract

The embodiment of the application relates to the field of storage equipment application, and discloses a hardware data management system, a related device and a write command processing method, wherein the hardware data management system comprises: the host processing module is used for acquiring a write command sent by the host and sending a data acquisition command to the host; and the data processing module is used for carrying out storage operation on the data and editing the effective bitmap instruction according to whether the same logical block address is stored in the hardware data management system or not, so as to send the effective bitmap instruction to the firmware. According to the method and the device, in the process of writing commands by the host, the hardware data management system interacts with the host, and the firmware is only used for receiving the effective bitmap instruction sent by the hardware data management system, so that the steps of receiving the writing commands sent by the host controller by the firmware, re-issuing the writing commands to the host controller and receiving data receiving finish information sent by the host are reduced, the writing delay is reduced, and the writing performance of the flash memory device is improved.

Description

Hardware data management system, related device and write command processing method

Technical Field

The present disclosure relates to the field of storage device applications, and in particular, to a hardware data management system, a related device, and a write command processing method.

Background

Flash memory devices, for example: the solid state disk (Solid State Drives, SSD) is a hard disk manufactured by adopting a solid state electronic memory chip array, and the solid state disk comprises a solid state disk controller and a flash memory, wherein the solid state disk controller mainly comprises a main controller and firmware.

At present, the firmware completes the writing of data from the host end to the flash memory end through data management and command scheduling of the host end and the flash memory end. The write data is mainly divided into two processes, a host write command process and a flash write command process.

In the host write command process, the first step: the main controller receives a write command sent by a host end and sends the write command to the firmware; and a second step of: when the firmware determines that the write command meets the receiving condition, the firmware re-transmits the write command to the main controller, and the main controller transmits data receiving information to the firmware after receiving the data; and a third step of: after confirming that the main controller completes data receiving, the firmware constructs a flash memory write command and issues the flash memory write command to the main controller. During a flash write command, the host controller writes data from a designated double rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SDRAM) to corresponding locations in the flash memory in accordance with the flash write command.

In the process of implementing the present application, the inventor finds that at least the following problems exist in the prior art:

during the host write command, the firmware and the host controller need to perform three interactive operations, including: the firmware receives a write command sent by the main controller, the firmware re-sends the write command to the main controller, the main controller sends data receiving completion information to the firmware, and frequent interaction operation of the main controller and the firmware can bring write delay, so that the write performance of the flash memory device is reduced, and the performance stability is deteriorated.

Disclosure of Invention

The embodiment of the application provides a hardware data management system, a related device and a write command processing method, so as to reduce the interaction operation of a main controller and firmware, reduce write delay and improve the write performance of flash memory equipment.

The embodiment of the application provides the following technical scheme:

in a first aspect, an embodiment of the present application provides a hardware data management system, where the hardware data management system is applied to a flash memory device, the flash memory device is communicatively connected to a host, the flash memory device includes firmware and a flash memory medium, and the hardware data management system includes:

the host processing module is used for acquiring a write command sent by the host and sending a data acquisition command to the host so as to receive a first logical block address and data corresponding to the data acquisition command sent by the host;

The data processing module is used for carrying out storage operation on the data and editing the effective bitmap instruction according to whether the same logical block address is stored in the hardware data management system or not, so that the effective bitmap instruction is sent to the firmware;

the valid bitmap instruction is used for indicating whether the firmware sends a flash memory write command to the hardware data management system, and the flash memory write command is used for indicating the hardware data management system to store data to the flash memory medium.

In a second aspect, an embodiment of the present application provides a memory control chip, including:

the hardware data management system of the first aspect;

and the firmware is connected with the hardware data management system and is used for acquiring the effective bitmap instruction and sending a flash memory write command to the hardware data management system.

In a third aspect, an embodiment of the present application provides a flash memory device, including:

the memory control chip of the second aspect;

and the at least one flash memory medium is in communication connection with the memory control chip.

In a fourth aspect, an embodiment of the present application provides a data transmission system, including:

the host is used for issuing a write command to the flash memory device;

the flash memory device of the third aspect, in communication with a host, for storing data according to a write command.

In a fifth aspect, an embodiment of the present application provides a write command processing method, where the write command processing method is applied to the flash memory device of the third aspect, and the flash memory device is communicatively connected to a host, and the write command processing method includes:

acquiring a write command sent by a host, and sending a data acquisition command to the host;

receiving a first logical block address and data sent by a host;

and performing storage operation on the data according to the first logic block address.

In a sixth aspect, embodiments of the present application also provide a non-volatile computer-readable storage medium storing computer-executable instructions that, when executed by a processor, cause the processor to perform a write command processing method as in the fifth aspect.

The beneficial effects of the embodiment of the application are that: in a situation different from the prior art, the hardware data management system provided in the embodiment of the present application is applied to a flash memory device, where the flash memory device is communicatively connected to a host, the flash memory device includes firmware and a flash memory medium, and the hardware data management system includes: the host processing module is used for acquiring a write command sent by the host and sending a data acquisition command to the host so as to receive a first logical block address and data corresponding to the data acquisition command sent by the host; the data processing module is used for carrying out storage operation on the data and editing the effective bitmap instruction according to whether the same logical block address is stored in the hardware data management system or not, so that the effective bitmap instruction is sent to the firmware; the valid bitmap instruction is used for indicating whether the firmware sends a flash memory write command to the hardware data management system, and the flash memory write command is used for indicating the hardware data management system to store data to the flash memory medium.

In one aspect, a write command sent by a host is obtained through a hardware data management system, a data obtaining command is sent to the host to receive a first logical block address and data sent by the host, and an effective bitmap command is sent to firmware.

On the other hand, through the hardware data management system, according to whether the same logical block address is stored in the hardware data management system, the data are stored, the effective bitmap instruction is edited, and the effective bitmap instruction is sent to the firmware to indicate whether the firmware sends a flash memory write command to the hardware data management system, when the same logical block address exists in a plurality of write commands sent by the host, the delay of writing a plurality of data corresponding to the same logical block address into the flash memory can be reduced, and therefore the write performance of the flash memory device is improved.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which the figures of the drawings are not to be taken in a limiting sense, unless otherwise indicated.

Fig. 1 is a schematic structural diagram of a flash memory device according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a hardware data management system according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a detailed structure of a hardware data management system according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a write command sent by a host according to an embodiment of the present application;

FIG. 5 is a schematic diagram of storing data in a hardware data management system according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a flash write command sent by firmware according to an embodiment of the present application;

FIG. 7 is a schematic diagram of storing another data in a hardware data management system according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a flash write command sent by another firmware according to an embodiment of the present application;

FIG. 9 is a schematic diagram of storing still another data in a hardware data management system according to an embodiment of the present application;

FIG. 10 is a schematic diagram of a flash write command sent by another firmware according to an embodiment of the present application;

FIG. 11 is a schematic diagram of a processing flow of a write command when the granularity of data of a first logical block address is the same as the granularity of a minimum unit of a flash memory device according to an embodiment of the present application;

FIG. 12 is a schematic diagram of a processing flow of a write command when the granularity of data of a first logical block address is different from the granularity of a minimum unit of a flash memory device according to an embodiment of the present application;

FIG. 13 is a schematic diagram of a memory control chip according to an embodiment of the present disclosure;

FIG. 14 is a schematic diagram of another embodiment of a flash memory device;

fig. 15 is a schematic structural diagram of a data transmission system according to an embodiment of the present application;

FIG. 16 is a flowchart of a method for processing a write command according to an embodiment of the present disclosure;

FIG. 17 is a schematic diagram of interaction of a host, a hardware data management system, and firmware provided by an embodiment of the present application;

fig. 18 is a detailed flowchart of a write command processing method according to an embodiment of the present application.

Reference numerals illustrate:

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

It should be noted that, if not conflicting, the various features in the embodiments of the present application may be combined with each other, which is within the protection scope of the present application. In addition, while functional block division is performed in a device diagram and logical order is shown in a flowchart, in some cases, the steps shown or described may be performed in a different order than the block division in the device, or in the flowchart. Moreover, the words "first," "second," "third," and the like as used herein do not limit the data and order of execution, but merely distinguish between identical or similar items that have substantially the same function and effect.

The following specifically describes the technical scheme of the present application with reference to the drawings of the specification:

referring to fig. 1, fig. 1 is a schematic structural diagram of a flash memory device according to an embodiment of the present application;

as shown in fig. 1, the flash memory device 100 includes a connector 101, a memory control chip 102, other peripheral units 103, a cache unit 104, and a flash memory medium 105.

Wherein, the connector 101 connects the storage control chip 102 with a host computer, and the host computer is used for communication with the host computer, for example: a computer or server; a memory control chip 102, connected to the connector 101, other peripheral units 103, the cache unit 104, and the flash memory medium 105, for managing an internal system of the flash memory device as a control operation unit, where the memory control chip 102 includes, but is not limited to, a solid state disk controller; the peripheral unit 103 is connected with the memory control chip 102 and comprises a serial port, a sensor, a register, a power chip and other components; the cache unit 104 is connected to the memory control chip 102, and is used as a cache and algorithm table storage unit, and the cache unit 104 is typically a dynamic random access memory (Dynamic Random Access Memory, DRAM).

The Flash memory medium 105, which is a storage medium of the Flash memory device 100, is also referred to as a Flash memory, a Flash memory, or a Flash granule, and is used as a storage unit for storing user data, system data, or the like. A plurality of channels are present between the memory control chip 102 and the flash memory medium 105, and one channel is independently connected to one flash memory medium, for example: channel 0 connects to one flash medium, channel 1 connects to one flash medium, … …, channel x connects to one flash medium.

In the embodiment of the application, the flash memory device includes, but is not limited to, a solid state disk, the solid state disk includes a solid state disk controller and a flash memory, and the solid state disk controller mainly includes a main controller and firmware. The read-write performance and performance stability are always an important index of the solid state disk.

Based on this, the embodiment of the application provides a hardware data management system, on one hand, through the interaction between the hardware data management system and the host in the process of writing commands by the host, the interaction operation between the host controller and the firmware is reduced, the writing delay is reduced, and the writing performance of the flash memory device is improved; on the other hand, through the hardware data management system, according to whether the same logical block address is stored in the hardware data management system, the data are stored, the effective bitmap instruction is edited, and the effective bitmap instruction is sent to the firmware to indicate whether the firmware sends a flash memory write command or not.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a hardware data management system according to an embodiment of the present application;

In an embodiment of the present application, the hardware data management system is applied to a flash memory device, where the flash memory device is communicatively connected to a host, and the flash memory device includes firmware and a flash memory medium.

As shown in fig. 2, the hardware data management system 200 includes a host processing module 201 and a data processing module 202. Wherein the host processing module 201 and the data processing module 202 are communicatively coupled.

The host processing module 201 is configured to obtain a write command sent by a host, and send a data obtaining command to the host, so as to receive a first logical block address and data corresponding to the data obtaining command sent by the host.

The data processing module 202 is configured to store data and edit an effective bitmap instruction according to whether the same logical block address is stored in the hardware data management system, so as to send the effective bitmap instruction to the firmware. The valid bitmap instruction is used for indicating whether the firmware sends a flash memory write command to the hardware data management system, and the flash memory write command is used for indicating the hardware data management system to store data to the flash memory medium.

Referring to fig. 3, fig. 3 is a detailed structural schematic diagram of a hardware data management system according to an embodiment of the present application;

as shown in fig. 3, the hardware data management system 200 includes a host processing module 201, a data processing module 202, and a firmware processing module 203. The data processing module 202 is respectively connected with the host processing module 201 and the firmware processing module 203 in a communication manner.

The hardware data management system 200 further includes a buffer space (not shown), where the buffer space is used to store the logical block address and the corresponding data, for example: and storing the first logic block address and the data to be written corresponding to the first logic block address.

The write command includes a start logical block address (StartLogical Block Address, SLBA) which is a start position of a logical block requiring a write operation, and an address Length (lba_length) which is an address range of a logical block requiring a write operation from the start logical block address, and the first logical block address is any logical block address (Logical Block Address, LBA) within the address Length from the start logical block address.

The data acquisition command is used for indicating the host to send the data corresponding to the logical block addresses to the hardware data management system, the data acquisition command comprises a first command or a second command, the first command is used for indicating the host to integrally send the data corresponding to the plurality of first logical block addresses to the hardware data management system, and the second command is used for indicating the host to send the data corresponding to the plurality of first logical block addresses to the hardware data management system in a segmented mode.

In the embodiment of the present application, the host processing module 201 is specifically configured to: receiving a write command sent by a host; determining the size of an idle space in the cache space; if the size of the free space is greater than or equal to the address length, a first command is sent to the host; and if the size of the free space is smaller than the address length, sending a second command to the host according to the size of the free space.

Specifically, the host processing module 201 receives a write command sent by a host, and determines the size of an empty space in the cache space, where the empty space is a storage space in an empty state in the cache space, and the empty space may be used to store data to be written corresponding to the first logical block address. It will be appreciated that the hardware data management system performs fragmentation management on the cache space, and when a certain storage space in the cache space is released, the size of the free space is not necessarily increased immediately, so that the hardware data management system supports segmentation to acquire data according to a write command sent by the host.

Specifically, if the size of the free space is greater than or equal to the address length, the host processing module 201 applies for a storage space with the size of the address length to the cache space to store data that is subsequently sent by the host, and sends a first command to the host, so that the host integrally sends data corresponding to a plurality of addresses of the first logical block to the hardware data management system 200.

If the size of the free space is smaller than the address length, the host processing module 201 determines the amount of data that can be stored in the free space according to the size of the free space, and sends a second command to the host, so that the host sends the data corresponding to the first logical block addresses one by one to the hardware data management system 200 in a segmented manner. Wherein the second command includes the amount of data that the free space is capable of storing, and the host computer sends the corresponding amount of data to the hardware data management system 200 in segments according to the amount.

Further, the host processing module 201 receives each first logical block address sent by the host and the data corresponding to the first logical block address (i.e. the data to be written in), stores the data in the buffer space, establishes a mapping relationship between each first logical block address and the data position of the corresponding data in the buffer space through a hash algorithm, and stores the mapping relationship in the hash table. Wherein the hash table is stored in a cache space, the hash algorithm includes, but is not limited to, a cuckoo hash algorithm (Cuckoo Hashing Algorithm). The cuckoo hash algorithm is an algorithm for implementing hash tables, the basic idea of which is to use two hash tables to store data, each consisting of a set of hash functions and an array of fixed size.

It will be appreciated that as the storage space of the host increases, the range of LBAs increases, requiring a very large space if LBA search matches are made directly. Therefore, the method adopts the hash algorithm to process the LBA based on the thought that less calculation is exchanged for larger space, and comprises three processing modes: LBA insertion, LBA lookup, and LBA deletion.

The data processing module 202 is configured to store data and edit an effective bitmap instruction according to whether the same logical block address is stored in the hardware data management system, so as to send the effective bitmap instruction to the firmware.

The valid bitmap instruction includes a start logical block address, an address length, and a valid bitmap parameter, each valid bit of the valid bitmap parameter corresponds to a first logical block address, each valid bit of the valid bitmap parameter is used to indicate whether the corresponding first logical block address needs to perform a flash write operation, each valid bit of the valid bitmap parameter may be set to a first value or a second value, the first value indicates that the corresponding first logical block address needs to perform a flash write operation, and the second value indicates that the corresponding first logical block address does not need to perform a flash write operation. Illustratively, the first value is 1 and the second value is 0.

Specifically, after the host processing module 201 receives any one of the first logical block address and the corresponding data, three situations exist in the hardware data management system 200, where the three situations are as follows:

first case: the same logical block address does not exist within the hardware data management system 200.

Second case: the hardware data management system 200 has a second logical block address within it that is the same as the first logical block address, and the second logical block address does not have a flash write status flag.

Third case: within the hardware data management system 200 there is a second logical block address that is the same as the first logical block address, and the second logical block address has a flash write status flag. The flash write status flag is used to indicate that the logical block address is performing a flash write operation, and the second logical block address is a logical block address stored in the buffer space before the host processing module 201 receives the first logical block address.

Based on this, the data processing module 202 performs a corresponding storage operation on the data corresponding to the first logical block address and edits the valid bitmap instruction according to whether the same logical block address is stored in the hardware data management system, so as to send the valid bitmap instruction to the firmware, so as to indicate whether the firmware sends the flash memory write command to the hardware data management system.

In this embodiment of the present application, when the granularity of the data of the first logical block address is the same as the granularity of the minimum unit of the flash memory device, the data processing module 202 is specifically configured to: based on a hash algorithm, searching a second logical block address stored in a cache space by taking each first logical block address as a key word in the cache space, and determining whether the same logical block address exists in the cache space; when a certain first logical block address is different from a second logical block address stored in the cache space, storing the first logical block address and corresponding data into the cache space, and setting the corresponding bit of the first logical block address in the effective bitmap parameter as a first numerical value.

Specifically, when the granularity of the data of the first logical block addresses and the granularity of the minimum unit of the flash memory device are both 4K, the data processing module 202 searches the hash table in the cache space for the second logical block addresses stored in the hash table by using each first logical block address as a Key (Key) based on the cuckoo hash algorithm. If the data processing module 202 queries that the hash table exists in the second logical block address which is the same as a certain first logical block address, the data processing module 202 determines that the same logical block address exists in the cache space; if the data processing module 202 does not query the hash table for the second logical block address that is the same as the certain first logical block address, the data processing module 202 determines that the same logical block address does not exist in the cache space.

Further, if the data processing module 202 determines that the same logical block address does not exist in the cache space, that is, a certain first logical block address is different from a second logical block address stored in the cache space, the data processing module 202 stores the first logical block address and corresponding data in the cache space, and sets a corresponding bit of the first logical block address in the valid bitmap parameter to a first value, for example: and setting the corresponding bit of the first logical block address in the valid bitmap parameter to 1 to indicate that the first logical block address needs to perform flash memory writing operation.

If the data processing module 202 determines that the same logical block address exists in the cache space, that is, if a certain first logical block address is the same as a certain second logical block address stored in the cache space, the data processing module 202 performs a corresponding storage operation on the data corresponding to the first logical block address and edits the valid bitmap instruction according to whether the second logical block address has the flash memory writing status flag.

In the embodiment of the present application, the data processing module 202 is further configured to: when a certain first logic block address is the same as a second logic block address stored in the cache space and the second logic block address does not have a flash memory writing state mark, replacing data corresponding to the first logic block address with data corresponding to the second logic block address stored in the cache space; the corresponding bit of the first logical block address in the valid bitmap parameter is set to a second value.

Specifically, when a certain first logical block address is the same as a second logical block address stored in the cache space and the second logical block address does not have a flash memory writing status flag, the data processing module 202 replaces data corresponding to the second logical block address stored in the cache space with data corresponding to the first logical block address, and sets a corresponding bit of the first logical block address in the valid bitmap parameter to a second value, for example: the corresponding bit of the first logical block address in the valid bitmap parameter is set to 0 to indicate that the first logical block address does not require a flash write operation. It will be appreciated that when the hardware data management system is performing a flash write operation on data corresponding to a logical block address, the hardware data management system sets a flash write status flag for the logical block address.

In the embodiment of the present application, the data processing module 202 is further configured to: when a certain first logic block address is the same as a second logic block address stored in the cache space and the second logic block address has a flash memory writing state mark, storing data corresponding to the first logic block address to a backup position in the cache space; the corresponding bit of the first logical block address in the valid bitmap parameter is set to a first value.

Specifically, when a certain first logical block address is the same as a second logical block address stored in the cache space and the second logical block address has a flash write status flag, the data processing module 202 stores data corresponding to the first logical block address to a backup location in the cache space, and sets a corresponding bit of the first logical block address in the valid bitmap parameter to a first value, for example: and setting the corresponding bit of the first logical block address in the valid bitmap parameter to 1 to indicate that the first logical block address needs to perform flash memory writing operation. It will be appreciated that since the cache space is based on fragmentation management, the backup locations within the cache space may be located at any storage location in free space, such as: the backup location may be adjacent to the storage location of the data corresponding to the second logical block address, which is not limited in this embodiment of the present application.

Further, the data processing module 202 determines, for each first logical block address included in a write command issued by the host, whether the same logical block address is stored in the hardware data management system, so as to perform a corresponding storage operation on data corresponding to the first logical block address, and set a corresponding bit of each first logical block address in an effective bitmap parameter until each effective bit of the effective bitmap parameter corresponding to the write command is set, and sends an effective bitmap instruction to the firmware.

Referring to fig. 4, fig. 4 is a schematic diagram of a write command sent by a host according to an embodiment of the present application;

as shown in fig. 4, the host sequentially issues a write command 1, a write command 2, and a write command 3 to the hardware data management system. Wherein, each first logical block address in the write command 1 is a logical block address 0 (LBA 0), a logical block address 1 (LBA 1), a logical block address 2 (LBA 2), and a logical block address 3 (LBA 3), respectively; each first logical block address in the write command 2 is a logical block address 2 (LBA 2), a logical block address 3 (LBA 3), a logical block address 4 (LBA 4), a logical block address 5 (LBA 5), respectively; each first logical block address in the write command 3 is a logical block address 4 (LBA 4), a logical block address 5 (LBA 5), a logical block address 6 (LBA 6), a logical block address 7 (LBA 7), respectively.

When the granularity of the data of the first logical block address is the same as the granularity of the minimum unit of the flash memory device, namely, the granularity of the data of the first logical block address and the granularity of the minimum unit of the flash memory device are both 4K.

When the data granularity of each first logical block address in the write command 1-write command 3 of fig. 4 is 4K, which is the same as the granularity of the minimum unit 4K of the flash memory device:

after issuing the write command 1, the data processing module 202 sequentially determines that the second logical block address identical to the LBA0, LBA1, LBA2, and LBA3 does not exist in the cache space, stores the data corresponding to the LBA0, LBA1, LBA2, and LBA3 in the cache space, and sets the corresponding bits of the valid bitmap parameters of the LBA0, LBA1, LBA2, and LBA3 to 1 to indicate that the flash memory write operation is required by the LBA0, LBA1, LBA2, and LBA3, and then the data processing module 202 sends a valid bitmap instruction to the firmware to inform that the data reception of the firmware write command 1 is completed, and indicates that the flash memory write operation is required by the LBA0, LBA1, LBA2, and LBA3 in the firmware write command 1. The starting logical block address in the valid bitmap instruction is LBA0, address length is 4, and valid bitmap parameter is 4' b1111.

It will be appreciated that the valid_bit_map=n' bbbcd, where n represents the address length, i.e., the number of first logical block addresses in a write command, and A, B, C, D represents the valid bit, D, C, B, A corresponds in turn to each first logical block address in the write command starting from the starting logical block address. For example: for write command 1, d, C, B, A correspond to LBA0, LBA1, LBA2, LBA3 in sequence.

Further, after receiving the valid bitmap instruction of the write command 1, the firmware determines that all of the LBA0, LBA1, LBA2, and LBA3 in the write command 1 need to perform a flash write operation, so that flash write commands corresponding to the LBA0, LBA1, LBA2, and LBA3 are sequentially sent to the hardware data management system.

After the write command 2 is issued, since the hardware data management system has already processed the write command 1, at this time, the data processing module 202 determines, based on the hash algorithm, that there are second logical block addresses in the cache space that are the same as LBA2 and LBA3 in the write command 2, and when neither of the two second logical block addresses has the flash memory write status flag, the data processing module 202 replaces the data corresponding to the two second logical block addresses with the data corresponding to LBA2 and LBA3 in the write command 2, and sets the corresponding bits of both LBA2 and LBA3 in the valid bitmap parameter to 0.

Meanwhile, the data processing module 202 determines, based on the hash algorithm, that the same logical block addresses as those of the LBA4 and the LBA5 in the write command 2 do not exist in the buffer space, stores the data corresponding to the LBA4 and the LBA5 in the buffer space, and sets the corresponding bits of the LBA4 and the LBA5 in the valid bitmap parameter to 1. The data processing module 202 then sends a valid bitmap instruction to the firmware to inform the firmware that the data reception of the firmware write command 2 is completed, and indicate that neither LBA2 nor LBA3 in the firmware write command 2 needs to perform a flash write operation, and that LBA4 and LBA5 need to perform a flash write operation. The starting logical block address in the valid bitmap instruction is LBA2, address length is 4, and valid bitmap parameter is 4' b1100. Wherein, for write command 2, D, C, B, A in the valid bitmap parameter (n' bABCD) corresponds to LBA2, LBA3, LBA4, LBA5 in sequence.

Further, after receiving the valid bitmap instruction of the write command 2, the firmware determines that neither LBA2 nor LBA3 in the write command 2 needs to perform a flash write operation, and LBA4 and LBA5 need to perform a flash write operation, so that flash write commands corresponding to LBA4 and LBA5 are sequentially sent to the hardware data management system. It will be appreciated that for a first logical block address where a flash write operation is not required, the firmware does not send a corresponding flash write command to the hardware data management system.

After the write command 3 is issued, since the hardware data management system has already processed the write command 2, at this time, the data processing module 202 determines, based on the hash algorithm, that there are second logical block addresses in the cache space that are the same as the LBA4 and LBA5 in the write command 3, and when neither of the two second logical block addresses has the flash memory write status flag, the data processing module 202 replaces the data corresponding to the two second logical block addresses with the data corresponding to the LBA4 and LBA5 in the write command 3, and sets the corresponding bits of the LBA4 and LBA5 in the valid bitmap parameter to 0.

Meanwhile, the data processing module 202 determines, based on the hashing algorithm, that the same logical block address as the LBA6, LBA7 in the write command 3 does not exist in the cache space, and sets the corresponding bits of the LBA6, LBA7 in the valid bitmap parameter to 1. The data processing module 202 then sends a valid bitmap instruction to the firmware to inform the firmware of the end of the data reception of the firmware write command 3, and indicates that neither LBA4 nor LBA5 in the firmware write command 3 needs to perform a flash write operation, and both LBA6 and LBA7 need to perform a flash write operation. The starting logical block address in the valid bitmap instruction is LBA4, address length is 4, and valid bitmap parameter is 4' b1100. Wherein D, C, B, A in the valid bitmap parameter (n' bABCD) corresponds to LBA4, LBA5, LBA6, LBA7 in sequence for write command 3.

Further, after receiving the valid bitmap instruction of the write command 3, the firmware determines that neither LBA4 nor LBA5 in the write command 3 needs to perform a flash write operation, and LBA6 and LBA7 need to perform a flash write operation, so that flash write commands corresponding to LBA6 and LBA7 are sequentially sent to the hardware data management system.

Referring to fig. 5, fig. 5 is a schematic diagram illustrating storage of data in a hardware data management system according to an embodiment of the present disclosure;

fig. 5 is a schematic diagram showing the storage of the data corresponding to the first logical block address in the write command 1-write command 3 in the buffer space in the hardware data management system, which is obtained according to the above processing manner after the hardware data management system receives the write command 1-write command 3 in fig. 4.

As shown in fig. 5, the hardware data management system stores only one corresponding data for each logical block address. Wherein d_lba0 represents data corresponding to LBA0, d_lba1 represents data corresponding to LBA1, d_lba2 represents data corresponding to LBA2, d_lba3 represents data corresponding to LBA3, d_lba4 represents data corresponding to LBA4, d_lba5 represents data corresponding to LBA5, d_lba6 represents data corresponding to LBA6, and d_lba7 represents data corresponding to LBA 7.

Referring to fig. 6, fig. 6 is a schematic diagram of a flash write command sent by firmware according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a number of flash write commands sent by firmware to the hardware data management system when the hardware data management system processes write command 1-write command 3 of FIG. 4 in the manner described above.

As shown in fig. 6, the firmware sequentially transmits flash write commands corresponding to LBA0, LBA1, LBA2, LBA3, LBA4, LBA5, LBA6, and LBA7 to the hardware data management system.

Therefore, the hardware data management system only receives the flash memory write commands corresponding to the LBA0, LBA1, LBA2, LBA3, LBA4, LBA5, LBA6 and LBA7 respectively, compared with the prior art that the host controller needs to receive the flash memory write commands corresponding to the LBA0, LBA1, LBA2 and LBA3 in the write command 1 respectively, the flash memory write commands corresponding to the LBA2, LBA3, LBA4 and LBA5 in the write command 2 respectively, and the total of 12 flash memory write commands corresponding to the LBA4, LBA5, LBA6 and LBA7 in the write command 3 respectively, when the same logical block address exists in a plurality of write commands sent by the host, the number of the flash memory write commands is reduced, and the write delay is reduced when the latest data corresponding to the logical block address is written to the corresponding position of the flash memory by the hardware data management system.

Referring to fig. 7, fig. 7 is a schematic diagram illustrating storage of another data in a hardware data management system according to an embodiment of the present disclosure;

specifically, after the hardware data management system receives the write command 1 in fig. 4, the data processing module 202 sequentially determines that the second logical block addresses that are the same as LBA0, LBA1, LBA2, and LBA3 do not exist in the cache space, stores the data corresponding to LBA0, LBA1, LBA2, and LBA3 in the cache space, and sets the valid bitmap parameter to 4' b1111, so as to send the valid bitmap instruction to the firmware, so as to indicate that all of LBA0, LBA1, LBA2, and LBA3 in the firmware write command 1 need to perform the flash memory write operation.

After the hardware data management system receives the write command 2 in fig. 4, since the hardware data management system has already processed the write command 1, at this time, the data processing module 202 determines, based on the hashing algorithm, that there is a second logical block address in the buffer space that is the same as the LBA2 and LBA3 in the write command 2, and when both the second logical block addresses have the flash write status flag, the data processing module 202 stores the data corresponding to the LBA2 and LBA3 in the write command 2 to the backup position in the buffer space, and sets the corresponding bits of the LBA2 and LBA3 in the valid bitmap parameter to 1.

Meanwhile, the data processing module 202 determines that the same logical block addresses as those of the LBA4 and the LBA5 in the write command 2 do not exist in the cache space based on the hash algorithm, and sets the corresponding bits of the LBA4 and the LBA5 in the valid bitmap parameter to 1, at this time, the valid bitmap parameter is 4' b1111, so that the data processing module 202 sends a valid bitmap instruction to the firmware to indicate that the LBA2, the LBA3, the LBA4 and the LBA5 in the firmware write command 2 all need to perform flash memory write operations.

After the hardware data management system receives the write command 3 in fig. 4, since the hardware data management system has already processed the write command 2, at this time, the data processing module 202 determines, based on the hashing algorithm, that there is a second logical block address in the buffer space that is the same as the LBA4 and LBA5 in the write command 3, and when both the second logical block addresses have the flash write status flag, the data processing module 202 stores the data corresponding to the LBA4 and LBA5 in the write command 3 to the backup location in the buffer space, and sets the corresponding bits of the LBA4 and LBA5 in the valid bitmap parameter to 1.

Meanwhile, the data processing module 202 determines that the same logical block addresses as those of the LBA6 and the LBA7 in the write command 3 do not exist in the cache space based on the hash algorithm, stores data corresponding to the LBA6 and the LBA7 in the cache space, and sets corresponding bits of the LBA6 and the LBA7 in the valid bitmap parameter to 1, at this time, the valid bitmap parameter is 4' b1111, so that the data processing module 202 sends a valid bitmap instruction to the firmware to indicate that the LBA4, the LBA5, the LBA6 and the LBA7 in the firmware write command 3 all need to perform flash memory write operations.

In this case, as shown in fig. 7, the hardware data management system stores the data corresponding to each logical block address in the write command 1-write command 3 into the buffer space.

Wherein d_lba0 represents data corresponding to LBA0 in command 1, d_lba1 represents data corresponding to LBA1 in command 1, d_lba2 represents data corresponding to LBA2 in command 1, d_lba2 'represents data corresponding to LBA2 in command 2, d_lba3 represents data corresponding to LBA3 in command 1, d_lba3' represents data corresponding to LBA3 in command 2, d_lba4 represents data corresponding to LBA4 in command 2, d_lba4 'represents data corresponding to LBA4 in command 3, d_lba5 represents data corresponding to LBA5 in command 2, d_lba5' represents data corresponding to LBA5 in command 3, d_lba6 represents data corresponding to LBA6 in command 3, and d_lba7 represents data corresponding to LBA7 in command 3.

Referring to fig. 8, fig. 8 is a schematic diagram of a flash write command sent by another firmware according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a number of flash write commands sent by firmware to a hardware data management system when the hardware data management system stores data in the manner of FIG. 7.

As shown in fig. 8, the firmware sequentially transmits a flash write command corresponding to LBA0 in command 1, a flash write command corresponding to LBA1 in command 1, a flash write command corresponding to LBA2 in command 1, a flash write command corresponding to LBA3 in command 1, a flash write command corresponding to LBA2 in command 2 (LBA 2 'in fig. 8), a flash write command corresponding to LBA3 in command 2 (LBA 3' in fig. 8), a flash write command corresponding to LBA4 in command 2, a flash write command corresponding to LBA5 in command 2 (LBA 4 'in fig. 8), a flash write command corresponding to LBA5 in command 3 (LBA 5' in fig. 8), a flash write command corresponding to LBA6 in command 3, and a flash write command corresponding to LBA7 in command 3 to the hardware data management system.

In some embodiments, when the granularity of the data of the first logical block address is different from the granularity of the smallest unit of the flash memory device, the data processing module 202 is configured to: acquiring effective sector parameters; determining the data granularity of the current write command according to the effective sector parameters; when a certain first logical block address is different from a logical block address stored in the cache space and at least one bit in the effective sector parameter is a second value, storing the first logical block address and corresponding data into the cache space, and setting each effective bit of the effective bitmap parameter as the second value; the valid bitmap parameters are sent to the firmware along with the data granularity of the current write command.

Specifically, when the granularity of the data of the first logical block address is 512B and the granularity of the minimum unit of the flash memory device is 4K, the granularity of the data of the first logical block address is different from the granularity of the minimum unit of the flash memory device, and LBA0, LBA1, LBA2, LBA3, LBA4, LBA5, LBA6, and LBA7 in fig. 4 belong to 8 partial units of LBA0 with the granularity of 4K.

When the hardware data management system receives the first logical block address of 512B and the corresponding data sent by the host, the data processing module 202 obtains the effective sector parameters sent by the nonvolatile memory flash memory module (NVMe module), and determines the data granularity of the current write command according to the effective sector parameters. The valid sector parameters are used for indicating whether a plurality of logical block addresses in the current write command form a complete 4KB, and each valid bit of the valid sector parameters is used for indicating whether the corresponding logical block address is acquired.

It can be understood that, in the process of sending data to the hardware data management system, the host computer passes through the NVMe module, and the NVMe module sends the valid sector parameters corresponding to the current write command to the hardware data management system. The effective sector parameter sector_valid=n' bbabcd_efgh, where N represents the quotient of the granularity of the smallest unit of the flash memory device and the data granularity of the first logical block address, for example: when the granularity of the data of the first logical block address is 512B and the granularity of the minimum unit of the flash memory device is 4K, n=8, and abcd_efgh corresponds to 8 partial units of LBA0 with the granularity of 4K, that is, valid bits, H, G, F, E, D, C, B, A sequentially correspond to LBA0, LBA1, LBA2, LBA3, LBA4, LBA5, LBA6, and LBA7 of 512B. The data granularity of the write command is the product of the data granularity of the first logical block address and the number of the first logical block addresses.

For example: when the hardware data management system receives the data corresponding to the write command 1 in fig. 4, the data processing module 202 simultaneously acquires the valid sector parameters sent by the NVMe module. Since write command 1 includes only 512B LBA0, LBA1, LBA2, and LBA3, the valid sector parameter is 8' B0000_1111, which indicates that only 512B LBA0, LBA1, LBA2, and LBA3 are acquired, and the data granularity of the write command is 512b×4.

Further, the data processing module 202 queries whether a second logical block address identical to a certain first logical block address is stored in the hardware data management system based on the cuckoo hash algorithm.

If a certain first logical block address is different from a second logical block address stored in the cache space, and at least one bit in the valid sector parameter is a second value, the data processing module 202 stores the first logical block address and the corresponding data in the cache space, and sets each valid bit of the valid bitmap parameter to the second value. After each valid bit in the valid bitmap parameter corresponding to a write command is set, the data processing module 202 sends the valid bitmap parameter and the data granularity of the current write command to the firmware, so as to inform the firmware that the data receiving of the current write command is finished, and instruct the firmware to perform subsequent operations.

For example: after issuing the write command 1 in fig. 4, the data processing module 202 sequentially determines that the second logical block addresses identical to the LBA0, LBA1, LBA2, and LBA3 in the write command 1 do not exist in the buffer space, stores the data corresponding to the LBA0, LBA1, LBA2, and LBA3 in the buffer space, and sets the valid bitmap parameter corresponding to the write command 1 to 4' b0000.

It will be appreciated that when 8 partial units of LBA with data granularity of 4K are not all received and cannot form LBA0 with data granularity of 4K, the data processing module 202 sets the valid bitmap parameter of the current write command to 4' b0000 to indicate that each first logical block address in the current write command of the firmware does not need to perform the flash write operation.

Further, the firmware receives the valid bitmap parameter sent by the data processing module 202 and the data granularity of the current write command, and if each valid bit in the valid bitmap parameter is a second value, for example, each valid bit is 0, the firmware determines not to send the flash write command to the hardware data management system.

And simultaneously, the firmware sends a filling read command to the hardware data management system according to the effective bitmap parameter and the data granularity of the current write command, wherein the filling read command is used for indicating the hardware data management system to read data from the flash memory medium.

For example: the effective bitmap parameter corresponding to the write command 1 in fig. 4 is 4' B0000, which only includes 4 LBA0, LBA1, LBA2, and LBA3 of 512B, where LBA4-LBA7 is absent, LBA0 with data granularity of 4K cannot be formed, at this time, data corresponding to LBA0 with data granularity of 4K needs to be read out from the flash memory medium, and data corresponding to LBA0-LBA3 of 512B is subjected to merging operation (merge) to obtain a complete 4K data, and then the 4K data is written into the flash memory. Therefore, after determining that LBA0-LBA3 of 4 512B in the write command 1 cannot form LBA0 with a data granularity of 4K, the firmware sends a fill read command to the hardware data management system, so that the hardware data management system reads data corresponding to LBA0 with a data granularity of 4K from the flash memory medium.

In some embodiments, when the granularity of the data of the first logical block address is different from the granularity of the smallest unit of the flash memory device, the data processing module 202 is further configured to: when a certain first logical block address is the same as a second logical block address stored in the cache space and at least one bit in the effective sector parameters is a second numerical value, replacing data corresponding to the first logical block address with data corresponding to the second logical block address stored in the cache space; each valid bit of the valid bitmap parameter is set to a second value.

Specifically, when a certain first logical block address is the same as a second logical block address stored in the cache space and at least one bit in the valid sector parameter is a second value, the data processing module 202 replaces the data corresponding to the second logical block address stored in the cache space with the data corresponding to the first logical block address, and sets each valid bit of the valid bitmap parameter to the second value.

For example: after issuing write command 2 in FIG. 4, the data processing module 202 receives a valid sector parameter of 8' B0011_1111, indicating that LBAs 0-LBA5 of 512B have been obtained. Since the hardware data management system has already processed the write command 1, at this time, the data processing module 202 determines, based on the hash algorithm, that there is a second logical block address in the buffer space that is the same as LBA2 and LBA3 in the write command 2, and at least one bit in the valid sector parameter is 0, and the data processing module 202 replaces the data corresponding to these two second logical block addresses with the data corresponding to LBA2 and LBA3 in the write command 2.

Meanwhile, the data processing module 202 determines, based on the hash algorithm, that the same logical block address as the LBA4 and LBA5 in the write command 2 does not exist in the cache space, stores the data corresponding to the LBA4 and LBA5 in the cache space, and sets the valid bitmap parameter corresponding to the write command 2 to 4' b0000. Thus, the firmware does not send a flash write command to the hardware data management system after receiving the valid bitmap parameter corresponding to write command 2 sent by the data processing module 202.

In some embodiments, when the granularity of the data of the first logical block address is different from the granularity of the smallest unit of the flash memory device, the data processing module 202 is further configured to: setting the last bit of the valid bitmap parameter as a first value when each bit in the valid sector parameter is the first value; the valid bitmap parameters and the data granularity of the current write command are sent to the firmware to cause the firmware to send the flash write command to the hardware data management system.

Specifically, when the host issues all of 8 partial units LBA0-LBA7 of LBA0 with a data granularity of 4K through multiple write commands, the NVMe module determines that the effective sector parameter at this time is 8' b1111_1111, and issues the effective sector parameter to the hardware data management system.

After receiving the first logical block address and the data sent by the host and the valid sector parameters sent by the NVMe module, the data processing module 202 queries whether a second logical block address identical to a certain first logical block address is stored in the hardware data management system. If a certain first logical block address is different from a second logical block address stored in the cache space, and each valid bit in the valid sector parameters is a first value, the data processing module 202 stores the first logical block address and corresponding data into the cache space; if a certain first logical block address is the same as a second logical block address stored in the cache space, and each valid bit in the valid sector parameters is a first value, the data processing module 202 replaces the data corresponding to the second logical block address stored in the cache space with the data corresponding to the first logical block address.

The data processing module 202 then sets the last bit of the valid bitmap parameter to a first value and sends the valid bitmap parameter with the data granularity of the current write command to the firmware to cause the firmware to send the flash write command to the hardware data management system.

For example: after issuing write command 3 in FIG. 4, the data processing module 202 receives a valid sector parameter of 8' B1111_1111, indicating that LBAs 0-LBA7 of 512B have been obtained. Since the hardware data management system has already processed the write command 2, at this time, the data processing module 202 determines, based on the hash algorithm, that there are second logical block addresses in the buffer space that are the same as the LBAs 4 and 5 in the write command 3, and the data processing module 202 replaces the data corresponding to the two second logical block addresses with the data corresponding to the LBAs 4 and 5 in the write command 3.

Meanwhile, the data processing module 202 determines that the same logical block addresses as those of the LBAs 6 and 7 in the write command 3 do not exist in the buffer space based on the hash algorithm, and stores the data corresponding to the LBAs 6 and 7 in the buffer space. Then, the data processing module 202 sets the last bit of the valid bitmap parameter corresponding to the write command 3 to the first value, where the valid bitmap parameter is 4' b0001, and sends the valid bitmap parameter and the data granularity of the current write command to the firmware, so that the firmware sends the flash write command to the hardware data management system. It will be appreciated that an effective bitmap parameter of 4' B0001 indicates that LBA0 with a data granularity of 4K can be flash written, and that the flash device can only be flash written when the host issues LBA0-LBA7 of 512B, all combined into a complete 4K.

Referring to fig. 9, fig. 9 is a schematic diagram illustrating storage of still another data in a hardware data management system according to an embodiment of the present application;

FIG. 9 is a schematic diagram illustrating the storage of the data obtained by processing the write commands 1-3 in FIG. 4 in the above manner in a hardware data management system when the granularity of the data of the first logical block address is different from the granularity of the minimum unit of the flash memory device.

As shown in fig. 9, the data corresponding to LBA0-LBA7 of 512B are all stored with d_lba0 of the same data granularity of 4K. D_lba0 represents data corresponding to LBA0 with a data granularity of 4K consisting of LBA0 to LBA7 of 512B.

Referring to fig. 10, fig. 10 is a schematic diagram of a flash write command sent by another firmware according to an embodiment of the present application;

FIG. 10 is a schematic diagram of a flash write command sent by firmware to a hardware data management system when the hardware data management system stores data in the manner of FIG. 9.

As shown in fig. 10, the firmware only sends a flash write command to the hardware data management system, where the flash write command is a flash write command corresponding to LBA0 with a data granularity of 4K.

Further, if the firmware has issued a fill read command corresponding to LBA0 of 4K to the hardware data management system, the firmware needs to wait for the hardware data management system to complete the read operation and issue a flash write command.

Firmware processing module 203, configured to: and acquiring a flash memory write command sent by the firmware, and writing data into the flash memory medium according to the flash memory write command.

In the embodiment of the present application, the firmware processing module 203 is specifically configured to: acquiring a flash memory write command sent by firmware; based on a hash algorithm, determining a storage position of data in a hardware data management system by taking a first logic block address as a key word; writing data from the storage location to the flash memory medium based on the target physical address; a write flag is sent to the firmware to cause the firmware to update a mapping table of logical addresses and physical addresses.

The flash memory write command comprises a first logical block address and a target physical address, wherein the target physical address is a physical address in a flash memory medium to which data corresponding to the first logical block address needs to be written, and a write mark is used for indicating that the current flash memory write command operation is completed.

Specifically, the firmware processing module 203 receives a flash memory write command sent by the firmware, and based on a hash algorithm, uses a first logical block address in the flash memory write command as a key, queries a mapping relationship between each first logical block address stored in the hash table and a data position of corresponding data in a cache space, and determines a storage position of the data corresponding to the first logical block address in the cache space. The firmware processing module 203 then reads the data from the storage location in the cache space and writes it to the target physical address in the flash media. After the write operation is completed, the firmware processing module 203 sends a write flag to the firmware.

Correspondingly, after receiving the writing mark, the firmware identifies the writing mark, determines that the hardware data management system completes the flash memory writing operation, and updates the physical address corresponding to the first logical block address into the target physical address in a mapping table (Logical address To Physical address, L2P) of the logical address and the physical address. And the firmware sends a deleting instruction to the hardware data management system, wherein the deleting instruction is used for instructing the hardware data management system to delete the mapping relation between the first logic block address stored in the hash table and the data position of the corresponding data in the cache space.

Further, after receiving the deleting instruction, the hardware data management system deletes the mapping relation between the first logic block address stored in the hash table and the data position of the corresponding data in the cache space based on a hash algorithm.

In some embodiments, when the first data and the second data corresponding to the first logical block address are stored in the hardware data management system at the same time, the firmware processing module 203 is configured to: after the first data corresponding to the first logical block address is written into the flash memory medium, the second data corresponding to the first logical block address is written into the flash memory medium.

Specifically, the first data corresponds to different write commands with the second data, for example: the hardware data management system in fig. 7 stores d_lba3 and d_lba3', where d_lba3 is first data corresponding to the first logical block address LBA3 in the write command 1, and d_lba3' is second data corresponding to the first logical block address LBA3 in the write command 2.

When the firmware processing module 203 prepares to write the second data d_lba3' corresponding to the LBA3 into the flash memory medium, it is queried that the first data d_lba3 corresponding to the LBA3 is being written into the flash memory medium, and then the firmware processing module 203 pauses the write operation of the d_lba3', writes the d_lba3 into the flash memory medium, and then writes the d_lba3' into the flash memory medium.

In some embodiments, when the granularity of data of the first logical block address is different from the granularity of the smallest unit of the flash memory device, the firmware processing module 203 is configured to: acquiring a filling read command sent by firmware; reading data corresponding to the third logical block address from the flash memory medium according to the filling read command; acquiring a flash memory write command sent by firmware, and combining data corresponding to N first logic block addresses with data corresponding to a third logic block address according to the flash memory write command to obtain combined data; the combined data is written to the flash medium.

The filling read command comprises a third logical block address and a physical address corresponding to the third logical block address, the data granularity of the third logical block address is the same as the granularity of the minimum unit of the flash memory device, and the N first logical block addresses are part of units of the third logical block address.

Specifically, when the granularity of data of the first logical block address is different from the granularity of the minimum unit of the flash memory device, for example: when the granularity of the data of the first logical block address is 512B and the granularity of the minimum unit of the flash memory device is 4K, the firmware processing module 203 obtains the filling read command sent by the firmware, and reads the data corresponding to the third logical block address from the flash memory medium according to the physical address corresponding to the third logical block address in the filling read command. After obtaining the flash memory write command sent by the firmware, the firmware processing module 203 determines storage positions of data corresponding to the N first logical block addresses 512B included in the third logical block address in the buffer space based on the hash algorithm according to the third logical block address in the flash memory write command, so as to combine the data corresponding to the N first logical block addresses 512B with the data corresponding to the third logical block address to obtain combined data, and then write the combined data into the target physical address in the flash memory medium.

For example: for write command 1 in FIG. 4, after determining that LBAs 0-LBA3 of 4 512B in write command 1 cannot constitute LBA0 with data granularity of 4K, the firmware sends a fill read command to the hardware data management system, the fill read command including a physical address corresponding to LBA0 with data granularity of 4K. The firmware processing module 203 reads data corresponding to the LBA0 with the data granularity of 4K from the flash memory medium according to the physical address corresponding to the LBA0 with the data granularity of 4K.

After obtaining the flash memory write command sent by the firmware, the firmware processing module 203 obtains data corresponding to 4 LBA0-LBA3 of 512B included in the data granularity of 4K according to the LBA0 of the data granularity of 4K in the flash memory write command, so as to combine the data corresponding to 4 LBA0-LBA3 of 512B with the data corresponding to the LBA0 of the data granularity of 4K to obtain combined data, and then writes the combined data into the target physical address in the flash memory medium.

In an embodiment of the present application, by providing a hardware data management system, the hardware data management system is applied to a flash memory device, the flash memory device is communicatively connected to a host, the flash memory device includes firmware and a flash memory medium, and the hardware data management system includes: the host processing module is used for acquiring a write command sent by the host and sending a data acquisition command to the host so as to receive a first logical block address and data corresponding to the data acquisition command sent by the host; the data processing module is used for carrying out storage operation on the data and editing the effective bitmap instruction according to whether the same logical block address is stored in the hardware data management system or not, so that the effective bitmap instruction is sent to the firmware; the valid bitmap instruction is used for indicating whether the firmware sends a flash memory write command to the hardware data management system, and the flash memory write command is used for indicating the hardware data management system to store data to the flash memory medium.

On the other hand, compared with the prior art, in the process of writing commands in the flash memory, the firmware checks the writing command field to determine whether the same writing command is in writing operation before the flash memory writing command is constructed, if the repeated writing command exists, the firmware pauses the current writing command, waits for the execution of the previous writing command to be ended, and then continues to execute the current writing command. This can result in increased write latency when the host issues the same write command frequently.

According to the method, the device and the system, the hardware data management system stores data and edits an effective bitmap instruction according to whether the same logical block address is stored in the hardware data management system or not, and sends the effective bitmap instruction to the firmware to indicate whether the firmware sends a flash memory write command to the hardware data management system or not.

Referring to fig. 11, fig. 11 is a schematic diagram of a processing flow of a write command when the granularity of data of a first logical block address is the same as the granularity of a minimum unit of a flash memory device according to an embodiment of the present application;

in this embodiment of the present application, the granularity of data of the first logical block address is 4K, the granularity of the smallest unit of the flash memory device is 4K, and the granularity of data of the first logical block address and the data of the smallest unit are the same.

As shown in fig. 11, when the data granularity of the first logical block address is the same as the granularity of the minimum unit of the flash memory device, the processing flow of the write command includes:

Step S1101: the host sends a write command;

specifically, the host 151 transmits a write command to the hardware data management system 200. Correspondingly, the hardware data management system 200 receives the write command, determines the size of the free space in the cache space, and applies for the storage space with the size of the address length to the cache space when the size of the free space is larger than or equal to the address length in the write command so as to store the data subsequently sent by the host; when the size of the free space is smaller than the address length, determining the amount of data which can be stored in the free space according to the size of the free space.

Step S1102: the hardware data management system sends a data acquisition command;

specifically, when the size of the free space is greater than or equal to the address length, the hardware data management system 200 sends a first command to the host 151, so that the host 151 integrally sends data corresponding to a plurality of first logical block addresses one by one to the hardware data management system 200; when the size of the free space is smaller than the address length, the hardware data management system 200 sends a second command to the host 151, so that the host 151 sends the data corresponding to the first logical block addresses one by one to the hardware data management system 200 in segments.

Step S1103: the host sends data;

specifically, the host 151 transmits the first logical block address and corresponding data to the hardware data management system 200 in response to a data acquisition command transmitted by the hardware data management system 200.

Accordingly, the hardware data management system 200 stores data into the cache space, and performs a storage operation and edits a valid bitmap instruction according to whether the same logical block address is stored in the hardware data management system 200.

Step S1104: the hardware data management system sends an effective bitmap instruction;

specifically, the hardware data management system 200 sends a valid bitmap instruction to the firmware 1021 to inform the firmware 1021 that the data reception of the current write command is completed, and instruct the firmware 1021 whether to send the flash write command to the hardware data management system 200.

Step S1105: firmware sends a flash memory write command;

specifically, firmware 1021 sends a flash write command to hardware data management system 200, where the flash write command includes a first logical block address and a target physical location.

Step S1106: the hardware data management system writes the data into the flash memory medium;

specifically, the hardware data management system 200 writes the data corresponding to the first logical block address into the target physical location in the flash memory medium 105 from the inside of the hardware data management system 200 according to the flash memory write command.

Step S1107: and finishing the execution of the flash memory write command.

Specifically, after the write operation is completed, the hardware data management system 200 sends a write flag to the firmware 1021 to inform that the flash write command is completed. Accordingly, the firmware identifies the write flag, and updates the mapping table of logical addresses and physical addresses.

Referring to fig. 12, fig. 12 is a schematic diagram of a processing flow of a write command when the granularity of data of a first logical block address is different from the granularity of a minimum unit of a flash memory device according to an embodiment of the present application;

in this embodiment of the present application, the granularity of data of the first logical block address is 512B, the granularity of the smallest unit of the flash memory device is 4K, and the granularity of data of the first logical block address and the data of the first logical block address are different.

As shown in fig. 12, when the granularity of data of the first logical block address is different from the granularity of the minimum unit of the flash memory device, the processing flow of the write command includes:

step S1201: the host sends a write command;

specifically, the host 151 transmits a write command to the hardware data management system 200. Accordingly, the hardware data management system 200 receives the write command, determines the size of the free space in the buffer space, and applies for the storage space with the size of the address length to the buffer space when the size of the free space is greater than or equal to the address length in the write command, so as to store the data subsequently sent by the host 151; when the size of the free space is smaller than the address length, determining the amount of data which can be stored in the free space according to the size of the free space.

Step S1202: the hardware data management system sends a data acquisition command;

Step S1203: the host sends data;

Step S1204: the hardware data management system sends an instruction;

specifically, the hardware data management system 200 sends an instruction to the firmware 1021, where the instruction includes a valid bitmap parameter and a data granularity of a current write command, so as to inform the firmware 1021 that the data reception of the current write command is finished, and instruct the firmware 1021 whether to send a padding read command or a flash write command to the hardware data management system 200.

Step S1205: the firmware sends a filling read command;

specifically, the firmware 1021 sends a send stuff read command to the hardware data management system 200, the stuff read command including the third logical block address and a physical address corresponding to the third logical block address.

Step S1206: the hardware data management system reads out the data;

specifically, the hardware data management system 200 reads the data corresponding to the third logical block address from the flash memory medium 105 to the inside of the hardware data management system 200 according to the physical address corresponding to the third logical block address.

Step S1207: finishing the data reading;

specifically, after reading the data corresponding to the third logical block address, the hardware data management system 200 sends reading completion information to the firmware 1021, where the reading completion information is used to indicate that the hardware data management system 200 completes the data reading operation.

Step S1208: firmware sends a flash memory write command;

specifically, firmware 1021 sends a flash write command to hardware data management system 200, where the flash write command includes a third logical block address and a target physical location.

Step S1209: the hardware data management system writes the data into the flash memory medium;

specifically, the hardware data management system 200 writes the data corresponding to the third logical block address into the target physical location in the flash memory medium 105 from the inside of the hardware data management system 200 according to the flash memory write command.

It is understood that it is not necessary to perform steps S1205-S1207 after each execution of step S1204. When the N first logical block addresses included in the current write command cannot form the third logical block address with the data granularity of 4K, step S1205 to step S1207 are required to be performed, and the data corresponding to the third logical block address is read out from the flash memory medium, so that the data corresponding to the third logical block address and the data corresponding to the N first logical block addresses are combined to obtain combined data, and the combined data is written into the target physical location in the flash memory medium.

Step S1210: finishing the execution of the flash memory write command;

specifically, after the write operation is completed, the hardware data management system 200 sends a write flag to the firmware 1021 to inform that the flash write command is completed. Accordingly, firmware 1021 identifies the write flag, and updates the mapping table of logical addresses and physical addresses.

Referring to fig. 13, fig. 13 is a schematic structural diagram of a memory control chip according to an embodiment of the present disclosure;

as shown in fig. 13, the memory control chip 102 includes a hardware data management system 200 and firmware 1021. Wherein hardware data management system 200 is communicatively coupled to firmware 1021.

Wherein the hardware data management system 200 includes a host processing module 201 and a data processing module 202.

In some embodiments, hardware data management system 200 also includes a firmware processing module. The firmware processing module is used for: and acquiring a flash memory write command sent by the firmware, and writing data into the flash memory medium according to the flash memory write command.

Firmware 1021 is coupled to hardware data management system 200 for obtaining valid bitmap instructions and sending flash write commands to hardware data management system 200.

In an embodiment of the present application, by providing a memory control chip, the memory control chip includes a hardware data management system and firmware. On one hand, the method and the device can reduce the interaction operation of the main controller and the firmware and reduce the write delay; on the other hand, the method and the device can reduce delay of writing a plurality of data corresponding to the same logical block address into the flash memory and improve writing performance of the flash memory device.

Specifically, referring to fig. 14, fig. 14 is a schematic structural diagram of another flash memory device according to an embodiment of the present application;

as shown in fig. 14, the flash memory device 100 includes a memory control chip 102 and at least one flash memory medium 105, and fig. 14 exemplifies one flash memory medium 105. Wherein the flash memory medium 105 is communicatively connected to the memory control chip 102.

The storage control chip 102 is configured to obtain a write command sent by a host, process the write command, obtain data sent by the host, and store the data in the flash memory medium 105.

Flash memory medium 105 for storing data.

In an embodiment of the present application, by providing a flash memory device, the flash memory device includes a memory control chip and at least one flash memory medium. The method and the device can reduce write delay and improve write performance of the flash memory device.

Referring to fig. 15, fig. 15 is a schematic structural diagram of a data transmission system according to an embodiment of the present application;

as shown in fig. 15, the data transfer system 150 includes a host 151 and a flash memory device 100. Wherein host 151 is communicatively coupled to flash memory device 100.

The host 151 is configured to issue a write command and data to the flash memory device 100.

The flash memory device 100 is used for storing data according to a write command issued by the host 151.

In an embodiment of the present application, a data transmission system is provided, which includes a host and a flash memory device. According to the method and the device, the delay of writing the data sent by the host into the flash memory device can be reduced, and the writing performance of the flash memory device is improved.

Referring to fig. 16, fig. 16 is a flowchart illustrating a write command processing method according to an embodiment of the present disclosure;

the write command processing method is applied to the flash memory device, the flash memory device is in communication connection with the host, and the flash memory device comprises a hardware data management system and firmware. The hardware data management system comprises a host processing module, a data processing module, a firmware processing module and a cache space.

As shown in fig. 16, the write command processing method includes:

step S1601: acquiring a write command sent by a host, and sending a data acquisition command to the host;

specifically, the host processing module obtains a write command sent by the host, and determines the size of the free space in the cache space. When the size of the free space is larger than or equal to the address length in the write command, the host processing module applies for a storage space with the size of the address length to the cache space so as to store data which is subsequently sent by the host, and sends a first command to the host, so that the host integrally sends data with a plurality of first logic block addresses in one-to-one correspondence to the hardware data management system.

When the size of the free space is smaller than the address length, the host processing module determines the amount of data which can be stored in the free space according to the size of the free space, and sends a second command to the host, so that the host can send the data corresponding to the addresses of the first logic blocks one by one to the hardware data management system in a segmented mode.

Step S1602: receiving a first logical block address and data sent by a host;

specifically, the data processing module receives the first logical block address and the data sent by the host.

Step S1603: and performing storage operation on the data according to the first logic block address.

Specifically, the data processing module performs a storage operation on the data and edits an effective bitmap instruction according to whether the same logical block address is stored in the cache space, so as to send the effective bitmap instruction to the firmware, so as to indicate whether the firmware sends a flash memory write command to the hardware data management system.

In the case that the data granularity of the first logical block address is the same as the granularity of the minimum unit of the flash memory device:

when a certain first logical block address is different from a second logical block address stored in the cache space, the data processing module stores the first logical block address and corresponding data into the cache space, and sets a corresponding bit of the first logical block address in the effective bitmap parameter as a first value.

When a certain first logic block address is the same as a second logic block address stored in the cache space and the second logic block address does not have a flash memory writing state mark, the data processing module replaces data corresponding to the second logic block address stored in the cache space with data corresponding to the first logic block address, and sets a corresponding bit of the first logic block address in the effective bitmap parameter to be a second numerical value.

When a certain first logic block address is the same as a second logic block address stored in the cache space and the second logic block address has a flash memory writing state mark, the data processing module stores data corresponding to the first logic block address to a backup position in the cache space and sets a corresponding bit of the first logic block address in an effective bitmap parameter as a first numerical value.

In the case that the data granularity of the first logical block address is different from the granularity of the smallest unit of the flash memory device:

the data processing module obtains the effective sector parameters and determines the data granularity of the current write command according to the effective sector parameters. When a certain first logical block address is different from a logical block address stored in the cache space and at least one bit in the effective sector parameters is a second numerical value, the data processing module stores the first logical block address and corresponding data into the cache space, sets each effective bit of the effective bitmap parameters as the second numerical value, and then sends the data granularity of the effective bitmap parameters and the current write command to the firmware so that the firmware sends a filling read command to the hardware data management system.

When a certain first logical block address is the same as a second logical block address stored in the cache space and at least one bit in the effective sector parameter is a second value, the data processing module replaces data corresponding to the first logical block address with data corresponding to the second logical block address stored in the cache space, and each effective bit of the effective bitmap parameter is set to be the second value.

When each bit in the effective sector parameter is a first value, the hardware data management system sets the last bit of the effective bitmap parameter as the first value, and sends the data granularity of the effective bitmap parameter and the current write command to the firmware, so that the firmware sends the flash memory write command to the hardware data management system.

Further, the firmware processing module obtains a flash memory write command sent by the firmware, and writes data into the flash memory medium according to the flash memory write command.

Referring to fig. 17, fig. 17 is an interaction schematic diagram of a host, a hardware data management system, and firmware according to an embodiment of the present application;

as shown in fig. 17, the interaction flow of the host, the hardware data management system and the firmware includes:

step S1701: the host sends a write command;

specifically, the host 151 sends a write command to the hardware data management system 200, the write command being { Start_LBA, LBA_Length }, where Start_LBA represents the starting logical block address and LBA_Length represents the address Length.

Step S1702: the hardware data management system sends a data acquisition command;

specifically, the hardware data management system 200 sends a data acquisition command that is { Start_LBA, LBA_Length }, where Start_LBA represents the starting logical block address and LBA_Length represents the address Length.

Step S1703: the host sends data;

specifically, the host 151 transmits the first logical block address and corresponding data to the hardware data management system 200.

Step S1704: the hardware data management system sends an effective bitmap instruction;

specifically, the hardware data management system 200 sends a Valid bitmap instruction to the firmware 1021, where the Valid bitmap instruction is { start_lba, lba_length, valid_bit_map }, where start_lba represents a Start logical block address, lba_length represents an address Length, and valid_bit_map represents a Valid bitmap parameter.

Step S1705: firmware sends a flash memory write command;

specifically, firmware 1021 sends a flash write command to hardware data management system 200, where the flash write command is, for example: { write_tag, LBA, PBA }, write_tag represents the write tag, LBA represents the first logical block address, and PBA represents the target physical location.

Step S1706: the hardware data management system sends a write flag.

Specifically, the hardware data management system 200 writes the data corresponding to the first logical block address into the target physical location in the flash memory medium from the inside of the hardware data management system 200 according to the flash memory write command, and sends a write flag to the firmware 1021 after the write operation is completed.

Referring to fig. 18, fig. 18 is a detailed flowchart of a write command processing method according to an embodiment of the present disclosure;

in the embodiment of the present application, the hardware data management system further includes a hash module 204, where the hash module 204 is configured to complete LBA insertion, LBA lookup, and LBA deletion operations based on a hash algorithm.

As shown in fig. 18, the detailed flow of the write command processing method includes:

step S1: the host computer sends a write command to the hardware data management system;

step S2: the host processing module obtains the size of the free space;

specifically, the host processing module receives the write command and determines the size of the free space in the cache space.

Step S3: the host processing module sends a data acquisition command to the host;

step S4: the host sends data;

step S5: the data processing module writes the data into the cache space;

step S6: the data processing module sends an LBA insertion request to the hash module;

Specifically, the LBA insertion request is used to instruct the hash module 204 to establish, through a hash algorithm, a mapping relationship between each first logical block address and a data location of the corresponding data in the cache space, and store the mapping relationship in the hash table.

Step S7: finishing data reception;

specifically, the data processing module 202 sends data reception completion information to the host 151, where the data reception completion information is used to indicate that the hardware data management system has received the data sent by the host 151.

Step S8: finishing the data receiving of the current writing command;

specifically, the hardware data management system sends a valid bitmap instruction to the firmware to inform the firmware that the data reception of the current write command is finished, and indicates whether the firmware sends a flash memory write command to the hardware data management system.

Step S9: the firmware sends a filling read command to the hardware data management system;

step S10: the firmware processing module reads data from the flash memory medium;

step S11: finishing the data reading;

the firmware processing module 203 sends data read completion information to the firmware, where the data read completion information is used to indicate that the hardware data management system has completed reading data.

Step S12: the firmware sends a flash memory write command to the hardware data management system;

Step S13: the firmware processing module sends an LBA searching request to the hash module;

specifically, the LBA lookup request is used to instruct the hash module 204 to determine, based on a hash algorithm, a storage location of data corresponding to the first logical block address in the flash write command in the cache space.

Step S14: the hash module feeds back the storage position of the data in the cache space to the firmware processing module;

step S15: the firmware processing module writes the data into the flash memory medium;

step S16: finishing the execution of the flash memory write command;

specifically, after the flash write operation is completed, the hardware data management system sends a write flag to the firmware to inform that the flash write command is completed. Accordingly, the firmware identifies the write flag, and updates the mapping table of logical addresses and physical addresses.

Step S17: the firmware sends an LBA deleting request to the hardware data management system;

specifically, the LBA delete request is used to instruct the hardware data management system to delete the first logical block address where the flash write operation has been completed within the hardware data management system. Accordingly, the hash module deletes the first logical block address stored in the hash table based on a hash algorithm according to the LBA deletion request.

When the granularity of the data of the first logical block address is different from the granularity of the minimum unit of the flash memory device, and the N512B first logical block addresses contained in the current write command cannot form LBA0 with the data granularity of 4K, executing the write command processing flow of step S1 to step S17; in the rest of the cases, the write command processing flows of step S1 to step S8 and step S12 to step S17 are sequentially executed.

In an embodiment of the present application, a write command processing method is provided, where the write command processing method is applied to a flash memory device, and the flash memory device is communicatively connected to a host, and the flash memory device includes a hardware data management system, and the write command processing method includes: acquiring a write command sent by a host, and sending a data acquisition command to the host; receiving a first logical block address and data sent by a host; and performing storage operation on the data according to the first logic block address. According to the method and the device, when the same logical block address exists in the plurality of write commands sent by the host, delay of writing the plurality of data corresponding to the same logical block address into the flash memory can be reduced, and therefore writing performance of the flash memory device is improved.

The present embodiments also provide a non-volatile computer storage medium storing computer-executable instructions that are executable by one or more processors, for example, the one or more processors may perform the write command processing method in any of the method embodiments described above, for example, perform the steps described above.

The apparatus or device embodiments described above are merely illustrative, in which the unit modules illustrated as separate components may or may not be physically separate, and the components shown as unit modules may or may not be physical units, may be located in one place, or may be distributed over multiple network module units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

From the above description of embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus a general purpose hardware platform, or may be implemented by hardware. Based on such understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the related art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., and include several instructions for up to a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method of each embodiment or some parts of the embodiments.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting thereof; the technical features of the above embodiments or in the different embodiments may also be combined under the idea of the present application, the steps may be implemented in any order, and there are many other variations of the different aspects of the present application as above, which are not provided in details for the sake of brevity; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A hardware data management system for use with a flash memory device, the flash memory device communicatively coupled to a host, the flash memory device including firmware and a flash memory medium, the hardware data management system comprising:

The data processing module is used for carrying out storage operation on the data and editing an effective bitmap instruction according to whether the same logical block address is stored in the hardware data management system or not, so that the effective bitmap instruction is sent to the firmware;

the valid bitmap instruction is used for indicating whether the firmware sends a flash memory write command to the hardware data management system, and the flash memory write command is used for indicating the hardware data management system to store the data to the flash memory medium.

2. The system of claim 1, wherein the hardware data management system comprises a cache space for storing logical block addresses and corresponding data;

the data acquisition command comprises a first command or a second command, the first command is used for indicating the host to integrally send data corresponding to a plurality of first logical block addresses to the hardware data management system, and the second command is used for indicating the host to send data segments corresponding to the plurality of first logical block addresses to the hardware data management system;

the host command processing module is specifically configured to:

receiving a write command sent by a host, wherein the write command comprises an address length;

Determining the size of the free space in the cache space;

if the size of the free space is larger than or equal to the address length, sending the first command to a host;

and if the size of the free space is smaller than the address length, sending the second command to the host according to the size of the free space.

3. The system of claim 2, wherein the valid bitmap instruction includes a starting logical block address, an address length, a valid bitmap parameter, each valid bit of the valid bitmap parameter for indicating whether a flash write operation is required for a corresponding first logical block address;

the data processing module is specifically configured to:

based on a hash algorithm, searching a second logical block address stored in the cache space by taking each first logical block address as a key word in the cache space, and determining whether the same logical block address exists in the cache space;

and when a certain first logic block address is different from a second logic block address stored in the cache space, storing the first logic block address and corresponding data into the cache space, and setting a corresponding bit of the first logic block address in the effective bitmap parameter as a first numerical value, wherein the first numerical value indicates that the corresponding first logic block address needs to perform flash memory writing operation.

4. A system according to claim 3, wherein the data processing module is further configured to:

when a certain first logic block address is the same as a second logic block address stored in the cache space and the second logic block address does not have a flash memory writing state mark, replacing data corresponding to the first logic block address with data corresponding to the second logic block address stored in the cache space;

setting a corresponding bit of the first logical block address in the valid bitmap parameter to a second value, wherein the second value indicates that the corresponding first logical block address does not need to perform a flash memory write operation.

5. A system according to claim 3, wherein the data processing module is further configured to:

when a certain first logic block address is the same as a second logic block address stored in the cache space and the second logic block address has a flash memory writing state mark, storing data corresponding to the first logic block address to a backup position in the cache space;

the first logical block address is set to a first value at a corresponding bit of the valid bitmap parameter.

6. The system of any of claims 3-5, wherein the data processing module is further configured to:

Acquiring effective sector parameters when the data granularity of the first logical block address is different from the granularity of the minimum unit of the flash memory device, wherein each effective bit of the effective sector parameters is used for indicating whether the corresponding logical block address is acquired;

determining the data granularity of the current write command according to the effective sector parameters;

when a certain first logical block address is different from the logical block address stored in the cache space and at least one bit in the effective sector parameter is a second value, storing the first logical block address and corresponding data into the cache space, and setting each effective bit of the effective bitmap parameter as the second value;

and sending the valid bitmap parameters and the data granularity of the current write command to firmware.

7. The system of claim 6, wherein the data processing module is further configured to, when the granularity of the data of the first logical block address is different from the granularity of the smallest unit of flash memory device:

when a certain first logical block address is the same as a second logical block address stored in the cache space and at least one bit in the effective sector parameters is a second numerical value, replacing data corresponding to the first logical block address with data corresponding to the second logical block address stored in the cache space;

Each valid bit of the valid bitmap parameter is set to a second value.

8. The system of claim 6, wherein the data processing module is further configured to, when the granularity of the data of the first logical block address is different from the granularity of the smallest unit of flash memory device:

setting the last bit of the valid bitmap parameter as a first value when each valid bit in the valid sector parameter is the first value;

and sending the valid bitmap parameters and the data granularity of the current write command to firmware so that the firmware sends the flash memory write command to a hardware data management system.

9. The system of claim 1, wherein the hardware data management system further comprises a firmware processing module;

the firmware processing module is used for:

acquiring a flash memory write command sent by firmware, wherein the flash memory write command comprises a first logical block address and a target physical address;

based on a hash algorithm, determining a storage position of the data in a hardware data management system by taking the first logic block address as a key word;

writing the data from the storage location to the flash memory medium based on the target physical address;

And sending a write mark to the firmware so that the firmware updates a mapping table of the logical address and the physical address, wherein the write mark is used for indicating that the current flash memory write command operation is completed.

10. The system of claim 9, wherein when the first data and the second data corresponding to the first logical block address are simultaneously stored in the hardware data management system, the firmware processing module is configured to:

after first data corresponding to a first logical block address is written into the flash memory medium, second data corresponding to the first logical block address is written into the flash memory medium, wherein the first data and the second data correspond to different write commands.

11. The system of claim 9, wherein the firmware processing module is configured to, when the granularity of the data of the first logical block address is different from the granularity of the smallest unit of the flash memory device:

acquiring a filling read command sent by firmware, wherein the filling read command comprises a third logic block address, and the data granularity of the third logic block address is the same as the granularity of the minimum unit of the flash memory device;

reading data corresponding to the third logical block address from the flash memory medium according to the filling read command;

Acquiring a flash memory write command sent by firmware, and carrying out merging operation on data corresponding to N first logic block addresses and data corresponding to a third logic block address according to the flash memory write command to obtain combined data, wherein the N first logic block addresses are part of units of the third logic block address;

and writing the combined data into the flash memory medium.

12. A memory control chip, comprising:

the hardware data management system of any of claims 1-11;

13. A flash memory device, comprising:

the memory control chip of claim 12;

14. A data transmission system, comprising:

the host is used for issuing a write command to the flash memory device;

the flash memory device of claim 13, communicatively coupled to the host, for storing data in accordance with the write command.

15. A method of processing a write command as applied to the flash memory device of claim 13, the flash memory device being communicatively coupled to a host, the method comprising:

receiving a first logical block address and data sent by a host;

and carrying out storage operation on the data according to the first logical block address.