CN117783820A - Chip detection device, system and method - Google Patents

Abstract

The invention relates to the technical field of chip detection, and discloses a chip detection device, a system and a method, wherein the chip detection device comprises a first probe set, a second probe set, a state information output part and a plurality of channel links; the first probe group and the second probe group are used for being electrically connected with two different chips to be tested respectively, each probe in the first probe group is connected with a corresponding probe in the second probe group through a channel link, and each channel link is used for being electrically connected with an external tester; the target channel links in the channel links are also electrically connected with the state information output part and are used for transmitting the state indication signals output by the state information output part to the chip so that the chip can switch the test mode into the parallel test mode or the mutual test mode according to the condition of the state indication signals. The chip testing device can realize two testing processes of a parallel testing mode and a mutual testing mode, and can realize the high-speed input and output type test of the chip while improving the testing efficiency.

Description

Chip detection device, system and method

Technical Field

The present disclosure relates to the technical field of chip detection, for example, to a chip detection device, a system and a method.

Background

At present, a parallel testing mode is generally adopted in the field of chip testing to improve the testing efficiency, so that the chip production efficiency is improved. In the chip testing device for realizing the parallel testing mode in the related art, two chips to be tested are respectively connected with two groups of probes, corresponding probes in the two groups of probes are connected, a testing machine outputs testing signals to the two chips based on the two groups of probes, whether the two chips are qualified or not is judged based on the testing result, the two chips are tested simultaneously at one time, and the testing efficiency is remarkably improved.

However, with the above-mentioned chip testing apparatus, the testing machine needs to transmit the test signal to the chip to be tested through a longer signal path, and the longer signal path may introduce more channel interference, so that the chip testing apparatus using the related art cannot test the chip with high-speed input/output. Therefore, the related art chip testing device cannot achieve both the effects of improving the testing efficiency and testing the chip for high-speed input/output.

It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview, and is intended to neither identify key/critical elements nor delineate the scope of such embodiments, but is intended as a prelude to the more detailed description that follows.

The embodiment of the disclosure provides a chip detection device, a system and a method, which can improve the test efficiency and realize the test of high-speed input and output types of chips.

According to a first aspect of the present disclosure, there is provided a chip detection apparatus including a first probe group, a second probe group, a status information output section, and a plurality of channel links;

the first probe group and the second probe group are used for being electrically connected with two different chips to be tested respectively, each probe in the first probe group is connected with a corresponding probe in the second probe group through a channel link, and each channel link is used for being electrically connected with an external tester;

the target channel links in the channel links are also electrically connected with the state information output part and are used for transmitting the state indication signals output by the state information output part to the chip so that the chip can switch the test mode into the parallel test mode or the mutual test mode according to the condition of the state indication signals.

In some embodiments, probes in the first probe set for electrical connection with the inter-test modules of the corresponding chips are electrically connected by target channel links with probes in the second probe set for electrical connection with the inter-test modules of the corresponding chips.

In some embodiments, the distance between the connection node of the target pathway link and the state information output and one probe to which the target pathway link is connected is greater than the distance between the connection node of the target pathway link and the state information output and another probe to which the target pathway link is connected.

In some embodiments, the status indication signal is a voltage signal, the status information output portion is a voltage output module, and the voltage output module is configured to output the voltage signal; the target channel link is electrically connected with the voltage output module.

In some embodiments, the status indication signal is a voltage signal, and the status information output part includes a voltage output module and a switch, where the voltage output module is used for outputting the voltage signal; the target channel link is electrically connected with the voltage output module through a switch.

According to a second aspect of the present disclosure, there is provided a chip testing system comprising a tester, and the chip testing apparatus provided in the first aspect of the present disclosure, a plurality of channel links in the chip testing apparatus being each for electrical connection with an external tester.

In some embodiments, the tester is electrically connected to a switch in the chip test apparatus, the tester being configured to control the switch to open or close.

In some embodiments, the chip detection system further comprises a switch controller electrically connected to the switch in the chip detection device, the switch controller for controlling the switch to be opened or closed.

According to a third aspect of the present disclosure, there is provided a chip testing method applied to the chip testing system provided in the second aspect of the present disclosure, wherein a first probe set and a second probe set in a chip testing device are electrically connected to two different chips to be tested, respectively, and the chip testing method includes:

receiving the state indication signal output by the state information output part through the target channel link;

switching the test mode into a parallel test mode or a mutual test mode according to the condition of the state indication signal;

and executing the test flow based on the current test mode.

In some embodiments, the case of the status indication signal switches the test mode to a concurrent test mode or a mutual test mode, comprising:

when the state indication signal is a first indication signal, configuring the mutual detection module to be disabled, and switching the test mode to the parallel test mode under the condition that the mutual detection module is disabled;

when the state indication signal is the second indication signal, the mutual detection module is configured to be enabled, and the test mode is switched to the mutual detection mode under the condition that the mutual detection module is enabled.

The chip detection device, system and method provided by the embodiment of the disclosure can realize the following technical effects:

the chip testing device provided by the embodiment of the disclosure is provided with a state information output part capable of outputting a state indication signal, and the chip to be tested is configured to switch the testing mode into a parallel testing mode or a mutual testing mode according to the state indication signal. When testing of non-high-speed input and output types is needed, the parallel testing mode can be switched, so that two chips can be tested at one time based on mutually paired probe groups, and the testing efficiency of the chips is improved; when the test of the high-speed input/output class is required, the test can be switched to a mutual test mode, the length of a signal path used in the mutual test mode is obviously shorter than that of a signal path used in a parallel test mode, and the channel interference in the signal path can be obviously reduced by using the mutual test mode, so that the test of the high-speed input/output class can be performed based on the mutual test mode. Therefore, the chip testing device provided by the embodiment of the disclosure can realize two testing processes of a parallel testing mode and a mutual testing mode, and can realize the high-speed input and output type testing of the chip while improving the testing efficiency.

The foregoing general description and the following description are exemplary and explanatory only and are not intended to limit the present disclosure.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which like reference numerals refer to similar elements, and in which:

FIG. 1 is a schematic diagram of a chip testing apparatus provided in an embodiment of the disclosure;

fig. 2 is an equivalent schematic diagram of connection between two chips to be tested through a chip detection device according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a chip testing system provided by an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of another chip testing apparatus provided by an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of another chip testing system provided by the disclosed embodiments;

fig. 6 is a schematic diagram of an application scenario of a chip detection system provided in an embodiment of the disclosure;

FIG. 7 is a schematic diagram of a chip testing method according to an embodiment of the disclosure;

fig. 8 is a schematic diagram of an application scenario of another chip detection system provided in an embodiment of the disclosure.

The description of the reference numerals is as follows:

100-chip detection device; 1-a first set of probes; 2-a second set of probes;

101-probe; 102-a status information output unit;

1021-a voltage output module; 1022-switch;

103—circuit board 103; 104-a target channel link;

200-a testing machine;

300-wafer; 301-a first chip; 302-a second chip.

Detailed Description

So that the manner in which the features and techniques of the disclosed embodiments can be understood in more detail, a more particular description of the embodiments of the disclosure, briefly summarized below, may be had by reference to the appended drawings, which are not intended to be limiting of the embodiments of the disclosure. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may still be practiced without these details. In other instances, well-known structures and devices may be shown simplified in order to simplify the drawing.

The terms first, second and the like in the description and in the claims of the embodiments of the disclosure and in the above-described figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe embodiments of the present disclosure. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion.

The term "plurality" means two or more, unless otherwise indicated.

In the embodiment of the present disclosure, the character "/" indicates that the front and rear objects are an or relationship. For example, A/B represents: a or B.

The term "and/or" is an associative relationship that describes an object, meaning that there may be three relationships. For example, a and/or B, represent: a or B, or, A and B.

The term "corresponding" may refer to an association or binding relationship, and the correspondence between a and B refers to an association or binding relationship between a and B.

At present, a parallel testing mode is generally adopted in the field of chip testing to improve the testing efficiency, so that the chip production efficiency is improved. In the chip testing device for realizing the parallel testing mode in the related art, two chips to be tested are respectively connected with two groups of probes, corresponding probes in the two groups of probes are connected, a testing machine outputs testing signals to the two chips based on the two groups of probes, whether the two chips are qualified or not is judged based on the testing result, the two chips are tested simultaneously at one time, and the testing efficiency is remarkably improved.

However, with the above-mentioned chip testing apparatus, the testing machine needs to transmit the test signal to the chip to be tested through a longer signal path, and the longer signal path may introduce more channel interference, so that the chip testing apparatus using the related art cannot test the chip with high-speed input/output.

The disclosed embodiments provide a chip detection apparatus 100, the chip detection apparatus 100 including a plurality of probes 101. Embodiments of the present disclosure may group a plurality of probes 101 to obtain a plurality of probe sets, each of which may be used for one chip electrical connection to be tested. The disclosed embodiments can pair a plurality of probe sets pairwise to obtain one or more probe units, and it is understood that each probe unit comprises two probe sets paired with each other, and each probe set comprises a plurality of probes. For ease of understanding and description, the disclosed embodiments define two probe sets paired with each other as a first probe set 1 and a second probe set 2, respectively.

Here, the number of probes 101 in the chip inspection apparatus 100 may be determined according to the actual requirements, if the number of probes 101 can be satisfied to simultaneously inspect two or more chips. Embodiments of the present disclosure may group a plurality of probes 101 to obtain more than two probe sets to determine at least one first probe set 1 and at least one second probe set 2. Furthermore, the number of probes 101 per probe set should be able to meet the number of requirements for testing one chip.

As shown in fig. 1, the chip inspection apparatus 100 includes a first probe group 1, a second probe group 2, a status information output section 102, and a plurality of channel links (not shown in the figure). The first probe set 1 and the second probe set 2 are two probe sets paired with each other in the chip detection device 100, and the first probe set 1 and the second probe set 2 are used for respectively electrically connecting with two different chips to be tested. It is to be understood that fig. 1 is an exemplary system showing the number and positional relationship of the first probe group 1 and the second probe group 2, and that although fig. 1 shows only one first probe group 1 and one second probe group 2, the chip detection apparatus 100 may further include more first probe groups 1 and second probe groups 2, and the first probe groups 1 and the second probe groups 2 are in one-to-one correspondence.

Each probe 101 in the first probe set 1 is connected to a corresponding probe 101 in the second probe set 2 by a channel link, each channel link being adapted for electrical connection to an external tester 200. In the embodiment of the present disclosure, the chip connected to the first probe set 1 and the chip connected to the second probe set 2 may transmit information (e.g., test information) to each other through the channel link. The chips connected to the first probe set 1 and the chips connected to the second probe set 2 may receive information (e.g., test information) output from the tester 200 through the channel link.

In the embodiments of the present disclosure, the channel links are circuits capable of transmitting information, and each channel link may be independent. Alternatively, each channel link may be each individual signal line; the external tester 200 is electrically connected to the chip to be tested through the signal lines, the first probe group 1 and the second probe group 2. Optionally, the chip detection apparatus 100 may further include a circuit board (Print Circuit Board, PCB) 103, and each channel link may be a separate circuit in the circuit board 103; the external tester 200 is electrically connected to the chip to be tested through the circuits in the circuit board 103, the first probe set 1 and the second probe set 2.

In the disclosed embodiment, each probe 101 includes a first end and a second end, the first end of the probe 101 is connected to the channel link, and the second end of the probe 101 is used for connecting with pins of the chip to be tested.

In the embodiment of the present disclosure, one channel link may be selected from among a plurality of channel links, and the selected channel link may be electrically connected to the status information output part 102. For ease of understanding and description, the embodiment of the disclosure defines a channel link selected from a plurality of channel links as a target channel link 104, where the target channel link 104 of the plurality of channel links is further electrically connected to the status information output unit 102, and the target channel link 104 is configured to transmit a status indication signal output by the status information output unit 102 to the chip, so that the chip switches the test mode to the parallel test mode or the mutual test mode according to the status of the status indication signal.

When the chips are switched to the parallel test mode, the two chips to be tested cannot mutually send information. One chip to be tested is electrically connected with an external testing machine 200 through the first probe set 1 and the channel link, the other chip to be tested is electrically connected with the external testing machine 200 through the second probe set 2 and the channel link, and the two chips to be tested synchronously receive the testing signals sent by the testing machine 200, so that the two chips are tested simultaneously at one time based on the probe sets matched with each other.

When the chip is switched to the inter-test mode, the chip does not receive the test signal transmitted from the external tester 200. The two chips to be tested are connected through the first probe set 1, the channel link and the second probe set 2 to transmit test information, so that the two chips are mutually tested. For example, a chip to be tested outputs a test signal, and the test signal is transmitted to another chip to be tested through the first probe set 1 connection, the channel link and the second probe set 2, and whether the two chips are qualified is judged according to the receiving condition of the test signal of the other chip to be tested.

It will be appreciated that when the chips are switched to the inter-test mode, the signal path between the two chips under test is made up of the first probe set 1 connection, the channel link and the second probe set 2. The length of the signal path used in the mutual test mode is significantly shorter than that of the signal path used in the parallel test mode, and the use of the mutual test mode can significantly reduce channel interference in the signal path, so that high-speed input and output type testing can be performed based on the mutual test mode.

The chip testing device provided in the embodiment of the present disclosure is provided with a status information output part 102 capable of outputting a status indication signal, and configures a chip to be tested to be capable of switching a test mode to a parallel test mode or a mutual test mode according to the status indication signal. When testing of non-high-speed input and output types is needed, the parallel testing mode can be switched, so that two chips can be tested at one time based on mutually paired probe groups, and the testing efficiency of the chips is improved; when the test of the high-speed input/output class is required, the test can be switched to a mutual test mode, the length of a signal path used in the mutual test mode is obviously shorter than that of a signal path used in a parallel test mode, and the channel interference in the signal path can be obviously reduced by using the mutual test mode, so that the test of the high-speed input/output class can be performed based on the mutual test mode. Therefore, the chip testing device provided by the embodiment of the disclosure can realize two testing processes of a parallel testing mode and a mutual testing mode, and can realize the high-speed input and output type testing of the chip while improving the testing efficiency.

As shown in conjunction with fig. 2, for ease of understanding and description, the disclosed embodiments define two chips to be tested as a first chip 301 and a second chip 302, wherein the first chip 301 is electrically connected to the first probe set 1 and the second chip 302 is electrically connected to the second probe set 2. The chip comprises a mutual testing module, and the testing mode of the chip can be switched by configuring the enabling state of the mutual testing module.

In the embodiment of the present disclosure, the probes 101 in one probe set for electrically connecting with the mutual testing modules of the corresponding chips are electrically connected with the probes 101 in the second probe set 2 for electrically connecting with the mutual testing modules of the corresponding chips through the target channel links 104. It can be understood that the probes 101 in the first probe set 1 for electrically connecting with the mutual measuring modules of the corresponding chips are the rightmost probes 101 in the dashed boxes corresponding to the first probe set 1; the probes 101 in the second probe set 2 for electrically connecting with the mutual testing modules of the corresponding chips are leftmost probes 101 in the dashed boxes corresponding to the second probe set 2.

The target channel link 104 may directly transmit the status indication signal output by the status information output unit 102 to the inter-test module of the chip, so that the enabled status of the inter-test module may configure the test mode of the chip, and then the configured enabled status of the inter-test module may switch the test mode of the chip.

In some embodiments, the status indication signal includes a first indication signal and a second indication signal. When the state indication signal is a first indication signal, configuring the mutual detection module to be disabled, and switching the test mode to the parallel test mode under the condition that the mutual detection module is disabled; when the state indication signal is the second indication signal, the mutual detection module is configured to be enabled, and the test mode is switched to the mutual detection mode under the condition that the mutual detection module is enabled.

In some embodiments, the distance between the connection node of the target pathway link 104 and the state information output 102 and one probe 101 to which the target pathway link 104 is connected is greater than the distance between the connection node of the target pathway link 104 and the state information output 102 and another probe 101 to which the target pathway link 104 is connected. Taking fig. 1 and 2 as an example, the distance between the connection node of the target path link 104 and the state information output section 102 and the probe 101 in the first probe group 1 to which the target path link 104 is connected is larger than the distance between the connection node of the target path link 104 and the state information output section 102 and the probe 101 in the second probe group 2 to which the target path link 104 is connected. The line segment AB in fig. 2 may be represented as the target path link 104, and the point a may be represented as a connection node between the target path link 104 and the state information output unit 102.

In some embodiments, the status indication signal is a voltage signal. The state information output unit 102 is a voltage output module, and the target channel link 104 is electrically connected to the voltage output module, where the voltage output module is configured to output a voltage signal. The voltage output module may output different voltage signals, and the target channel link 104 is configured to transmit the voltage signals output by the voltage output module to the chip, so that the chip switches the test mode to the parallel test mode or the mutual test mode according to the voltage signal condition.

Referring to fig. 3, an embodiment of the disclosure provides a chip testing system, where the chip testing system includes a tester 200 and the chip testing device 100 provided in the foregoing embodiment of the disclosure, and a plurality of channel links in the chip testing device 100 are all used to electrically connect with the tester 200.

In some embodiments, the status indication signal is a voltage signal. As shown in fig. 4, the status information output section 102 includes a voltage output module 1021 and a switch 1022, and the target channel link 104 is electrically connected to the voltage output module 1021 through the switch 1022, and the voltage output module 1021 is configured to output a voltage signal. The target channel link 104 is used for transmitting the voltage signal output by the voltage output module 1021 to a chip, the voltage signal can be changed by opening or closing the switch 1022, and the chip switches the test mode to the parallel test mode or the mutual test mode according to the condition of the voltage signal.

Alternatively, when switch 1022 is open, the chip switches the test mode to the inter-test mode. By providing the switch 1022 between the target channel link 104 and the voltage output module 1021, when the switch 1022 is turned off, the signal path from the tester 200 to the target channel link 104 is isolated from the first probe set 1 and the second probe set 2, so that the channel interference in the signal path from the tester 200 to the target channel link 104 is prevented from affecting the testing process of the inter-test mode.

Referring to fig. 5, an embodiment of the disclosure provides a chip testing system, where the chip testing system includes a tester 200 and the chip testing device 100 provided in the foregoing embodiment of the disclosure, and a plurality of channel links in the chip testing device 100 are all used to electrically connect with the tester 200.

In some embodiments, the testing machine 200 is electrically connected to a switch 1022 (not shown) in the chip inspection apparatus 100, and the testing machine 200 is configured to control the switch 1022 to be opened or closed.

In some embodiments, the chip detection system further includes a switch controller (not shown in the figures), which is electrically connected to the switch 1022 in the chip detection apparatus 100, and the switch controller is used to control the switch 1022 to be opened or closed.

The embodiment of the disclosure provides an application scenario schematic diagram of a chip detection system, and referring to fig. 6, a first probe set 1 and a second probe set 2 in a chip detection device 100 are respectively electrically connected to two different chips to be tested. For ease of understanding and description, the disclosed embodiments define two chips to be tested as a first chip 301 and a second chip 302, where the first chip 301 is electrically connected to the first probe set 1 and the second chip 302 is electrically connected to the second probe set 2.

Alternatively, the object to which the chip inspection system provided in the embodiment of the present disclosure is directed may be the wafer 300 that is not divided after the fabrication is completed as shown in fig. 6. When the wafer 300 is not packaged, a plurality of dies (die) are regularly distributed on the wafer 300 in this state, and the dies to be tested in the embodiment of the disclosure, that is, the first die 301 and the second die 302 are all dies on the wafer 300. A die, also called a die, die or die, is a small body of unpackaged integrated circuit fabricated from semiconductor material, and the intended function of the integrated circuit is to be implemented on this small semiconductor. When the wafer 300 has completed packaging, a plurality of packaged crystals are regularly distributed on the wafer 300 in this state, and the chips to be tested in the embodiment of the present disclosure may be packaged crystals, that is, the first chip 301 and the second chip 302 are packaged crystals on the wafer 300.

Alternatively, the object to which the chip detection system provided in the embodiments of the present disclosure is directed may be an independent chip, that is, the first chip 301 and the second chip 302 are independent from each other.

In combination with the chip testing system shown in fig. 3 and the application scenario shown in fig. 4, the embodiment of the disclosure provides a chip testing method, as shown in fig. 7, where the chip testing method includes:

s701, the first chip and the second chip receive the status indication signal output by the status information output section through the target channel link.

S702, the first chip and the second chip switch the test mode into a parallel test mode or a mutual test mode according to the condition of the state indication signals.

S703, the first chip and the second chip execute a test flow based on the current test mode.

When the current test mode is the parallel test mode, that is, when the first chip 301 and the second chip 302 are switched to the parallel test mode, information cannot be transmitted between the first chip 301 and the second chip 302. The first chip 301 is electrically connected with the external testing machine 200 through the first probe set 1 connection and the channel link, the second chip 302 is electrically connected with the external testing machine 200 through the second probe set 2 connection and the channel link, and the first chip 301 and the second chip 302 synchronously receive the testing signals sent by the testing machine 200, so that two chips can be tested simultaneously at one time.

When the current test mode is the inter-test mode, that is, when the first chip 301 and the second chip 302 are switched to the inter-test mode, the first chip 301 and the second chip 302 do not receive the test signal sent by the external tester 200. The first chip 301 and the second chip 302 are connected through the first probe set 1, the channel link and the second probe set 2 transmit test information, so that the first chip 301 and the second chip 302 are tested mutually.

Optionally, when the first chip 301 and the second chip 302 are switched to the mutual test mode, the chips of the first chip 301 output test signals, and the test signals are transmitted to the second chip 302 through the first probe set 1 connection, the channel link and the second probe set 2, and whether the first chip 301 and the second chip 302 are qualified is determined according to the receiving condition of the test signals of the second chip 302.

Optionally, when the first chip 301 and the second chip 302 are switched to the mutual test mode, the chips of the second chip 302 output test signals, and the test signals are transmitted to the first chip 301 through the connection of the second probe set 2, the channel link and the first probe set 1, and whether the first chip 301 and the second chip 302 are qualified is determined according to the receiving condition of the test signals of the first chip 301.

It will be appreciated that when the first chip 301 and the second chip 302 are switched to the mutual test mode, the signal path between the first chip 301 and the second chip 302 is made up of the first probe set 1 connection, the channel link and the second probe set 2. The length of the signal path used in the mutual test mode is significantly shorter than that of the signal path used in the parallel test mode, and the use of the mutual test mode can significantly reduce channel interference in the signal path, so that high-speed input and output type testing can be performed based on the mutual test mode.

In some embodiments, the status indication signal includes a first indication signal and a second indication signal. When the state indication signal is a first indication signal, configuring the mutual detection module to be disabled, and switching the test mode to the parallel test mode under the condition that the mutual detection module is disabled; when the state indication signal is the second indication signal, the mutual detection module is configured to be enabled, and the test mode is switched to the mutual detection mode under the condition that the mutual detection module is enabled.

In some embodiments, the status indication signal is a voltage signal. The status information output part 102 is a voltage output module 1021, and the target channel link 104 is electrically connected to the voltage output module 1021, and the voltage output module 1021 is configured to output a voltage signal. The voltage output module 1021 may output different voltage signals, and the target channel link 104 is configured to transmit the voltage signals output by the voltage output module 1021 to the chip, so that the chip switches the test mode to the parallel test mode or the mutual test mode according to the voltage signal.

Optionally, the voltage signal comprises a first voltage signal and a second voltage signal. When the voltage signal is a first voltage signal, configuring the mutual testing module to be disabled, and switching the testing mode to the parallel testing mode under the condition that the mutual testing module is disabled; when the voltage signal is the second voltage signal, the mutual testing module is configured to be enabled, and the testing mode is switched to the mutual testing mode under the condition that the mutual testing module is enabled.

The embodiment of the disclosure provides an application scenario schematic diagram of a chip detection system, and referring to fig. 8, a first probe set 1 and a second probe set 2 in a chip detection device 100 are respectively electrically connected to two different chips to be tested. For ease of understanding and description, the disclosed embodiments define two chips to be tested as a first chip 301 and a second chip 302, where the first chip 301 is electrically connected to the first probe set 1 and the second chip 302 is electrically connected to the second probe set 2.

In the embodiment of the present disclosure, the status indication signal is a voltage signal, the status information output portion 102 includes a voltage output module 1021 and a switch 1022, the target channel link 104 is electrically connected to the voltage output module 1021 through the switch 1022, and the voltage output module 1021 is configured to output the voltage signal. The target channel link 104 is used for transmitting the voltage signal output by the voltage output module 1021 to a chip, the voltage signal can be changed by opening or closing the switch 1022, and the chip switches the test mode to the parallel test mode or the mutual test mode according to the condition of the voltage signal.

Optionally, the voltage signal comprises a first voltage signal and a second voltage signal. The voltage output module 1021 fixedly outputs a first voltage signal, and the second voltage signal is a signal with a voltage value smaller than that of the first voltage signal, for example, the voltage value of the second voltage signal is 0. When the switch 1022 is closed, the voltage signal is a first voltage signal, the mutual detection module is configured to be disabled, and the test mode is switched to the parallel detection mode under the condition that the mutual detection module is disabled; when the switch 1022 is turned off, the voltage signal becomes the second voltage signal, the mutual detection module is configured to be enabled, and the test mode is switched to the mutual detection mode when the mutual detection module is enabled.

In some embodiments, the tester 200 is electrically connected to a switch 1022 in the chip inspection apparatus 100, and the tester 200 is configured to control the switch 1022 to be opened or closed. When the concurrent test mode test is required, the tester 200 controls the switch 1022 to be closed; when the test in the mutual test mode is required, the tester 200 controls the switch 1022 to be turned off.

In some embodiments, the chip detection system further comprises a switch controller electrically connected to the switch 1022 in the chip detection apparatus 100, the switch controller being configured to control the switch 1022 to be opened or closed. When a concurrent test mode test is required, the switch controller controls the switch 1022 to be closed; when a test in the mutual test mode is required, the switch controller controls the switch 1022 to be turned off.

In some embodiments, the switch 1022 may be controlled to open or close in a manually controlled manner.

In some embodiments, the distance between the connection node of the target pathway link 104 and the state information output 102 and one probe 101 to which the target pathway link 104 is connected is greater than the distance between the connection node of the target pathway link 104 and the state information output 102 and another probe 101 to which the target pathway link 104 is connected.

Taking fig. 1 as an example, the distance between the connection node of the target path link 104 and the state information output section 102 and the probe 101 in the first probe group 1 to which the target path link 104 is connected is larger than the distance between the connection node of the target path link 104 and the state information output section 102 and the probe 101 in the second probe group 2 to which the target path link 104 is connected. The mutual detection module of the first chip 301 may receive the status indication signal before the mutual detection module of the second chip 302. When the mutual testing module of the first chip 301 receives the second indication signal, the mutual testing module of the first chip 301 is configured to be enabled, and for the pins connected with the channel link through the first probe set 1 in the first chip 301, the pins are set as output pins for outputting test signals to corresponding pins in the second chip 301. Meanwhile, the first chip 301 may send an instruction to the mutual testing module of the second chip 302 through the mutual testing module to configure the mutual testing module of the second chip 302 to be enabled, and for the pin connected with the channel link in the second chip 302 through the second probe set 2, the pin is set as an input pin, so as to receive the test signal output by the corresponding pin in the first chip 301. The second indication signal may be the second voltage signal.

Embodiments of the present disclosure provide a computer-readable storage medium storing computer-executable instructions configured to perform a chip detection method.

Embodiments of the present disclosure may be embodied in a software product stored on a storage medium, including one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of a method according to embodiments of the present disclosure. While the aforementioned storage medium may be a non-transitory storage medium, such as: a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk or an optical disk, or the like, which can store program codes.

The above description and the drawings illustrate embodiments of the disclosure sufficiently to enable those skilled in the art to practice them. Other embodiments may involve structural, logical, electrical, process, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in, or substituted for, those of others. Moreover, the terminology used in the present application is for the purpose of describing embodiments only and is not intended to limit the claims. As used in the description of the embodiments and the claims, the singular forms "a," "an," and "the" (the) are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the term "and/or" as used in this application is meant to encompass any and all possible combinations of one or more of the associated listed. Furthermore, when used in this application, the terms "comprises," "comprising," and/or "includes," and variations thereof, mean that the stated features, integers, steps, operations, elements, and/or components are present, but that the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof is not precluded. Without further limitation, an element defined by the phrase "comprising one …" does not exclude the presence of other like elements in a process, method or apparatus comprising such elements. In this context, each embodiment may be described with emphasis on the differences from the other embodiments, and the same similar parts between the various embodiments may be referred to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method sections disclosed in the embodiments, the description of the method sections may be referred to for relevance.

Those of skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. The skilled artisan may use different methods for each particular application to achieve the described functionality, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. It will be clearly understood by those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.

In the embodiments disclosed herein, the disclosed methods, articles of manufacture (including but not limited to devices, apparatuses, etc.) may be practiced in other ways. For example, the apparatus embodiments described above are merely illustrative, and for example, the division of the units may be merely a logical function division, and there may be additional divisions when actually implemented, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. In addition, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form. The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to implement the present embodiment. In addition, each functional unit in the embodiments of the present disclosure may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. In the description corresponding to the flowcharts and block diagrams in the figures, operations or steps corresponding to different blocks may also occur in different orders than that disclosed in the description, and sometimes no specific order exists between different operations or steps. For example, two consecutive operations or steps may actually be performed substantially in parallel, they may sometimes be performed in reverse order, which may be dependent on the functions involved. Each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Claims (10)

1. The chip detection device is characterized by comprising a first probe group, a second probe group, a state information output part and a plurality of channel links;

the first probe group and the second probe group are used for being electrically connected with two different chips to be tested respectively, each probe in the first probe group is connected with a corresponding probe in the second probe group through a channel link, and each channel link is used for being electrically connected with an external tester;

the target channel links in the channel links are also electrically connected with the state information output part and are used for transmitting the state indication signals output by the state information output part to the chip so that the chip can switch the test mode into the parallel test mode or the mutual test mode according to the condition of the state indication signals.

2. The chip inspection apparatus of claim 1, wherein probes of the first probe set for electrical connection with the inter-test modules of the corresponding chips are electrically connected with probes of the second probe set for electrical connection with the inter-test modules of the corresponding chips through the target channel link.

3. The chip inspection apparatus according to claim 1, wherein a distance between the connection node of the target path link and the state information output section and one probe to which the target path link is connected is greater than a distance between the connection node of the target path link and the state information output section and the other probe to which the target path link is connected.

4. The chip inspection apparatus according to any one of claim 1 to 3, wherein,

the state indication signal is a voltage signal, the state information output part is a voltage output module, and the voltage output module is used for outputting the voltage signal;

the target channel link is electrically connected with the voltage output module.

5. The chip inspection apparatus according to any one of claim 1 to 3, wherein,

the state indication signal is a voltage signal, and the state information output part comprises a voltage output module and a switch, wherein the voltage output module is used for outputting the voltage signal;

the target channel link is electrically connected with the voltage output module through a switch.

6. A chip testing system comprising a tester and a chip testing device according to any one of claims 1 to 5, wherein a plurality of channel links in the chip testing device are each adapted to be electrically connected to an external tester.

7. The chip inspection system according to claim 6, wherein the tester is electrically connected to the switch in the chip inspection device, and the tester is configured to control the switch to be opened or closed.

8. The chip inspection system of claim 6, further comprising a switch controller electrically connected to the switch in the chip inspection device, the switch controller for controlling the switch to be opened or closed.

9. A chip testing method applied to the chip testing system according to any one of claims 6 to 8, wherein the first probe set and the second probe set in the chip testing device are electrically connected to two different chips to be tested, respectively, and the chip testing method comprises:

receiving the state indication signal output by the state information output part through the target channel link;

switching the test mode into a parallel test mode or a mutual test mode according to the condition of the state indication signal;

and executing the test flow based on the current test mode.

10. The method for testing a chip according to claim 9, wherein switching the test mode to the parallel test mode or the inter-test mode according to the condition of the status indication signal comprises:

when the state indication signal is a first indication signal, configuring the mutual detection module to be disabled, and switching the test mode to the parallel test mode under the condition that the mutual detection module is disabled;

when the state indication signal is the second indication signal, the mutual detection module is configured to be enabled, and the test mode is switched to the mutual detection mode under the condition that the mutual detection module is enabled.