CN117767718A - Full-chip electrostatic surge protection circuit suitable for alternating current-direct current converter - Google Patents
Full-chip electrostatic surge protection circuit suitable for alternating current-direct current converter Download PDFInfo
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Abstract
The invention belongs to the technical field of electrostatic discharge protection and anti-surge of integrated circuits, and relates to a full-chip electrostatic surge protection circuit suitable for an alternating current-direct current converter. The full-chip ESD/EOS protection circuit designed by the invention has the characteristics of quick start, strong voltage clamp, low on-resistance and high ESD/EOS protection efficiency ratio. In addition, the full-chip ESD/EOS protection scheme provided by the invention realizes the functions of small area and high unit area robustness by sharing part of diodes and triodes, can be used for enhancing the ESD/EOS protection capability of the AC-DC converter and improves the reliability and stability of products.
Description
Technical Field
The invention belongs to the technical field of electrostatic discharge protection and anti-surge of integrated circuits, and relates to a full-chip electrostatic surge protection circuit suitable for an alternating current-direct current converter.
Background
Electrostatic discharge (ESD) or surge (EOS) is a common physical phenomenon that is ubiquitous in real life; however, in the processes of chip manufacturing, transportation, application, etc., the high-intensity transient pulse generated by ESD/EOS is very liable to cause irreversible damage to the chip, and in severe cases, the reliability and stability of the portable electronic product are deteriorated. The alternating current-direct current converter is responsible for converting alternating current signals into stable direct current signals in the circuit, and is an important module for ensuring the normal operation of various electronic products; with the continuous progress of integrated circuit technology, the minimum line width of a chip is continuously reduced, the gate oxide layer of a MOS tube is thinner and thinner, and the problems of large leakage, voltage clamping capability, weak ESD/EOS protection robustness and the like in the traditional ESD/EOS protection are required to be solved under the condition that the AC-DC converter meets the requirements of normal working characteristics; therefore, high performance ac-dc conversion is increasingly demanded for high performance full-chip ESD/EOS protection.
Because of the randomness of ESD/EOS, the input/output (IO), power (VDD), and ground (VSS) terminals inside the chip all need to design corresponding ESD/EOS protection circuits. In the prior art, in order to realize the bidirectional ESD/EOS protection requirement between IO and VDD or between IO and VSS, the traditional protection circuits such as diodes, gate-grounded NMOS (GGNMOS) and the like are mostly adopted, the circuits are of unidirectional structures, the bidirectional ESD/EOS protection is mostly realized in a reverse stacking mode, and the protection circuits occupy large chip area and have obvious parasitic effects; when the parasitic effect is obvious, the problems of leakage current and parasitic capacitance increase, static power consumption of the chip increase, and signal transmission is damaged or lost are caused, so that the circuit performance is affected. In the prior art, in order to realize the bidirectional ESD/EOS protection requirement between VDD and VSS, RC auxiliary trigger MOS circuits are mostly adopted, and the circuit structure is easy to generate false trigger, and has the problems of poor robustness in unit area, low ESD/EOS protection efficiency and the like.
Disclosure of Invention
Therefore, the invention aims to solve the technical problems of large occupied chip area, slow response time and poor robustness of unit area in the full-chip ESD/EOS protection circuit in the prior art.
In order to solve the above technical problems, the present invention provides a full-chip electrostatic surge protection circuit suitable for an ac-dc converter, comprising: the voltage regulator ZD1, the voltage regulator ZD2, the voltage regulator ZD3, the resistor R1, the resistor R2, the resistor R3, the PNP triode T1, the NPN triode T2, the NPN triode T3, the NPN triode T4, the PNP triode T5, the PNP triode T6, the NPN triode T7, the power supply terminal VDD, the input/output terminal IO and the ground terminal VSS; a voltage-stabilizing clamp circuit and an electrostatic surge bleeder circuit can be formed;
the voltage stabilizing clamp circuit includes: the first voltage stabilizing clamp circuit, the second voltage stabilizing clamp circuit and the third voltage stabilizing clamp circuit;
the first voltage stabilizing clamp circuit includes: the resistor R2, the voltage stabilizing tube ZD3 and the resistor R3; one end of a resistor R2 is connected with a power supply end VDD, the other end of the resistor R2 is connected with the cathode of a voltage stabilizing tube ZD2, the anode of the voltage stabilizing tube ZD2 is connected with the anode of a voltage stabilizing tube ZD3, the cathode of the voltage stabilizing tube ZD3 is connected with one end of the resistor R3, and the other end of the resistor R3 is connected with a grounding end VSS;
the second voltage stabilizing clamp circuit includes: the resistor R1, the voltage stabilizing tube ZD2 and the resistor R2; one end of a resistor R1 is connected with an input/output port IO, the other end of the resistor R1 is connected with the cathode of a voltage stabilizing tube ZD1, the anode of the voltage stabilizing tube ZD1 is connected with the anode of a voltage stabilizing tube ZD2, the cathode of the voltage stabilizing tube ZD2 is connected with one end of the resistor R2, and the other end of the resistor R2 is connected with a power supply end VDD;
the third voltage stabilizing clamp circuit includes: the resistor R1, the voltage stabilizing tube ZD3 and the resistor R3; one end of a resistor R1 is connected with an input/output port IO, the other end of the resistor R1 is connected with the cathode of a voltage stabilizing tube ZD1, the anode of the voltage stabilizing tube ZD1 is connected with the anode of a voltage stabilizing tube ZD3, the cathode of the voltage stabilizing tube ZD3 is connected with one end of the resistor R3, and the other end of the resistor R3 is connected with a grounding end VSS;
the electrostatic surge bleeder circuit comprises: the first SCR bleeder circuit, the second SCR bleeder circuit and the third SCR bleeder circuit;
the first SCR bleeder circuit comprises: the resistor R2, the NPN triode T2, the PNP triode T5, the NPN triode T4 and the resistor R3; the second SCR bleeder circuit comprises: the resistor R1, the NPN triode T3, the PNP triode T1, the NPN triode T2 and the resistor R2; the third SCR bleeder circuit comprises: the resistor R1, the NPN triode T3, the PNP triode T6, the NPN triode T4 and the resistor R3;
one end of the resistor R2 is connected with the power supply end VDD and the emitter of the NPN triode T2; the other end of the resistor R2 is connected with the base electrode of the NPN triode T2, the emitter electrode of the PNP triode T5, the collector electrode of the PNP triode T1, the collector electrode of the NPN triode T7 and the cathode of the voltage stabilizing tube ZD 2; the collector of the NPN triode T2 is connected with the base of the PNP triode T5, the collector of the NPN triode T4, the collector of the NPN triode T3, the base of the PNP triode T1 and the base of the PNP triode T6; the base electrode of the NPN triode T4 is connected with the collector electrode of the PNP triode T5, one end of the resistor R3, the cathode of the voltage stabilizing tube ZD3, the emitter electrode of the NPN triode T7 and the collector electrode of the PNP triode T6, and the emitter electrode of the NPN triode T4 is connected with the other end of the resistor R3 and the ground terminal VSS; the anode of the voltage stabilizing tube ZD3 is connected with the anode of the voltage stabilizing tube ZD2, the base electrode of the NPN triode T7 and the anode of the voltage stabilizing tube ZD 1; the cathode of the voltage stabilizing tube ZD1 is connected with the base electrode of the NPN triode T3, the emitter electrode of the PNP triode T6, the emitter electrode of the PNP triode T1 and the other end of the resistor R1; one end of the resistor R1 and the emitter of the NPN triode T3 are connected with the input/output end IO;
when the electrostatic surge stress acts between the power supply end VDD and the ground end VSS, the electrostatic surge stress is released through the first voltage-stabilizing clamping circuit and the first SCR bleeder circuit;
when the electrostatic surge stress acts between the input/output end IO and the power supply end VDD, the electrostatic surge stress is released through the second voltage stabilizing clamp circuit and the second SCR bleeder circuit;
when the electrostatic surge stress acts between the input/output terminal IO and the ground terminal VSS, the electrostatic surge stress is released through the third voltage stabilizing clamp circuit and the third SCR bleeder circuit.
In one embodiment of the present invention, the first voltage stabilizing clamp circuit is used for enhancing the fast turn-on and voltage clamping functions in the protection of electrostatic surge between the power supply terminal VDD and the ground terminal VSS; the second voltage-stabilizing clamp circuit is used for enhancing the rapid starting and voltage clamping functions in the electrostatic surge protection between the input/output end IO and the power supply end VDD; the third voltage stabilizing clamp circuit is used for enhancing the rapid starting and voltage clamping functions in electrostatic surge protection between the input/output end IO and the ground end VSS.
In one embodiment of the present invention, a forward electrostatic surge stress is applied between the power supply terminal VDD and the ground terminal VSS, and the resistor R2, the regulator ZD3 and the resistor R3 in the first voltage-stabilizing clamp circuit are turned on, and the circuit has low leakage, low on-resistance, fast response speed and high maintenance voltage characteristics; along with the continuous increase of the forward static surge stress, a resistor R2, an NPN triode T2, a PNP triode T5, an NPN triode T4 and a resistor R3 in the first SCR bleeder circuit are started to release the static surge current, so that the protection capability of the static surge full-chip protection circuit is enhanced; meanwhile, the collector of the NPN triode T7 and the voltage stabilizing tube ZD2 share the same semiconductor structure, and the emitter of the NPN triode T7 and the voltage stabilizing tube ZD3 share the same semiconductor structure, so that the conduction uniformity of the full-chip electrostatic surge protection circuit can be enhanced, and the robustness is further improved; in addition, when the forward or reverse electrostatic surge stress is applied between the power supply end VDD and the ground end VSS, the electrical structure of the electrostatic surge protection circuit is identical to the layout, and the circuit has the functions of small area and bidirectional protection.
In one embodiment of the present invention, a forward electrostatic surge stress is applied between the input/output port IO and the power supply terminal VDD, and the resistor R1, the regulator ZD2 and the resistor R2 in the second voltage-stabilizing clamp circuit are turned on, and the circuit has low leakage, low on-resistance, fast response speed and high maintenance voltage characteristics; along with the continuous increase of the forward static surge stress, a resistor R1, an NPN triode T3, a PNP triode T1, an NPN triode T2 and a resistor R2 in the second SCR bleeder circuit are started to release the static surge current, so that the protection capability of the full-chip static surge protection circuit is enhanced; in addition, when the forward or reverse electrostatic surge stress is applied between the input/output port IO and the power supply end VDD, the electrical structure of the electrostatic surge protection circuit is identical to the layout, and the circuit has the functions of small-area and bidirectional protection.
In one embodiment of the present invention, a forward electrostatic surge stress is applied between the input/output port IO and the ground terminal VSS, and the resistor R1, the regulator ZD3, and the resistor R3 in the third voltage stabilizing clamp circuit are turned on, and the circuit has low leakage, low on-resistance, fast response speed, and high maintenance voltage characteristics; along with the continuous increase of the forward static surge stress, a resistor R1, an NPN triode T3, a PNP triode T6, an NPN triode T4 and a resistor R3 in the third SCR bleeder circuit are started to release the static surge current, so that the protection capability of the full-chip static surge protection circuit is enhanced; in addition, a forward or reverse static surge stress is applied between the input/output port IO and the ground terminal VSS, the electrical structure of the static surge protection circuit is identical to the layout, and the circuit has the functions of small area and bidirectional protection.
In one embodiment of the present invention, the regulator tube ZD2 and the resistor R2 are shared by the first voltage stabilizing clamp circuit and the second voltage stabilizing clamp circuit; the first voltage stabilizing clamp circuit and the third voltage stabilizing clamp circuit share a voltage stabilizing tube ZD3 and a resistor R3; the second voltage stabilizing clamp circuit and the third voltage stabilizing clamp circuit share a voltage stabilizing tube ZD1 and a resistor R1; the first SCR bleeder circuit and the second SCR bleeder circuit share a resistor R2 and an NPN triode T2; the first SCR bleeder circuit and the third SCR bleeder circuit share an NPN triode T4 and a resistor R3; the second SCR bleeder circuit and the third SCR bleeder circuit share the resistor R1 and the NPN triode T3, so that the multiplexing rate of the internal modules of the circuit is improved, the area of a full-chip electrostatic surge protection circuit of an alternating current-direct current conversion chip is reduced, and the efficiency ratio is improved.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
(1) The full-chip electrostatic surge protection circuit suitable for the alternating current-direct current converter realizes the bidirectional ESD/EOS protection requirement among the VDD, IO, VSS three ports by designing the voltage stabilizing clamping circuit and the electrostatic surge bleeder circuit with special circuit structures, and realizes the characteristics of quick starting, strong voltage clamping, low on-resistance and high ESD/EOS protection efficiency ratio;
(2) The invention relates to a full-chip electrostatic surge protection circuit suitable for an alternating current-direct current converter, which is characterized in that a part of diodes and triodes are shared, namely a voltage stabilizing tube ZD2 and a resistor R2 are shared by a first voltage stabilizing clamp circuit and a second voltage stabilizing clamp circuit, a voltage stabilizing tube ZD3 and a resistor R3 are shared by the first voltage stabilizing clamp circuit and a third voltage stabilizing clamp circuit, a voltage stabilizing tube ZD1 and a resistor R1 are shared by the second voltage stabilizing clamp circuit and the third voltage stabilizing clamp circuit, a resistor R2 and an NPN triode T2 are shared by a first SCR bleeder circuit and a second SCR bleeder circuit, an NPN triode T4 and a resistor R3 are shared by the first SCR bleeder circuit and the third SCR bleeder circuit, and a resistor R1 and an NPN triode T3 are shared by the second SCR bleeder circuit and the third SCR bleeder circuit; thereby improving the multiplexing rate of the modules in the circuit, reducing the area of a full-chip electrostatic surge protection circuit of the alternating current-direct current conversion chip and improving the efficiency ratio; the ESD/EOS protection capability of the alternating current-direct current converter is enhanced, and the reliability and stability of the product are improved.
Drawings
In order that the invention may be more readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof that are illustrated in the appended drawings, in which
FIG. 1 is a diagram of a full-chip electrostatic surge protection circuit provided by the present invention;
FIG. 2 is a circuit diagram of the electrostatic surge protection from the power supply terminal to the ground terminal provided by the present invention;
FIG. 3 is a circuit diagram of the electrostatic surge protection circuit from the input/output terminal to the power terminal provided by the present invention;
fig. 4 is a circuit diagram of the electrostatic surge protection circuit from the input/output terminal to the ground terminal according to the present invention.
Detailed Description
The present invention will be further described with reference to the accompanying drawings and specific examples, which are not intended to be limiting, so that those skilled in the art will better understand the invention and practice it.
Referring to fig. 1, in order to solve the problems of large area, slow response time and poor robustness of unit area in the traditional full-chip ESD/EOS protection circuit, the invention designs a full-chip electrostatic surge protection circuit suitable for an ac-dc converter, which comprises a voltage stabilizing clamp circuit and an electrostatic surge bleeder circuit, aiming at the ESD/EOS protection requirement of the ac-dc converter; the specific circuit structure is as follows:
the voltage stabilizing clamp circuit comprises a first voltage stabilizing clamp circuit, a second voltage stabilizing clamp circuit and a third voltage stabilizing clamp circuit;
the first voltage stabilizing clamp circuit includes: resistor R2, voltage stabilizing tube ZD3 and resistor R3; one end of a resistor R2 is connected with a power supply end VDD, the other end of the resistor R2 is connected with the cathode of a voltage stabilizing tube ZD2, the anode of the voltage stabilizing tube ZD2 is connected with the anode of a voltage stabilizing tube ZD3, the cathode of the voltage stabilizing tube ZD3 is connected with one end of the resistor R3, and the other end of the resistor R3 is connected with a grounding end VSS;
the second voltage stabilizing clamp circuit includes: the resistor R1, the voltage stabilizing tube ZD2 and the resistor R2; one end of a resistor R1 is connected with an input/output port IO, the other end of the resistor R1 is connected with the cathode of a voltage stabilizing tube ZD1, the anode of the voltage stabilizing tube ZD1 is connected with the anode of a voltage stabilizing tube ZD2, the cathode of the voltage stabilizing tube ZD2 is connected with one end of the resistor R2, and the other end of the resistor R2 is connected with a power supply end VDD;
the third voltage stabilizing clamp circuit includes: the resistor R1, the voltage stabilizing tube ZD3 and the resistor R3; one end of a resistor R1 is connected with an input/output port IO, the other end of the resistor R1 is connected with the cathode of a voltage stabilizing tube ZD1, the anode of the voltage stabilizing tube ZD1 is connected with the anode of a voltage stabilizing tube ZD3, the cathode of the voltage stabilizing tube ZD3 is connected with one end of the resistor R3, and the other end of the resistor R3 is connected with a grounding end VSS;
the electrostatic surge bleeder circuit comprises a first SCR bleeder circuit, a second SCR bleeder circuit and a third SCR bleeder circuit;
the first SCR bleeder circuit comprises: the resistor R2, the NPN triode T2, the PNP triode T5, the NPN triode T4 and the resistor R3; the second SCR bleeder circuit comprises: the resistor R1, the NPN triode T3, the PNP triode T1, the NPN triode T2 and the resistor R2; the third SCR bleeder circuit: the resistor R1, the NPN triode T3, the PNP triode T6, the NPN triode T4 and the resistor R3 are included;
one end of the resistor R2 is connected with the power supply end VDD and the emitter of the NPN triode T2; the other end of the resistor R2 is connected with the base electrode of the NPN triode T2, the emitter electrode of the PNP triode T5, the collector electrode of the PNP triode T1, the collector electrode of the NPN triode T7 and the cathode of the voltage stabilizing tube ZD 2; the collector of the NPN triode T2 is connected with the base of the PNP triode T5, the collector of the NPN triode T4, the collector of the NPN triode T3, the base of the PNP triode T1 and the base of the PNP triode T6; the base electrode of the NPN triode T4 is connected with the collector electrode of the PNP triode T5, one end of the resistor R3, the cathode of the voltage stabilizing tube ZD3, the emitter electrode of the NPN triode T7 and the collector electrode of the PNP triode T6, and the emitter electrode of the NPN triode T4 is connected with the other end of the resistor R3 and the ground terminal VSS; the anode of the voltage stabilizing tube ZD3 is connected with the anode of the voltage stabilizing tube ZD2, the base electrode of the NPN triode T7 and the anode of the voltage stabilizing tube ZD 1; the cathode of the voltage stabilizing tube ZD1 is connected with the base electrode of the NPN triode T3, the emitter electrode of the PNP triode T6, the emitter electrode of the PNP triode T1 and the other end of the resistor R1; one end of the resistor R1 and the emitter of the NPN triode T3 are connected with the input/output end IO;
when the electrostatic surge stress acts between the power supply end VDD and the ground end VSS, the electrostatic surge stress is released through the first voltage-stabilizing clamping circuit and the first SCR bleeder circuit;
when the electrostatic surge stress acts between the input/output end IO and the power supply end VDD, the electrostatic surge stress is released through the second voltage stabilizing clamp circuit and the second SCR bleeder circuit;
when the electrostatic surge stress acts between the input/output terminal IO and the ground terminal VSS, the electrostatic surge stress is released through the third voltage stabilizing clamp circuit and the third SCR bleeder circuit.
Referring to fig. 2, fig. 2 is a circuit diagram of electrostatic surge protection from a power supply end to a ground end according to the present invention; the method comprises the following steps:
applying a forward electrostatic surge stress between a power supply end VDD and a ground end VSS, wherein a resistor R2, a voltage stabilizing tube ZD3 and a resistor R3 in the first voltage stabilizing clamp circuit are started, and the circuit has the characteristics of low electric leakage, low on-resistance, high response speed and high maintenance voltage; along with the continuous increase of the forward static surge stress, a resistor R2, an NPN triode T2, a PNP triode T5, an NPN triode T4 and a resistor R3 in the first SCR bleeder circuit are started to release the static surge current, so that the protection capability of the static surge full-chip protection circuit is enhanced; meanwhile, the collector of the NPN triode T7 and the voltage stabilizing tube ZD2 share the same semiconductor structure, the emitter of the NPN triode T7 and the voltage stabilizing tube ZD3 share the same semiconductor structure, so that the conduction uniformity of the full-chip electrostatic surge protection circuit is enhanced, and the robustness is further improved; in addition, a forward or reverse static surge stress is applied between the power supply end VDD and the ground end VSS, the electrical structure of the static surge protection circuit is identical to the layout, and the circuit has the functions of small area and bidirectional protection.
Referring to fig. 3, fig. 3 is a circuit diagram of esd protection from input/output to power supply according to the present invention; the method comprises the following steps:
applying a forward electrostatic surge stress between the input/output port IO and the power supply end VDD, wherein a resistor R1, a voltage stabilizing tube ZD2 and a resistor R2 in the second voltage stabilizing clamp circuit are started, and the circuit has the characteristics of low electric leakage, low on resistance, high response speed and high maintenance voltage; along with the continuous increase of the forward static surge stress, a resistor R1, an NPN triode T3, a PNP triode T1, an NPN triode T2 and a resistor R2 in the second SCR bleeder circuit are started to release the static surge current, so that the protection capability of the full-chip static surge protection circuit is enhanced; in addition, a forward or reverse static surge stress is applied between the input/output port IO and the power supply end VDD, the electrical structure of the static surge protection circuit is identical to the layout, and the circuit has the functions of small-area and bidirectional protection.
Referring to fig. 4, fig. 4 is a schematic diagram of an esd protection circuit from an input/output terminal to a ground terminal according to the present invention; the method comprises the following steps:
applying a forward electrostatic surge stress between the input/output port IO and the ground terminal VSS, wherein a resistor R1, a voltage stabilizing tube ZD3 and a resistor R3 in the third voltage stabilizing clamp circuit are started, and the circuit has the characteristics of low leakage, low on resistance, high response speed and high maintenance voltage; along with the continuous increase of the forward static surge stress, a resistor R1, an NPN triode T3, a PNP triode T6, an NPN triode T4 and a resistor R3 in the third SCR bleeder circuit are started to release the static surge current, so that the protection capability of the full-chip static surge protection circuit is enhanced; in addition, a forward or reverse static surge stress is applied between the input/output port IO and the ground terminal VSS, the electrical structure of the static surge protection circuit is identical to the layout, and the circuit has the functions of small-area and bidirectional protection.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations and modifications of the present invention will be apparent to those of ordinary skill in the art in light of the foregoing description. It is not necessary here nor is it exhaustive of all embodiments. And obvious variations or modifications thereof are contemplated as falling within the scope of the present invention.
Claims (6)
1. A full-chip electrostatic surge protection circuit for an ac-dc converter, comprising: the voltage regulator ZD1, the voltage regulator ZD2, the voltage regulator ZD3, the resistor R1, the resistor R2, the resistor R3, the PNP triode T1, the NPN triode T2, the NPN triode T3, the NPN triode T4, the PNP triode T5, the PNP triode T6, the NPN triode T7, the power supply terminal VDD, the input/output terminal IO and the ground terminal VSS; a voltage-stabilizing clamp circuit and an electrostatic surge bleeder circuit can be formed;
the voltage stabilizing clamp circuit includes: the first voltage stabilizing clamp circuit, the second voltage stabilizing clamp circuit and the third voltage stabilizing clamp circuit;
the first voltage stabilizing clamp circuit includes: the resistor R2, the voltage stabilizing tube ZD3 and the resistor R3; one end of a resistor R2 is connected with a power supply end VDD, the other end of the resistor R2 is connected with the cathode of a voltage stabilizing tube ZD2, the anode of the voltage stabilizing tube ZD2 is connected with the anode of a voltage stabilizing tube ZD3, the cathode of the voltage stabilizing tube ZD3 is connected with one end of the resistor R3, and the other end of the resistor R3 is connected with a grounding end VSS;
the second voltage stabilizing clamp circuit includes: the resistor R1, the voltage stabilizing tube ZD2 and the resistor R2; one end of a resistor R1 is connected with an input/output port IO, the other end of the resistor R1 is connected with the cathode of a voltage stabilizing tube ZD1, the anode of the voltage stabilizing tube ZD1 is connected with the anode of a voltage stabilizing tube ZD2, the cathode of the voltage stabilizing tube ZD2 is connected with one end of the resistor R2, and the other end of the resistor R2 is connected with a power supply end VDD;
the third voltage stabilizing clamp circuit includes: the resistor R1, the voltage stabilizing tube ZD3 and the resistor R3; one end of a resistor R1 is connected with an input/output port IO, the other end of the resistor R1 is connected with the cathode of a voltage stabilizing tube ZD1, the anode of the voltage stabilizing tube ZD1 is connected with the anode of a voltage stabilizing tube ZD3, the cathode of the voltage stabilizing tube ZD3 is connected with one end of the resistor R3, and the other end of the resistor R3 is connected with a grounding end VSS;
the electrostatic surge bleeder circuit comprises: the first SCR bleeder circuit, the second SCR bleeder circuit and the third SCR bleeder circuit;
the first SCR bleeder circuit comprises: the resistor R2, the NPN triode T2, the PNP triode T5, the NPN triode T4 and the resistor R3; the second SCR bleeder circuit comprises: the resistor R1, the NPN triode T3, the PNP triode T1, the NPN triode T2 and the resistor R2; the third SCR bleeder circuit comprises: the resistor R1, the NPN triode T3, the PNP triode T6, the NPN triode T4 and the resistor R3;
one end of the resistor R2 is connected with the power supply end VDD and the emitter of the NPN triode T2; the other end of the resistor R2 is connected with the base electrode of the NPN triode T2, the emitter electrode of the PNP triode T5, the collector electrode of the PNP triode T1, the collector electrode of the NPN triode T7 and the cathode of the voltage stabilizing tube ZD 2; the collector of the NPN triode T2 is connected with the base of the PNP triode T5, the collector of the NPN triode T4, the collector of the NPN triode T3, the base of the PNP triode T1 and the base of the PNP triode T6; the base electrode of the NPN triode T4 is connected with the collector electrode of the PNP triode T5, one end of the resistor R3, the cathode of the voltage stabilizing tube ZD3, the emitter electrode of the NPN triode T7 and the collector electrode of the PNP triode T6, and the emitter electrode of the NPN triode T4 is connected with the other end of the resistor R3 and the ground terminal VSS; the anode of the voltage stabilizing tube ZD3 is connected with the anode of the voltage stabilizing tube ZD2, the base electrode of the NPN triode T7 and the anode of the voltage stabilizing tube ZD 1; the cathode of the voltage stabilizing tube ZD1 is connected with the base electrode of the NPN triode T3, the emitter electrode of the PNP triode T6, the emitter electrode of the PNP triode T1 and the other end of the resistor R1; one end of the resistor R1 and the emitter of the NPN triode T3 are connected with the input/output end IO;
when the electrostatic surge stress acts between the power supply end VDD and the ground end VSS, the electrostatic surge stress is released through the first voltage-stabilizing clamping circuit and the first SCR bleeder circuit;
when the electrostatic surge stress acts between the input/output end IO and the power supply end VDD, the electrostatic surge stress is released through the second voltage stabilizing clamp circuit and the second SCR bleeder circuit;
when the electrostatic surge stress acts between the input/output terminal IO and the ground terminal VSS, the electrostatic surge stress is released through the third voltage stabilizing clamp circuit and the third SCR bleeder circuit.
2. The full-chip electrostatic surge protection circuit for an ac-dc converter according to claim 1, wherein the first voltage stabilizing clamp circuit is configured to enhance a fast turn-on and voltage clamping function in electrostatic surge protection between the power supply terminal VDD and the ground terminal VSS; the second voltage-stabilizing clamp circuit is used for enhancing the rapid starting and voltage clamping functions in the electrostatic surge protection between the input/output end IO and the power supply end VDD; the third voltage stabilizing clamp circuit is used for enhancing the rapid starting and voltage clamping functions in electrostatic surge protection between the input/output end IO and the ground end VSS.
3. The full-chip electrostatic surge protection circuit for an ac-dc converter according to claim 1, wherein a forward electrostatic surge stress is applied between a power supply terminal VDD and a ground terminal VSS, and a resistor R2, a regulator ZD3 and a resistor R3 in the first voltage-stabilizing clamp circuit are turned on, and the circuit has low leakage, low on-resistance, fast response speed, and high sustain voltage characteristics; along with the continuous increase of the forward static surge stress, a resistor R2, an NPN triode T2, a PNP triode T5, an NPN triode T4 and a resistor R3 in the first SCR bleeder circuit are started to release the static surge current, so that the protection capability of the static surge full-chip protection circuit is enhanced; meanwhile, the collector of the NPN triode T7 and the voltage stabilizing tube ZD2 share the same semiconductor structure, and the emitter of the NPN triode T7 and the voltage stabilizing tube ZD3 share the same semiconductor structure, so that the conduction uniformity of the full-chip electrostatic surge protection circuit can be enhanced, and the robustness is further improved; in addition, when the forward or reverse electrostatic surge stress is applied between the power supply end VDD and the ground end VSS, the electrical structure of the electrostatic surge protection circuit is identical to the layout, and the circuit has the functions of small area and bidirectional protection.
4. The full-chip electrostatic surge protection circuit for an ac-dc converter according to claim 1, wherein a forward electrostatic surge stress is applied between the input/output port IO and the power supply terminal VDD, and the resistor R1, the regulator ZD2 and the resistor R2 in the second regulator clamp circuit are turned on, and the circuit has low leakage, low on-resistance, fast response speed, and high sustain voltage characteristics; along with the continuous increase of the forward static surge stress, a resistor R1, an NPN triode T3, a PNP triode T1, an NPN triode T2 and a resistor R2 in the second SCR bleeder circuit are started to release the static surge current, so that the protection capability of the full-chip static surge protection circuit is enhanced; in addition, when the forward or reverse electrostatic surge stress is applied between the input/output port IO and the power supply end VDD, the electrical structure of the electrostatic surge protection circuit is identical to the layout, and the circuit has the functions of small-area and bidirectional protection.
5. The full-chip electrostatic surge protection circuit for an ac-dc converter according to claim 1, wherein a forward electrostatic surge stress is applied between the input/output port IO and the ground terminal VSS, and the resistor R1, the regulator ZD3, and the resistor R3 in the third regulator clamp circuit are turned on, and the circuit has low leakage, low on-resistance, fast response speed, and high sustain voltage characteristics; along with the continuous increase of the forward static surge stress, a resistor R1, an NPN triode T3, a PNP triode T6, an NPN triode T4 and a resistor R3 in the third SCR bleeder circuit are started to release the static surge current, so that the protection capability of the full-chip static surge protection circuit is enhanced; in addition, a forward or reverse static surge stress is applied between the input/output port IO and the ground terminal VSS, the electrical structure of the static surge protection circuit is identical to the layout, and the circuit has the functions of small-area and bidirectional protection.
6. The full-chip electrostatic surge protection circuit for an ac-dc converter according to claim 1, wherein the regulator ZD2 and the resistor R2 are shared by the first voltage-stabilizing clamp circuit and the second voltage-stabilizing clamp circuit; the first voltage stabilizing clamp circuit and the third voltage stabilizing clamp circuit share a voltage stabilizing tube ZD3 and a resistor R3; the second voltage stabilizing clamp circuit and the third voltage stabilizing clamp circuit share a voltage stabilizing tube ZD1 and a resistor R1;
the first SCR bleeder circuit and the second SCR bleeder circuit share a resistor R2 and an NPN triode T2; the first SCR bleeder circuit and the third SCR bleeder circuit share an NPN triode T4 and a resistor R3; the second SCR bleeder circuit and the third SCR bleeder circuit share the resistor R1 and the NPN triode T3, so that the multiplexing rate of the internal modules of the circuit is improved, the area of a full-chip electrostatic surge protection circuit of an alternating current-direct current conversion chip is reduced, and the efficiency ratio is improved.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311807109.1A CN117767718A (en) | 2023-12-26 | 2023-12-26 | Full-chip electrostatic surge protection circuit suitable for alternating current-direct current converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311807109.1A CN117767718A (en) | 2023-12-26 | 2023-12-26 | Full-chip electrostatic surge protection circuit suitable for alternating current-direct current converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117767718A true CN117767718A (en) | 2024-03-26 |
Family
ID=90314183
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311807109.1A Pending CN117767718A (en) | 2023-12-26 | 2023-12-26 | Full-chip electrostatic surge protection circuit suitable for alternating current-direct current converter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117767718A (en) |
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2023
- 2023-12-26 CN CN202311807109.1A patent/CN117767718A/en active Pending
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