CN117766473A - Semiconductor structure and manufacturing method thereof - Google Patents

Abstract

Embodiments of the present disclosure provide a semiconductor structure and a method of manufacturing the same. The semiconductor structure includes: a substrate; a device structure disposed on a middle region of the substrate; a transition layer and a first sealing layer disposed on an edge region of the substrate, the transition layer being provided with a plurality of grooves, a cross-sectional width of the grooves at least one depth position being greater than or equal to a cross-sectional width of the grooves at a top surface thereof in a cross-section perpendicular to the substrate; a plurality of protrusions are arranged at the position, opposite to the grooves, of the first sealing layer, and the grooves of the transition layer and the protrusions of the first sealing layer are mutually embedded; wherein the edge region surrounds the intermediate region.

Description

Semiconductor structure and manufacturing method thereof

Technical Field

The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a semiconductor structure and a manufacturing method thereof.

Background

The fabrication process of semiconductor devices involves a large number of film structures, some of which need to be removed and some of which need to be permanently retained in the semiconductor device for protection or shielding. For the film structures that need to be retained in the semiconductor device, adhesion between the film structures is critical. If the adhesion between the film structures is poor or the adhesion between the film structures is destructive in the subsequent process, the film structures are easy to fall off and cannot exert the due protection effect.

Disclosure of Invention

Accordingly, embodiments of the present disclosure provide a semiconductor structure and a method for fabricating the same to solve at least one technical problem existing in the prior art.

In order to achieve the above purpose, the technical scheme of the present disclosure is realized as follows:

in a first aspect, embodiments of the present disclosure provide a semiconductor structure comprising:

a substrate;

a device structure disposed on a middle region of the substrate;

a transition layer and a first sealing layer disposed on an edge region of the substrate, the transition layer being provided with a plurality of grooves, a cross-sectional width of the grooves at least one depth position being greater than or equal to a cross-sectional width of the grooves at a top surface thereof in a cross-section perpendicular to the substrate; a plurality of protrusions are arranged at the position, opposite to the grooves, of the first sealing layer, and the grooves of the transition layer and the protrusions of the first sealing layer are mutually embedded; wherein the edge region surrounds the intermediate region.

In some embodiments, the semiconductor structure further comprises a second sealing layer; wherein,

the second sealing layer is arranged on one side of the device structure far away from the substrate, the second sealing layer covers the substrate, and a first cavity is formed between the second sealing layer and the middle area of the substrate; the device structure is located within the first cavity.

In some embodiments, the sidewalls of the recess are uneven surfaces; and/or, the bottom surface of the groove is an uneven surface.

In some embodiments, a ratio between a cross-sectional width at a bottom surface of the groove and a depth of the groove is greater than or equal to 10 in a cross-section perpendicular to the substrate.

In some embodiments, the depth of the recess is greater than 500nm in a direction perpendicular to the substrate;

the cross-sectional width at the bottom surface of the recess is greater than 5 μm in a cross-section perpendicular to the substrate.

In some embodiments, where the device structure is a thin film bulk acoustic resonator, the thin film bulk acoustic resonator includes a lower electrode layer, a piezoelectric layer, and an upper electrode layer with a second cavity therebetween, in a direction pointing away from the substrate proximate to the substrate; wherein the material of the transition layer and the piezoelectric layer is the same, and the transition layer and the piezoelectric layer are formed in the same process step.

In some embodiments, the device structure further includes an etched hole extending at least through the piezoelectric layer.

In some embodiments, the distribution density of the grooves on the transition layer proximate to the etch holes is greater than the distribution density of the grooves distal to the etch holes;

The depth of the groove on the transition layer, which is close to the etching hole, is greater than the depth of the groove, which is far away from the etching hole, along the direction perpendicular to the substrate.

In some embodiments, where the device structure is a thin film bulk acoustic resonator, the thin film bulk acoustic resonator includes a lower electrode layer, a piezoelectric layer, an upper electrode layer, and a tuning layer, with a second cavity therebetween, pointing away from the substrate in a direction proximal to the substrate; wherein the material of the transition layer and the adjustment layer is the same, and the transition layer and the adjustment layer are formed in the same process step.

In some embodiments, the transition layer is formed by a plating process;

the first sealing layer is formed through a spin coating process.

In some embodiments, the material of the transition layer comprises an etchant resistant material;

the material of the first sealing layer comprises a curable photoresist and/or a resin.

In some embodiments, the material of the transition layer comprises at least one of: aluminum nitride AlN, aluminum scandium nitride AlScN, zinc oxide ZnO, lead zirconate titanate PZT, molybdenum Mo, gold Au, ruthenium Ru, chromium Cr and platinum Pt;

The material of the first sealing layer comprises at least one of the following: polyimide PI, polybenzoxazole PBO, benzocyclobutene BCB, silicone and acrylate.

In a second aspect, embodiments of the present disclosure provide a semiconductor structure comprising:

a wafer; the wafer comprises a plurality of chip areas;

a device structure disposed on a middle region of each of the chip regions;

a transition layer and a first sealing layer disposed on an edge region of each of the chip regions, the transition layer being provided with a plurality of grooves, a cross-sectional width of the grooves at least one depth position being greater than or equal to a cross-sectional width of the grooves at a top surface thereof in a cross-section perpendicular to the wafer; a plurality of protrusions are arranged at the position, opposite to the grooves, of the first sealing layer, and the grooves of the transition layer and the protrusions of the first sealing layer are mutually embedded; wherein the edge region surrounds the intermediate region.

In some embodiments, the distribution density of the grooves on the transition layer near the edge regions of the wafer and/or the die region is greater than the distribution density of the grooves away from the edge regions of the wafer and/or the die region;

The depth of the groove on the transition layer near the edge area of the wafer and/or the chip area is larger than the depth of the groove far away from the edge area of the wafer and/or the chip area along the direction perpendicular to the wafer.

In some embodiments, the semiconductor structure further comprises a second sealing layer; wherein,

the second sealing layer is arranged on one side of the device structure far away from the wafer, the second sealing layer covers the chip area, and a first cavity is formed between the second sealing layer and the middle area of the chip area; the device structure is located within the first cavity.

In some embodiments, where the device structure is a thin film bulk acoustic resonator, the thin film bulk acoustic resonator includes a lower electrode layer, a piezoelectric layer, and an upper electrode layer in a direction pointing away from the wafer proximate to the wafer;

the semiconductor structure further comprises a welding pad, wherein the upper electrode layer and the lower electrode layer of the film bulk acoustic resonator in each chip area are electrically connected with the welding pad through electrode leads; wherein,

the distribution density of the grooves on the transition layer, which are close to the welding pad, is greater than that of the grooves, which are far away from the welding pad;

The depth of the groove on the transition layer, which is close to the welding pad, is larger than the depth of the groove, which is far away from the welding pad, along the direction perpendicular to the wafer.

In a third aspect, embodiments of the present disclosure provide a method of manufacturing a semiconductor structure, the method comprising:

providing a substrate;

forming a transition layer on an edge region of the substrate while forming a device structure in a middle region of the substrate;

forming a plurality of grooves on the transition layer; in a cross-section perpendicular to the substrate, a cross-sectional width at least one depth position of the recess is greater than or equal to a cross-sectional width at a top surface of the recess;

coating a first sealing material on the transition layer to form a first sealing layer having a plurality of protrusions opposite the grooves; wherein the grooves of the transition layer and the protrusions of the first sealing layer are mutually embedded; the edge region surrounds the intermediate region.

Embodiments of the present disclosure provide a semiconductor structure and a method of manufacturing the same. The semiconductor structure includes: a substrate; a device structure disposed on a middle region of the substrate; a transition layer and a first sealing layer disposed on an edge region of the substrate, the transition layer being provided with a plurality of grooves, a cross-sectional width of the grooves at least one depth position being greater than or equal to a cross-sectional width of the grooves at a top surface thereof in a cross-section perpendicular to the substrate; a plurality of protrusions are arranged at the position, opposite to the grooves, of the first sealing layer, and the grooves of the transition layer and the protrusions of the first sealing layer are mutually embedded; wherein the edge region surrounds the intermediate region. In the embodiment of the disclosure, the transition layer is arranged between the substrate and the first sealing layer, the transition layer is provided with the plurality of grooves, and the section width of at least one depth position of each groove is larger than or equal to the section width of the top surface of each groove, so that the grooves on the transition layer and the protrusions on the first sealing layer are mutually embedded to form a similar buckle structure, the adhesion between the transition layer and the first sealing layer is improved, and the adhesion between the substrate and the first sealing layer is improved.

Drawings

Fig. 1 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the disclosure;

fig. 2 is a schematic flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;

fig. 3A is a cross-sectional view of a process for fabricating a semiconductor structure provided in an embodiment of the present disclosure;

fig. 3B is a second cross-sectional view of a process for fabricating a semiconductor structure provided in an embodiment of the present disclosure;

fig. 3C is a third cross-sectional view of a process for fabricating a semiconductor structure provided by an embodiment of the present disclosure;

fig. 3D is a cross-sectional view of a process for fabricating a semiconductor structure provided by an embodiment of the present disclosure;

FIG. 4A is a schematic diagram of a cross-sectional structure of a groove according to an embodiment of the disclosure;

fig. 4B is a schematic diagram of a cross-sectional structure of a groove according to an embodiment of the disclosure;

fig. 4C is a schematic diagram of a cross-sectional structure of a groove according to an embodiment of the disclosure;

fig. 4D is a schematic cross-sectional view of a groove according to an embodiment of the disclosure;

fig. 4E is a schematic diagram showing a cross-sectional structure of a groove according to an embodiment of the present disclosure;

fig. 4F is a schematic cross-sectional view of a groove according to an embodiment of the disclosure;

fig. 5 is a schematic cross-sectional view of another semiconductor structure according to an embodiment of the disclosure;

Fig. 6A is a schematic cross-sectional view of a thin film bulk acoustic resonator according to an embodiment of the present disclosure;

fig. 6B is a schematic diagram of a cross-sectional structure of a thin film bulk acoustic resonator according to an embodiment of the disclosure;

FIG. 7 is a schematic cross-sectional view of another thin film bulk acoustic resonator according to an embodiment of the present disclosure;

fig. 8 is a partial perspective view of a top view of a semiconductor structure provided by an embodiment of the present disclosure;

the drawings include: 101. 201, 301, a substrate; 101a, 201a, 301a, a middle region of the substrate; 101b, 201b, 301b, edge regions of the substrate; 102. a device structure; 103. 203, 306, a transition layer; 104. 104a, 104b, 104c, 104d, 104e, 104f, 204, 307, grooves; 105. 209, 309, a first sealing layer; 106. 210, 310, protrusions; 107. a patterned photoresist layer; 108. 211, 311, a second sealing layer; 202. 302, a lower electrode layer; 205. 303, a piezoelectric layer; 206. 304, 404, etching holes; 207. 305, 403, upper electrode layer; 208. 308, a conditioning layer; 401. a wafer; 402. a chip region; 405. an electrode lead; 406. and (5) welding pads.

Detailed Description

The following description of the embodiments of the present disclosure will be made clearly and fully with reference to the embodiments of the present disclosure and the accompanying drawings, it being apparent that the described embodiments are only some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without inventive effort, based on the embodiments in this disclosure are intended to be within the scope of this disclosure.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present disclosure.

Spatially relative terms, such as "under … …," "under … …," "below," "under … …," "above … …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under … …" and "under … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

For a thorough understanding of the present disclosure, detailed steps and detailed structures will be presented in the following description in order to illustrate the technical aspects of the present disclosure. Preferred embodiments of the present disclosure are described in detail below, however, the present disclosure may have other implementations in addition to these detailed descriptions.

During the fabrication of semiconductor devices (e.g., semiconductor devices including cavities), a sacrificial layer Release (Release) process may be used to form cavities in the semiconductor devices. Specifically, an appropriate etchant may be selected by a dry etching and/or wet etching method, and the etchant may be injected into the etching holes exposing the sacrificial layer such that the etchant contacts and chemically reacts with the exposed sacrificial layer to remove the sacrificial layer and form the cavity.

The fabrication process of semiconductor devices involves a large number of film structures, some of which need to be removed and some of which need to be permanently retained in the semiconductor device for protection or shielding. For the film structures that need to be retained in the semiconductor device, adhesion between the film structures is critical. If the adhesion between the film structures themselves is poor or the adhesion between the film structures is destructive by a subsequent process (e.g., a sacrificial layer release process), the film structures are easily detached and cannot exert a proper protective effect. For example, polyimide (PI) is a preferred material, and has the advantages of good heat resistance, insulation, resistance to damp heat, resistance to high-temperature radiation, and the like, and good adhesion between Polyimide and a substrate (e.g., a silicon wafer) itself, but poor adhesion between Polyimide and a substrate becomes poor after a sacrificial layer release process. This is because the longer Hydrogen Fluoride (HF) environment in the sacrificial layer release process can damage the adhesion between the polyimide and the silicon wafer.

In view of the above, embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same.

Referring to fig. 1, fig. 1 is a schematic cross-sectional structure of a semiconductor structure according to an embodiment of the disclosure. As shown in fig. 1, a semiconductor structure provided in an embodiment of the present disclosure includes: a substrate 101; a device structure 102 disposed on the intermediate region 101a of the substrate; a transition layer 103 and a first sealing layer 105 provided on an edge region 101b of the substrate, the transition layer 103 being provided with a plurality of grooves 104, a cross-sectional width at least one depth position of the grooves 104 being greater than or equal to a cross-sectional width at a top surface of the grooves 104 in a cross-section perpendicular to the substrate 101; a plurality of protrusions 106 are provided at positions of the first sealing layer 105 opposite to the grooves 104, and the grooves 104 of the transition layer 103 and the protrusions 106 of the first sealing layer 105 are fitted to each other; wherein the edge region 101b of the substrate surrounds the middle region 101a of the substrate.

It should be noted that the cross-sectional shape of the groove shown in fig. 1 in a cross-section perpendicular to the substrate appears rectangular, that is, the cross-sectional width at each depth position of the groove is the same. For example, the cross-sectional width at the bottom surface of the groove is the same as the cross-sectional width at the top surface of the groove.

In the embodiment of the disclosure, the transition layer is arranged between the substrate and the first sealing layer, the transition layer is provided with the plurality of grooves, and the section width of at least one depth position of each groove is larger than or equal to the section width of the top surface of each groove, so that the grooves on the transition layer and the protrusions on the first sealing layer are mutually embedded to improve the adhesion between the transition layer and the first sealing layer, and further improve the adhesion between the substrate and the first sealing layer. The adhesion between the substrate and the transition layer itself was good.

Referring to fig. 2, fig. 2 is a flow chart illustrating a method for manufacturing a semiconductor structure according to an embodiment of the disclosure. As shown in fig. 2, a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure includes the following steps:

step S201: providing a substrate;

step S202: forming a transition layer on an edge region of a substrate while forming a device structure in a middle region of the substrate;

step S203: forming a plurality of grooves on the transition layer; in a cross-section perpendicular to the substrate, the cross-sectional width at least one depth position of the recess is greater than or equal to the cross-sectional width at the top surface of the recess;

Step S204: coating a first sealing material on the transition layer to form a first sealing layer having a plurality of protrusions opposite the grooves; wherein, the groove of the transition layer and the bulge of the first sealing layer are mutually embedded; the edge region surrounds the middle region.

The method for manufacturing the semiconductor structure according to the embodiment of the present disclosure will be described in detail below with reference to fig. 3A to 3D.

Referring to fig. 3A, a transition layer 103 is formed on an edge region 101b of a substrate while a device structure 102 is formed on a middle region 101a of the substrate. Wherein the edge region 101b of the substrate surrounds the middle region 101a of the substrate.

Referring to fig. 3B, a patterned photoresist layer 107 is formed on the transition layer 103. The pattern of the photoresist layer is used for defining the shape of the groove formed on the transition layer in the subsequent process.

Referring to fig. 3C, the transition layer 103 is etched through the patterned photoresist layer 107 to form the grooves 104.

In embodiments of the present disclosure, the transition layer may be etched using dry etching, wet etching, or a combination thereof to form the recess. Here, the number and distribution density of the grooves may be set according to the needs of those skilled in the art. The wet etching is performed by using an etchant, for example, an acid-base solution; the dry etching includes physical etching, chemical etching and physicochemical etching. Wherein, the physical etching is to ionize gas into positively charged ions by glow discharge, then accelerate the ions by bias voltage, and splash the ions on the surface of the etched object to knock out the atoms of the etched object; the chemical etching uses plasma to ionize etching gas and form charged ions, molecules and atomic groups with strong reactivity, and the charged ions, molecules and atomic groups react with surface atoms of an etched object to generate a volatile reaction product after being diffused to the surface of the etched object, and the volatile reaction product is pumped out of the reaction cavity by vacuum equipment.

Still referring to fig. 3C, the cross-sectional shape of the groove 104 appears rectangular in a cross-section perpendicular to the substrate. Wherein, along the direction vertical to the substrate, the depth of the groove 104 is H ₁ The method comprises the steps of carrying out a first treatment on the surface of the In a cross section perpendicular to the substrate, the cross section width at the top surface of the groove 104 is W ₁ The cross-sectional width at the bottom surface of the groove 104 is W ₂ 。

In the embodiment of the disclosure, the depth of the groove is smaller than the thickness of the transition layer along the direction perpendicular to the substrate. In other words, the transition layer is etched to form a groove, and the bottom of the groove does not expose the surface of the substrate.

It should be noted that FIG. 3C illustrates that the cross-sectional shape of the groove is rectangular, and therefore, the cross-sectional width W at the top surface of the groove ₁ And a cross-sectional width W at the bottom surface of the groove ₂ The same applies.

In the embodiment of the present disclosure, a ratio between a cross-sectional width at a bottom surface of the groove and a depth of the groove is greater than or equal to 10 in a cross-section perpendicular to the substrate.

In the embodiment of the disclosure, the depth H of the groove is along the direction perpendicular to the substrate ₁ Greater than 500nm; cross-sectional width W at bottom surface of groove in cross-section perpendicular to substrate ₂ Greater than 5 μm.

Referring to fig. 3D, the patterned photoresist layer is removed, and a first sealing material is coated on the transition layer 103 to form a first sealing layer 105 having a plurality of protrusions 106 opposite the grooves 104; wherein the grooves 104 of the transition layer 103 and the protrusions 106 of the first sealing layer 105 are engaged with each other.

In the embodiment of the present disclosure, the first sealing layer may be formed by a spin coating process. The transition layer is coated with the first sealing material, the first sealing material enters the groove of the transition layer in the coating process, and then the first sealing material is solidified in a post-baking mode and the like, so that the first sealing layer can be embedded into the groove of the transition layer, the contact area between the transition layer and the first sealing layer is increased, the adhesiveness between the transition layer and the first sealing layer is improved, and the adhesiveness between the substrate and the first sealing layer is improved.

Here, the process of forming the first sealing layer using the spin coating process is as follows: and coating the first sealing material on the transition layer, rotating at a certain speed, wherein the first sealing material can enter the groove of the transition layer in the rotating process, and forming the bulge of the first sealing layer after the first sealing material entering the groove of the transition layer is solidified, so that the first sealing layer with a certain thickness is finally formed.

It should be noted that during the formation of the device structure on the intermediate region of the substrate, a sacrificial layer release process may be used to form the cavity. According to the semiconductor structure provided by the embodiment of the disclosure, the transition layer is arranged between the substrate and the first sealing layer, and the grooves on the transition layer and the protrusions on the first sealing layer are mutually embedded, so that even if a long-time hydrogen fluoride environment exists in a sacrificial layer release process, the adhesion between the substrate and the first sealing layer is difficult to damage, the adhesion between the substrate and the first sealing layer can be improved, the performance of the device structure is improved, and the service life of the device structure is prolonged. It should be noted that the adhesion between the substrate and the transition layer is good even in the hydrogen fluoride environment.

The different cross-sectional shapes of the grooves provided by the embodiments of the present disclosure will be described in detail below in conjunction with fig. 4A through 4E.

Referring to fig. 4A, the transition layer 103 is etched to form a plurality of grooves 104A; the depth of the groove 104a is H in the direction perpendicular to the substrate ₂ The method comprises the steps of carrying out a first treatment on the surface of the In a cross section perpendicular to the substrate, the cross section width at the top surface of the groove 104a is W ₃ The cross-sectional width at the bottom surface of the groove 104a is W ₄ . The cross-sectional shape of the groove 104A illustrated in fig. 4A still appears rectangular, and the cross-sectional width W at the top surface of the groove 104A ₃ And a cross-sectional width W at the bottom surface of the groove 104a ₄ The same; and a plurality of tooth-like projections are formed at the side walls and bottom of the groove 104 a.

In the embodiment of the disclosure, the side wall of the groove is an uneven surface; and/or the bottom surface of the groove is an uneven surface. Here, increasing the roughness of the side walls of the groove and/or the bottom surface of the groove may increase the interaction force between the groove and the protrusions of the first sealing layer, which is advantageous for improving the fitting effect between the transition layer and the first sealing layer, and thus improving the adhesion between the transition layer and the first sealing layer.

In the embodiment of the disclosure, the toothed protrusions are formed on the side wall and the bottom of the groove, so that the roughness of the side wall and the bottom of the groove is increased, and the adhesiveness between the groove and the first sealing layer is further increased.

Referring to fig. 4B, the transition layer 103 is etched to form a plurality of grooves 104B; the depth of the groove 104b is H in the direction perpendicular to the substrate ₃ The method comprises the steps of carrying out a first treatment on the surface of the In a cross section perpendicular to the substrate, the cross section width at the top surface of the groove 104b is W ₅ The cross-sectional width at the bottom surface of the groove 104b is W ₆ Wherein the cross-sectional width W at the top surface of the groove 104b ₅ Less than the cross-sectional width W at the bottom surface of the groove 104b ₆ . The cross-sectional shape of the groove 104B illustrated in FIG. 4B includes two rectangles, the first rectangle having a cross-sectional width W ₅ The second rectangle has a cross-sectional width W ₆ The sum of the depths of the two rectangles in the direction perpendicular to the substrate is H ₃ 。

Here, the etching may be performed stepwise, and the etching is performed longitudinally along a direction perpendicular to the substrate to form a depth H ₃ Cross-sectional width W ₅ Is a pre-groove of (a); and then transversely etching to increase the cross-sectional width of the bottom of the pre-groove to W ₆ To form the recess 104b. Typically, the vertical etching is performed using a dry etching process and the lateral etching is performed using a wet etching process.

Referring to fig. 4C, the transition layer 103 is etched to form a plurality of grooves 104C; the depth of the groove 104c is H in the direction perpendicular to the substrate ₄ The method comprises the steps of carrying out a first treatment on the surface of the In a cross section perpendicular to the substrate, the cross section width at the top surface of the groove 104c is W ₇ The cross-sectional width at the bottom surface of the groove 104c is W ₈ Wherein the cross-sectional width W at the top surface of the groove 104c ₇ Less than the cross-sectional width W at the bottom surface of the groove 104c ₈ . The cross-sectional shape of the groove 104C illustrated in fig. 4C exhibits a trapezoid shape with a narrow top and a wide bottom, and the cross-sectional width of the groove 104C increases as the depth of the groove 104C increases from the top surface of the groove 104C.

Referring to fig. 4D, the transition layer 103 is etched to form a plurality of grooves 104D; the depth of the groove 104d is H in the direction perpendicular to the substrate ₅ The method comprises the steps of carrying out a first treatment on the surface of the In a cross section perpendicular to the substrate, the cross section width at the top surface of the groove 104d is W ₉ The cross-sectional width of the groove 104d at a depth position is W ₁₀ Wherein W is ₁₀ Is a grooveMaximum cross-sectional width of 104d, cross-sectional width W at the top surface of groove 104d ₉ Less than the cross-sectional width W at a depth position of the groove 104d ₁₀ . The cross-sectional shape of the groove 104D illustrated in fig. 4D is rendered polygonal, and the cross-sectional width of the groove 104D increases and decreases from the top surface of the groove 104D as the depth of the groove 104D increases.

Referring to fig. 4E, the transition layer 103 is etched to form a plurality of grooves 104E; the depth of the groove 104e is H in the direction perpendicular to the substrate ₆ The method comprises the steps of carrying out a first treatment on the surface of the In a cross section perpendicular to the substrate, the cross section width at the top surface of the groove 104e is W ₁₁ The cross-sectional width of the groove 104e at a depth position is W ₁₂ Wherein W is ₁₂ For the maximum cross-sectional width of the groove 104e, the cross-sectional width W at the top surface of the groove 104e ₁₁ Less than the cross-sectional width W at a depth position of the groove 104e ₁₂ . The cross-sectional shape of the groove 104E illustrated in fig. 4E is shaped like a profile, and the side walls of the groove 104E are formed by connecting a plurality of arcs, and the cross-sectional width of the groove 104E increases and decreases from the top surface of the groove 104E as the depth of the groove 104E increases.

Referring to fig. 4F, the transition layer 103 is etched to form a plurality of grooves 104F; the depth of the groove 104f is H in the direction perpendicular to the substrate ₇ The method comprises the steps of carrying out a first treatment on the surface of the In a cross section perpendicular to the substrate, the cross section width at the top surface of the groove 104f is W ₁₃ The cross-sectional width at the bottom surface of the groove 104f is W ₁₄ Wherein W is ₁₄ Cross-sectional width W at the top surface of groove 104f, which is the maximum cross-sectional width of groove 104e ₁₃ Less than the cross-sectional width W at a depth position of the groove 104f ₁₄ . The cross-sectional shape of the groove 104F illustrated in FIG. 4F includes a rectangular shape having a cross-sectional width W and a trapezoid having a narrow upper portion and a wide lower portion ₁₃ The width of the top edge of the trapezoid is W ₁₃ The width of the bottom edge of the trapezoid is W ₁₄ The sum of the depths of the rectangle and trapezoid in the direction perpendicular to the substrate is H ₇ . In other words, the cross-sectional width of the groove 104f increases from the top surface of the groove 104f as the depth of the groove 104f increases. Here, the recess of the transition layer is truncatedThe effect of the snap-fit between the portion of increased face width (i.e., the portion of trapezoidal cross-sectional shape) and the protrusion of the first sealing layer increases the interaction force between the transition layer and the first sealing layer.

In an embodiment of the present disclosure, in a cross section perpendicular to the substrate, a cross-sectional width at least one depth position of the groove is greater than or equal to a cross-sectional width at a top surface of the groove. In other words, when the first sealing material is coated on the transition layer, the first sealing material enters the groove of the transition layer in the coating process, and then the first sealing material is solidified in a post-baking mode and the like, so that the first sealing layer can be embedded into the groove of the transition layer, and as the groove with a special shape is arranged on the transition layer, a buckle-like effect is formed between the groove of the transition layer and the bulge of the first sealing layer, the interaction force between the transition layer and the first sealing layer is increased, the adhesiveness between the transition layer and the first sealing layer is improved, and the adhesiveness between the substrate and the first sealing layer is further improved.

Referring to fig. 5, fig. 5 is a schematic cross-sectional structure of another semiconductor structure according to an embodiment of the disclosure. As shown in fig. 5, the semiconductor structure further includes a second sealing layer 108; wherein the second sealing layer 108 is disposed on a side of the device structure 102 away from the substrate 101, and the second sealing layer 108 covers the substrate 101, and a first cavity is formed between the second sealing layer 108 and the middle region 101a of the substrate; the device structure 102 is located within the first cavity.

In the embodiment of the disclosure, a sacrificial layer covering the device structure may be formed on the intermediate region of the substrate, the sacrificial layer is removed by a sacrificial layer release process, a first cavity is formed between the second sealing layer and the intermediate region of the substrate, and the device structure is located in the first cavity. In the embodiment of the disclosure, a device structure with a cavity can be formed on the middle area of the substrate, wherein the cavity in the device structure is formed through a sacrificial layer release process.

In an embodiment of the present disclosure, the material of the transition layer includes an etchant resistant material. Here, the etchant inevitably contacts the transition layer during the formation of the first cavity through the sacrificial layer release process and during the formation of the device structure having the cavity through the sacrificial layer release process. The transition layer is formed by selecting the material resistant to the etchant, and the etching rate of the etchant to the transition layer is obviously lower than that of the etchant to the sacrificial layer, so that the etchant can not obviously etch and damage the transition layer in the process of removing the sacrificial layer by using the etchant. Even the transition layer can be formed by selecting a proper etching-resistant material, and the transition layer is not etched when the sacrificial layer is etched and removed.

In embodiments of the present disclosure, a sacrificial layer release process is used to form a first cavity between a middle region of a substrate and a second sealing layer and to form a device structure having a cavity. According to the semiconductor structure provided by the embodiment of the disclosure, the transition layer is arranged between the substrate and the first sealing layer, the plurality of grooves are formed in the transition layer, the section width of at least one depth position of each groove is larger than or equal to that of the top surface of each groove, and the grooves on the transition layer are mutually embedded with the protrusions on the first sealing layer.

In one specific example, the device structure may include a thin film bulk acoustic resonator (Thin Film Bulk Acoustic Wave Resonator, FBAR).

The semiconductor structure and the method for manufacturing the same according to the embodiments of the present disclosure will be described in detail below with reference to fig. 6A, 6B, and 7.

Fig. 6A and 6B are schematic cross-sectional views showing a case where the device structure is a thin film bulk acoustic resonator in one specific example.

Referring to fig. 6A, a semiconductor structure provided by an embodiment of the present disclosure includes: a substrate 201; forming a thin film bulk acoustic resonator on the intermediate region 201a of the substrate, the thin film bulk acoustic resonator comprising a lower electrode layer 202, a piezoelectric layer 205 and an upper electrode layer 207, with a second cavity between the lower electrode layer 202 and the substrate 201, in a direction pointing away from the substrate 201 towards the substrate 201; wherein the material of the transition layer 203 and the piezoelectric layer 205 is the same, and the transition layer 203 and the piezoelectric layer 205 are formed in the same process step. The thin film bulk acoustic resonator also includes an etched hole 206 through the piezoelectric layer 205.

The semiconductor structure provided by the embodiment of the disclosure further comprises: a first sealing layer 209 disposed on the transition layer 203 on the edge region 201b of the substrate; the transition layer 203 is provided with a plurality of grooves 204, the cross-sectional width of at least one depth position of the grooves 204 is larger than or equal to the cross-sectional width of the top surface of the grooves 204, the position of the first sealing layer 209 opposite to the grooves 204 is provided with a plurality of protrusions 210, and the grooves 204 of the transition layer 203 and the protrusions 210 of the first sealing layer 209 are mutually embedded; wherein the edge region 201b of the substrate surrounds the middle region 201a of the substrate.

The semiconductor structure provided by the embodiment of the disclosure further comprises: a second sealing layer 211; the second sealing layer 211 is arranged on one side of the thin film bulk acoustic resonator, which is far away from the substrate 201, and the second sealing layer 211 covers the substrate 201, and a first cavity is formed between the second sealing layer 211 and the middle region 201a of the substrate; the thin film bulk acoustic resonator is located within the first cavity.

The specific process of forming the thin film bulk acoustic resonator in the semiconductor structure provided by the embodiment of the disclosure is as follows: forming a sacrificial layer (not illustrated in fig. 6A) and a lower electrode layer 202 covering the sacrificial layer on the intermediate region 201a of the substrate; forming a transition layer 203 on an edge region 201b of the substrate while forming a piezoelectric layer 205 covering the lower electrode layer 202 on the intermediate region 201a of the substrate; an upper electrode layer 207 covering the piezoelectric layer 205 is formed on the intermediate region 201a of the substrate; forming an etched hole 206 penetrating at least the piezoelectric layer 205; the transition layer 203 is etched to form a plurality of grooves 204, and a first sealing material is coated on the transition layer 203 to form a first sealing layer 209 having a plurality of protrusions 210 opposite the grooves 204.

In an embodiment of the present disclosure, the material of the transition layer and the material of the piezoelectric layer may be the same, and the material of the transition layer includes at least one of: aluminum nitride AlN, aluminum scandium nitride AlScN, zinc oxide ZnO and lead zirconate titanate PZT.

In the embodiment of the disclosure, the piezoelectric layer located on the middle region of the substrate and the transition layer located on the edge region of the substrate may be simultaneously formed through a plating process.

In embodiments of the present disclosure, the material of the sacrificial layer may be silicon dioxide.

Forming a thin film bulk acoustic resonator within a semiconductor structure provided by the disclosed embodiments further includes the steps of: and selecting a proper etchant by a wet etching method, and injecting the etchant into the etching hole exposing the sacrificial layer, so that the etchant contacts with the sacrificial layer and reacts chemically to generate a liquid product or a gaseous product, thereby removing the sacrificial layer and forming a second cavity between the lower electrode layer and the substrate.

In a specific example, when the material of the sacrificial layer is silicon dioxide, hydrogen fluoride may be selected as an etchant to remove the sacrificial layer. After hydrogen fluoride reacts with the sacrificial layer through the etching holes, gaseous silicon fluoride and liquid water are generated.

In some embodiments, etching holes may be formed through the upper electrode layer, the piezoelectric layer, and the lower electrode layer. In other embodiments, the lower electrode layer and the upper electrode layer may be formed while exposing the positions of the piezoelectric layer corresponding to the etching holes, where the etching holes penetrate through the piezoelectric layer only to expose the sacrificial layer.

In the embodiment of the present disclosure, as shown in fig. 6A, the resonance region of the thin film bulk acoustic resonator includes a lower electrode layer 202, a piezoelectric layer 205, and an upper electrode layer 207 on the second cavity.

Forming the semiconductor structure provided by the disclosed embodiments further includes the steps of: a second sealing layer 211 covering the substrate 201 is formed on the first sealing layer 209.

In the embodiment of the disclosure, the second sealing layer is used for shielding and protecting the film bulk acoustic resonator. Here, a gap exists between the second sealing layer and the resonance region of the thin film bulk acoustic resonator, which gap can be used to reflect an acoustic wave.

In embodiments of the present disclosure, the constituent material of the second sealing layer may include a layered structure, such as a dry film or the like, that can be used for encapsulation.

In the embodiment of the disclosure, in the same process step, the transition layer and the piezoelectric layer are formed simultaneously, the materials of the transition layer and the piezoelectric layer are the same, the adhesion between the substrate and the first sealing layer is improved through the transition layer, and the process step for forming the transition layer is not required to be additionally added, so that the manufacturing time and the manufacturing cost are saved. The adhesion between the transition layer and the substrate itself, which is the same material as the piezoelectric layer, is good, and even in the hydrogen fluoride environment, the adhesion between the transition layer and the substrate is good.

Referring to fig. 6B, a semiconductor structure provided by an embodiment of the present disclosure includes: a substrate 201; forming a thin film bulk acoustic resonator on the intermediate region 201a of the substrate, the thin film bulk acoustic resonator comprising a lower electrode layer 202, a piezoelectric layer 205, an upper electrode layer 207 and a tuning layer 208, with a second cavity between the lower electrode layer 202 and the substrate 201, in a direction pointing away from the substrate 201 near the substrate 201; wherein the material of the transition layer 203 and the piezoelectric layer 205 is the same, and the transition layer 203 and the piezoelectric layer 205 are formed in the same process step. The thin film bulk acoustic resonator also includes an etched hole 206 through the piezoelectric layer 205.

It should be noted that the trimming (trimming) adjustment layer is a frequency modulation process for the device structure. Specifically, frequency modulation of the device structure can be achieved by thinning the adjustment layer.

In the embodiment of the present disclosure, as shown in fig. 6B, the resonance region of the thin film bulk acoustic resonator includes a lower electrode layer 202, a piezoelectric layer 205, an upper electrode layer 207, and a tuning layer 208 on the second cavity.

In the embodiment of the disclosure, the distribution density of the grooves on the transition layer, which are close to the etching holes, is greater than the distribution density of the grooves, which are far away from the etching holes; the depth of the groove on the transition layer, which is close to the etching hole, is greater than the depth of the groove, which is far away from the etching hole, along the direction perpendicular to the substrate.

It should be noted that the greater the distribution density of the grooves on the transition layer, the stronger the adhesion between the transition layer and the first sealing layer; the greater the depth of the groove in the transition layer, the greater the adhesion between the transition layer and the first sealing layer. However, the greater the distribution density of the grooves on the transition layer and the greater the depth of the grooves on the transition layer, the weaker the strength of the transition layer, and the more grooves result in the transition layer being prone to fracture. Therefore, it is necessary to adjust the distribution density and depth of the grooves on the transition layer in consideration of both the adhesion between the transition layer and the first sealing layer and the strength of the transition layer. Providing the distribution density and depth of the grooves on the transition layer requires compromise between the strength of the transition layer and the adhesion between the transition layer and the first sealing layer.

In the embodiment of the disclosure, the distribution density of the grooves close to the etching holes on the transition layer is higher than the distribution density of the grooves far away from the etching holes; and the depth of the groove on the transition layer, which is close to the etching hole, is greater than that of the groove, which is far away from the etching hole, so that a closed cavity is formed, the sealing performance of the cavity is improved, the problem that external small molecules enter the closed cavity and adhere to the film bulk acoustic resonator is avoided, the performance of the film bulk acoustic resonator is improved, and the service life of the film bulk acoustic resonator is prolonged.

Fig. 7 is a schematic cross-sectional view showing a case where the device structure is a thin film bulk acoustic resonator in a specific example. As shown in fig. 7, a semiconductor structure provided by an embodiment of the present disclosure includes: a substrate 301; forming a thin film bulk acoustic resonator on the intermediate region 301a of the substrate, the thin film bulk acoustic resonator comprising a lower electrode layer 302, a piezoelectric layer 303, an upper electrode layer 305 and a tuning layer 308, with a second cavity between the lower electrode layer 302 and the substrate 301, in a direction pointing away from the substrate 301 towards the substrate 301; wherein the material of the transition layer 306 and the adjustment layer 308 is the same, and the transition layer 306 and the adjustment layer 308 are formed in the same process step. The thin film bulk acoustic resonator also includes an etched hole 304 through the tuning layer 308 and the piezoelectric layer 303.

The semiconductor structure provided by the embodiment of the disclosure further comprises: a first sealing layer 309 disposed on the transition layer 306 on the edge region 301b of the substrate; the transition layer 306 is provided with a plurality of grooves 307, the cross-sectional width of at least one depth position of the grooves 307 is greater than or equal to the cross-sectional width of the top surface of the grooves 307, the position of the first sealing layer 309 opposite to the grooves 307 is provided with a plurality of protrusions 310, and the grooves 307 of the transition layer 306 and the protrusions 310 of the first sealing layer 309 are mutually embedded; wherein the edge region 301b of the substrate surrounds the middle region 301a of the substrate.

The semiconductor structure provided by the embodiment of the disclosure further comprises: a second sealing layer 311; the second sealing layer 311 is arranged on one side of the thin film bulk acoustic resonator away from the substrate 301, the second sealing layer 311 covers the substrate 301, and a first cavity is formed between the second sealing layer 311 and the middle region 301a of the substrate; the thin film bulk acoustic resonator is located within the first cavity.

The specific process of forming the thin film bulk acoustic resonator in the semiconductor structure provided by the embodiment of the disclosure is as follows: forming a sacrificial layer (not illustrated in fig. 7) and a lower electrode layer 302 covering the sacrificial layer on the intermediate region 301a of the substrate; forming a piezoelectric layer 303 covering the lower electrode layer 302 on the substrate 301, and forming an upper electrode layer 305 covering the piezoelectric layer 303 on the intermediate region 301a of the substrate; forming a transition layer 306 on an edge region 301b of the substrate while forming a conditioning layer 308 covering the upper electrode layer 305 on the intermediate region 301a of the substrate; forming an etched hole 304 penetrating at least the piezoelectric layer 303 and the adjustment layer 308; the transition layer 306 is etched to form a plurality of recesses 307, and a first sealing material is coated on the transition layer 306 to form a first sealing layer 309 having a plurality of protrusions 310 opposite the recesses 307.

In an embodiment of the present disclosure, the material of the transition layer and the material of the adjustment layer may be the same, and the material of the transition layer includes at least one of: molybdenum Mo, gold Au, ruthenium Ru, chromium Cr, and platinum Pt.

In the embodiment of the disclosure, the adjusting layer positioned on the middle area of the substrate and the transition layer positioned on the edge area of the substrate can be simultaneously formed through a coating process.

Forming a thin film bulk acoustic resonator within a semiconductor structure provided by the disclosed embodiments further includes the steps of: and injecting an etchant into the etching hole exposing the sacrificial layer by a wet etching method, so that the etchant contacts with the sacrificial layer and reacts chemically to generate a liquid product or a gaseous product, and removing the sacrificial layer to form a second cavity between the lower electrode layer and the substrate.

In an embodiment of the present disclosure, the material of the first sealing layer includes at least one of: curable photoresists and resins.

Here, the curable photoresist may include an ultraviolet curable photoresist. And coating the ultraviolet curable photoresist on the transition layer by using a spin coating process, and performing cross-linking reaction after ultraviolet irradiation to form a first sealing layer after curing.

Here, the resin may include polyimide PI, polybenzoxazole PBO, benzocyclobutene BCB, silicone, and acrylate.

In the embodiment of the disclosure, it is considered that the adhesion between the first sealing layer and the substrate is easily damaged by the hydrogen fluoride environment, so that in the same process step, the transition layer and the adjustment layer are formed simultaneously, the materials of the transition layer and the adjustment layer are the same, the adhesion between the substrate and the first sealing layer is improved through the transition layer, no additional process step for forming the transition layer is required, and the manufacturing time and the manufacturing cost are saved. Therefore, even if a hydrogen fluoride environment exists for a long time in the sacrificial layer release process, the adhesiveness between the substrate and the first sealing layer is difficult to break, so that the adhesiveness between the substrate and the first sealing layer can be improved, the performance of the film bulk acoustic resonator is improved, and the service life of the film bulk acoustic resonator is prolonged. The adhesion between the substrate and the piezoelectric layer itself was good, and even in the hydrogen fluoride atmosphere, the adhesion between the substrate and the piezoelectric layer was good.

Referring to fig. 8, fig. 8 is a partial perspective view of a top view of a semiconductor structure provided by an embodiment of the present disclosure, more specifically, a top view through a second sealing layer on top of the semiconductor structure. As shown in fig. 8, the semiconductor structure includes: a wafer 401; wafer 401 includes a plurality of die areas 402 thereon (shown in phantom in fig. 8); a device structure disposed on a middle region of each chip region 402; a transition layer and a first sealing layer disposed on an edge region of each chip region 402, the transition layer having a plurality of grooves disposed thereon, a cross-sectional width of the grooves at least one depth position being greater than or equal to a cross-sectional width of the grooves at a top surface thereof in a cross-section perpendicular to the wafer; a plurality of protrusions are arranged at the position, opposite to the grooves, of the first sealing layer, and the grooves of the transition layer are mutually embedded with the protrusions of the first sealing layer; wherein the edge region of the chip region surrounds the middle region of the chip region.

In an embodiment of the present disclosure, the semiconductor structure further includes a second sealing layer; the second sealing layer is arranged on one side of the device structure far away from the wafer, and covers the chip area, and a first cavity is formed between the second sealing layer and the middle area of the chip area; the device structure is located within the first cavity. Fig. 8 is only used to illustrate the placement of the individual die regions on the wafer through the second encapsulant layer on top of the semiconductor structure, and does not illustrate the specific device structure within each die region.

In the embodiment of the disclosure, the distribution density of the grooves on the transition layer near the edge area of the wafer and/or the chip area is greater than the distribution density of the grooves far away from the edge area of the wafer and/or the chip area; the depth of the grooves on the transition layer near the edge regions of the wafer and/or the chip regions is greater than the depth of the grooves far from the edge regions of the wafer and/or the chip regions in a direction perpendicular to the wafer.

It should be noted that the greater the distribution density of the grooves on the transition layer, the stronger the adhesion between the transition layer and the first sealing layer; the greater the depth of the groove in the transition layer, the greater the adhesion between the transition layer and the first sealing layer. However, the greater the distribution density of the grooves on the transition layer and the greater the depth of the grooves on the transition layer, the weaker the strength of the transition layer, and the more grooves result in the transition layer being prone to fracture. Therefore, it is necessary to adjust the distribution density and depth of the grooves on the transition layer in consideration of both the adhesion between the transition layer and the first sealing layer and the strength of the transition layer.

In the embodiment of the disclosure, the distribution density of the grooves on the transition layer, which is close to the edge area of the wafer and/or the chip area, is greater than the distribution density of the grooves on the transition layer, which is far away from the edge area of the wafer and/or the chip area; and the depth of the groove on the transition layer, which is close to the edge area of the wafer and/or the chip area, is larger than that of the groove, which is far away from the edge area of the wafer and/or the chip area, so that a closed cavity is more favorable to be formed, the problem that external small molecules enter the closed cavity and adhere to the film bulk acoustic resonator is avoided, the performance of the film bulk acoustic resonator is improved, and the service life of the film bulk acoustic resonator is prolonged.

Fig. 8 also illustrates that the device structure of each chip region 402 may be a thin film bulk acoustic resonator comprising a lower electrode layer, a piezoelectric layer and an upper electrode layer 403, and an etched hole 404 extending at least through the piezoelectric layer, in a direction pointing away from the wafer 401 near the wafer 401. The semiconductor structure further includes a bonding pad 406, and the upper electrode layer 403 and the lower electrode layer of the thin film bulk acoustic resonator in each chip region 402 are electrically connected to the bonding pad 406 through an electrode lead 405.

In the embodiment of the disclosure, the distribution density of the grooves close to the welding pad on the transition layer is greater than the distribution density of the grooves far away from the welding pad; the depth of the groove on the transition layer, which is close to the bonding pad, is greater than that of the groove, which is far away from the bonding pad, along the direction perpendicular to the wafer.

In the embodiment of the disclosure, the distribution density of the grooves close to the welding pad on the transition layer is greater than the distribution density of the grooves far away from the welding pad; and the depth of the groove close to the welding pad on the transition layer is larger than that of the groove far away from the welding pad, so that a closed cavity is formed, the problem that external small molecules enter the closed cavity and adhere to the film bulk acoustic resonator is avoided, the performance of the film bulk acoustic resonator is improved, and the service life of the film bulk acoustic resonator is prolonged.

Embodiments of the present disclosure provide a semiconductor structure and a method of manufacturing the same. The semiconductor structure includes: a substrate; a device structure disposed on a middle region of the substrate; a transition layer and a first sealing layer disposed on an edge region of the substrate, the transition layer being provided with a plurality of grooves, a cross-sectional width of the grooves at least one depth position being greater than or equal to a cross-sectional width of the grooves at a top surface thereof in a cross-section perpendicular to the substrate; a plurality of protrusions are arranged at the position, opposite to the grooves, of the first sealing layer, and the grooves of the transition layer and the protrusions of the first sealing layer are mutually embedded; wherein the edge region surrounds the intermediate region. In the embodiment of the disclosure, the transition layer is arranged between the substrate and the first sealing layer, the transition layer is provided with the plurality of grooves, and the section width of at least one depth position of the grooves is larger than or equal to the section width of the top surface of the grooves, so that the grooves on the transition layer and the protrusions on the first sealing layer are mutually embedded to improve the adhesion between the substrate and the first sealing layer.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by their functions and internal logic, and should not constitute any limitation on the implementation of the embodiments of the present disclosure. The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments.

The foregoing description is only of the preferred embodiments of the present disclosure, and is not intended to limit the scope of the present disclosure, but rather, the equivalent structural changes made by the present disclosure and the accompanying drawings under the inventive concept of the present disclosure, or the direct/indirect application in other related technical fields are included in the scope of the present disclosure.

Claims (17)

1. A semiconductor structure, the semiconductor structure comprising:

a substrate;

a device structure disposed on a middle region of the substrate;

a transition layer and a first sealing layer disposed on an edge region of the substrate, the transition layer being provided with a plurality of grooves, a cross-sectional width of the grooves at least one depth position being greater than or equal to a cross-sectional width of the grooves at a top surface thereof in a cross-section perpendicular to the substrate; a plurality of protrusions are arranged at the position, opposite to the grooves, of the first sealing layer, and the grooves of the transition layer and the protrusions of the first sealing layer are mutually embedded; wherein the edge region surrounds the intermediate region.

2. The semiconductor structure of claim 1, further comprising a second sealing layer; wherein,

the second sealing layer is arranged on one side of the device structure far away from the substrate, the second sealing layer covers the substrate, and a first cavity is formed between the second sealing layer and the middle area of the substrate; the device structure is located within the first cavity.

3. The semiconductor structure of claim 1, wherein sidewalls of the recess are uneven surfaces; and/or, the bottom surface of the groove is an uneven surface.

4. The semiconductor structure of claim 1, wherein a ratio between a cross-sectional width at a bottom surface of the recess and a depth of the recess in a cross-section perpendicular to the substrate is greater than or equal to 10.

5. The semiconductor structure of claim 4, wherein,

the depth of the groove is greater than 500nm along the direction perpendicular to the substrate;

the cross-sectional width at the bottom surface of the recess is greater than 5 μm in a cross-section perpendicular to the substrate.

6. The semiconductor structure of claim 2, wherein in the case where the device structure is a thin film bulk acoustic resonator, the thin film bulk acoustic resonator comprises a lower electrode layer, a piezoelectric layer, and an upper electrode layer with a second cavity therebetween, in a direction pointing away from the substrate proximate to the substrate; wherein the material of the transition layer and the piezoelectric layer is the same, and the transition layer and the piezoelectric layer are formed in the same process step.

7. The semiconductor structure of claim 6, wherein the device structure further comprises an etched hole at least through the piezoelectric layer.

8. The semiconductor structure of claim 7, wherein,

the distribution density of the grooves on the transition layer, which are close to the etching holes, is greater than that of the grooves, which are far away from the etching holes;

the depth of the groove on the transition layer, which is close to the etching hole, is greater than the depth of the groove, which is far away from the etching hole, along the direction perpendicular to the substrate.

9. The semiconductor structure of claim 2, wherein in the case where the device structure is a thin film bulk acoustic resonator, the thin film bulk acoustic resonator comprises a lower electrode layer, a piezoelectric layer, an upper electrode layer, and a tuning layer, with a second cavity therebetween, pointing away from the substrate in a direction toward the substrate; wherein the material of the transition layer and the adjustment layer is the same, and the transition layer and the adjustment layer are formed in the same process step.

10. The semiconductor structure of claim 1, wherein,

the transition layer is formed by a coating process;

the first sealing layer is formed through a spin coating process.

11. The semiconductor structure of claim 1, wherein,

The material of the transition layer comprises an etchant-resistant material;

the material of the first sealing layer comprises a curable photoresist and/or a resin.

12. The semiconductor structure of claim 11, wherein,

the material of the transition layer comprises at least one of the following: aluminum nitride AlN, aluminum scandium nitride AlScN, zinc oxide ZnO, lead zirconate titanate PZT, molybdenum Mo, gold Au, ruthenium Ru, chromium Cr and platinum Pt;

the material of the first sealing layer comprises at least one of the following: polyimide PI, polybenzoxazole PBO, benzocyclobutene BCB, silicone and acrylate.

13. A semiconductor structure, the semiconductor structure comprising:

a wafer; the wafer comprises a plurality of chip areas;

a device structure disposed on a middle region of each of the chip regions;

a transition layer and a first sealing layer disposed on an edge region of each of the chip regions, the transition layer being provided with a plurality of grooves, a cross-sectional width of the grooves at least one depth position being greater than or equal to a cross-sectional width of the grooves at a top surface thereof in a cross-section perpendicular to the wafer; a plurality of protrusions are arranged at the position, opposite to the grooves, of the first sealing layer, and the grooves of the transition layer and the protrusions of the first sealing layer are mutually embedded; wherein the edge region surrounds the intermediate region.

14. The semiconductor structure of claim 13, wherein,

the distribution density of the grooves on the transition layer, which is close to the edge area of the wafer and/or the chip area, is greater than the distribution density of the grooves, which is far away from the edge area of the wafer and/or the chip area;

the depth of the groove on the transition layer near the edge area of the wafer and/or the chip area is larger than the depth of the groove far away from the edge area of the wafer and/or the chip area along the direction perpendicular to the wafer.

15. The semiconductor structure of claim 13, further comprising a second sealing layer; wherein,

the second sealing layer is arranged on one side of the device structure far away from the wafer, the second sealing layer covers the chip area, and a first cavity is formed between the second sealing layer and the middle area of the chip area; the device structure is located within the first cavity.

16. The semiconductor structure of claim 15, wherein in the case where the device structure is a thin film bulk acoustic resonator, the thin film bulk acoustic resonator comprises a lower electrode layer, a piezoelectric layer, and an upper electrode layer in a direction toward the wafer away from the wafer;

The semiconductor structure further comprises a welding pad, wherein the upper electrode layer and the lower electrode layer of the film bulk acoustic resonator in each chip area are electrically connected with the welding pad through electrode leads; wherein,

the distribution density of the grooves on the transition layer, which are close to the welding pad, is greater than that of the grooves, which are far away from the welding pad;

the depth of the groove on the transition layer, which is close to the welding pad, is larger than the depth of the groove, which is far away from the welding pad, along the direction perpendicular to the wafer.

17. A method of fabricating a semiconductor structure, the method comprising:

providing a substrate;

forming a transition layer on an edge region of the substrate while forming a device structure in a middle region of the substrate;

forming a plurality of grooves on the transition layer; in a cross-section perpendicular to the substrate, a cross-sectional width at least one depth position of the recess is greater than or equal to a cross-sectional width at a top surface of the recess;

coating a first sealing material on the transition layer to form a first sealing layer having a plurality of protrusions opposite the grooves; wherein the grooves of the transition layer and the protrusions of the first sealing layer are mutually embedded; the edge region surrounds the intermediate region.