CN117747429A - JBS diode structure and preparation method thereof - Google Patents
JBS diode structure and preparation method thereof Download PDFInfo
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- CN117747429A CN117747429A CN202211124170.1A CN202211124170A CN117747429A CN 117747429 A CN117747429 A CN 117747429A CN 202211124170 A CN202211124170 A CN 202211124170A CN 117747429 A CN117747429 A CN 117747429A
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- 238000002347 injection Methods 0.000 claims abstract description 40
- 239000007924 injection Substances 0.000 claims abstract description 40
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- 238000002513 implantation Methods 0.000 claims description 58
- 238000005468 ion implantation Methods 0.000 claims description 34
- 238000005530 etching Methods 0.000 claims description 27
- 238000004519 manufacturing process Methods 0.000 claims description 13
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
Abstract
The invention provides a JBS diode structure and a preparation method thereof, wherein the JBS diode structure comprises a first conductive type substrate, a first conductive type epitaxial layer, a second conductive type well region, a first electrode and a second electrode, wherein the epitaxial layer is positioned on the upper surface of the substrate; the well regions are arranged at intervals and positioned on the upper surface layer of the epitaxial layer, and comprise a first injection region and a second injection region, the second injection region is formed by a plurality of doped regions of the second conductivity type which are sequentially stacked upwards, and the transverse width of the doped regions is larger than that of the first injection region; the first electrode is positioned on the upper surface of the epitaxial layer and is electrically connected with the epitaxial layer and the well region, and the second electrode is positioned on the lower surface of the substrate and is electrically connected with the substrate. According to the invention, the process for forming the well region is regulated, so that the side wall of the well region forms the tip region with larger curvature, the electric field intensity of the tip region is increased, the electric field intensity peak value of the device is transferred to the tip region of the side wall of the well region, the leakage current of the device is reduced, and the reverse breakdown voltage of the device is improved.
Description
Technical Field
The invention belongs to the field of semiconductor integrated circuit manufacturing, and relates to a JBS diode structure and a preparation method thereof.
Background
Silicon carbide (SiC) is used as a third generation wide forbidden band semiconductor material, has the characteristics of high electron saturation speed, high pressure resistance, radiation resistance, high temperature resistance and the like, and overcomes the defects of the traditional silicon material in the fields of high power density, high temperature and high frequency application. So that a power semiconductor device based on SiC, in particular a SiC Schottky diode with high current density, is one of the hot researches on the front edge of the current SiC field. The SiC JBS (silicon carbide junction barrier diode) structure device is one of SiC schottky diodes, and has become a mainstream design scheme in the current SiC schottky diode due to the characteristic of higher reverse withstand voltage.
Since the forward current characteristic of the SiC JBS diode mainly depends on the area of the active region, when the area of the active region of the chip increases, the forward output characteristic of the device increases in proportion, but at the same time, the leakage current of the active region generated during reverse withstand voltage increases in multiple, and the leakage current of the active region and the multiple of the area increase are in square ratio, which greatly exceeds the influence of the leakage current of the terminal.
As shown in fig. 1, a schematic cross-sectional structure of a SiC JBS diode includes a substrate 01, an epitaxial layer 02, a well 021, a first electrode 03 and a second electrode 04, where the JBS diode is affected by a schottky barrier, the leakage current is greater than that of a conventional PN junction in the reverse withstand voltage process, the current density increases with the product replacement, the surface electric field of the N-type region increases with the increase of the current density, the leakage current is increased, and at present, the leakage current of the device is usually reduced by adjusting the ion implantation dosage, but the leakage current is reduced, and at the same time, the Breakdown Voltage (BV) of the device is also reduced to a certain extent, which cannot increase the breakdown voltage of the device and also can reduce the leakage current, and also the breakdown voltage of the device is increased by using a high-energy implantation to increase the implantation depth or using a trench etching and high-energy ion implantation method, but an apparatus suitable for the process is required to be additionally configured.
Therefore, there is an urgent need to find a method for manufacturing a JBS diode structure that reduces the leakage current of the JBS diode while improving the breakdown voltage without additional configuration equipment.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a JBS diode structure and a method for manufacturing the same, which are used for solving the problems of reducing JBS diode leakage current and increasing device breakdown voltage and requiring additional configuration equipment in the prior art.
To achieve the above and other related objects, the present invention provides a method for manufacturing a JBS diode structure, comprising the steps of:
providing a first conductive type substrate, and forming a first conductive type epitaxial layer on the upper surface of the substrate;
forming a patterned shielding layer on the upper surface of the epitaxial layer to obtain a plurality of openings which are arranged at intervals;
forming a first injection region of a second conductivity type with a preset depth on the upper surface layer of the epitaxial layer based on the opening;
etching the edge of the opening in the shielding layer for multiple times to enable the edge of the opening to be expanded outwards, forming a second conductive type doped region with the transverse width larger than that of the first implanted region below the first implanted region based on the expanded opening after each etching, and sequentially stacking a plurality of doped regions upwards to form a second conductive type second implanted region, wherein the bottom surface of the first implanted region is in contact with the upper surface of the second implanted region, and the first implanted region and the second implanted region form a second conductive type well region;
and forming a first electrode electrically connected with the epitaxial layer and the well region on the upper surface of the epitaxial layer, and forming a second electrode electrically connected with the substrate on the lower surface of the substrate.
Optionally, the material of the shielding layer includes polysilicon.
Optionally, after forming the opening, each time before etching the edge of the opening, a step of oxidizing the surface layer of the shielding layer is further included.
Optionally, the method of etching the edge of the opening includes wet etching.
Optionally, the method of forming the first implant region includes ion implantation; the method of forming the doped region includes ion implantation.
Optionally, the implantation energy of the ion implantation to form the first implantation region is smaller than the implantation energy of the ion implantation to form the doped region.
Optionally, the ion implantation energy is different each time the doped region is formed, and the doping concentration of the doped region in the second implantation region is the same.
Optionally, a tip region is formed on a sidewall of the second implantation region.
The invention also provides a JBS diode structure, comprising:
a first conductivity type substrate;
an epitaxial layer of a first conductivity type on an upper surface of the substrate;
the second conductive type well regions are arranged at intervals and are positioned on the upper surface layer of the epitaxial layer, the second conductive type well regions comprise second conductive type first injection regions and second conductive type second injection regions, the bottom surfaces of the first injection regions are in contact with the upper surfaces of the second injection regions, a plurality of second conductive type doped regions which are sequentially stacked upwards form the second injection regions, and the transverse width of the doped regions is larger than that of the first injection regions;
the first electrode is positioned on the upper surface of the epitaxial layer and is electrically connected with the epitaxial layer and the well region, and the second electrode is positioned on the lower surface of the substrate and is electrically connected with the substrate.
Optionally, the side wall of the second injection region is provided with a tip region.
As described above, the JBS diode structure and the method for fabricating the same of the present invention forms the opening in the shielding layer by adjusting the forming process of the well region, forms the first implantation region based on the opening, oxidizes the surface layer of the shielding layer multiple times, etches the oxide layer of the surface layer of the shielding layer after each oxidation of the surface layer of the shielding layer to expand the opening, forms the doped layer based on each expanded opening, forms the second implantation region by stacking a plurality of doped layers, expands the opening by oxidizing the surface layer of the shielding layer multiple times and then removing the oxide layer after each oxidation, obtains the gradually expanded opening, ensures uniformity of sidewall morphology of the expanded opening, and reduces the influence of lateral scattering of particles during ion implantation, forming the doped region below the first implanted region based on the opening after each expansion, forming the second implanted region by a plurality of stacked doped regions, wherein the upper surface of the second implanted region is contacted with the lower surface of the first implanted region, then obtaining the well region formed by the first implanted region and the second implanted region, and forming a tip region on the side wall of the second implanted region, so that the side wall of the well region is provided with a tip region with larger curvature, then increasing the electric field intensity of the tip region of the side wall of the well region, leading to the peak value of the electric field intensity in the device being transferred from the upper surface of the epitaxial layer to the tip region of the side wall of the well region, reducing the surface electric field intensity of the device, simultaneously reducing the leakage current of the device, improving the problem of overlarge leakage current caused by mirror force, improving the reverse breakdown voltage of the device, and no additional equipment is needed to be configured and the ion implantation dosage is adjusted, so that the process is simple and has high industrial utilization value.
Drawings
Fig. 1 is a schematic cross-sectional view of a JBS diode structure.
Fig. 2 shows a process flow diagram of a method for fabricating a JBS diode structure according to the present invention.
Fig. 3 is a schematic cross-sectional view of a JBS diode structure according to the present invention after forming an epitaxial layer.
Fig. 4 is a schematic cross-sectional view of a JBS diode structure according to the present invention after forming a first implantation region.
Fig. 5 is a schematic cross-sectional view of a JBS diode structure according to the present invention after forming a well region.
Fig. 6 is a schematic cross-sectional view of a JBS diode structure according to another embodiment of the invention after forming another well region.
Fig. 7 is a schematic diagram of a cross-sectional mechanism of the JBS diode structure according to the present invention after removing the shielding layer.
Fig. 8 is a schematic cross-sectional view of a JBS diode structure according to the present invention after forming a first electrode and a second electrode.
Fig. 9 shows the electric field strength of the JBS diode structure of fig. 1 and the JBS diode structure of the present invention as a function of epitaxial layer depth.
FIG. 10 is a graph showing the leakage current of the JBS diode structure in FIG. 1 and the JBS diode structure of the present invention according to the reverse bias voltage.
Description of the reference numerals
01. Substrate and method for manufacturing the same
02. Epitaxial layer
021. Well region
03. First electrode
04. Second electrode
1. Substrate and method for manufacturing the same
2. Epitaxial layer
21. A first implantation region
22. A second implantation region
23. Well region
24. Doped region
3. Masking layer
31. An opening
4. First electrode
5. Second electrode
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 2 to fig. 10. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Example 1
The embodiment provides a method for preparing a JBS diode structure, as shown in fig. 2, which is a process flow chart of the method for preparing the JBS diode structure, and includes the following steps:
s1: providing a first conductive type substrate, and forming a first conductive type epitaxial layer on the upper surface of the substrate;
s2: forming a patterned shielding layer on the upper surface of the epitaxial layer to obtain a plurality of openings which are arranged at intervals;
s3: forming a first injection region of a second conductivity type with a preset depth on the upper surface layer of the epitaxial layer based on the opening;
s4: etching the edge of the opening in the shielding layer for multiple times to enable the edge of the opening to be expanded outwards, forming a second conductive type doped region with the transverse width larger than that of the first implanted region below the first implanted region based on the expanded opening after each etching, and sequentially stacking a plurality of doped regions upwards to form a second conductive type second implanted region, wherein the bottom surface of the first implanted region is in contact with the upper surface of the second implanted region, and the first implanted region and the second implanted region form a second conductive type well region;
s5: and forming a first electrode electrically connected with the epitaxial layer and the well region on the upper surface of the epitaxial layer, and forming a second electrode electrically connected with the substrate on the lower surface of the substrate.
Referring to fig. 3 to 6, the steps S1, S2, 3 and S4 are performed: providing a first conductive type substrate 1, and forming a first conductive type epitaxial layer 2 on the upper surface of the substrate 1; forming a patterned shielding layer 3 on the upper surface of the epitaxial layer 2 to obtain a plurality of openings 31 arranged at intervals; forming a second conductive type first implantation region 21 of a predetermined depth on the upper surface layer of the epitaxial layer 2 based on the opening 31; and etching the edge of the opening 31 in the shielding layer 3 for a plurality of times, so that the edge of the opening 31 is expanded outwards, forming a second conductive type doped region 24 with a transverse width larger than that of the first doped region 21 under the first doped region 21 based on the expanded opening 31 after each etching, sequentially stacking a plurality of doped regions 24 upwards to form a second conductive type second doped region 22, wherein the bottom surface of the first doped region 21 is contacted with the upper surface of the second doped region 22, and the first doped region 21 and the second doped region 22 form a second conductive type well region 23.
Specifically, the first conductivity type includes one of an N-type or a P-type, the second conductivity type includes one of an N-type or a P-type, and the first conductivity type is opposite to the second conductivity type. In this embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.
Specifically, the material of the substrate 1 includes silicon carbide or other suitable semiconductor materials.
Specifically, the material of the epitaxial layer 2 includes silicon carbide or other suitable semiconductor materials.
Specifically, as shown in fig. 3, to schematically illustrate the cross-sectional structure of the epitaxial layer 2 after the epitaxial layer 2 is formed, the method for forming the epitaxial layer 2 includes chemical vapor deposition or other suitable methods.
Specifically, the method of forming the shielding layer 3 includes physical vapor deposition, chemical vapor deposition, or other suitable methods.
The material of the shielding layer 3 may include polysilicon or other suitable material, for example. In this embodiment, a single polysilicon layer is used as the shielding layer 3, so that the opening 31 is flared by oxidation and oxide layer etching, so that the opening 31 with gradually-changed opening size can be formed, and meanwhile, uniformity of sidewall morphology of the flared opening 31 is ensured, and influence of lateral scattering is reduced.
Specifically, patterning the shielding layer 3 includes the following steps: forming a photoresist layer (not shown) on the upper surface of the shielding layer 3, and forming photoresist openings with preset patterns in the photoresist layer; the masking layer is etched based on the photoresist openings to obtain the openings 31.
In particular, the method of forming the photoresist layer includes coating or other suitable methods.
Specifically, the method of etching the shielding layer 3 includes dry etching, wet etching, or other suitable methods.
Specifically, in the etching process of forming the opening 31, the etching reagent has a high etching selectivity to the shielding layer 3 and the epitaxial layer 2, so as to avoid damaging the epitaxial layer 2 in the process of forming the opening 31.
Specifically, the size of the opening 31 may be selected according to the actual situation, while ensuring the device performance, and is not limited.
Specifically, as shown in fig. 4, to schematically illustrate the cross-sectional structure of the first implantation region 21 after forming the first implantation region 21, the method for forming the first implantation region 21 includes ion implantation or other suitable methods.
Specifically, the doping concentration of the first implantation region 21 may be selected according to the actual situation, while ensuring the device performance, which is not limited.
Specifically, the thickness of the first implantation region 21 may be selected according to the actual situation, while ensuring the device performance, which is not limited; the depth of the bottom surface of the first implantation region 21 may be selected according to practical situations, and is not limited herein, where the thickness refers to the distance between the bottom surface of the first implantation region 21 and the upper surface of the first implantation region 21 (the upper surface of the epitaxial layer 2), and the depth refers to the distance between the bottom surface of the first implantation region 21 and the upper surface of the epitaxial layer 2. In this embodiment, the first implantation region 21 is formed by ion implantation, and the ion implantation energy of the ion implantation is not more than 300KeV, so that the implantation depth of the first implantation region 21 is less than 0.4 μm, i.e. the thickness of the first implantation region 21 is less than 0.4 μm.
Specifically, the photoresist layer may be removed after the opening 31 is formed and before the first implantation region 21 is formed, or may be removed after the first implantation region 21 is formed and before the opening 31 is flared.
Specifically, since the method for removing the photoresist layer is a common process method, details are not repeated here.
As an example, after forming the opening 31, each time before etching the edge of the opening 31, a step of oxidizing the surface layer of the shielding layer 3 is further included.
By way of example, the method of etching the edges of the openings 31 includes wet etching or other suitable etching methods.
Specifically, the shielding layer 3 is oxidized, so that an oxide layer with a preset thickness is formed on the surface layer of the shielding layer 3, etching is conveniently performed by using an etching reagent with a high selectivity, the etching reagent only etches the oxide layer on the surface layer of the shielding layer 3, the purpose of expanding the edge of the opening 31 is achieved, the opening 31 is expanded for multiple times, oxidation is performed after each expansion, the surface layer of the shielding layer 3 is oxidized, and then the opening 31 with gradually-changed opening size is obtained, so that the well region 23 with a tip area on the side wall is conveniently obtained, the uniformity of the side wall morphology of the opening 31 after expansion is ensured, and the influence of transverse scattering is reduced. In this embodiment, the opening 31 is subjected to two outexpansions, that is, two oxidations are performed on the shielding layer 3, and the second implantation region 22 is composed of two doped regions 24.
Specifically, in the process of expanding the opening 31, the etching reagent has a higher etching selectivity ratio to the oxide layer on the surface layer of the shielding layer 3, the epitaxial layer 2 and the shielding layer 3, and almost no damage is caused to the epitaxial layer 2 while etching the oxide layer on the surface layer of the shielding layer 3, and after expanding the opening 31 each time, the remaining shielding layer 22 can still serve as a mask layer to shield the non-ion implantation region of the epitaxial layer 2 and prevent ions from entering the non-ion implantation region of the epitaxial layer 2.
By way of example, the method of forming doped region 24 includes ion implantation or other suitable method. In this embodiment, the doped region 24 is formed by ion implantation, and the ion implantation energy is not less than 300KeV,
as an example, the implantation energy of the ion implantation to form the first implantation region 21 is smaller than the implantation energy of the ion implantation to form the second implantation region 22, so that the particles when forming the doped region 24 enter the epitaxial layer 2 to a deeper depth, and then the first implantation region 21 is located above the doped region 24.
As an example, the ion implantation energy is different each time the doped region 24 is formed, the doping concentration of the doped region 24 in the second implanted region 22 is the same.
Specifically, the depth and thickness of each doped region 24 formed is controlled by controlling the ion implantation energy to form the doped region 24, and the morphology of the second implanted region 22 is controlled.
As an example, the sidewalls of the second implant region 22 are formed with tip regions.
Specifically, since the side wall of the second implantation region 22 is formed with the tip region with a larger curvature, the peak value of the electric field intensity in the device is transferred from the upper surface of the epitaxial layer 2 to the tip region of the second implantation region 22, the surface electric field of the device is reduced, the leakage current of the device is reduced, the problem of overlarge leakage current caused by the mirror force is solved, the reverse breakdown voltage of the device is improved, no additional configuration equipment or adjustment of ion implantation dosage is needed, and the process is simple.
Specifically, as shown in fig. 5 and fig. 6, the schematic cross-sectional structure after forming one type of the well region 23 and the schematic cross-sectional structure after forming another type of the well region 23 may be located at any position of the sidewall of the second injection region 22, that is, the sidewall of the second injection region 22 may be in a convex shape, or may be formed at the bottom of the second injection region 22, that is, the tip may be composed of the sidewall of the second injection region 22 and the bottom surface of the second injection region 22, under the condition of ensuring the device performance.
Specifically, when the tip is located on the sidewall of the second implantation region 22, at least two ion implantations with different ion implantation energies may be performed after each expansion of the opening 31, so as to form the doped regions 24 with different depths.
Specifically, the number of tips on the sidewalls of the second implantation region 22 may be one or more while ensuring the device performance. In this embodiment, the number of tips of the sidewalls of the second implantation region 22 is one.
Specifically, the doping concentration of the doped region 24 may be selected according to the actual situation, while ensuring the device performance, which is not limited. In this embodiment, the doping concentration of the first implantation region 21 is the same as that of the doping region 24.
Specifically, the thickness of the second implantation region 22 may be selected according to practical situations, and is not limited herein, and the thickness refers to the distance from the upper surface of the second implantation region 22 (the lower surface of the first implantation region 21) to the lower surface of the second implantation region 22, while ensuring the device performance.
Specifically, in the case of forming the second implantation region 22 while ensuring the device performance, the depth of the bottom surface of the second implantation region 22 may be selected according to practical situations, and is not limited herein, where the depth refers to the distance between the bottom surface of the second implantation region 22 and the upper surface of the epitaxial layer 2. In this embodiment, the depth of the bottom surface of the second implantation region 22 is not less than 0.4 μm.
Specifically, after forming the well region 23, an annealing step is further included.
Specifically, after the well region 23 is formed, the dopant ions in the well region 23 are uniformly distributed and activated by annealing, and the lattice damage of the epitaxial layer 2 caused by ion implantation is reduced.
Specifically, as shown in fig. 7, after the well region 23 is formed to form a schematic cross-sectional structure after removing the shielding layer 3, a step of removing the shielding layer 3 is further included.
Specifically, since the method for removing the shielding layer 3 is a common method, details are not repeated here.
Referring to fig. 8 again, the step S5 is performed: a first electrode 4 electrically connected to the epitaxial layer 2 and the well region 23 is formed on the upper surface of the epitaxial layer 2, and a second electrode 5 electrically connected to the substrate 1 is formed on the lower surface of the substrate 1.
Specifically, the method of forming the first electrode 4 includes sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.
Specifically, the method of forming the second electrode 5 includes sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.
According to the preparation method of the JBS diode, the process of forming the well region 23 is adjusted, the opening 31 is formed in the shielding layer 3, the first injection region 21 positioned on the upper surface layer of the epitaxial layer 2 is formed based on the opening 31, after the first injection region 21 is formed, the opening 31 is subjected to multiple expansion, the surface layer of the shielding layer 3 is subjected to oxidation treatment after each expansion, the oxide layer on the surface layer of the shielding layer 3 is etched, the opening 31 is enlarged by a method of oxidizing the surface layer of the shielding layer 3 and removing the oxide layer, so that the opening 31 with the gradual change opening size is obtained, the uniformity of the side wall morphology of the opening 31 after the expansion is ensured, and the influence of particle transverse scattering during ion injection is reduced; the doped region 24 under the first implanted region 21 is formed based on the opening 31 after each expansion, the lower surface of the first implanted region 21 is in contact with the upper surface of the second implanted region 22 composed of the doped region 24, and the sidewall of the second implanted region 22 is formed with a tip so that the sidewall of the well region 23 is formed with a tip region having a larger curvature, and the process is simple.
Example two
The present embodiment provides a JBS diode structure, as shown in fig. 8, which is a schematic cross-sectional structure of the JBS diode structure, and includes a first conductivity type substrate 1, a first conductivity type epitaxial layer 2, a second conductivity type well region 23, a first electrode 4, and a second electrode 5, wherein the epitaxial layer 2 is located on the upper surface of the substrate 1; the well regions 23 are arranged at intervals, the well regions 23 are positioned on the upper surface layer of the epitaxial layer 2, the well regions 23 comprise a first injection region 21 with a second conductivity type and a second injection region 22 with a second conductivity type, the bottom surface of the first injection region 21 is contacted with the upper surface of the second injection region 22, a plurality of doped regions 24 with the second conductivity type, which are sequentially stacked upwards, form the second injection region 22, and the transverse width of the doped regions 24 is larger than that of the first injection region 21; the first electrode 4 is located on the upper surface of the epitaxial layer 2 and is electrically connected to the epitaxial layer 2 and the well region 23, and the second electrode 5 is located on the lower surface of the substrate 1 and is electrically connected to the substrate 1.
Specifically, the thickness of the substrate 1 may be selected according to the actual situation, while ensuring the device performance, and is not limited here.
Specifically, in the case of ensuring the device performance and the ohmic contact between the substrate 1 and the second electrode 5, the doping concentration of the substrate 1 may be selected according to practical situations, which is not limited herein.
Specifically, the thickness of the epitaxial layer 2 may be selected according to practical situations under the condition of ensuring the performance of the device, which is not limited here; the doping concentration of the epitaxial layer 2 may be set according to practical situations, and is not limited here.
As an example, the sidewalls of the second implant region 22 are provided with tip regions.
Specifically, since the side wall of the second implantation region 22 is provided with the tip region, the side wall of the well region 23 is provided with the region (tip position) with larger curvature, so that the electric field intensity at the tip of the side wall of the second implantation region 22 is enhanced, the peak value of the electric field intensity of the device is transferred from the upper surface of the epitaxial layer 2 to the tip region of the side wall of the well region 23, the surface electric field of the device is reduced, and meanwhile, the problem of overlarge leakage current caused by mirror force is reduced.
Specifically, the material of the first electrode 4 may include one of titanium, titanium nitride, silver, gold, copper, aluminum and tungsten, or may be other suitable conductive materials.
Specifically, the material of the second electrode 5 may include one of titanium, titanium nitride, silver, gold, copper, aluminum and tungsten, or may be other suitable conductive materials.
Specifically, as shown in fig. 8 and fig. 9, the electric field strength of the JBS diode structure in fig. 1 and the electric field strength of the JBS diode structure in the present invention are the same as the doping concentration and the effective size of the well region 021 of the JBS diode in the present invention, and the leakage current of the JBS diode structure in fig. 1 and the electric field strength of the JBS diode structure in the present invention are the same as the change curve of the reverse voltage, wherein the depth is the vertical distance from the upper surface of the epitaxial layer 2 to the inside of the epitaxial layer 2, the doping concentration and the size of the epitaxial layer 02 and the substrate 01 of the JBS diode are the same as the doping concentration and the size of the epitaxial layer 2 and the substrate 1 of the JBS diode in the present invention, the doping concentration and the effective size of the well region 021 of the JBS diode in the present invention are the same as the doping concentration and the effective size of the well region 23 in the present invention, the effective size is the cross-sectional area of the well region 021 is the same as the cross-sectional area of the well region 23, and it can be seen from fig. 8 that the maximum electric field strength of the JBS diode is located on the surface of the epitaxial layer, and the maximum electric field strength of the JBS diode is located on the surface of the epitaxial layer, and the maximum electric field strength of the electric field strength is located on the surface layer is located on the surface distance; as can be seen from fig. 9, the leakage current of the JBS diode of the present invention is significantly lower than that of the JBS diode, and the reverse breakdown voltage of the JBS diode of the present invention is also significantly higher than that of the JBS diode (the test data in fig. 9 is about 150V higher), and by adjusting the process of forming the well region 23, the leakage current of the device is reduced and the reverse breakdown voltage of the device is improved, without additional configuration equipment and adjustment of ion implantation dose (doping concentration), and the process is simple.
According to the JBS diode structure of the embodiment, the tip region is arranged on the side wall of the well region 23, so that the side wall of the well region 23 is provided with the tip region with larger curvature, the electric field intensity at the tip region of the side wall of the well region 23 is increased, then the peak value of the electric field intensity in the device is transferred from the upper surface of the epitaxial layer 2 to the tip region of the side wall of the well region 23, the surface electric field of the device is reduced, meanwhile, the leakage current of the device is reduced, the problem of overlarge leakage current caused by mirror force is solved, the reverse breakdown voltage of the device is improved, additional configuration equipment and adjustment of ion implantation dosage are not needed, and the process is simple.
In summary, the JBS diode structure and the method for fabricating the same of the present invention form an opening by adjusting the process of forming a well region, form a first implantation region on the upper surface of the epitaxial layer based on the opening, oxidize the surface layer of the shielding layer multiple times, and etch the oxide layer on the surface layer of the shielding layer after each oxidation of the surface layer of the shielding layer to obtain an opening with gradually enlarged opening size, simultaneously ensure uniformity of sidewall morphology of the opening during the opening expansion, reduce the influence of lateral scattering of particles during ion implantation, form a doped region under the first implantation region and in contact with the lower surface of the first implantation region based on the opening after each expansion, the doped regions which are stacked upwards in sequence form a second injection region with a tip region on the side wall, then a well region which is formed by the first injection region and the second injection region and is provided with the tip region on the side wall is obtained, so that the side wall of the well region is provided with the tip region with larger curvature, then the electric field intensity of the tip region on the side wall of the well region is increased, the peak value of the electric field intensity in the device is transferred from the upper surface of the epitaxial layer to the tip region on the side wall of the well region, the surface electric field of the device is reduced, meanwhile, the leakage current of the device is reduced, the problem of overlarge leakage current caused by mirror force is solved, the reverse breakdown voltage of the device is improved, additional configuration equipment and ion injection dosage adjustment are not needed, and the process is simple. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. The preparation method of the JBS diode structure is characterized by comprising the following steps:
providing a first conductive type substrate, and forming a first conductive type epitaxial layer on the upper surface of the substrate;
forming a patterned shielding layer on the upper surface of the epitaxial layer to obtain a plurality of openings which are arranged at intervals;
forming a first injection region of a second conductivity type with a preset depth on the upper surface layer of the epitaxial layer based on the opening;
etching the edge of the opening in the shielding layer for multiple times to enable the edge of the opening to be expanded outwards, forming a second conductive type doped region with the transverse width larger than that of the first implanted region below the first implanted region based on the expanded opening after each etching, and sequentially stacking a plurality of doped regions upwards to form a second conductive type second implanted region, wherein the bottom surface of the first implanted region is in contact with the upper surface of the second implanted region, and the first implanted region and the second implanted region form a second conductive type well region;
and forming a first electrode electrically connected with the epitaxial layer and the well region on the upper surface of the epitaxial layer, and forming a second electrode electrically connected with the substrate on the lower surface of the substrate.
2. The method for manufacturing a JBS diode structure according to claim 1, wherein: the shielding layer is made of polysilicon.
3. The method for manufacturing a JBS diode structure according to claim 1, wherein: after forming the opening, each time before etching the edge of the opening, the method further comprises the step of oxidizing the surface layer of the shielding layer.
4. The method for manufacturing a JBS diode structure according to claim 1, wherein: the method of etching the edge of the opening includes wet etching.
5. The method for manufacturing a JBS diode structure according to claim 1, wherein: the method for forming the first implantation region comprises ion implantation; the method of forming the doped region includes ion implantation.
6. The method for manufacturing a JBS diode structure according to claim 5, wherein: the implantation energy of the ion implantation for forming the first implantation region is smaller than the implantation energy of the ion implantation for forming the doped region.
7. The method for manufacturing a JBS diode structure according to claim 5, wherein: the ion implantation energy of each time the doped region is formed is different, and the doping concentration of the doped region in the second implantation region is the same.
8. The method for manufacturing a JBS diode structure according to claim 1, wherein: the side wall of the second injection region is formed with a tip region.
9. A JBS diode structure comprising:
a first conductivity type substrate;
an epitaxial layer of a first conductivity type on an upper surface of the substrate;
the second conductive type well regions are arranged at intervals and are positioned on the upper surface layer of the epitaxial layer, the second conductive type well regions comprise second conductive type first injection regions and second conductive type second injection regions, the bottom surfaces of the first injection regions are in contact with the upper surfaces of the second injection regions, a plurality of second conductive type doped regions which are sequentially stacked upwards form the second injection regions, and the transverse width of the doped regions is larger than that of the first injection regions;
the first electrode is positioned on the upper surface of the epitaxial layer and is electrically connected with the epitaxial layer and the well region, and the second electrode is positioned on the lower surface of the substrate and is electrically connected with the substrate.
10. The JBS diode structure of claim 9, wherein: the side wall of the second injection region is provided with a tip region.
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| CN202211124170.1A CN117747429A (en) | 2022-09-15 | 2022-09-15 | JBS diode structure and preparation method thereof |
| PCT/CN2023/117550 WO2024055902A1 (en) | 2022-09-15 | 2023-09-07 | Jbs diode structure and preparation method therefor |
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| CN202211124170.1A CN117747429A (en) | 2022-09-15 | 2022-09-15 | JBS diode structure and preparation method thereof |
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| US8772144B2 (en) * | 2011-11-11 | 2014-07-08 | Alpha And Omega Semiconductor Incorporated | Vertical gallium nitride Schottky diode |
| JP6505625B2 (en) * | 2016-03-16 | 2019-04-24 | 株式会社東芝 | Semiconductor device |
| CN109473482A (en) * | 2017-09-08 | 2019-03-15 | 创能动力科技有限公司 | Schottky device and its manufacturing method |
| US11222782B2 (en) * | 2020-01-17 | 2022-01-11 | Microchip Technology Inc. | Self-aligned implants for silicon carbide (SiC) technologies and fabrication method |
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