CN117729814A

CN117729814A - Display device

Info

Publication number: CN117729814A
Application number: CN202311199865.0A
Authority: CN
Inventors: 申铉亿; 朴俊龙; 李周炫
Original assignee: Samsung Display Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2022-09-16
Filing date: 2023-09-18
Publication date: 2024-03-19
Also published as: KR20240038870A; US20240099091A1

Abstract

The display device includes: a first sub-pixel region and a second sub-pixel region; a first pixel electrode in the first sub-pixel region and including a first conductive layer including a metal material and a second conductive layer including tungsten oxide sequentially stacked; a second pixel electrode in the second sub-pixel region and including a third conductive layer and a fourth conductive layer sequentially stacked, the third conductive layer and the first conductive layer including the same material, the fourth conductive layer and the second conductive layer including the same material; a thickness compensation pattern on the second pixel electrode and including a first thickness compensation layer including a first transparent conductive oxide and a second thickness compensation layer including a second transparent conductive oxide sequentially stacked; a first light emitting layer on the first pixel electrode; and a second light emitting layer on the thickness compensation pattern.

Description

Display device

Technical Field

Embodiments relate generally to a display device. Embodiments relate to a display device and a method of manufacturing the same.

Background

With the development of information technology, the importance of display devices, which are communication media between users and information, is increasing. Accordingly, the use of display devices such as liquid crystal display devices, organic light emitting display devices, and plasma display devices is increasing.

The display device may include a light emitting element, and the light emitting element may include a pixel electrode, a common electrode, and a light emitting layer disposed between the pixel electrode and the common electrode. In order to improve the power efficiency of the light emitting element, functional layers (e.g., a hole transporting layer, an electron transporting layer, an auxiliary layer, and the like) may be further disposed above and below the light emitting layer.

It should be appreciated that this background section is intended in part to provide a useful background for understanding the technology. However, the background section may also include ideas, or insights that are not part of what is known or understood by those of skill in the relevant art prior to the corresponding effective filing date of the subject matter disclosed herein.

Disclosure of Invention

The embodiment provides a display device capable of realizing high resolution.

Embodiments provide a method of manufacturing the display device.

A display device may include: a first sub-pixel region emitting a first light and a second sub-pixel region emitting a second light different from the first light; a first pixel electrode disposed in the first sub-pixel region on the substrate and including a first conductive layer including a metal material and a second conductive layer including tungsten oxide sequentially stacked; a second pixel electrode disposed in the second sub-pixel region on the substrate and including a third conductive layer and a fourth conductive layer sequentially stacked, the third conductive layer and the first conductive layer including the same material, the fourth conductive layer and the second conductive layer including the same material; a thickness compensation pattern disposed on the second pixel electrode and including a first thickness compensation layer including a first transparent conductive oxide and a second thickness compensation layer including a second transparent conductive oxide sequentially stacked; a first light emitting layer disposed on the first pixel electrode; and a second light emitting layer disposed on the thickness compensation pattern.

In an embodiment, the tungsten oxide included in the second conductive layer may further include tantalum.

In an embodiment, the metallic material may include aluminum.

In an embodiment, the thickness of the first conductive layer may be substantially equal to the thickness of the third conductive layer, and the thickness of the second conductive layer may be substantially equal to the thickness of the fourth conductive layer.

In an embodiment, the thickness of the first conductive layer may be greater than the thickness of the second conductive layer, and the thickness of the third conductive layer may be greater than the thickness of the fourth conductive layer.

In an embodiment, the thickness of the first thickness compensation layer may be less than the thickness of the third conductive layer.

In an embodiment, each of the thickness of the second conductive layer and the thickness of the fourth conductive layer may be greater than the thickness of the second thickness compensation layer.

In an embodiment, the first transparent conductive oxide may include at least one selected from the group consisting of indium zinc oxide and indium gallium zinc oxide, and the second transparent conductive oxide may include indium tin oxide.

In an embodiment, the thickness compensation pattern may have an etching rate higher than that of the first pixel electrode or the second pixel electrode with respect to the same etchant.

In an embodiment, the display device may further include a third sub-pixel region emitting third light different from the first light emitted by the first sub-pixel region and the second light emitted by the second sub-pixel region.

In an embodiment, the display device may further include: a third pixel electrode disposed in the third sub-pixel region; and a third light emitting layer disposed on the third pixel electrode. The first light emitting layer may overlap the first sub-pixel region in a plan view, the second light emitting layer may overlap the second sub-pixel region in a plan view, and the third light emitting layer may overlap the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region in a plan view.

In an embodiment, the display device may further include: and a third pixel electrode disposed in the third sub-pixel region, the third pixel electrode and the first pixel electrode having the same structure.

In an embodiment, the display device may further include: a third pixel electrode disposed in the third sub-pixel region, the third pixel electrode and the second pixel electrode having the same structure; and a first thickness compensation pattern disposed on the third pixel electrode, the first thickness compensation pattern and the thickness compensation pattern having the same structure.

A method of manufacturing a display device may include: sequentially forming a first conductive film including a metal material and a second conductive film including tungsten oxide on a substrate including a first sub-pixel region that emits first light and a second sub-pixel region that emits second light different from the first light; forming a first conductive layer and a second conductive layer sequentially stacked in the first sub-pixel region and a third conductive layer and a fourth conductive layer sequentially stacked in the second sub-pixel region by etching the first conductive film and the second conductive film by dry etching; sequentially forming a third conductive film including a first transparent conductive oxide and a fourth conductive film including a second transparent conductive oxide over the substrate, the third conductive layer, and the fourth conductive layer; forming a first thickness compensation layer and a second thickness compensation layer sequentially stacked on the fourth conductive layer by etching the third conductive film and the fourth conductive film; forming a first light emitting layer on the second conductive layer; and forming a second light emitting layer on the second thickness compensation layer.

In an embodiment, the forming of the first thickness compensation layer and the second thickness compensation layer may include: forming a photosensitive organic layer on the third conductive layer and the fourth conductive layer; forming a photosensitive organic pattern overlapping the second sub-pixel region in a plan view by exposing the photosensitive organic layer; removing portions of the third conductive film and the fourth conductive film using the photosensitive organic pattern as a mask; the photosensitive organic pattern is removed.

In an embodiment, the upper surface of the photosensitive organic pattern may have a substantially convex shape in a cross section.

In an embodiment, in the removal of the portions of the third conductive film and the fourth conductive film, the first thickness compensation layer and the second thickness compensation layer may be formed by leaving the third conductive film and the fourth conductive film overlapping the second sub-pixel region in a plan view.

In an embodiment, forming the first thickness compensation layer and the second thickness compensation layer may be performed by wet etching or dry etching.

In an embodiment, the metallic material may include aluminum.

In an embodiment, the first transparent conductive oxide may include at least one selected from the group consisting of indium zinc oxide and indium gallium zinc oxide, and the second transparent conductive oxide may include indium tin oxide. The thickness of the third conductive layer may be greater than the thickness of the fourth conductive layer, the thickness of the first thickness compensation layer may be less than the thickness of the third conductive layer, and the thickness of the fourth conductive layer may be greater than the thickness of the second thickness compensation layer.

In the display device according to the embodiment, there is a display device including Al/WO _x The first pixel electrode of the multi-layer structure of (a) may be disposed in the first sub-pixel region emitting the first light, and have a structure including Al/WO _x The third pixel electrode of the multi-layered structure of (a) may be disposed in a third sub-pixel region emitting a third light different from the first light. A thickness compensation pattern having a multi-layer structure including IZO (or IGZO)/ITO may be disposed on the third pixel electrode. Accordingly, the display device may achieve high resolution (e.g., the number of pixels per inch of the display device is about 2000 (e.g., about 2000 ppi) or more).

In the method of manufacturing a display device according to the embodiment, there is a method of manufacturing a display device including Al/WO _x The pixel electrode of the multi-layered structure of (c) may be formed by a dry etching process. Accordingly, in the process of forming the pixel electrode, the deflection due to the overetch can be improved.

Drawings

Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

Fig. 1 is a schematic plan view schematically illustrating a display device according to an embodiment.

Fig. 2 is a schematic cross-sectional view taken along line I-I' of fig. 1.

Fig. 3 is an enlarged schematic cross-sectional view of region a of fig. 2.

Fig. 4 is an enlarged schematic cross-sectional view of region B of fig. 2.

Fig. 5 is a schematic cross-sectional view schematically illustrating the display device of fig. 2.

Fig. 6, 7, 8, 9, 10, 11, 12 and 13 are schematic cross-sectional views of a method for manufacturing the display device of fig. 2.

Fig. 14 is a view illustrating the reflectivity of a pixel electrode according to the wavelength band of external light incident on the pixel electrode according to the comparative example and the example.

Fig. 15 is a schematic cross-sectional view illustrating a display device according to an embodiment.

Fig. 16 is a block diagram illustrating an electronic device including the display device of fig. 1.

Fig. 17 is a diagram illustrating an example in which the electronic apparatus of fig. 16 is implemented as a television.

Fig. 18 is a diagram illustrating an example in which the electronic device of fig. 16 is implemented as a smart phone.

Detailed Description

Hereinafter, a display device and a method of manufacturing the same according to embodiments will be explained in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and redundant description of the same components may be omitted.

The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments are shown. This disclosure may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the drawings, the size, thickness, ratio and dimensions of elements may be exaggerated for ease of description and for clarity.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

In the description and claims, the term "and/or" is intended for purposes of its meaning and explanation to include any combination of the terms "and" or ". For example, "a and/or B" may be understood to mean "A, B or a and B". The terms "and" or "may be used in a combined or separate sense and are to be understood as being equivalent to" and/or ".

In the specification and claims, the phrase "at least one of … …" is intended for the purposes of its meaning and explanation to include at least one selected from the group of "… …". For example, "at least one of a and B" may be understood to mean "A, B or a and B".

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure.

The term "overlap" or "overlapped" means that a first object may be above or below or to the side of a second object, and vice versa. In addition, the term "overlapping" may include layered placement, stacking, facing, or variants thereof, extending over … …, covering or partially covering, or any other suitable term as will be appreciated and understood by those of ordinary skill in the art.

When an element is described as being "non-overlapping" or "to" non-overlapping "with" another element, this may include the elements being spaced apart, offset or separated from each other or any other suitable terminology as would be appreciated and understood by one of ordinary skill in the art.

The term "facing" and variations thereof mean that a first element may be directly or indirectly opposite a second element. In the case where the third element is interposed between the first element and the second element, the first element and the second element may be understood as being indirectly opposed to each other although still facing each other.

The terms "comprises," "comprising," "includes," "including," "having," and/or variations thereof, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and/or groups thereof, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.

In view of the measurements in question and the errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), as used herein, "about" or "approximately" includes the stated values and is meant to be within an acceptable range of deviation of the particular value as determined by one of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated values.

Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

It will be understood that when an element (or region, layer or section, etc.) is referred to in the specification as being "on," "connected to," or "coupled to" another element, it can be directly on, connected or coupled to the other element or intervening elements may be present therebetween.

It will be understood that the term "connected to" or "coupled to" may include a physical or electrical connection or a physical or electrical coupling. Embodiments may be described in terms of functional blocks, units, and/or modules and are illustrated in the figures.

Those skilled in the art will appreciate that the blocks, units, and/or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wired connections, or the like, which may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques.

Where the blocks, units, and/or modules are implemented by microprocessors or other similar hardware, they may be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and/or software.

It is also contemplated that each block, unit, and/or module may be implemented with dedicated hardware, or as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) for performing other functions.

Each block, unit, and/or module of an embodiment may be physically separated into two or more interacting and discrete blocks, units, and/or modules without departing from the scope of the present disclosure.

Furthermore, the blocks, units, and/or modules of the embodiments may be physically combined into more complex blocks, units, and/or modules without departing from the scope of the present disclosure.

Referring to fig. 1, a display device DD according to an embodiment may include a display area DA and a non-display area NDA. The display area DA may be an area capable of displaying an image by generating light or adjusting transmittance of light supplied from an external light source. The non-display area NDA may be an area where an image is not displayed. The non-display area NDA may be located around the display area DA. For example, the non-display area NDA may completely surround the display area DA. The non-display area NDA may be adjacent to the display area DA.

The display device DD may have a rectangular planar shape with rounded corners. However, the configuration of the present disclosure is not limited thereto. For example, in a plan view, the display device DD may have various shapes (e.g., a rectangular planar shape with vertical corners). It should be understood that the shapes disclosed herein may also include substantially the same shapes as those disclosed herein.

The display area DA may include a pixel area PA. Pixels may be disposed in each of the pixel regions PA. Since the pixels emit light, the display area DA may display an image.

Each of the pixel regions PA may include a first sub-pixel region SPA1, a second sub-pixel region SPA2, and a third sub-pixel region SPA3. Each of the first, second, and third sub-pixel regions SPA1, SPA2, and SPA3 may be a region where light emitted from the light emitting element is emitted to the outside of the display device DD.

The first, second and third sub-pixel regions SPA1, SPA2 and SPA3 may emit different colors of light. For example, the first sub-pixel region SPA1 emits first light, the second sub-pixel region SPA2 may emit second light, and the third sub-pixel region SPA3 may emit third light. In an embodiment, the first light may be red light, the second light may be green light, and the third light may be blue light. However, the configuration of the present disclosure is not limited thereto. For example, the first, second, and third sub-pixel regions SPA1, SPA2, and SPA3 may be combined to emit yellow, cyan, and magenta light.

The first, second, and third sub-pixel regions SPA1, SPA2, and SPA3 may emit light of four or more colors. For example, the first, second and third sub-pixel regions SPA1, SPA2 and SPA3 may be combined to further emit at least one of yellow, cyan and magenta light in addition to red, green and blue light. The first, second and third sub-pixel regions SPA1, SPA2 and SPA3 may be combined to further emit white light.

Each of the first, second, and third sub-pixel regions SPA1, SPA2, and SPA3 may have a triangular planar shape, a quadrangular planar shape, a circular planar shape, a track-shaped planar shape, or an elliptical planar shape, etc., within the spirit and scope of the present disclosure. In an embodiment, each of the first, second, and third sub-pixel regions SPA1, SPA2, and SPA3 may have a rectangular planar shape.

In a plan view, the first, second, and third sub-pixel regions SPA1, SPA2, and SPA3 may be repeatedly arranged or disposed along the row and column directions. For example, the first, second, and third sub-pixel regions SPA1, SPA2, and SPA3 may be repeatedly arranged or disposed in the first direction DR1 and the second direction DR2 intersecting the first direction DR1.

In this specification, a plane may be defined by a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, the second direction DR2 may be perpendicular to the first direction DR1.

Fig. 2 is a schematic cross-sectional view taken along line I-I' of fig. 1. Fig. 3 is an enlarged schematic cross-sectional view of region a of fig. 2. Fig. 4 is an enlarged schematic cross-sectional view of region B of fig. 2.

Referring to fig. 2, 3 and 4, the display device DD according to the embodiment may include a substrate SUB, a buffer layer BUF, first, second and third transistors TR1, TR2 and TR3, a gate insulating layer GI, an interlayer insulating layer ILD, a VIA insulating layer VIA, a pixel defining layer PDL, first, second and third light emitting elements EL1, EL2 and EL3, and an encapsulation layer TFE.

Here, the first transistor TR1 may include a first active pattern ACT1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1. The second transistor TR2 may include a second active pattern ACT2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2. The third transistor TR3 may include a third active pattern ACT3, a third gate electrode GE3, a third source electrode SE3, and a third drain electrode DE3.

The first light emitting element EL1 may include a first pixel electrode PE1, an organic layer OL, and a common electrode CE. The second light emitting element EL2 may include a second pixel electrode PE2, an organic layer OL, and a common electrode CE. The third light emitting element EL3 may include a third pixel electrode PE3, a thickness compensation pattern TCP, an organic layer OL, and a common electrode CE.

The substrate SUB may include a transparent material or an opaque material. The substrate SUB may be made of a transparent resin substrate. Examples of the transparent resin substrate may include a polyimide substrate and the like within the spirit and scope of the present disclosure. The polyimide substrate may include a first organic layer, a first barrier layer, and a second organic layer. By way of example, the substrate SUB may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate, a soda lime glass substrate, an alkali-free glass substrate, and the like, within the spirit and scope of the present disclosure. These may be used alone or in combination with each other.

The buffer layer BUF may be disposed on the substrate SUB. The buffer layer BUF may prevent metal atoms or impurities from diffusing from the substrate SUB into the first transistor TR1, the second transistor TR2, and the third transistor TR 3. In the case of non-uniformity of the surface of the substrate SUB, the buffer layer BUF may improve the flatness of the surface of the substrate SUB. For example, the buffer layer BUF may include an inorganic material such as silicon oxide, silicon nitride, and silicon oxynitride, etc., within the spirit and scope of the present disclosure. These may be used alone or in combination with each other.

The first, second, and third active patterns ACT1, ACT2, and ACT3 may be disposed on the buffer layer BUF. Each of the first, second, and third active patterns ACT1, ACT2, and ACT3 may include a metal oxide semiconductor, an inorganic semiconductor (e.g., amorphous silicon, polycrystalline silicon), or an organic semiconductor. The first, second, and third active patterns ACT1, ACT2, and ACT3 may include the same material or similar materials. For example, each of the first, second, and third active patterns ACT1, ACT2, and ACT3 may include a source region, a drain region, and a channel region between the source region and the drain region.

It is within the spirit and scope of the present disclosure that the metal oxide semiconductor may include a two-component compound ("AB") comprising indium ("In"), zinc ("Zn"), gallium ("Ga"), tin ("Sn"), titanium ("Ti"), aluminum ("Al"), hafnium ("Hf"), zirconium ("Zr"), magnesium ("Mg"), and the like _x ") and ternary compounds (" AB) _x C _y ") and four component compounds (" AB) _x C _y D _z ") and the like. For example, the number of the cells to be processed,it is within the spirit and scope of the present disclosure that the metal oxide semiconductor may include zinc oxide ("ZnO" _x ") gallium oxide (" GaO) _x ") and tin oxide (" SnO) _x ") indium oxide (" InO) _x "), indium gallium oxide (" IGO "), indium zinc oxide (" IZO "), indium tin oxide (" ITO "), indium zinc tin oxide (" IZTO "), and indium gallium zinc oxide (" IGZO "), and the like. These may be used alone or in combination with each other.

The gate insulating layer GI may be disposed on the buffer layer BUF. The gate insulating layer GI may cover the first, second, and third active patterns ACT1, ACT2, and ACT3. For example, the gate insulating layer GI may sufficiently cover the first, second, and third active patterns ACT1, ACT2, and ACT3, and may have a substantially flat upper surface without causing steps around the first, second, and third active patterns ACT1, ACT2, and ACT3. By way of example, the gate insulating layer GI may cover the first, second, and third active patterns ACT1, ACT2, and ACT3, and may have a uniform thickness along the outline of the first, second, and third active patterns ACT1, ACT2, and ACT3.

For example, the gate insulating layer GI may include, for example, silicon oxide ("SiO"), within the spirit and scope of the present disclosure _x ") silicon nitride (" SiN) _x ") and silicon carbide (" SiC) _x ") silicon oxynitride (" SiO) _x N _y ") and silicon oxycarbide (" SiO ") _x C _y ") and the like. These may be used alone or in combination with each other.

The first, second, and third gate electrodes GE1, GE2, and GE3 may be disposed on the gate insulating layer GI. The first gate electrode GE1 may overlap a channel region of the first active pattern ACT1, the second gate electrode GE2 may overlap a channel region of the second active pattern ACT2, and the third gate electrode GE3 may overlap a channel region of the third active pattern ACT 3.

For example, each of the first, second, and third gate electrodes GE1, GE2, and GE3 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like, within the spirit and scope of the present disclosure. These may be used alone or in combination with each other. The first, second and third gate electrodes GE1, GE2 and GE3 may include the same material or similar materials.

An interlayer insulating layer ILD may be disposed on the gate insulating layer GI. The interlayer insulating layer ILD may cover the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3. For example, the interlayer insulating layer ILD may sufficiently cover the first, second, and third gate electrodes GE1, GE2, and GE3, and may have a substantially flat upper surface without causing steps around the first, second, and third gate electrodes GE1, GE2, and GE3. By way of example, the interlayer insulating layer ILD may cover the first, second, and third gate electrodes GE1, GE2, and GE3 and may have a uniform thickness along the contours of the first, second, and third gate electrodes GE1, GE2, and GE3.

For example, the interlayer insulating layer ILD may include an inorganic material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, and the like, within the spirit and scope of the present disclosure. These may be used alone or in combination with each other.

The first, second, and third source electrodes SE1, SE2, and SE3 may be disposed on the interlayer insulating layer ILD. The first source electrode SE1 may be connected to the source region of the first active pattern ACT1 through a contact hole penetrating the first portion of the gate insulating layer GI and the interlayer insulating layer ILD. The second source electrode SE2 may be connected to the source region of the second active pattern ACT2 through a contact hole penetrating the second portion of the gate insulating layer GI and the interlayer insulating layer ILD. The third source electrode SE3 may be connected to the source region of the third active pattern ACT3 through a contact hole penetrating the gate insulating layer GI and the third portion of the interlayer insulating layer ILD.

The first, second, and third drain electrodes DE1, DE2, and DE3 may be disposed on the interlayer insulating layer ILD. The first drain electrode DE1 may be connected to a drain region of the first active pattern ACT1 through a contact hole penetrating the gate insulating layer GI and the fourth portion of the interlayer insulating layer ILD. The second drain electrode DE2 may be connected to the drain region of the second active pattern ACT2 through a contact hole penetrating the gate insulating layer GI and the fifth portion of the interlayer insulating layer ILD. The third drain electrode DE3 may be connected to the drain region of the third active pattern ACT3 through a contact hole penetrating the gate insulating layer GI and the sixth portion of the interlayer insulating layer ILD.

For example, each of the first, second, and third source electrodes SE1, SE2, and SE3 and the first, second, and third drain electrodes DE1, DE2, and DE3 may be a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like, within the spirit and scope of the present disclosure. These may be used alone or in combination with each other. The first, second and third drain electrodes DE1, DE2 and DE3 may include the same material or similar materials as the first, second and third source electrodes SE1, SE2 and SE 3.

Accordingly, the first transistor TR1 including the first active pattern ACT1, the first gate electrode GE1, the first source electrode SE1, and the first drain electrode DE1 may be disposed on the substrate SUB. The second transistor TR2 including the second active pattern ACT2, the second gate electrode GE2, the second source electrode SE2, and the second drain electrode DE2 may be disposed on the substrate SUB. The third transistor TR3 including the third active pattern ACT3, the third gate electrode GE3, the third source electrode SE3, and the third drain electrode DE3 may be disposed on the substrate SUB.

The VIA insulating layer VIA may be disposed on the interlayer insulating layer ILD. The VIA insulating layer VIA may sufficiently cover the first, second, and third source electrodes SE1, SE2, and SE3, and the first, second, and third drain electrodes DE1, DE2, and DE3. The VIA insulating layer VIA may include an inorganic material or an organic material. In an embodiment, the VIA insulating layer VIA may include an organic material. For example, the VIA insulating layer VIA may be made of a phenolic resin, a polyacrylate resin, a polyimide resin, a polyamide resin, a silicone resin, an epoxy resin, and the like, within the spirit and scope of the present disclosure. These may be used alone or in combination with each other.

The first, second and third pixel electrodes PE1, PE2 and PE3 may be disposed on the VIA insulating layer VIA. The first pixel electrode PE1 may overlap the first sub-pixel region SPA1, the second pixel electrode PE2 may overlap the second sub-pixel region SPA2, and the third pixel electrode PE3 may overlap the third sub-pixel region SPA 3.

Each of the first, second, and third pixel electrodes PE1, PE2, and PE3 may have a multi-layered structure. In an embodiment, each of the first, second, and third pixel electrodes PE1, PE2, and PE3 may have a two-layer structure. However, the configuration of the present disclosure is not limited thereto. Each of the first, second, and third pixel electrodes PE1, PE2, and PE3 may have a structure of three or more layers.

In an embodiment, the first pixel electrode PE1 may include a first conductive layer 101a and a second conductive layer 101b sequentially stacked one on another on the VIA insulating layer VIA, and the third pixel electrode PE3 may include a third conductive layer 102a and a fourth conductive layer 102b sequentially stacked one on another on the VIA insulating layer VIA. The second pixel electrode PE2 may have the same structure as the first pixel electrode PE 1. For example, the second pixel electrode PE2 may have a structure in which two conductive layers including the same material or a similar material as the first conductive layer 101a and the second conductive layer 101b of the first pixel electrode PE1 may be sequentially stacked on each other. Therefore, description of the stacked structure of the second pixel electrode PE2 may be omitted.

The first conductive layer 101a may include a metal or an alloy. For example, the first conductive layer 101a can include silver ("Ag"), an alloy including silver, aluminum ("Al"), an alloy including aluminum, molybdenum ("Mo"), an alloy including molybdenum, tungsten ("W"), nickel ("Ni"), chromium ("Cr"), titanium ("Ti"), tantalum ("Ta"), copper ("Cu"), platinum ("Pt"), scandium ("Sc"), and the like, within the spirit and scope of the present disclosure. These may be used alone or in combination with each other. In an embodiment, the first conductive layer 101a may include aluminum.

The second conductive layer 101b may include a conductive metal oxide having a relatively high work function. In an embodiment, the second conductive layer 101b may include tungsten oxide ("WO _x "). For example, the work function of tungsten oxide may be in the range of about 5.2eV to about 5.6 eV.

In an embodiment, tungsten oxide included in the second conductive layer 101b may further include tantalum. For example, in the case where tungsten oxide included in the second conductive layer 101b further includes tantalum, the content of tantalum may be about 10at%. Accordingly, in the process of forming the second conductive layer 101b, the second conductive layer 101b including tungsten oxide including tantalum may be prevented from being dissolved in water, a developer (e.g., tetramethylammonium hydroxide ("TMAH")) or the like within the spirit and scope of the present disclosure.

The third conductive layer 102a may include the same material as the first conductive layer 101a or a similar material. For example, the third conductive layer 102a may be provided at the same layer as the first conductive layer 101 a. The fourth conductive layer 102b may include the same material as the second conductive layer 101b or a similar material. For example, the fourth conductive layer 102b may be provided at the same layer as the second conductive layer 101 b.

The thickness compensation pattern TCP may be disposed on the third pixel electrode PE 3. The resonance thickness of the light emitted from the organic layer OL may be controlled by the thickness compensation pattern TCP. In an embodiment, the thickness compensation pattern TCP may include a first thickness compensation layer 103a and a second thickness compensation layer 103b sequentially stacked on each other.

The thickness compensation pattern TCP may have an etch rate different from that of the pixel electrodes PE1, PE2, and PE3 with respect to the same etchant. In an embodiment, the thickness compensation pattern TCP may have an etching rate higher than that of the pixel electrodes PE1, PE2, and PE3 with respect to the same etchant. The thickness compensation pattern TCP and the pixel electrodes PE1, PE2, and PE3 as shown in fig. 2 may be formed by a difference in etching rate between the thickness compensation pattern TCP and the pixel electrodes PE1, PE2, and PE 3.

The first thickness compensation layer 103a may include a first transparent conductive oxide. In an embodiment, the first transparent conductive oxide may include indium zinc oxide ("IZO"), indium gallium zinc oxide ("IGZO"), and the like, within the spirit and scope of the present disclosure. These may be used alone or in combination with each other. However, the present disclosure is not limited thereto, and the first thickness compensation layer 103a may include various transparent conductive oxides.

The second thickness compensation layer 103b may include a second transparent conductive oxide different from the first transparent conductive oxide. In an embodiment, the second thickness compensation layer 103b may include indium tin oxide ("ITO"). However, the present disclosure is not limited thereto, and the second thickness compensation layer 103b may include various transparent conductive oxides.

The thickness T1 of the first conductive layer 101a may be different from the thickness T2 of the second conductive layer 101 b. In an embodiment, the thickness T1 of the first conductive layer 101a may be greater than the thickness T2 of the second conductive layer 101 b. For example, the thickness T1 of the first conductive layer 101a may be aboutTo about->And the thickness T2 of the second conductive layer 101b may be within a range of aboutTo about->Within a range of (2). The thickness T1 of the first conductive layer 101a may be about +. >And the thickness T2 of the second conductive layer 101b may be about +.>The thickness T1 of the third conductive layer 102a may be equal to the thickness T1 of the first conductive layer 101a, and the thickness T2 of the fourth conductive layer 102b may be equal to the thickness T2 of the second conductive layer 101 b.

The thickness T3 of the first thickness compensation layer 103a may be different from the thickness T1 of the third conductive layer 102 a. In an embodiment, the thickness T3 of the first thickness compensation layer 103a may be smaller than the thickness T1 of the third conductive layer 102 a. The thickness T4 of the second thickness compensation layer 103b may be different from the thickness T2 of the fourth conductive layer 102 b. In an embodiment, the thickness T4 of the second thickness compensation layer 103b may be smaller than that of the fourth conductive layer 102bThickness T2. For example, the thickness T3 of the first thickness compensation layer 103a may be aboutTo about->And the thickness T4 of the second thickness compensation layer 103b may be within a range of about +.>To about->Within a range of (2). The thickness T3 of the first thickness compensation layer 103a may be about +.>And the thickness T4 of the second thickness compensation layer 103b may be about +.>

Here, each of the first and second pixel electrodes PE1 and PE2 may be defined as a first anode electrode. The third pixel electrode PE3 and the thickness compensation pattern TCP may be collectively defined as a second anode electrode.

In the case where the thickness compensation pattern TCP does not include IZO (or IGZO) but includes only ITO, residues may remain on the thickness compensation pattern TCP due to overetching in a process of forming the thickness compensation pattern TCP. Water may remain. Accordingly, in the case where the thickness compensation pattern TCP includes IZO (or IGZO) and ITO sequentially stacked, residues remaining on the thickness compensation pattern TCP may be minimized.

Accordingly, the first light emitting element EL1 including the first pixel electrode PE1, the organic layer OL, and the common electrode CE may be disposed in the first SUB-pixel region SPA1 on the substrate SUB, the second light emitting element EL2 including the second pixel electrode PE2, the organic layer OL, and the common electrode CE may be disposed in the second SUB-pixel region SPA2 on the substrate SUB, and the third light emitting element EL3 including the third pixel electrode PE3, the thickness compensation pattern TCP, the organic layer OL, and the common electrode CE may be disposed in the third SUB-pixel region SPA3 on the substrate SUB.

The pixel defining layer PDL may be disposed on the VIA insulating layer VIA. The pixel defining layer PDL may expose a portion of an upper surface of each of the first pixel electrode PE1, the second pixel electrode PE2, and the thickness compensation pattern TCP. The pixel defining layer PDL may include an inorganic material or an organic material. In an embodiment, the pixel defining layer PDL may comprise an organic material. For example, the pixel defining layer PDL may include an organic material such as polyimide.

In an embodiment, the pixel defining layer PDL may further include a black light blocking material. For example, the pixel defining layer PDL may further include a light blocking material such as a black pigment, a black dye, and carbon black, etc., within the spirit and scope of the present disclosure. These may be used alone or in combination with each other.

The organic layer OL may be disposed on the pixel defining layer PDL, the first pixel electrode PE1, the second pixel electrode PE2, and the thickness compensation pattern TCP. The organic layer OL may include an electron transport layer, an electron injection layer, a light emitting layer, a hole transport layer, a hole injection layer, and the like within the spirit and scope of the present disclosure. For example, the organic layer OL may continuously extend throughout the display area DA. Some elements included in the organic layer OL (e.g., the first and third light emitting layers EML1 and EML3 of fig. 5) may be disposed in the first and third sub-pixel regions SPA1 and SPA3, respectively. A detailed description of the organic layer OL will be given later.

The thickness of the organic layer OL may be determined according to the resonance thickness of light emitted from each of the sub-pixel regions SPA1, SPA2, and SPA 3. The resonance thickness may represent the thickness at which optical resonance occurs. For example, light generated in the organic layer OL may resonate between the pixel electrodes PE1, PE2, and PE3 and the common electrode CE.

The resonant thickness may vary depending on the wavelength of the light. Accordingly, in the case where the distance between the pixel electrode and the common electrode CE in each of the sub-pixel regions SPA1, SPA2, and SPA3 is equal to or close to the resonance thickness of the light emitted from each of the sub-pixel regions SPA1, SPA2, and SPA3, light of a specific or given wavelength may be emitted or the light intensity may be increased.

For example, in the case where the thickness compensation pattern TCP is not disposed on the third pixel electrode PE3 in the third sub-pixel region SPA3, the distance between the third pixel electrode PE3 and the common electrode CE may be different from the resonance thickness of the light emitted from the third sub-pixel region SPA 3. However, in the case where the thickness compensation pattern TCP is disposed on the third pixel electrode PE3 in the third sub-pixel region SPA3, the distance between the third pixel electrode PE3 and the common electrode CE may have a value corresponding to the resonance thickness of light due to the thickness compensation pattern TCP disposed on the third pixel electrode PE 3.

The common electrode CE may be disposed on the organic layer OL. The common electrode CE may continuously extend throughout the display area DA. For example, the common electrode CE may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like, within the spirit and scope of the present disclosure. These may be used alone or in combination with each other. For example, the common electrode CE may operate as a cathode electrode.

The encapsulation layer TFE may be disposed on the common electrode CE. The encapsulation layer TFE can prevent impurities, moisture, and the like from penetrating into the first light emitting element EL1, the second light emitting element EL2, and the third light emitting element EL3 from the outside. The encapsulation layer TFE may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, the inorganic encapsulation layer may include silicon oxide, silicon nitride, silicon oxynitride, and the like, within the spirit and scope of the present disclosure. These may be used alone or in combination with each other. The organic encapsulation layer may include a polymer cured material such as polyacrylate.

The display device DD may include an organic light emitting display device ("OLED"), a liquid crystal display device ("LCD"), a field emission display device ("FED"), a plasma display device ("PDP"), an electrophoretic display device ("EPD"), a quantum dot display device, or an inorganic light emitting display device.

In the display device DD according to the embodiment, there is a display device DD including Al/WO _x The first pixel electrode P of the multi-layer structure of (2)E1 may be disposed in the first sub-pixel area SPA1 emitting the first light and having a first light-emitting area including Al/WO _x The third pixel electrode PE3 of the multi-layer structure of (a) may be disposed in the third sub-pixel region SPA3 emitting third light different from the first light. A thickness compensation pattern TCP having a multi-layer structure including IZO (or IGZO)/ITO may be disposed on the third pixel electrode PE 3. Accordingly, the manufacturing process of the display device DD can be simplified. For example, the organic thickness compensation pattern formed through a fine metal mask ("FMM") process may be omitted due to the thickness compensation pattern TCP disposed on the third pixel electrode PE 3. The display device DD may achieve high resolution (e.g., the number of pixels per inch of the display device DD is about 2000 (e.g., about 2000 ppi) or more).

Referring to fig. 2 and 5, the display device DD according to the embodiment may include a first light emitting element EL1, a second light emitting element EL2, and a third light emitting element EL3. As described above, the first light emitting element EL1 may include the first pixel electrode PE1, the organic layer OL, and the common electrode CE, the second light emitting element EL2 may include the second pixel electrode PE2, the organic layer OL, and the common electrode CE, and the third light emitting element EL3 may include the third pixel electrode PE3, the thickness compensation pattern TCP, the organic layer OL, and the common electrode CE.

The organic layer OL may include a light emitting layer that emits light according to an applied current. For example, the organic layer OL may include a hole transport region HTR, a first light emitting layer EML1, a second light emitting layer EML2, a third light emitting layer EML3, and an electron transport region ETR. The first light emitting layer EML1 may be included in the first light emitting element EL1, the second light emitting layer EML2 may be included in all of the first light emitting element EL1, the second light emitting element EL2, and the third light emitting element EL3, and the third light emitting layer EML3 may be included in the third light emitting element EL3.

The hole transport region HTR may be disposed on the first, second, and third pixel electrodes PE1, PE2, and PE3 and the thickness compensation pattern TCP, and may overlap the first, second, and third sub-pixel regions SPA1, SPA2, and SPA 3. The hole transport region HTR may include a hole injection layer HIL and a hole transport layer HTL. By way of example, the hole transport region HTR may further include a hole buffer layer, an electron blocking layer, and the like, within the spirit and scope of the present disclosure.

The first emission layer EML1 may be disposed on the hole transport region HTR and may overlap the first subpixel region SPA 1. In the case where electrons and holes are injected into the first light emitting layer EML1, the first light emitting layer EML1 may emit light of a first color. For example, the first color may be red, and the first light emitting layer EML1 may include an organic material that emits red light.

The first light emitting layer EML1 may include a first auxiliary layer. The first auxiliary layer may enhance resonance of light emitted from the first light emitting layer EML 1. For example, the first auxiliary layer may include an amine-based organic compound, and resonance may be enhanced by adjusting the thickness of the first auxiliary layer. By way of example, the first auxiliary layer may include a metal having high reflectivity such as Ag or MgAg, such as SiN _x 、SiO _x 、TiO ₂ 、Ta ₂ O ₅ Material for adjusting the optical path of ITO or IZO. These may be used alone or in combination with each other.

The second light emitting layer EML2 may be disposed on the first light emitting layer EML1 and may overlap the first, second, and third sub-pixel regions SPA1, SPA2, and SPA 3. For example, the second light emitting layer EML2 may be commonly disposed in the display area DA. In the case where electrons and holes are injected into the second light emitting layer EML2, the second light emitting layer EML2 may emit light of a second color. For example, the second color may be green, and the second light emitting layer EML2 may include an organic material emitting green light.

The third light emitting layer EML3 may be disposed on the second light emitting layer EML2 and may overlap the third sub-pixel region SPA 3. In the case where electrons and holes are injected into the third light emitting layer EML3, the third light emitting layer EML3 may emit light of a third color. For example, the third color may be blue, and the third light emitting layer EML3 may include an organic material that emits blue light.

The third light emitting layer EML3 may include a thirdThree auxiliary layers. The third auxiliary layer may enhance resonance of light emitted from the third light emitting layer EML 3. For example, the third auxiliary layer may include an amine-based organic compound, and resonance may be enhanced by adjusting the thickness of the third auxiliary layer. By way of example, the third auxiliary layer may include a metal having high reflectivity such as Ag or MgAg, such as SiN _x 、SiO _x 、TiO ₂ 、Ta ₂ O ₅ Material for adjusting the optical path of ITO or IZO. These may be used alone or in combination with each other.

The electron transport region ETR may be disposed on the first, second, and third light emitting layers EML1, EML2, and EML3, and may overlap the first, second, and third sub-pixel regions SPA1, SPA2, and SPA 3. For example, the electron transport regions ETR may be commonly disposed in the display area DA. The electron transport region ETR may include at least one of an electron injection layer and an electron transport layer. By way of example, the electron transport region ETR may further include an electron buffer layer, a hole blocking layer, and the like, within the spirit and scope of the present disclosure.

For example, a fine metal mask ("FMM") may be used twice to form the first, second, and third light emitting layers EML1, EML2, and EML3. Accordingly, the manufacturing process of the display device DD may be simplified as compared with a case where the light emitting layer is formed in each of the first, second, and third sub-pixel regions SPA1, SPA2, and SPA3, respectively.

The display device DD may have a structure in which a first color light (e.g., red light) and a second color light (e.g., green light) resonate once inside the first light emitting element EL1 and the second light emitting element EL2, respectively, and in which a third color light (e.g., blue light) resonates twice inside the third light emitting element EL 3.

Referring to fig. 5, it has been described that the first light emitting layer EML1 emits red light, the second light emitting layer EML2 emits green light, and the third light emitting layer EML3 emits blue light, but the present disclosure is not limited thereto. For example, each of the first, second, and third light emitting layers EML1, EML2, and EML3 may emit any one of red, green, and blue light.

Referring to fig. 6, a buffer layer BUF, a first active pattern ACT1, a second active pattern ACT2, and a third active pattern ACT3, a gate insulating layer GI, a first gate electrode GE1, a second gate electrode GE2, and a third gate electrode GE3, an interlayer insulating layer ILD, a first source electrode SE1, a second source electrode SE2, and a third source electrode SE3, a first drain electrode DE1, a second drain electrode DE2, and a third drain electrode DE3, and a VIA insulating layer VIA may be sequentially disposed on a substrate SUB.

Referring to fig. 7 and 8, the first, second, and third contact holes CNT1, CNT2, and CNT3 may be formed by removing a portion of the VIA insulating layer VIA. The first, second and third contact holes CNT1, CNT2 and CNT3 may be formed simultaneously. The first contact hole CNT1 may expose a portion of the upper surface of the first drain electrode DE1, the second contact hole CNT2 may expose a portion of the upper surface of the second drain electrode DE2, and the third contact hole CNT3 may expose a portion of the upper surface of the third drain electrode DE 3.

The first conductive film CF1 and the second conductive film CF2 may be sequentially formed on the VIA insulating layer VIA. The first conductive film CF1 and the second conductive film CF2 may be commonly formed throughout the display area DA. The first conductive film CF1 may fill the first, second, and third contact holes CNT1, CNT2, and CNT3. For example, the first conductive film CF1 may be formed using aluminum, and the second conductive film CF2 may be formed using tungsten oxide.

Referring to fig. 8 and 9, a photosensitive organic film may be formed on the VIA insulating layer VIA. For example, the photosensitive organic film may be formed using a photoresist. Portions of the photosensitive organic film that do not overlap the first, second, and third sub-pixel regions SPA1, SPA2, and SPA3 may be removed by an exposure process using a photomask. Accordingly, a photosensitive organic pattern overlapping each of the first, second, and third sub-pixel regions SPA1, SPA2, and SPA3 may be formed.

The first conductive film CF1 and the second conductive film CF2 may be etched by a first etching process using the photosensitive organic pattern as a mask. In an embodiment, the first etching process may be a dry etching process.

Since the first conductive film CF1 and the second conductive film CF2 are etched, the first pixel electrode PE1 including the first conductive layer 101a and the second conductive layer 101b may be formed in the first sub-pixel region SPA1 on the VIA insulating layer VIA. Meanwhile, since the first conductive film CF1 and the second conductive film CF2 are etched, the second pixel electrode PE2 including the first conductive layer 101a and the second conductive layer 101b may be formed in the second sub-pixel region SPA2 on the VIA insulating layer VIA. Meanwhile, the third pixel electrode PE3 including the third conductive layer 102a and the fourth conductive layer 102b may be formed in the third sub-pixel region SPA3 on the VIA insulating layer VIA.

Referring to fig. 10, a third conductive film CF3 and a fourth conductive film CF4 may be sequentially formed on the VIA insulating layer VIA. The third conductive film CF3 and the fourth conductive film CF4 may be commonly formed throughout the display area DA, and may cover the first pixel electrode PE1, the second pixel electrode PE2, the third conductive layer 102a, and the fourth conductive layer 102b. For example, the third conductive film CF3 may be formed using indium zinc oxide or indium gallium zinc oxide, and the fourth conductive film CF4 may be formed using indium tin oxide.

A photosensitive organic layer PR' may be formed on the fourth conductive film CF4. For example, the photosensitive organic layer PR' may be formed using a photoresist.

Referring to fig. 11, a portion of the photosensitive organic layer PR' may be removed by an exposure process using a photomask. For example, all of the photosensitive organic layer PR' that does not overlap the third sub-pixel region SPA3 may be removed by an exposure process. Accordingly, the photosensitive organic layer PR' overlapped with the third sub-pixel region SPA3 may remain and the photosensitive organic pattern PR may be formed through an exposure process. For example, the upper surface of the photosensitive organic pattern PR may have a convex shape in cross section.

Referring to fig. 12, the third conductive film CF3 and the fourth conductive film CF4 may be etched by a second etching process using the photosensitive organic pattern PR as a mask. In an embodiment, the second etching process may be a wet etching process. In an embodiment, the second etching process may be a dry etching process. The third conductive film CF3 and the fourth conductive film CF4 may have an etching rate higher than those of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 with respect to the same etchant. Therefore, in the etching process for the third and fourth conductive films CF3 and CF4, the first, second and third pixel electrodes PE1, PE2 and PE3 may not be etched.

A thickness compensation pattern TCP including a first thickness compensation layer 103a and a second thickness compensation layer 103b sequentially stacked on the fourth conductive layer 102b may be formed in the third sub-pixel region SPA 3. In the removal of the portions of the third conductive film CF3 and the fourth conductive film CF4, the first thickness compensation layer 103a and the second thickness compensation layer 103b may be formed by leaving the third conductive film CF3 and the fourth conductive film CF4 overlapping the third sub-pixel region SPA3 in a plan view. After the thickness compensation pattern TCP is formed, the photosensitive organic pattern PR may be removed.

Referring to fig. 13, a pixel defining layer PDL may be formed on the VIA insulating layer VIA. An opening exposing an upper surface of each of the first pixel electrode PE1, the second pixel electrode PE2, and the thickness compensation pattern TCP may be formed in the pixel defining layer PDL. For example, the pixel defining layer PDL may be formed using an organic material such as polyimide.

The organic layer OL may be formed on the first pixel electrode PE1, the second pixel electrode PE2, the thickness compensation pattern TCP, and the pixel defining layer PDL. The organic layer OL may be commonly formed throughout the display area DA. The common electrode CE may be formed on the organic layer OL. The common electrode CE may be commonly formed throughout the display area DA.

Referring back to fig. 2, the encapsulation layer TFE may be formed on the common electrode CE. The encapsulation layer TFE may be commonly formed throughout the display area DA. The encapsulation layer TFE may include at least one inorganic layer and at least one organic layer.

Accordingly, the display device DD shown in fig. 2 can be manufactured.

According to the comparative example and the example, the pixel electrode having a two-layer structure was manufactured by a sputtering process.

In comparative example 1 (CEX 1), a composition including Al (thickness:) ITO (thickness: />) Is provided. In comparative example 2 (CEX 2), a steel comprising Al (thickness:. About.: A)>) ITO (thickness: />) Is provided. In comparative example 3, a composition comprising Al (thickness:. About.>) IGZO (thickness: />) Is provided.

In example 1 (EX 1), a metal alloy including Al (thickness:)/WO _x (thickness:. About.>) Is provided. In example 2 (EX 2), a sputtering film comprising Al (thickness:. About.>)/WO _x (thickness:. About.>) Is provided. In example 3 (EX 3), a steel including Al (thickness:. Times. >)/WO _x (thickness:. About.>) Is provided. In example 4 (EX 4), a steel including Al (thickness:. Times.>)/WO _x (thickness:. About.>) Is provided. In example 3 (EX 3) and example 4 (EX 4), oxygen was not added during the deposition process by the sputtering process.

For each wavelength band of external light, the reflectances of the pixel electrodes satisfying comparative example 1 (CEX 1), comparative example 2 (CEX 2), example 1 (EX 1), example 2 (EX 2), example 3 (EX 3), and example 4 (EX 4) were measured. The contact resistance of the pixel electrodes satisfying comparative example 2 (CEX 2), comparative example 3, and example 3 (EX 3) was measured. In table 1 below, the reflectance of external light having a wavelength of about 450nm for the pixel electrode pairs satisfying comparative example 2 (CEX 2), comparative example 3, and example 3 (EX 3) was measured.

As a result, referring to FIG. 14 and Table 1 below, it can be seen that the reflectivity of the pixel electrode to external light may include Al/WO at the pixel electrode _x Is substantially similar to the case where the pixel electrode includes Al/ITO. For reference, the reflectivity in table 1 below indicates reflectivity for external light having a wavelength of about 450 nm.

With reference to Table 1 below, it can be seen that the composition includes Al/WO _x The contact resistance of the pixel electrode is smaller than that of the pixel electrode including Al/ITO or Al/IGZO.

TABLE 1

Referring to fig. 15, the display device DD' according to the embodiment may include a substrate SUB, a buffer layer BUF, first and third transistors TR1 and TR2, a gate insulating layer GI, an interlayer insulating layer ILD, a VIA insulating layer VIA, a pixel defining layer PDL, first, second and third light emitting elements EL1, EL2 and EL3, and an encapsulation layer TFE. Hereinafter, a description repeated with the description of the display device DD described with reference to fig. 2, 3, and 4 may be omitted or simplified.

The first, second and third pixel electrodes PE1, PE2 and PE3 may be disposed on the VIA insulating layer VIA. For example, each of the first, second, and third pixel electrodes PE1, PE2, and PE3 may have a two-layer structure. The second pixel electrode PE2 may have the same structure as the third pixel electrode PE 3. For example, the second pixel electrode PE2 may have a structure in which two conductive layers including the same material or similar materials as the third conductive layer 102a and the fourth conductive layer 102b of the third pixel electrode PE3 may be sequentially stacked on each other. In other words, the second pixel electrode PE2 including the first conductive layer 101a and the second conductive layer 101b may be formed in the second sub-pixel region SPA2 on the VIA insulating layer VIA.

A thickness compensation pattern TCP including a first thickness compensation layer 103a and a second thickness compensation layer 103b sequentially stacked on each other may be disposed on the third pixel electrode PE 3. A thickness compensation pattern TCP' including the third thickness compensation layer 104a and the fourth thickness compensation layer 104b sequentially stacked on the second pixel electrode PE2 may be provided. The third thickness compensation layer 104a may include the same material or a similar material as the first thickness compensation layer 103a, and the fourth thickness compensation layer 104b may include the same material or a similar material as the second thickness compensation layer 103 b. For example, the third thickness compensation layer 104a may include indium zinc oxide or indium gallium zinc oxide, and the fourth thickness compensation layer 104b may include indium tin oxide.

However, the present disclosure is not limited thereto. For example, the thickness compensation patterns TCP and TCP' may be disposed on at least one pixel electrode among the first, second, and third pixel electrodes PE1, PE2, and PE 3.

Fig. 16 is a block diagram illustrating an electronic device including the display device of fig. 1. Fig. 17 is a diagram illustrating an example in which the electronic apparatus of fig. 16 is implemented as a television. Fig. 18 is a diagram illustrating an example in which the electronic device of fig. 16 is implemented as a smart phone.

Referring to fig. 16, 17, and 18, in an embodiment, an electronic device 900 may include a processor 910, a memory device 920, a storage device 930, an input/output ("I/O") device 940, a power supply 950, and a display device 960. The display device 960 may correspond to the display device DD described with reference to fig. 1, 2, 3, 4, and 5. The electronic device 900 may further include various ports capable of communicating with video cards, sound cards, memory cards, USB devices, and the like within the spirit and scope of the present disclosure.

In an embodiment, as shown in fig. 17, electronic device 900 may be implemented as a television. In an embodiment, as shown in fig. 18, the electronic device 900 may be implemented as a smart phone. However, embodiments are not so limited, and in an embodiment, the electronic device 900 may be implemented as a cellular telephone, video telephone, smart tablet, smart watch, tablet personal computer ("PC"), car navigation system, computer monitor, laptop computer, or head mounted (e.g., mounted) display ("HMD"), etc., within the spirit and scope of the present disclosure.

Processor 910 may perform various computing functions. In an embodiment, the processor 910 may be a microprocessor, a central processing unit ("CPU"), or an application processor ("AP"), etc., within the spirit and scope of the present disclosure. The processor 910 may be coupled to or connected to other components via an address bus, a control bus, a data bus, or the like, within the spirit and scope of the present disclosure. The processor 910 may be coupled to or connected to an expansion bus, such as a peripheral component interconnect ("PCI") bus.

Memory device 920 may store data for the operation of electronic device 900. In an embodiment, the memory device 920 may include at least one non-volatile memory device such as an erasable programmable read-only memory ("EPROM") device, an electrically erasable programmable read-only memory ("EEPROM") device, a flash memory device, a phase change random access memory ("PRAM") device, a resistive random access memory ("RRAM") device, a nano floating gate memory ("NFGM") device, a polymer random access memory ("PoRAM") device, a magnetic random access memory ("MRAM") device, or a ferroelectric random access memory ("FRAM") device, and/or at least one non-volatile memory device such as a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, or a mobile DRAM device, and the like, within the spirit and scope of the present disclosure.

Storage 930 may include a solid state drive ("SSD") device, a hard disk drive ("HDD") device, or a CD-ROM device, among others, within the spirit and scope of the present disclosure.

The I/O device 940 may include an input device such as a keyboard, a keypad, a mouse device, a touch pad or a touch screen, etc., and an output device such as a printer or speakers, etc., within the spirit and scope of the present disclosure.

The power supply 950 may provide power for the operation of the electronic device 900. The display device 960 may be coupled to or connected to other components via a bus or other communication link. In an embodiment, the display device 960 may be included in the I/O device 940.

The present disclosure can be applied to various display devices. For example, the present disclosure may be applied to various display devices such as display devices for vehicles, ships, and airplanes, display devices for portable communication devices, display devices for exhibitions or information transmission, and medical display devices, etc., within the spirit and scope of the present disclosure.

The foregoing is illustrative of the embodiments and is not to be construed as limiting thereof. Although embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without materially departing from the novel teachings and advantages of this disclosure. Accordingly, all such modifications are intended to be included within the scope of this disclosure and as defined in the claims. Therefore, it is to be understood that the foregoing is illustrative of various embodiments and is not to be construed as limited to the disclosed embodiments, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims.

Claims

1. A display device, comprising:

a first sub-pixel region that emits first light and a second sub-pixel region that emits second light different from the first light;

a first pixel electrode disposed in the first sub-pixel region on the substrate and including a first conductive layer including a metal material and a second conductive layer including tungsten oxide sequentially stacked;

a second pixel electrode disposed in the second sub-pixel region on the substrate and including a third conductive layer and a fourth conductive layer sequentially stacked, the third conductive layer and the first conductive layer including the same material, the fourth conductive layer and the second conductive layer including the same material,

a thickness compensation pattern disposed on the second pixel electrode and including a first thickness compensation layer including a first transparent conductive oxide and a second thickness compensation layer including a second transparent conductive oxide, which are sequentially stacked;

a first light emitting layer disposed on the first pixel electrode; and

and a second light emitting layer disposed on the thickness compensation pattern.

2. The display device according to claim 1, wherein the tungsten oxide included in the second conductive layer further comprises tantalum.

3. The display device according to claim 1, wherein the metal material comprises aluminum.

4. The display device according to claim 1, wherein,

the thickness of the first conductive layer is equal to the thickness of the third conductive layer,

the thickness of the second conductive layer is equal to the thickness of the fourth conductive layer,

the thickness of the first conductive layer is greater than the thickness of the second conductive layer,

the thickness of the third conductive layer is greater than the thickness of the fourth conductive layer,

the first thickness compensation layer has a thickness less than the thickness of the third conductive layer, and

each of the thickness of the second conductive layer and the thickness of the fourth conductive layer is greater than a thickness of the second thickness compensation layer.

5. The display device according to claim 1, wherein,

the first transparent conductive oxide includes at least one selected from the group consisting of indium zinc oxide and indium gallium zinc oxide, and

the second transparent conductive oxide includes indium tin oxide.

6. The display device according to claim 1, wherein the thickness compensation pattern has an etching rate higher than that of the first pixel electrode or the second pixel electrode with respect to the same etchant.

7. The display device according to any one of claims 1 to 6, further comprising a third sub-pixel region that emits third light different from the first light emitted by the first sub-pixel region and the second light emitted by the second sub-pixel region.

8. The display device according to claim 7, further comprising:

a third pixel electrode disposed in the third sub-pixel region; and

a third light emitting layer disposed on the third pixel electrode, wherein,

the first light emitting layer overlaps the first sub-pixel region in a plan view,

the second light-emitting layer overlaps the second sub-pixel region in the plan view, and

the third light emitting layer overlaps the first, second, and third sub-pixel regions in the plan view.

9. The display device according to claim 7, further comprising:

and a third pixel electrode disposed in the third sub-pixel region, the third pixel electrode and the first pixel electrode having the same structure.

10. The display device according to claim 7, further comprising:

a third pixel electrode disposed in the third sub-pixel region, the third pixel electrode and the second pixel electrode having the same structure; and

And a first thickness compensation pattern disposed on the third pixel electrode, the first thickness compensation pattern and the thickness compensation pattern having the same structure.