CN117727792B - Structure, manufacturing method and electronic equipment of super-junction silicon carbide transistor - Google Patents
Structure, manufacturing method and electronic equipment of super-junction silicon carbide transistor Download PDFInfo
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- CN117727792B CN117727792B CN202410176524.XA CN202410176524A CN117727792B CN 117727792 B CN117727792 B CN 117727792B CN 202410176524 A CN202410176524 A CN 202410176524A CN 117727792 B CN117727792 B CN 117727792B
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 65
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 65
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 25
- 230000000694 effects Effects 0.000 claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims description 29
- 239000002184 metal Substances 0.000 claims description 29
- 238000003860 storage Methods 0.000 claims description 28
- 230000002146 bilateral effect Effects 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 6
- 230000005669 field effect Effects 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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Abstract
A structure, a manufacturing method and electronic equipment of a super-junction silicon carbide transistor belong to the technical field of semiconductors, and comprise two laterally symmetrical sub-field effect transistor structures, wherein symmetrical tangential planes are sagittal planes, and each sub-field effect transistor structure comprises a substrate, a drift layer, a first well, a first active layer, a grid structure, a source electrode groove, a semiconductor column, a first active region and a third active region; the substrate, the drift layer, the first well and the first active layer are sequentially arranged from bottom to top; the grid structure covers the drift layer, the first well and the first active region, and the source electrode grooves on one side of the sagittal plane penetrate through the first active region and the third active region; the first active region is positioned on the upper surface of the drift layer and is arranged on the side surface of the source groove; the second active region is positioned at the bottom and below the side surface of the source electrode groove and is arranged on the upper surface of the semiconductor column; the third active region is positioned between the first active region and the second active region and is arranged on the side surface of the source electrode groove; the follow current channel is easy to open, so that the conduction loss and the chip area are reduced, and the process is simplified.
Description
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to a structure, a manufacturing method and electronic equipment of a super-junction silicon carbide transistor.
Background
Planar gate silicon carbide (SiC) power metal-oxide-semiconductor field effect transistors (MOSFETs) are widely used due to their simple process.
However, the planar gate MOSFET cell area is larger and a JEFT region exists under the gate thereof, which results in a larger on-resistance and increased on-loss. In addition, an inductance element exists in an actual application circuit, and a large reverse current can be generated at the moment of switching of the circuit to impact the MOSFET, and at the moment, a diode is required to be conducted to enable the large inductance current to pass through, so that the damage of the inductance current to the MOSFET is avoided; typically, silicon-based MOSFETs use body diode reverse freewheeling, but for SiC MOSFETs, the material bandgap is wider, the body diode turn-on voltage (about 2.7V) is much higher than that of silicon-based MOSFETs (about 1.5V), and the freewheeling channel is difficult to turn on, so that the device may be damaged in application, and the device reliability is affected.
Usually, the anti-parallel integration of SiC MOSFET and schottky barrier diode (schottky barrier diode, SBD) or junction field-effect transistor (JFET) can play a role of reverse freewheeling, but is usually parallel connected in a plane, which increases the chip area; there are also related silicon carbide transistors that control the opening of the freewheel channel through split gates, but they have problems of gate reliability, complex process and low current density.
Therefore, the related planar gate silicon carbide transistor has the defects of difficult opening of a follow current channel, large conduction loss, large chip area, poor reliability, complex process and low current density.
Disclosure of Invention
The application aims to provide a structure, a manufacturing method and electronic equipment of a super-junction silicon carbide transistor, and aims to solve the problems that a related planar gate silicon carbide transistor freewheel channel is difficult to open, the conduction loss is large, the chip area is large, the reliability is poor, the process is complex and the current density is low.
The embodiment of the application provides a structure of a super-junction silicon carbide transistor, which comprises two bilateral symmetry sub-field effect transistor structures, wherein the bilateral symmetry section is a sagittal plane, and the sub-field effect transistor structures comprise:
A substrate;
a drift layer located on an upper surface of the substrate;
a first well located on the upper surface of the drift layer;
a first active layer located on the upper surface of the first well;
A gate structure located on a side away from the sagittal plane and covering the drift layer, the first well, and the first active layer;
the first active region is positioned on the upper surface of the drift layer and is arranged on the side surface of the source groove;
the second active region is positioned at the bottom of the source electrode groove, below the side surface of the source electrode groove and arranged on the upper surface of the semiconductor column;
a third active region located between the first active region and the second active region and disposed on a side of the source trench;
A source trench located on one side of the sagittal plane and extending through the first active region and the third active region;
The semiconductor column is positioned on the lower surface of the second active region;
Wherein the semiconductor pillars, the first wells, the first active regions, and the second active regions are of a first type; the substrate, the drift layer, the first active layer, and the third active region are of a second type.
In one embodiment, the sub-field effect transistor structure further includes:
a charge storage layer located between the drift layer and the first well;
the first active region is positioned on the upper surface of the charge storage layer and is arranged on the side surface of the source electrode groove;
the second active region is positioned at the bottom of the source electrode groove, below the side surface of the source electrode groove and arranged on the upper surface of the semiconductor column.
In one embodiment, the sub-field effect transistor structure further includes:
and the dielectric column is arranged inside the semiconductor column and positioned on the lower surface of the second active region.
In one embodiment, the first type is P-type and the second type is N-type; or alternatively
The first type is N-type, and the second type is P-type.
In one embodiment, the method further comprises:
a first metal layer covering the first active layer, the first active region, and the source trench;
a second metal layer located on the lower surface of the substrate;
A third metal layer connected to the gate structure;
The first metal layer is a source electrode of the super-junction silicon carbide transistor, the second metal layer is a drain electrode of the super-junction silicon carbide transistor, and the third metal layer is a gate electrode of the super-junction silicon carbide transistor.
In one embodiment, the gate structure material includes silicon dioxide and polysilicon; the materials of the semiconductor pillars, the drift layer, the first well, the first active layer, the first active region, the second active region, and the third active region include silicon carbide.
The embodiment of the application also provides a manufacturing method of the super-junction silicon carbide transistor, wherein the super-junction silicon carbide transistor is bilaterally symmetrical, and a bilaterally symmetrical tangential plane is a sagittal plane, and the manufacturing method comprises the following steps:
forming a drift layer on the upper surface of the substrate;
Forming a semiconductor column on one side of a sagittal plane in the drift layer;
forming a second active region on the upper surface of the semiconductor column, and forming a third active region on the upper surface of the second active region;
Forming a first well on the upper surface of the drift layer, forming a first active layer on the upper surface of the first well, and forming a first active region on the upper surface of the third active region;
Forming a source electrode groove on one side of the sagittal plane; wherein the source trenches each penetrate through the first active region and the third active region;
a gate structure is formed overlying the drift layer, the first well, and the first active region on a side remote from the sagittal plane.
In one embodiment, after forming the drift layer on the upper surface of the substrate, the method further includes:
Forming a charge storage layer on the upper surface of the drift layer and the upper surface of the semiconductor pillar;
forming a first well on the upper surface of the drift layer, forming a first active layer on the upper surface of the first well, and forming a first active region on the upper surface of the third active region specifically includes:
And forming a first well on the upper surface of the charge storage layer, forming a first active layer on the upper surface of the first well, and forming a first active region on the upper surface of the third active region.
In one embodiment, the forming a semiconductor pillar on the sagittal plane side in the drift layer specifically includes:
forming a semiconductor pillar on one side of a sagittal plane in the drift layer, and forming a dielectric pillar inside the semiconductor pillar;
the forming a second active region on the upper surface of the semiconductor column, and forming a third active region on the upper surface of the second active region specifically comprises:
And forming a second active region on the upper surface of the semiconductor column and the upper surface of the dielectric column, and forming a third active region on the upper surface of the second active region.
The embodiment of the application also provides electronic equipment, which comprises the structure of the super-junction silicon carbide transistor.
Compared with the prior art, the embodiment of the invention has the beneficial effects that: since the drift layer and the substrate are used as a drain electrode, the first well is used as a gate electrode, and the first active layer is used as a source electrode; when the super-junction silicon carbide transistor is applied with forward voltage, the drain electrode and the source electrode are conducted, and the PN junction formed by the first active region and the third active region enables the side wall freewheel channel to be closed due to depletion effect, namely the freewheel channel is cut off. When the super-junction silicon carbide transistor is applied with reverse voltage, the drain electrode and the source electrode are turned off, the PN junction formed by the first active region and the third active region is forward biased, the depletion layer disappears, so that the side wall freewheeling channel is conducted, the reverse freewheeling effect can be achieved without anti-parallel integration of the SiC MOSFET and the Schottky barrier diode or the junction field effect transistor, the freewheeling channel is easy to open, the conduction loss and the chip area are reduced, the reliability and the current density are increased, and the process is simplified. Meanwhile, the drift layer and the semiconductor column alternately form depletion layers, so that the super-junction silicon carbide transistor allows higher doping concentration under the same withstand voltage, on-resistance is reduced when forward voltage is applied, and larger follow current capability is achieved when reverse voltage is applied.
Drawings
In order to more clearly illustrate the technical invention in the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it will be apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.
FIG. 1 is a schematic diagram of a super-junction silicon carbide transistor according to an embodiment of the present application;
FIG. 2 is a schematic diagram of another embodiment of a super junction silicon carbide transistor according to the present application;
FIG. 3 is a schematic diagram of another embodiment of a super junction silicon carbide transistor according to the present application;
FIG. 4 is a schematic diagram of another embodiment of a super junction silicon carbide transistor according to the present application;
FIG. 5 is a schematic diagram illustrating formation of a drift layer in a method for fabricating a super-junction silicon carbide transistor according to an embodiment of the present application;
Fig. 6 is a schematic diagram of a semiconductor pillar formed in a method of fabricating a super junction silicon carbide transistor according to an embodiment of the present application;
Fig. 7 is a schematic diagram illustrating formation of a second active region and a third active region in a method for fabricating a super junction silicon carbide transistor according to an embodiment of the present application;
Fig. 8 is a schematic diagram illustrating formation of a first well, a first active layer, and a first active region in a method for fabricating a super junction silicon carbide transistor according to an embodiment of the present application;
Fig. 9 is a schematic diagram illustrating a method for forming a source trench in a method for manufacturing a super-junction silicon carbide transistor according to an embodiment of the present application;
fig. 10 is a schematic diagram illustrating a gate structure formed in a method for manufacturing a super-junction silicon carbide transistor according to an embodiment of the present application;
FIG. 11 is a schematic diagram of a method of forming a charge storage region in a method of fabricating a super junction silicon carbide transistor according to an embodiment of the present application;
fig. 12 is a schematic diagram of a method of forming a dielectric pillar in a method of fabricating a super junction silicon carbide transistor according to an embodiment of the present application.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
It will be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are merely for convenience in describing and simplifying the description based on the orientation or positional relationship shown in the drawings, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus are not to be construed as limiting the application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Fig. 1 shows the structure of a super-junction silicon carbide transistor provided in an embodiment of the present invention, and for convenience of explanation, only the portions relevant to the embodiment of the present invention are shown in detail as follows:
The super-junction silicon carbide transistor structure comprises two bilateral symmetry sub-field effect transistor structures, wherein the bilateral symmetry section is a sagittal plane, and each sub-field effect transistor structure comprises a substrate 90, a drift layer 01, a first well 02, a first active layer 03, a gate structure 04, a source electrode groove 05, a semiconductor column 09, a first active region 06, a second active region 07 and a third active region 08.
The drift layer 01 is located on the upper surface of the substrate 90.
The first well 02 is located on the upper surface of the drift layer 01.
The first active layer 03 is located on the upper surface of the first well 02.
The gate structure 04 is located on the side away from the sagittal plane and covers the drift layer 01, the first well 02 and the first active layer 03.
The source trench 05 is located on the sagittal plane side and extends through the first and third active regions 06 and 08.
The first active region 06 is located on the upper surface of the drift layer 01 and is disposed on the side of the source trench 05.
The second active region 07 is located at the bottom of the source trench 05 and below the side of the source trench 05 and is disposed on the upper surface of the semiconductor pillar 09.
The third active region 08 is located between the first and second active regions 06 and 07 and is disposed laterally of the source trench 05.
The semiconductor pillars 09 are located on the lower surface of the second active region 07.
Wherein the semiconductor pillars 09, the first well 02, the first active region 06, and the second active region 07 are of a first type; the substrate 90, the drift layer 01, the first active layer 03 and the third active region 08 are of the second type.
In a specific implementation, the drift layer 01 and the substrate 90 serve as drains, the first well 02 serves as a gate, and the first active layer 03 serves as a source. Taking the first type as P type and the second type as N type as an example, when the super-junction silicon carbide transistor applies forward voltage, the source electrode is connected with low potential, the drain electrode and the source electrode are conducted, and the PN junction formed by the first active region 06 and the third active region 08 causes the side wall freewheeling channel to be closed due to depletion effect, namely the freewheeling channel is cut off. When the super-junction silicon carbide transistor is applied with reverse voltage, the source electrode is connected with high potential, the drain electrode and the source electrode are turned off, the PN junction formed by the first active region 06 and the third active region 08 is forward biased, the depletion layer disappears, so that the side wall freewheel channel is conducted, the reverse freewheel effect can be achieved without anti-parallel integration of the SiC MOSFET and the SBD or junction field effect transistor JFET, the freewheel channel is easy to open, the conduction loss and the chip area are reduced, the reliability and the current density are increased, and the process is simplified. Meanwhile, the drift layer 01 and the semiconductor column 09 alternately form depletion layers, so that the super-junction silicon carbide transistor allows higher doping concentration under the same withstand voltage, the on-resistance is reduced when forward voltage is applied, and the super-junction silicon carbide transistor has larger freewheel capability when reverse voltage is applied. It should be emphasized that the freewheeling ability is further improved because the freewheeling channels are connected in parallel to both sides of the source trench 05.
The second active region 07 at the bottom of the source trench 05 may function to protect the gate oxide at the bottom corner of the gate structure 04, and at the same time, isolate the drain from the bottom of the source trench 05.
As shown in fig. 2, the sub-field effect transistor structure further includes a charge storage layer 10 (charge storage layer, CSL).
The charge storage layer 10 is located between the drift layer 01 and the first well 02.
The first active region 06 is located on the upper surface of the charge storage layer 10 and is disposed on the side of the source trench 05.
The second active region 07 is located at the bottom of the source trench 05 and below the side of the source trench 05 and is disposed on the upper surface of the semiconductor pillar 09.
Note that the doping type of the charge storage layer 10 is the second type. The doping concentration of the charge storage layer 10 is greater than the doping concentration of the drift layer 01 and less than the doping concentration of the third active region 08. The material of the charge storage region is silicon carbide.
To ensure that the freewheel path is normally closed, the charge storage layer 10 has a thickness of 0.1 μm to 0.2 μm, the doping concentration of the third active region 08 is approximately 1E19, and the doping concentration of the charge storage layer 10 is between 1E16 and 8E 16.
By providing the charge storage layer 10, forward conduction current of the super junction silicon carbide transistor is improved, and forward on-resistance is reduced.
It should be noted that the first type is P-type, and the second type is N-type; or alternatively
The first type is N type and the second type is P type.
As shown in fig. 3, the sub-field effect transistor structure further includes a dielectric pillar 20.
The dielectric pillar 20 is disposed inside the semiconductor pillar 09 and on the lower surface of the second active region 07.
By providing the dielectric pillars 20, the width of the depletion layer formed by the conductive pillars and the drift layer 01 is controllable, thereby improving flexibility in controlling the forward on-resistance and reverse freewheeling ability.
Note that the gate structure 04 includes a dielectric layer and a conductive pillar.
A dielectric layer is positioned on the side far away from the sagittal plane and covers the drift layer 01, the first well 02 and the first active layer 03; the conductive posts are disposed in the dielectric layer.
As shown in fig. 4, the structure of the superjunction silicon carbide transistor further includes a first metal layer 70, a second metal layer 80, and a third metal layer.
The first metal layer 70 covers the first active layer 03, the first active region 06, and the source trench 05.
The second metal layer 80 is located on the lower surface of the substrate 90.
The third metal layer is connected to the gate structure 04.
The first metal layer 70 is a source electrode of the super-junction silicon carbide transistor, the second metal layer 80 is a drain electrode of the super-junction silicon carbide transistor, and the third metal layer is a gate electrode of the super-junction silicon carbide transistor.
It is emphasized that the material of the gate structure 04 includes silicon dioxide and polysilicon; the materials of the semiconductor pillars 09, the drift layer 01, the first well 02, the first active layer 03, the first active region 06, the second active region 07, and the third active region 08 include silicon carbide.
By way of example and not limitation, the third active region 08 is at a distance of 0.5 microns or more from the bottom of the source trench 05.
Since the distance between the third active region 08 and the bottom of the source trench 05 is 0.5 μm or more, the possibility of ground breakdown due to electric field concentration in the third active region 08 is reduced, and the influence on withstand voltage is reduced.
In accordance with one embodiment of the present invention, there is also provided an embodiment of a method of manufacturing a superjunction silicon carbide transistor.
A method for manufacturing a super-junction silicon carbide transistor is provided, wherein the super-junction silicon carbide transistor is bilaterally symmetrical, and a section of the bilaterally symmetrical section is a sagittal section 100, and the method comprises steps 401 to 406.
In step 401, as shown in fig. 5, a drift layer 01 is formed on the upper surface of a substrate 90.
The drift layer 01 is formed on the upper surface of the substrate 90 by vapor deposition or sputtering.
In step 402, as shown in fig. 6, a semiconductor pillar 09 is formed on the sagittal plane side of the drift layer 01.
The semiconductor pillars 09 are formed on the sagittal plane side in the drift layer 01 by ion implantation.
In step 403, as shown in fig. 7, a second active region 07 is formed on the upper surface of the semiconductor pillar 09, and a third active region 08 is formed on the upper surface of the second active region 07.
A second active region 07 is formed on the upper surface of the semiconductor pillar 09 by ion implantation, and a third active region 08 is formed on the upper surface of the second active region 07 by ion implantation.
In step 404, as shown in fig. 8, a first well 02 is formed on the upper surface of the drift layer 01, a first active layer 03 is formed on the upper surface of the first well 02, and a first active region 06 is formed on the upper surface of the third active region 08.
A first well 02 is formed on the upper surface of the drift layer 01 by an epitaxial process and ion implantation, a first active layer 03 is formed on the upper surface of the first well 02 by an epitaxial process and ion implantation, and a first active region 06 is formed on the upper surface of the third active region 08 by ion implantation.
In step 405, as shown in fig. 9, a source trench 05 is formed on the sagittal plane side; wherein the source trenches 05 each penetrate the first and third active regions 06 and 08.
Source trench 05 is formed on the sagittal plane side by etching.
In step 406, as shown in fig. 10, a gate structure 04 covering the drift layer 01, the first well 02, and the first active region 06 is formed on a side away from the sagittal plane.
A dielectric layer is formed covering the drift layer 01, the first well 02 and the first active region 06, a first trench is etched in the dielectric layer, and a conductive pillar is filled in the first trench to form a gate structure 04.
In particular, step 402 is followed by step 402-2.
In step 402-2, as shown in fig. 11, a charge storage layer 10 is formed on the upper surface of the drift layer 01 and the upper surface of the semiconductor pillar 09.
The first well 02 is formed on the upper surface of the drift layer 01, the first active layer 03 is formed on the upper surface of the first well 02, and the first active region 06 is formed on the upper surface of the third active region 08 specifically:
A first well 02 is formed on the upper surface of the charge storage layer 10, a first active layer 03 is formed on the upper surface of the first well 02, and a first active region 06 is formed on the upper surface of the third active region 08.
It is emphasized that, as shown in fig. 12, the formation of the semiconductor pillar 09 on the sagittal plane side in the drift layer 01 may be specifically: a semiconductor pillar 09 is formed on the sagittal plane side in the drift layer 01, and a dielectric pillar 20 is formed inside the semiconductor pillar 09. The formation of the second active region 07 on the upper surface of the semiconductor pillar 09 and the formation of the third active region 08 on the upper surface of the second active region 07 may be specifically: a second active region 07 is formed on the upper surface of the semiconductor pillar 09 and the upper surface of the dielectric pillar 20, and a third active region 08 is formed on the upper surface of the second active region 07.
In specific implementation, step 406 may further include steps 407 to 409.
In step 407, a first metal layer is formed on the upper surface of the first active layer, the upper surface of the first active region, and the inside of the source trench.
In step 408, a second metal layer is formed on the lower surface of the substrate.
In step 409, a third metal layer is formed in connection with the gate structure.
It is emphasized that the first metal layer is the source electrode of the super-junction silicon carbide transistor, the second metal layer is the drain electrode of the super-junction silicon carbide transistor, and the third metal layer is the gate electrode of the super-junction silicon carbide transistor.
It is noted that the metal layer may be gold or palladium. The contacts of the respective metal layers may be ohmic contacts.
The embodiment of the invention comprises two bilateral symmetry sub-field effect tube structures, wherein the bilateral symmetry section is a sagittal plane, and each sub-field effect tube structure comprises a substrate, a drift layer, a first well, a first active layer, a grid structure, a source electrode groove, a semiconductor column, a first active region, a second active region and a third active region; a drift layer located on an upper surface of the substrate; the first well is positioned on the upper surface of the drift layer; the first active layer is positioned on the upper surface of the first well; the grid structure is positioned on one side far away from the sagittal plane and covers the drift layer, the first well and the first active layer; the source electrode groove is positioned on one side of the sagittal plane and penetrates through the first well and the first active layer; the first active region is positioned on the upper surface of the drift layer and is arranged on the side surface of the source groove; the second active region is positioned at the bottom of the source electrode groove, below the side surface of the source electrode groove and arranged on the upper surface of the semiconductor column; the third active region is positioned between the first active region and the second active region and is arranged on the side surface of the source electrode groove; the semiconductor column is positioned on the lower surface of the second active region; the semiconductor column, the first well, the first active region and the second active region are of a first type; the substrate, the drift layer, the charge storage layer, the first active layer and the third active region are of a second type; the freewheel channel is easy to open, the conduction loss and the chip area are reduced, the reliability and the current density are increased, the process is simplified, the forward conduction resistance is reduced, and the reverse freewheel capability is increased.
It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic, and should not limit the implementation process of the embodiment of the present application.
The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (6)
1. The utility model provides a structure of super junction carborundum transistor which characterized in that includes two bilateral symmetry's sub-field effect transistor structures, bilateral symmetry's tangent plane is the sagittal, sub-field effect transistor structure includes:
A substrate;
a drift layer located on an upper surface of the substrate;
a charge storage layer located on an upper surface of the drift layer;
a first well on an upper surface of the charge storage layer;
a first active layer located on the upper surface of the first well;
the first active region is positioned on the upper surface of the charge storage layer and is arranged on the side surface of the source electrode groove;
a gate structure located on a side away from the sagittal plane and overlying the charge storage layer, the first well, and the first active layer;
the second active region is positioned at the bottom of the source electrode groove, below the side surface of the source electrode groove and arranged on the upper surface of the semiconductor column;
a third active region located between the first active region and the second active region and disposed on a side of the source trench;
A source trench located on one side of the sagittal plane and extending through the first active region and the third active region;
The semiconductor column is positioned on the lower surface of the second active region;
a first metal layer covering the first active layer, the first active region, and the source trench; the first metal layer is a source electrode of the super-junction silicon carbide transistor;
the source electrode is in contact with the first active region, the second active region and the third active region;
Wherein the semiconductor pillars, the first well, the first active region, and the second active region are of a first conductivity type; the substrate, the drift layer, the charge storage layer, the first active layer, and the third active region are of a second conductivity type.
2. The structure of the super junction silicon carbide transistor of claim 1, wherein the first conductivity type is P-type and the second conductivity type is N-type; or alternatively
The first conductivity type is N-type, and the second conductivity type is P-type.
3. The structure of the super junction silicon carbide transistor of claim 1, further comprising:
a second metal layer located on the lower surface of the substrate;
A third metal layer connected to the gate structure;
The second metal layer is a drain electrode of the super-junction silicon carbide transistor, and the third metal layer is a gate electrode of the super-junction silicon carbide transistor.
4. A structure of a super junction silicon carbide transistor according to any of claims 1 to 3 wherein the material of the gate structure comprises silicon dioxide and polysilicon; materials of the semiconductor pillars, the drift layer, the charge storage layer, the first well, the first active layer, the first active region, the second active region, and the third active region include silicon carbide.
5. A method of fabricating a superjunction silicon carbide transistor, wherein the superjunction silicon carbide transistor is bilaterally symmetric and a tangential plane of the bilaterally symmetric is a sagittal plane, the method comprising:
Forming a drift layer on the upper surface of the substrate; forming a semiconductor column on one side of a sagittal plane in the drift layer;
Forming a charge storage layer on the upper surface of the drift layer and the upper surface of the semiconductor pillar;
forming a second active region on the upper surface of the semiconductor column, and forming a third active region on the upper surface of the second active region;
forming a first well on the upper surface of the charge storage layer, forming a first active layer on the upper surface of the first well, and forming a first active region on the upper surface of the third active region;
Forming a source electrode groove on one side of the sagittal plane; wherein the source trenches each penetrate through the first active region and the third active region;
Forming a gate structure covering the charge storage layer, the first well and the first active layer on a side away from the sagittal plane;
Wherein the semiconductor pillars, the first well, the first active region, and the second active region are of a first conductivity type; the substrate, the drift layer, the charge storage layer, the first active layer, and the third active region are of a second conductivity type.
6. An electronic device comprising the structure of the super junction silicon carbide transistor of any one of claims 1 to 4.
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| CN102347356A (en) * | 2010-07-27 | 2012-02-08 | 株式会社电装 | Semiconductor device having switching element and free wheel diode and method for controlling the same |
| CN112768532A (en) * | 2021-02-23 | 2021-05-07 | 湖南大学 | SiC MOSFET device of single-chip integrated freewheeling diode and preparation method thereof |
| CN117334746A (en) * | 2023-12-01 | 2024-01-02 | 深圳天狼芯半导体有限公司 | Source electrode groove integrated SBD super-junction SiC MOS with oxide layer and preparation method |
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| CN102347356A (en) * | 2010-07-27 | 2012-02-08 | 株式会社电装 | Semiconductor device having switching element and free wheel diode and method for controlling the same |
| CN112768532A (en) * | 2021-02-23 | 2021-05-07 | 湖南大学 | SiC MOSFET device of single-chip integrated freewheeling diode and preparation method thereof |
| CN117334746A (en) * | 2023-12-01 | 2024-01-02 | 深圳天狼芯半导体有限公司 | Source electrode groove integrated SBD super-junction SiC MOS with oxide layer and preparation method |
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