CN117727757A - Semiconductor device with a semiconductor layer having a plurality of semiconductor layers - Google Patents

Abstract

The application provides a semiconductor device, which comprises an insulating substrate, a channel layer, a barrier layer, a first grid electrode, a first source electrode, a first drain electrode, a second grid electrode, a second source electrode and a second drain electrode. The channel layer, the barrier layer, the first gate, the first source and the first drain form a first transistor, the channel layer, the barrier layer, the second gate, the second source and the second drain form a second transistor, and the first transistor and the second transistor are arranged on an insulating substrate. Through the configuration of the insulating substrate, crosstalk between the first transistor and the second transistor is suppressed, so that the first transistor and the second transistor are not affected by a substrate bias effect, and short-circuiting of the first source electrode and the substrate and short-circuiting of the second source electrode and the substrate are not required.

Description

Semiconductor device with a semiconductor layer having a plurality of semiconductor layers

Technical Field

The application relates to the technical field of semiconductors, in particular to a semiconductor device.

Background

Gallium nitride high electron mobility transistor (GaN High electron mobility transistor, gaN HEMT) technology opens the era of power converters, achieving unprecedented high operating frequencies and power densities. The power converter adopting the discrete GaN device inevitably has larger parasitic parameters, and can cause oscillation and voltage/current spike in the high-speed switching process, thereby threatening the safe operation of the power system. In order to minimize parasitic parameters and exploit the potential of GaN HEMT technology in high frequency applications, gallium nitride-based monolithic power integrated circuits (GaN integrated circuit, gaN ICs) have become a mainstream solution.

Half-bridge circuits consisting of High Side (HS) and Low Side (LS) transistors are widely used in power converters, and in order to maximize device performance, gaN HEMTs are typically used for both the high side and low side transistors, and the sources of both the HS and LS transistors should be electrically connected to the substrate. However, si-based GaN monolithic power integrated circuits have only one common conductive substrate, so it is impractical for both the sources of the HS and LS transistors to be connected to the substrate, and transistors without source-to-substrate shorting can suffer from cross-talk or from substrate bias effects through the common substrate. In the prior art, for example, the source of the GaN HEMT in the LS transistor is connected to the substrate, and the source of the GaN HEMT in the HS transistor is connected to the switching voltage, which causes a voltage difference between the source of the GaN HEMT in the HS transistor and the substrate, which affects the current of the HS transistor, in other words, the GaN HEMT in the HS transistor suffers from crosstalk or substrate bias effect through the common substrate, resulting in the performance degradation of the whole half bridge circuit.

Disclosure of Invention

According to the foregoing, the present application provides a semiconductor device that solves the problem of crosstalk or liner bias effects of gallium nitride high electron mobility transistors.

In view of the above, the present application provides a semiconductor device including an insulating substrate, a channel layer, a barrier layer, a first gate, a first source, a first drain, a second gate, a second source, and a second drain. The insulating substrate includes a first region and a second region. The channel layer is disposed on the insulating substrate. The barrier layer is disposed on the channel layer. The first grid electrode is arranged in the first area and is positioned on the barrier layer. The first source electrode is arranged on the barrier layer of the first region and is positioned on one side of the first grid electrode. The first drain electrode is arranged on the barrier layer of the first region and positioned on the other side of the first grid electrode. The second grid electrode is arranged in the second area and is positioned on the barrier layer. The second source electrode is arranged on the barrier layer of the second region and is positioned on one side of the second grid electrode. The second drain electrode is arranged on the barrier layer of the second region and positioned on the other side of the second grid electrode. The channel layer, the barrier layer, the first gate, the first source and the first drain form a first transistor, the channel layer, the barrier layer, the second gate, the second source and the second drain form a second transistor, and the lattice of the insulating substrate is close to the lattice of the channel layer.

In the embodiment of the application, the crystal structure of the insulating substrate and the crystal structure of the channel layer are hexagonal structures.

In the embodiment of the application, the lattice mismatch degree of the insulating substrate and the channel layer is small.

In embodiments of the present application, the insulating substrate is sapphire or high-resistance silicon carbide or aluminum nitride or zinc oxide.

In an embodiment of the present application, the semiconductor device further includes a first cap layer disposed between the first gate and the barrier layer of the first region, and a second cap layer disposed between the second gate and the barrier layer of the second region.

In an embodiment of the present application, the semiconductor device further includes a buffer layer disposed between the insulating substrate and the channel layer.

In an embodiment of the present application, the semiconductor device further includes a trench and an insulating layer. The trench is disposed between the first region and the second region, and extends from the barrier layer to the buffer layer, and the insulating layer is disposed in the trench.

In an embodiment of the present application, a trench is located between the first drain and the second source.

In an embodiment of the present application, the semiconductor device further includes a dielectric layer disposed between the first cap layer and the first source electrode, between the first cap layer and the first drain electrode, between the second cap layer and the second source electrode, between the second cap layer and the second drain electrode, and between the second source electrode and the first drain electrode.

In an embodiment of the present application, the first source, the first drain, the second source, and the second drain extend to the channel layer.

In an embodiment of the present application, the semiconductor device further includes a connection electrode, the first drain electrode is adjacent to the second source electrode, the connection electrode is connected to the first drain electrode and the second source electrode, the first source electrode is connected to a ground potential, and the second drain electrode is connected to an input voltage.

In the embodiment of the application, the number of the first transistors is N, the N first transistors are sequentially arranged in parallel and share the barrier layer and the buffer layer, N is greater than or equal to 2, two first drains of every two adjacent first transistors are located on opposite sides of the corresponding first source, and each of the N first gates is located between the corresponding first drain and the first source.

In the embodiment of the application, the number of the second transistors is N, the N second transistors are sequentially arranged in parallel and share the barrier layer and the buffer layer, N is greater than or equal to 2, two second drains or second sources of every two adjacent second transistors are located on opposite sides of the corresponding second drains, and each of the N second gates is located between the corresponding second drains and second sources.

In an embodiment of the present application, a conductive structure is further included to connect the first drain of the adjacent first transistor and the second source of the second transistor and serve as an output terminal of the semiconductor device.

In summary, in the semiconductor device of the present application, based on the configuration of the insulating substrate, the insulating substrate does not have the same overall potential, and there is no influence on the switching operation of the first transistor and the second transistor, and in addition, there is no need for shorting the first source and the substrate and shorting the second source and the substrate, and the first transistor and the second transistor are not affected by the substrate bias effect, and there is no need for a specially designed substrate, and no additional cost is added.

The foregoing description is only an overview of the technical solution of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention can be implemented according to the content of the specification, and the following detailed description of the preferred embodiments of the present invention will be given with reference to the accompanying drawings.

Drawings

Fig. 1A is a schematic diagram illustrating a semiconductor device according to an embodiment of the present application.

Fig. 1B is an equivalent circuit diagram of a semiconductor device according to an embodiment of the present application.

Fig. 2 is a schematic diagram illustrating a semiconductor device according to another embodiment of the present application.

Fig. 3 is a schematic diagram illustrating a semiconductor device according to another embodiment of the present application.

Fig. 4 is a graph of current and voltage waveforms for a high side transistor and a low side transistor in combination with a silicon substrate.

Fig. 5 is a current and voltage waveform diagram of the semiconductor device of the present application.

Reference numerals illustrate:

10: substrate and method for manufacturing the same

20: channel layer

30: barrier layer

40: buffer layer

50: dielectric layer

60: insulating layer

C1: first cap layer

C2: second cap layer

CS1: conductive structure

CE1: connection electrode

D1, D11, D12: first drain electrode

D2: second drain electrode

G1, G11, G12: first grid electrode

G2, G21, G22: second grid electrode

GND: grounding end

S1: first source electrode

S2, S21, S22: second source electrode

T1: first transistor

T2: second transistor

TR1: groove(s)

Vin: input voltage

Vout: output voltage

Vct1: first control voltage

Vct2: second control voltage

Idd: electric current

Detailed Description

Further advantages and effects of the present application will be readily apparent to those skilled in the art from the present disclosure, by describing the embodiments of the present application with specific examples.

It should be noted that, without conflict, the embodiments and features of the embodiments in the present application may be combined with each other. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments. In order to make the present application solution better understood by those skilled in the art, the following description will be made in detail and with reference to the accompanying drawings in the embodiments of the present application, it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.

It should be noted that the terms "first," "second," and the like in the description and claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

A common solution to the problem of the substrate bias effect of the gan hemt is to use a specially processed substrate, such as a silicon on insulator (Silicon On Insulator, SOI) substrate or an engineered PN junction silicon (Si) substrate, which still requires a source-to-substrate via and metal interconnect process, resulting in additional process steps and manufacturing costs.

Referring to fig. 1A and 1B, schematic diagrams of a semiconductor device according to an embodiment of the present application and equivalent circuit diagrams of the semiconductor device according to an embodiment of the present application are shown. As shown in fig. 1A and 1B, the semiconductor device includes an insulating substrate 10, a channel layer 20, a barrier layer 30, a first gate G1, a first source S1, a first drain D1, a second gate G2, a second source S2, and a second drain D2. The insulating substrate 10 includes a first region and a second region. The channel layer 20 is disposed on the insulating substrate 10. The barrier layer 30 is disposed on the channel layer 20. The first gate G1 is disposed in the first region and on the barrier layer 30. The first source S1 is disposed on the barrier layer 30 of the first region and is located at one side of the first gate G1. The first drain D1 is disposed on the barrier layer 30 of the first region and located at the other side of the first gate G1. The second gate G2 is disposed in the second region and on the barrier layer 30. The second source S2 is disposed on the barrier layer 30 of the second region and is located at one side of the second gate G2. The second drain D2 is disposed on the barrier layer 30 of the second region and is located at the other side of the second gate G2. The channel layer 20, the barrier layer 30, the first gate G1, the first source S1, and the first drain D1 form a first transistor T1, the channel layer 20, the barrier layer 30, the second gate G2, the second source S2, and the second drain D2 form a second transistor T2, and the lattice of the insulating substrate 10 is close to the lattice of the channel layer 20. For example, the first transistor T1 is a low-side transistor, and the second transistor T2 is a high-side transistor.

The insulating substrate 10 may be a sapphire (sapphire) substrate, a high-resistance silicon carbide (SiC) substrate, an aluminum nitride (AlN) substrate. The material of the channel layer 20 includes gallium nitride (GaN). The crystal structures of gallium nitride and aluminum gallium nitride are closely packed hexagonal lattices, and the crystal structures of a sapphire (sapphire) substrate, a silicon carbide (SiC) substrate, and an aluminum nitride (AlN) substrate are also closely packed hexagonal lattices, so that the lattice of the insulating substrate 10 and the lattice of the channel layer 20 have a small degree of lattice mismatch, and thus lattice defects due to lattice mismatch can be effectively suppressed.

The barrier layer 30 covers the entire channel layer 20, and the material of the barrier layer 30 includes aluminum gallium nitride (AlGaN). The energy gap of the aluminum gallium nitride is higher than that of the gallium nitride, namely, the energy gap of the barrier layer 30 is higher than that of the channel layer 20, so that a heterostructure is formed at the junction of the barrier layer 30 and the channel layer 20.

The first source S1 and the first drain D1 are disposed on opposite sides of the first gate G1, and the first gate G1 receives the first control voltage Vct1. For example, the first source S1 is disposed on the left side of the first gate G1, and the first drain D1 is disposed on the right side of the first gate G1. The first source S1 is separated from the first gate G1, the first source S1 is separated from the first gate G1 by a first distance, and the first source S1 is connected to the ground GND (i.e. the ground potential). The first drain D1 is disposed apart from the first gate G1 and adjacent to the second source S2, the first drain D1 is separated from the first gate G1 by a second distance, the second distance is greater than the first distance, and the first drain D1 is connected to the second source S2 to output the output voltage Vout. In other words, the first gate G1 is closer to the first source S1 but farther from the first drain D1, and a side of the first drain D1 opposite to the second source S2 is the first gate G1. The materials of the first source electrode S1, the first drain electrode D1, and the first gate electrode G1 may include titanium nitride (TiN), tantalum nitride (TaN), aluminum (Al), titanium aluminide (TiAL), indium (In), tiN (Sn), gold (Au), platinum (Pt), indium (In), zinc (Zn), germanium (Ge), silver (Ag), lead (Pb), palladium (Pd), copper (Cu), beryllium (AuBe), beryllium (BeGe), nickel (Ni), lead stannate (PbSn), chromium (Cr), zinc (AuZn), titanium (Ti), tungsten (W), titanium Tungsten (TiW), or alloys thereof. The materials of the first source electrode S1, the first drain electrode D1, and the first gate electrode G1 are only examples, and are not intended to limit the present application.

The second source S2 and the second drain D2 are disposed on opposite sides of the second gate G2, and the second gate G2 receives the second control voltage Vct2. For example, the second source S2 is disposed on the left side of the second gate G2, and the second drain D2 is disposed on the right side of the second gate G2. The second source electrode S2 is separated from the second gate electrode G2, and the second source electrode S2 is separated from the second gate electrode G2 by a third distance. The second drain D2 is separated from the second gate G2, the second drain D2 is separated from the second gate G2 by a fourth distance, the fourth distance is greater than the third distance, and the second drain D2 receives the input voltage Vin. In other words, the second gate G2 is closer to the second source S2 but farther from the second drain D2, and a side of the second source S2 opposite to the first drain D1 is the second gate G2. The materials of the second source electrode S2, the second drain electrode D2 and the second gate electrode G2 are the same as those of the first source electrode S1, the first drain electrode D1 and the first gate electrode G1.

In one embodiment, the contact between the first gate G1 and the first cap layer C1 and the contact between the first gate G2 and the first cap layer C2 are ohmic contacts. In another embodiment, the contact between the first gate G1 and the first cap layer C1 and the contact between the first gate G2 and the first cap layer C2 are schottky contacts.

The semiconductor device further includes a buffer layer 40, a first cap layer C1, and a second cap layer C2. The buffer layer 40 is disposed between the insulating substrate 10 and the channel layer 20 to alleviate defects caused by lattice mismatch of the insulating substrate 10 and the channel layer 20; in other words, the channel layer 20 is disposed on the buffer layer 40. Buffer layer 40 may also include a nucleation layer AlN, which may be selected from III-V compound materials such as GaN, alGaN, and the like. The first cap layer C1 is disposed between the first gate electrode G1 and the barrier layer 30 of the first region; in other words, the first cap layer C1 is provided with a first source S1 and a first drain D1 on opposite sides thereof, the first source S1 and the first drain D1 are separately disposed from the first cap layer C1, and the first cap layer C1 is closer to the first source S1 but farther from the first drain D1. The second cap layer C2 is disposed between the second gate electrode G2 and the barrier layer 30 of the second region; in other words, the second cap layer C2 is provided with a second source S2 and a second drain D2 on opposite sides thereof, the second source S2 and the second drain D2 are separately disposed from the second cap layer C2, and the second cap layer C2 is closer to the second source S2 but farther from the second drain D2. Through the configuration of the second cap layer C2, the threshold voltage of the second transistor T2 is increased. The materials of the first cap layer C1 and the second cap layer C2 may include P-type gallium nitride or semiconductor materials, and the semiconductor materials may include aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum indium gallium nitride (AlInGaN), or a combination thereof.

According to the values of the first control voltage Vct1 and the second control voltage Vct2, one of the first transistor T1 and the second transistor T2 is controlled to be conductive and the other is controlled to be non-conductive, or both the first transistor T1 and the second transistor T2 are controlled to be non-conductive.

In the semiconductor device of this embodiment, since the insulating substrate does not have the same overall potential, there is no voltage difference between the insulating substrate and the source of the high-side transistor and between the insulating substrate and the source of the low-side transistor, so that crosstalk between the high-side transistor and the low-side transistor is suppressed, and no specially designed substrate is required, and no shorting of the source of the high-side transistor and the low-side transistor to the substrate is required.

Referring to fig. 2, a schematic diagram of a semiconductor device according to another embodiment of the present application is shown. As shown in fig. 2, the semiconductor device includes an insulating substrate 10, a channel layer 20, a barrier layer 30, a buffer layer 40, a first gate G1, a first source S1, a first drain D1, a second gate G2, a second source S2, a second drain D2, a first cap layer C1, a second cap layer C2, a dielectric layer 50, an insulating layer 60, a connection electrode CE1, and a trench TR1, wherein the configuration of the insulating substrate 10, the channel layer 20, the barrier layer 30, the buffer layer 40, the first gate G1, the second gate G2, the first cap layer C1, and the second cap layer C2 is the same as the configuration of the insulating substrate 10, the channel layer 20, the barrier layer 30, the first gate G1, the second gate G2, the first cap layer C1, and the second cap layer C2 shown in fig. 1A and 1B, and will not be repeated here.

The first source S1, the first drain D1, the second source S2, and the second drain D2 may be located on the upper surface of the barrier layer 30, or extend into the barrier layer 30, or contact the surface of the channel layer 20 through the barrier layer 30.

The trench TR1 is disposed at the boundary of the first region and the second region, and extends from the barrier layer 30 to the buffer layer 40. Specifically, the trench TR1 is located at a boundary between the first transistor T1 and the second transistor T2, extends from the surface of the barrier layer 30 in the direction of the insulating substrate 10, and stops on the surface of the insulating substrate 10. Further, the trench TR1 is located between the first drain D1 and the second source S2. The insulating layer 60 is disposed in the trench TR1. Specifically, the insulating layer 60 covers the side surfaces of the channel layer 20, the side surfaces of the barrier layer 30, the side surfaces of the buffer layer, and the surface of the insulating substrate 10, and fills the entire trench TR1. The first transistor T1 and the second transistor T2 are electrically isolated from each other by the arrangement of the trench TR1 having the insulating layer 60. The material of the insulating layer 60 may include silicon oxide (SiOx), silicon oxynitride (SiON), silicon oxycarbide (SiOC), aluminum oxide (AlOx), hafnium oxide (HfO 2), silicon nitride (SiNx), silicon carbonitride boride (SiCBN), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), yttrium oxide (Y2O 3), yttrium titanium pentoxide (Y2 TiO 5), ytterbium trioxide (Yb 2O 3), zirconium dioxide (ZrO 2), titanium dioxide (TiO 2), tantalum pentoxide (Ta 2O 5), or combinations thereof. The materials of the insulating layer 60 are only exemplified, and are not intended to limit the present application.

The dielectric layer 50 is disposed between the first cap layer C1 and the first source electrode S1, and between the first cap layer C1 and the first drain electrode D1, so that the first source electrode S1, the first drain electrode D1, and the first gate electrode G1 are electrically isolated from each other. The dielectric layer 50 is disposed between the second cap layer C2 and the second source electrode S2, and between the second cap layer C2 and the second drain electrode D2, so that the second source electrode S2, the second drain electrode D2, and the second gate electrode G2 are electrically isolated from each other. The dielectric layer 50 is disposed between the second source electrode S2 and the first drain electrode D1, so that the second source electrode S2 and the first drain electrode D1 are electrically isolated from each other, and the dielectric layer 50 contacts the insulating layer 60. The material of dielectric layer 50 is the same as that of insulating layer 60 and will not be repeated here.

The connection electrode CE1 connects the first drain electrode D1 and the second source electrode S2. Specifically, the connection electrode CE1 is disposed on the dielectric layer 50, one end of the connection electrode CE1 is connected to the first drain D1, and the other end of the connection electrode CE1 is connected to the second source S2.

In the semiconductor device of the present embodiment, the high-side transistor and the low-side transistor are electrically isolated by the trench TR1 having the insulating layer 60 and the dielectric layer 50, and the source, the drain and the gate of the high-side transistor are electrically isolated from each other and the source, the drain and the gate of the low-side transistor are electrically isolated from each other, so that the high-side transistor and the low-side transistor do not interfere with each other.

Referring to fig. 3, a schematic diagram of a semiconductor device according to another embodiment of the present application is shown. As shown in fig. 3, the semiconductor device includes an insulating substrate 10, a channel layer 20, a barrier layer 30, a buffer layer 40, first gates G11 and G12, a first source S1, first drains D11 and D12, second gates G21 and G22, second sources S21 and S22, a second drain D2, first cap layers C11 and C12, second cap layers C21 and C22, a dielectric layer 50, an insulating layer 60, a conductive structure CS1, and a trench TR1, wherein the configuration of the insulating substrate 10, the channel layer 20, the barrier layer 30, the buffer layer 40, the first source S1, the second drain D2, the dielectric layer 50, the insulating layer 60, and the trench TR1 is the same as that of fig. 2, and a description thereof will not be repeated.

As shown in fig. 3, the first drains D11 and D12 are located at opposite sides of the first source S1, and the first gates G11 and G12 and the first source S1 are located between the first drains D11 and D12. For example, the first drain D11 and the first gate G11 are located at the right side of the first source S1, and the first drain D12 and the first gate G12 are located at the left side of the first source S1. The first gate G11 is disposed between the first drain D11 and the first source S1, and the first cap layer C11 is disposed between the first gate G11 and the barrier layer 30 of the first region; in other words, the first drain electrode D11 and the first source electrode S1 are located at opposite sides of the first cap layer C11. The first gate G12 is disposed between the first drain D12 and the first source S1, and the first cap layer C12 is disposed between the first gate G12 and the barrier layer 30 of the first region; in other words, the first drain D12 and the first source S1 are located at opposite sides of the first gate G12.

In one embodiment, the contact between the first gate G11 and the first cap layer C11 and the contact between the first gate G12 and the first cap layer C12 are ohmic contacts. In another embodiment, the contact between the first gate G11 and the first cap layer C11 and the contact between the first gate G12 and the first cap layer C12 are schottky contacts.

The first drain D11, the first gate G11, the first cap layer C11, and the first source S1 form one first transistor, and the first drain D12, the first gate G12, the first cap layer C12, and the first source S1 form another first transistor, and the two first transistors are arranged in parallel and share the first source S1, the channel layer 20, the barrier layer 30, and the buffer layer 40.

The second sources S21 and S22 are located at opposite sides of the second drain D2, and the second gates G21 and G22 and the second drain D2 are located between the second sources S21 and S22. For example, the second source S21 and the second gate G21 are located at the right side of the second drain D2, and the second source S22 and the second gate G22 are located at the left side of the second drain D2. The second gate G21 is disposed between the second source S21 and the second drain D2, and the second cap layer C21 is disposed between the second gate G21 and the barrier layer 30 of the second region; in other words, the second source electrode S21 and the second drain electrode D2 are located at opposite sides of the second cap layer C21. The second gate G22 is disposed between the second source S22 and the second drain D2, and the second cap layer C22 is disposed between the second gate G22 and the barrier layer 30 of the second region; in other words, the second source electrode S22 and the second drain electrode D2 are located at opposite sides of the second cap layer C22.

In one embodiment, the contact between the second gate G21 and the second cap layer C21 and the contact between the second gate G22 and the second cap layer C22 are ohmic contacts. In another embodiment, the contact between the second gate G21 and the second cap layer C21 and the contact between the second gate G22 and the second cap layer C22 are schottky contacts.

The second drain D2, the second gate G21, the second cap layer C21, and the second source S21 form one second transistor, and the second drain D2, the second gate G22, the second cap layer C22, and the second source S22 form another second transistor, and the two second transistors share the second drain D2, the channel layer 20, the barrier layer 30, and the buffer layer 40.

The conductive structure CS1 connects the first drain D11 of the adjacent first transistor and the second source S22 of the second transistor and serves as an output terminal of the semiconductor device. Specifically, the conductive structure CS1 is disposed on the dielectric layer 50, and a projection of the conductive structure CS1 on the insulating substrate 10 overlaps a projection of the insulating layer 60 on the insulating substrate 10, where one end of the conductive structure CS1 is connected to the first drain D11 of the first transistor, and the other end of the conductive structure CS1 is connected to the second source S22 of the second transistor.

The configuration of the two first drains, the two first gates, the two first caps, the two second sources, the two second gates, and the two second caps further illustrates that the high-side transistor is two interconnected GaN transistors and the low-side transistor is two interconnected GaN transistors. Of course, the high-side transistor may be N interconnected GaN transistors and the low-side transistor may be N interconnected GaN transistors, where the high-side transistor includes N GaN first transistors arranged in parallel in sequence, and shares the barrier layer and the buffer layer, and each two adjacent first transistors share a source or a drain; the low-side transistor comprises N GaN second transistors which are sequentially arranged in parallel, the barrier layer and the buffer layer are shared, the source electrode or the drain electrode of each two adjacent second transistors are shared, and N is more than or equal to 2 and is not limited to the range stated in the application.

Please refer to fig. 4, which is a current and voltage waveform diagram of a high-side transistor and a low-side transistor with a silicon substrate. As shown in fig. 4, the high-side transistor and the low-side transistor are GaN transistors, and the substrates of the high-side transistor and the low-side transistor are silicon substrates. The circuit configuration of the high-side transistor and the low-side transistor is shown in fig. 1B, the high-side transistor can be regarded as a second transistor T2, the low-side transistor can be regarded as a first transistor T1, a constant current source id=0.12a is connected between the output terminal and the source of the low-side transistor, and the silicon substrate is connected to the source of T1. When the low-side transistor is in an off state and the high-side transistor is in an on state, the channel of the high-side transistor cannot be completely turned on due to the liner bias effect of the silicon substrate, and a voltage drop of 1.6V exists between the input voltage Vin and the output voltage Vout.

Please refer to fig. 5, which is a voltage waveform diagram and a current and voltage waveform diagram of the semiconductor device of the present application. As shown in fig. 5, and in conjunction with fig. 1A and 1B, a constant current source id=0.12a is connected between the first drain D1 and the first source S1. When the first transistor T1 is in the off state and the second transistor T2 is in the on state, the channel of the second transistor T2 is fully turned on due to the effective suppression of the liner bias effect by the insulating substrate 10, and there is only a voltage drop of 0.8V between the input voltage Vin and the output voltage Vout.

In summary, in the semiconductor device of the present application, crosstalk between the first transistor and the second transistor is suppressed based on the configuration of the insulating substrate, so that the first transistor and the second transistor are not affected by the substrate bias effect, and short-circuiting of the first source and the substrate and short-circuiting of the second source and the substrate are not required.

Claims (14)

1. A semiconductor device, comprising:

an insulating substrate including a first region and a second region;

a channel layer disposed on the insulating substrate;

a barrier layer disposed on the channel layer;

a first gate electrode disposed on the first region and on the barrier layer;

the first source electrode is arranged on the barrier layer of the first region and is positioned on one side of the first grid electrode;

the first drain electrode is arranged on the barrier layer of the first region and is positioned on the other side of the first grid electrode;

a second gate electrode disposed on the second region and on the barrier layer;

the second source electrode is arranged on the barrier layer of the second region and is positioned on one side of the second grid electrode; and

the second drain electrode is arranged on the barrier layer of the second region and is positioned on the other side of the second grid electrode;

the channel layer, the barrier layer, the first gate, the first source and the first drain form a first transistor, the channel layer, the barrier layer, the second gate, the second source and the second drain form a second transistor, and a lattice of the insulating substrate is close to a lattice of the channel layer.

2. The semiconductor device according to claim 1, wherein a crystal structure of the insulating substrate and a crystal structure of the channel layer are both hexagonal structures.

3. The semiconductor device according to claim 1, wherein a lattice mismatch between the insulating substrate and the channel layer is small.

4. The semiconductor device according to claim 1, wherein the insulating substrate is sapphire or high-resistance silicon carbide or aluminum nitride or zinc oxide.

5. The semiconductor device of claim 1, further comprising a first cap layer disposed between the first gate and the barrier layer of the first region and a second cap layer disposed between the second gate and the barrier layer of the second region.

6. The semiconductor device according to claim 1, further comprising a buffer layer disposed between the insulating substrate and the channel layer.

7. The semiconductor device according to claim 6, further comprising a trench disposed between the first region and the second region and extending from the barrier layer to the buffer layer, and an insulating layer disposed in the trench.

8. The semiconductor device according to claim 7, wherein the trench is located between the first drain and the second source.

9. The semiconductor device of claim 1, further comprising a dielectric layer disposed between the first cap layer and the first source, between the first cap layer and the first drain, between the second cap layer and the second source, between the second cap layer and the second drain, and between the second source and the first drain.

10. The semiconductor device according to claim 1, wherein the first source, the first drain, the second source, and the second drain extend to the channel layer.

11. The semiconductor device according to claim 1, further comprising a connection electrode, wherein the first drain is adjacent to the second source, wherein the connection electrode is connected to the first drain and the second source, wherein the first source is connected to a ground potential, and wherein the second drain is connected to an input voltage.

12. The semiconductor device according to claim 6, wherein the number of the first transistors is N, the N first transistors are arranged in parallel in order and share the barrier layer and the buffer layer, the first source or the first drain of each adjacent two of the first transistors is shared, N is 2 or more, the two first drains of each adjacent two of the first transistors are located on opposite sides of the corresponding first source, and each of the N first gates is located between the corresponding first drain and the first source.

13. The semiconductor device according to claim 12, wherein the number of the second transistors is N, the N second transistors are arranged in parallel in order and share the barrier layer and the buffer layer, the second drain or the second source of each adjacent two of the second transistors is shared, N is 2 or more, the two second sources of each adjacent two of the second transistors are located on opposite sides of the corresponding second drain, and each of the N second gates is located between the corresponding second drain and second source.

14. The semiconductor device of claim 13, further comprising a conductive structure to connect the first drain of the first transistor and the second source of the second transistor adjacent to each other and to serve as an output of the semiconductor device.