CN117727713A - Packaged chip, packaged chip preparation method and power device - Google Patents
Packaged chip, packaged chip preparation method and power device Download PDFInfo
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- CN117727713A CN117727713A CN202311749330.6A CN202311749330A CN117727713A CN 117727713 A CN117727713 A CN 117727713A CN 202311749330 A CN202311749330 A CN 202311749330A CN 117727713 A CN117727713 A CN 117727713A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 91
- 239000002184 metal Substances 0.000 claims abstract description 90
- 238000004806 packaging method and process Methods 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 claims description 168
- 239000012044 organic layer Substances 0.000 claims description 25
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 239000007769 metal material Substances 0.000 claims description 14
- 238000005538 encapsulation Methods 0.000 claims description 13
- 239000003292 glue Substances 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 230000017525 heat dissipation Effects 0.000 abstract description 11
- 230000000694 effects Effects 0.000 abstract description 10
- 238000000034 method Methods 0.000 description 29
- 230000008569 process Effects 0.000 description 12
- 239000012790 adhesive layer Substances 0.000 description 11
- 229910000679 solder Inorganic materials 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000009471 action Effects 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
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- 229910010272 inorganic material Inorganic materials 0.000 description 3
- 239000011147 inorganic material Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910001316 Ag alloy Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 description 2
- WMGRVUWRBBPOSZ-UHFFFAOYSA-N [Cu].[Ni].[Ag].[Sn] Chemical compound [Cu].[Ni].[Ag].[Sn] WMGRVUWRBBPOSZ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
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- 229920006336 epoxy molding compound Polymers 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
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Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The application discloses a packaged chip, a packaged chip preparation method and a power device, wherein the packaged chip comprises: the chip comprises a first surface, a second surface and a side surface connecting the first surface and the second surface; the metal layer is at least arranged on one side of the first surface or the side surface of the chip; and the packaging layer is at least arranged on one side of the second surface of the chip. According to the embodiment of the invention, the heat dissipation effect of the chip is improved by arranging the metal layer, and the heat of the chip is rapidly conducted out by utilizing the good heat conduction property of the metal layer, so that the reliability of the chip is ensured.
Description
Technical Field
The application belongs to the technical field of packaging, and particularly relates to a packaged chip, a packaged chip preparation method and a power device.
Background
The chip package is a back-end processing technology of a semiconductor chip, and provides physical protection, signal interconnection, heat dissipation, fixation and other functions for a chip core structure. Advanced packaging technology is becoming increasingly important for chip applications, especially as semiconductors enter post-molar generations.
Disclosure of Invention
The embodiment of the application provides a packaged chip, a packaged chip preparation method and a power device, wherein a metal layer is arranged to improve the heat dissipation effect of the chip and ensure the reliability of the chip.
In one aspect, an embodiment of the present application provides a packaged chip, including: a chip comprising opposing first and second surfaces and a side connecting the first and second surfaces; the metal layer is arranged on at least one side of the first surface and one side surface of the chip; and the packaging layer is at least arranged on one side of the second surface of the chip.
According to one aspect of the application, the metal layer includes a first portion, the first portion being provided on the first surface side of the chip; preferably, the packaged chip further includes a signal line disposed on the second surface side of the chip, and the signal line is electrically connected to the chip; preferably, the packaged chip further comprises a dielectric layer arranged on one side of the second surface of the chip, wherein the dielectric layer is provided with a via hole for the signal wire to pass through; preferably, the thermal conductivity of the metal layer is greater than or equal to 100W/(m·k).
According to one aspect of the application, the metal layer includes a second portion, the second portion being provided on the side of the side face of the chip; preferably, the thickness of the second portion is greater than or equal to the thickness of the chip in a direction perpendicular to the first surface.
According to one aspect of the application, the die further comprises a glue layer, wherein the glue layer is arranged between the metal layer and the chip so as to bond the metal layer and the chip.
According to one aspect of the application, the chip further comprises an organic layer, wherein the organic layer is arranged on one side of the side face of the chip; the thickness of the organic layer is greater than or equal to the side of the chip in a direction perpendicular to the first surface.
According to one aspect of the application, the packaging structure further comprises an organic layer, wherein the organic layer is arranged on one side of the side face of the chip, and the organic layer is arranged on the surface of one side, facing the packaging layer, of the second part.
The invention also provides a preparation method of the packaged chip, which comprises the following steps: forming a metal layer and a chip, wherein the chip comprises a first surface and a second surface which are opposite to each other and a side surface connecting the first surface and the second surface, and the metal layer is formed on at least one side of one of the first surface and the side surface of the chip; and forming an encapsulation layer at least on one side of the second surface of the chip.
According to another aspect of the present application, in the step of forming the metal layer and the chip, the method includes: providing a bearing layer; forming a first metal material layer and a second metal material layer on one side of the bearing layer; patterning the second metal material layer to form second parts, wherein grooves are formed between the second parts; and coating a glue layer in the groove, fixing the chip in the groove through the glue layer, wherein the first metal material layer forms a first part arranged on one side of the first surface of the chip, and the first part and the second part form the metal layer.
According to another aspect of the present application, further comprising: forming an opening in the encapsulation layer; forming a weld within the aperture; and removing the bearing layer.
The invention also provides a power device, which comprises the packaged chip in any embodiment.
Compared with the prior art, the packaged chip provided by the embodiment of the invention comprises the chip, the metal layer and the packaging layer, wherein the metal layer is at least arranged on one side of the first surface and one side of the chip so as to rapidly lead out the heat of the chip by utilizing the good heat conduction property of the metal layer, for example, the metal layer can be arranged on one side of the first surface of the chip only, can be directly arranged on the first surface of the chip, namely, the metal layer covers the first surface of the chip, can also be indirectly arranged on the first surface of the chip, and can be further provided with other adhesive layers between the chip and the metal layer, as long as the heat conduction between the metal layer and the chip is ensured, namely, the chip can dissipate the heat by utilizing the metal layer.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a diagram of a film structure of a packaged chip according to an embodiment of the present invention;
FIG. 2 is a top view of a metal layer according to an embodiment of the present invention;
FIG. 3 is a diagram of a film structure of another packaged chip according to an embodiment of the present invention;
FIG. 4 is a diagram of a film structure of another packaged chip according to an embodiment of the present invention;
FIG. 5 is a flow chart of a method for manufacturing a packaged chip according to an embodiment of the present invention;
FIG. 6 is a schematic cross-sectional view of the structure obtained in step S110 in a method for manufacturing a packaged chip according to an embodiment of the present invention;
FIG. 7 is a schematic cross-sectional view of the structure obtained in step S110 in a method for manufacturing a packaged chip according to another embodiment of the present invention;
FIG. 8 is a schematic cross-sectional view of the structure obtained in step S120 in a method for manufacturing a packaged chip according to an embodiment of the present invention;
FIG. 9 is a schematic cross-sectional view of a structure obtained in a method of manufacturing a packaged chip according to an embodiment of the present invention;
FIG. 10 is a schematic cross-sectional view of a structure obtained in a method of manufacturing a packaged chip according to another embodiment of the present invention;
FIG. 11 is a schematic cross-sectional view of a structure obtained in a method for manufacturing a packaged chip according to still another embodiment of the present invention;
FIG. 12 is a schematic cross-sectional view of a structure obtained in a method for manufacturing a packaged chip according to still another embodiment of the present invention;
FIG. 13 is a schematic cross-sectional view of a structure obtained in a method for manufacturing a packaged chip according to still another embodiment of the present invention;
fig. 14 is a schematic cross-sectional view of a structure obtained in a method for manufacturing a packaged chip according to still another embodiment of the present invention.
In the accompanying drawings:
1-chip; 2-a metal layer; 21-a first part; 22-a second part; 3-signal lines; 4-packaging layer; 5-an adhesive layer; 6-a dielectric layer; 61-a first dielectric layer; 62-a second dielectric layer; 7-welding part; 8-an organic layer; 9-a carrier layer; f1-a first surface; f2-a second surface; c-side; k-grooves.
Detailed Description
Features and exemplary embodiments of various aspects of the present application are described in detail below to make the objects, technical solutions and advantages of the present application more apparent, and to further describe the present application in conjunction with the accompanying drawings and the detailed embodiments. It should be understood that the specific embodiments described herein are merely configured to explain the present application and are not configured to limit the present application. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by showing examples of the present application.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
It will be understood that when a layer, an area, or a structure is described as being "on" or "over" another layer, another area, it can be referred to as being directly on the other layer, another area, or another layer or area can be included between the layer and the other layer, another area. And if the component is turned over, that layer, one region, will be "under" or "beneath" the other layer, another region.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Accordingly, this application is intended to cover such modifications and variations of this application as fall within the scope of the appended claims (the claims) and their equivalents. The embodiments provided in the examples of the present application may be combined with each other without contradiction.
In the prior art, the existing hard plastic package body is formed by using epoxy resin in a hot-press mode, so that the packaging of the chip is realized, but the epoxy resin is small in heat conduction coefficient, is not suitable for packaging the chip with high power and fast heat dissipation, and cannot meet the heat dissipation requirement of the chip.
In order to solve the above problems, according to the packaged chip provided by the embodiment of the application, the metal layer is arranged on one side of at least the first surface and the side surface of the chip, so that the heat of the chip is rapidly led out by utilizing the good heat conduction property of the metal layer, the heat dissipation effect of the chip is improved, and the reliability of the chip is ensured.
Embodiments of the present application provide a packaged chip, a method for manufacturing the packaged chip, and a power device, and embodiments of the packaged chip and the method for manufacturing the packaged chip will be described below with reference to fig. 1 to 14.
Referring to fig. 1 to 2, a packaged chip provided in an embodiment of the present application includes: a chip 1, the chip 1 including opposite first and second surfaces F1 and F2, and a side surface C connecting the first and second surfaces F1 and F2; a metal layer 2 provided on at least one side of the first surface F1 and the side surface C of the chip 1, the metal layer 2 having heat conduction with the chip 1; a signal line 3 provided on the second surface F2 side of the chip 1, the signal line 3 being electrically connected to the chip 1; the packaging layer 4 is at least arranged on one side of the signal wire 3 away from the chip 1.
The packaged chip provided by the embodiment of the invention comprises a chip 1, a metal layer 2, a signal wire 3 and a packaging layer 4, wherein the metal layer 2 is at least arranged on one side of a first surface F1 and a side surface C of the chip 1, so that heat of the chip 1 can be rapidly led out by utilizing good heat conduction performance of the metal layer 2, for example, the metal layer 2 can be arranged on one side of the first surface F1 of the chip 1, can be directly arranged on the first surface F1 of the chip 1, namely, the metal layer 2 covers the first surface F1 of the chip 1, can also be indirectly arranged on the first surface F1 of the chip 1, and can be provided with other adhesive layers between the chip 1 and the metal layer 2, as long as heat conduction between the metal layer 2 and the chip 1 is ensured, namely, the chip 1 can dissipate heat by utilizing the metal layer 2.
In the present embodiment, the specific material and type of the chip 1 are not particularly limited, and the chip 1 may specifically be a semiconductor chip 1, for example, an LED (Light Emitting Diode ) chip 1 or the like, and in the present embodiment, the package layer 4 is provided to protect, fix, or the like the signal line 3 and the chip 1. It can be understood that the heat generated by the high-power chip 1 is also high, and the high-power chip 1 can be applied in this embodiment to improve the heat dissipation effect of the high-power chip 1 and improve the working stability of the high-power chip 1.
Alternatively, the encapsulation layer 4 may be made of an organic material or an inorganic material, and for example, the encapsulation layer 4 may be made of PI (Polyimide), silicon oxide, silicon nitride, silicon oxynitride, or the like, without particular limitation.
Optionally, a solder portion 7 connected to the signal line 3 may be further provided, in this embodiment, an opening may be formed in the package layer 4 by photolithography, development, or etching, and the solder portion 7 may be made in the opening area, where the solder portion 7 may be solder such as tin, tin-silver alloy, tin-silver-copper-nickel alloy, or the like. The process for producing the welded portion 7 may be, but not limited to, electroplating, printing, ball mounting, and the like.
In this embodiment, the signal line 3 may include a plurality of segments of wires located in different layers, and the segments of wires are connected by vias, so as to improve the connectable range of the signal line 3, and facilitate connection between the signal line 3 and external components.
Optionally, the packaged chip further includes a dielectric layer 6 disposed on the second surface F2 side of the chip 1, where the dielectric layer 6 is provided with a via hole for passing the signal line 3. The dielectric layer 6 plays an insulating role, and the dielectric layer 6 may be a photosensitive polyimide paste formed by a photolithography process, or may be an inorganic material such as silicon oxide, silicon nitride, silicon oxynitride, or the like formed by a deposition process, and is not particularly limited.
Alternatively, the metal layer 2 is made of metal, specifically, a metal simple substance or an alloy may be used, and is not particularly limited. For example, the metal elements such as copper, nickel, gold, silver, aluminum, or the like, or alloys thereof may be used. Metals have excellent electrical and thermal conductivity properties, with thermal conductivity being particularly pronounced. In this embodiment, in order to ensure the heat conductive property of the metal layer 2, the heat conductive coefficient of the material used for the metal layer 2 may be limited. For example, the thermal conductivity of the metal layer 2 is 100W/(mK) or more. Copper has a thermal conductivity of 401W/(m·k), aluminum has a thermal conductivity of 237W/(m·k), silver has a thermal conductivity of 429W/(m·k), nickel has a thermal conductivity of 90W/(m·k), and nickel has a thermal conductivity of less than 100W/(m·k), but the thermal conductivity of the metal layer 2 can be satisfied, that is, the specific material of the metal layer 2 can be selected according to the actual situation and is not particularly limited.
Referring to fig. 1, 3 and 4, in some alternative embodiments, the metal layer 2 includes a first portion 21, and the first portion 21 is disposed on the first surface F1 side of the chip 1.
In this embodiment, the metal layer 2 is directly disposed on the first surface F1 side of the chip 1 as a carrier structure of the chip 1, that is, the first portion 21 is in contact with the first surface F1 of the chip 1, or the first portion 21 may be in indirect contact with the chip 1.
For example, the packaged chip further includes a glue layer 5, and the glue layer 5 is disposed between the metal layer 2 and the chip 1 to bond the metal layer 2 and the chip 1. Since the metal layer 2 is usually not sticky, the adhesive layer 5 is disposed between the metal layer 2 and the chip 1 in this embodiment, so as to achieve adhesion fixation between the metal layer 2 and the chip 1, and meanwhile, the adhesive layer 5 can also be used for conducting heat between the metal layer 2 and the chip 1, so as to ensure a heat conduction effect between the metal layer 2 and the chip 1.
Referring to fig. 1, 3 and 4, in some alternative embodiments, the metal layer 2 includes a second portion 22, and the second portion 22 is disposed on the side C of the chip 1.
In this embodiment, the second portion 22 may be disposed completely around the side face C of the chip 1, for example, when the cross section of the chip 1 is rectangular, that is, when the chip 1 has four side faces C, the metal layers 2 may be disposed corresponding to all four side faces C of the chip 1, so that the chip 1 may dissipate heat from four directions of the side faces C at the same time, so as to improve the heat dissipation effect. Of course, the second portion 22 may be provided around only a part of the side face C of the chip 1 according to actual needs, and is not particularly limited.
It should be noted that the first portion 21 and the second portion 22 of the metal layer 2 may be disposed at the same time to improve the heat dissipation effect, or only one of the first portion 21 and the second portion 22 may be disposed to reduce the process difficulty and facilitate the preparation.
When the first portion 21 and the second portion 22 are simultaneously arranged, a whole layer of the first portion 21 can be formed first, then the patterned second portion 22 is formed, the second portion 22 is provided with the groove K, the adhesive layer 5 can be directly coated in the groove K, namely, the side face C of the second portion 22 corresponding to the groove K and the bottom face of the first portion 21 corresponding to the groove K can be coated with the adhesive layer 5, then the chip 1 is directly fixed in the groove K, and the fixing effect of the chip 1 is further improved and the reliability of the chip 1 is improved by utilizing the adhesive layer 5 and the groove K.
Alternatively, the thickness of the second portion 22 is greater than or equal to the thickness of the chip 1 in a direction perpendicular to the first surface F1, and the second portion 22 may be disposed corresponding to the entire side surface C of the chip 1, so as to ensure that heat at each position of the side surface C of the chip 1 can be conducted out through the second portion 22. It can also be understood that the orthographic projection of the second portion 22 on the chip 1 covers the side C of the chip 1 in the direction parallel to the first surface F1, i.e. the orthographic projection of the second portion 22 on the chip 1 covers the side C of the chip 1, so as to ensure that the second portion 22 effectively improves the heat dissipation effect of the chip 1, and on the other hand, the second portion 22 can also have a better fixing effect on the chip 1.
Referring to fig. 3, in some alternative embodiments, the packaged chip further includes an organic layer 8, the organic layer 8 is disposed on the side C of the chip 1, and the organic layer 8 is disposed on a surface of the second portion 22 facing the packaging layer 4.
In this embodiment, the metal layer 2 and the organic layer 8 are disposed at the same time, and the organic layer 8 is disposed on a side surface of the second portion 22 facing the encapsulation layer 4, that is, the organic layer 8 is used to replace a part of the metal layer 2 to perform the functions of heat conduction and heat dissipation.
Optionally, the organic layer 8 may be made of EMC (Epoxy Molding Compound, epoxy) material, and although the thermal conductivity of the organic layer 8 is weaker than that of the metal layer 2, the difficulty in patterning the organic layer 8 is smaller than that of the metal layer 2, so that the groove K is more conveniently formed, the process difficulty can be effectively reduced, and the cost of the organic layer 8 is low.
Referring to fig. 4, in other alternative embodiments, the packaged chip further includes an organic layer 8, where the organic layer 8 is disposed on a side C of the chip 1; the thickness of the organic layer 8 is greater than or equal to the side face C of the chip 1 in the direction perpendicular to the first surface F1.
It should be noted that, in this embodiment, the first portion 21 of the metal layer 2 and the organic layer 8 are disposed at the same time, and the second portion 22 of the metal layer 2 is not disposed, that is, the side C of the chip 1 dissipates heat by disposing the organic layer 8, so that the second portion 22 of the metal layer 2 is not required to be prepared, so as to further reduce the process difficulty and facilitate the preparation.
Referring to fig. 5, the embodiment of the invention further provides a method for preparing a packaged chip, which includes the following steps:
s110: forming a metal layer 2 and a chip 1, wherein the chip 1 comprises a first surface F1 and a second surface F2 which are opposite to each other and a side surface C connecting the first surface F1 and the second surface F2, the metal layer 2 is formed at least on one side of one of the first surface F1 and the side surface C of the chip 1, and the metal layer 2 and the chip 1 have heat conduction, as shown in fig. 6 to 7;
s120: an encapsulation layer 4 is formed at least on the second surface F2 side of the chip 1, as shown in fig. 8.
According to the preparation method of the packaged chip provided by the embodiment of the invention, the metal layer 2 is formed on at least one side of the first surface F1 and the side surface C of the chip 1, so that the heat of the chip 1 can be rapidly conducted out by utilizing the good heat conduction property of the metal layer 2, for example, the metal layer 2 can be only arranged on one side of the first surface F1 of the chip 1, can be directly arranged on the first surface F1 of the chip 1, namely, the metal layer 2 covers the first surface F1 of the chip 1, can be indirectly arranged on the first surface F1 of the chip 1, and can be further provided with other adhesive layers between the chip 1 and the metal layer 2, as long as the heat conduction between the metal layer 2 and the chip 1 is ensured, namely, the chip 1 can dissipate heat by utilizing the chip 1.
In step S110, the preparation order of the metal layer 2 and the chip 1 is not particularly limited, and may be specifically determined according to the arrangement position of the metal layer 2 with respect to the chip 1 and the preparation process, for example, when the metal layer 2 includes the first portion 21 and the second portion 22, the following preparation order may be adopted.
Referring to fig. 6 to 7, in the step of forming the metal layer 2 and the chip 1, it includes: providing a carrier layer 9; forming a first metal material layer and a second metal material layer on one side of the bearing layer 9; patterning the second metal material layer to form second portions 22, wherein grooves K are formed between the second portions 22; the adhesive layer 5 is coated in the groove K, and the chip 1 is fixed in the groove K through the adhesive layer 5, the first metal material layer forms a first portion 21 arranged on one side of the first surface F1 of the chip 1, and the first portion 21 and the second portion 22 form the metal layer 2.
In this embodiment, the first metal material layer may be first prepared as the first portion 21 of the metal layer 2, then the second metal material layer is formed, and patterning treatment is performed, and specifically, etching or other processes may be used to form the groove K.
In step S120, the encapsulation layer 4 may be made of an organic material or an inorganic material, and for example, the encapsulation layer 4 may be made of PI (Polyimide), silicon oxide, silicon nitride, silicon oxynitride, or the like.
Optionally, referring to fig. 9, between step S110 and step S120, a signal line 3 is formed on the second surface F2 side of the chip 1, and the signal line 3 is electrically connected to the chip 1. Referring to fig. 10 to 12, a dielectric layer 6 may be formed on the second surface F2 side of the chip 1, and a via hole may be formed, as shown in fig. 10, then a portion of the signal line 3 may be formed in the via hole and = the first dielectric layer 61 away from the chip 1, as shown in fig. 11, then a second dielectric layer 62 may be formed, as shown in fig. 12, and finally another portion of the signal line 3 may be formed. Of course, there are also more dielectric layers 6 and corresponding signal lines 3 provided according to actual needs to increase the wiring space of the signal lines 3 and the connectable range of the signal lines 3.
In some alternative embodiments, after the step of forming the encapsulation layer 4 at least on the side of the signal line 3 facing away from the chip 1, it further comprises: forming an opening in the encapsulation layer 4; forming a welded portion 7 in the opening; the carrier layer 9 is removed as shown in fig. 13.
In this embodiment, openings may be formed in the encapsulation layer 4 by photolithography, development, etching, or the like, and the solder portion 7 may be made in the opening area, and the solder portion 7 may be solder such as tin, tin-silver alloy, tin-silver-copper-nickel alloy, or the like. The process for producing the welded portion 7 may be, but not limited to, electroplating, printing, ball mounting, and the like.
The carrier layer 9 may be separated from the metal layer 2 and the chip 1 thereon by means of debonding, which may be laser, heating, chemical liquid immersion, etc.
After the carrier layer 9 is removed, the packaged chips may be further divided into individual packages according to actual needs, as shown in fig. 14, each individual package includes at least one chip 1, a signal line 3 connected to the chip 1, and a metal layer 2 corresponding to the chip 1, where the cutting mode may be laser cutting, mechanical cutting, plasma cutting, and the like, and is not limited in particular.
The embodiment of the invention also provides a power device, which comprises the packaging chip in any embodiment, and is an important semiconductor component used in a power electronic circuit and is commonly used in the fields of vehicles, solar energy and industry, such as an inverter and a rectifier.
In the foregoing, only the specific embodiments of the present application are described, and it will be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the systems, modules and units described above may refer to the corresponding processes in the foregoing method embodiments, which are not repeated herein. It should be understood that the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the present application, which are intended to be included in the scope of the present application.
It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, the present application is not limited to the order of the above-described steps, that is, the steps may be performed in the order mentioned in the embodiments, may be different from the order in the embodiments, or several steps may be performed simultaneously.
Claims (10)
1. A packaged chip, comprising:
a chip comprising opposing first and second surfaces and a side connecting the first and second surfaces;
the metal layer is arranged on at least one side of the first surface and one side surface of the chip;
and the packaging layer is at least arranged on one side of the second surface of the chip.
2. The packaged chip of claim 1, wherein said metal layer comprises a first portion, said first portion being disposed on a side of said first surface of said chip;
preferably, the packaged chip further includes a signal line disposed on the second surface side of the chip, and the signal line is electrically connected to the chip;
preferably, the packaged chip further comprises a dielectric layer arranged on one side of the second surface of the chip, and the dielectric layer is provided with a via hole;
preferably, the thermal conductivity of the metal layer is greater than or equal to 100W/(m·k).
3. The packaged chip of claim 1 or 2, wherein the metal layer comprises a second portion, the second portion being provided on the side of the chip;
preferably, the thickness of the second portion is greater than or equal to the thickness of the chip in a direction perpendicular to the first surface.
4. The packaged chip of claim 1, further comprising a glue layer disposed between said metal layer and said chip.
5. The packaged chip of claim 1, further comprising an organic layer disposed on said side of said chip;
the thickness of the organic layer is greater than or equal to the side of the chip in a direction perpendicular to the first surface.
6. The packaged chip of claim 3 further comprising an organic layer disposed on said side of said chip and disposed on a surface of said second portion facing said packaging layer.
7. The preparation method of the packaged chip is characterized by comprising the following steps of:
forming a metal layer and a chip, wherein the chip comprises a first surface and a second surface which are opposite to each other and a side surface connecting the first surface and the second surface, and the metal layer is formed on at least one side of one of the first surface and the side surface of the chip;
and forming an encapsulation layer at least on one side of the second surface of the chip.
8. The method of manufacturing a packaged chip as defined by claim 7 wherein, in the step of forming a metal layer and a chip, comprising:
providing a bearing layer;
forming a first metal material layer and a second metal material layer on one side of the bearing layer;
patterning the second metal material layer to form second parts, wherein grooves are formed between the second parts;
and coating a glue layer in the groove, fixing the chip in the groove through the glue layer, wherein the first metal material layer forms a first part arranged on one side of the first surface of the chip, and the first part and the second part form the metal layer.
9. The method of manufacturing a packaged chip of claim 8, further comprising:
forming an opening in the encapsulation layer;
forming a weld within the aperture;
and removing the bearing layer.
10. A power device comprising the packaged chip of any one of claims 1 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311749330.6A CN117727713A (en) | 2023-12-18 | 2023-12-18 | Packaged chip, packaged chip preparation method and power device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311749330.6A CN117727713A (en) | 2023-12-18 | 2023-12-18 | Packaged chip, packaged chip preparation method and power device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117727713A true CN117727713A (en) | 2024-03-19 |
Family
ID=90210287
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311749330.6A Pending CN117727713A (en) | 2023-12-18 | 2023-12-18 | Packaged chip, packaged chip preparation method and power device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117727713A (en) |
-
2023
- 2023-12-18 CN CN202311749330.6A patent/CN117727713A/en active Pending
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