CN117724453A - Fault time delay circuit and device - Google Patents
Fault time delay circuit and device Download PDFInfo
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- CN117724453A CN117724453A CN202311747389.1A CN202311747389A CN117724453A CN 117724453 A CN117724453 A CN 117724453A CN 202311747389 A CN202311747389 A CN 202311747389A CN 117724453 A CN117724453 A CN 117724453A
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Abstract
The invention discloses a fault delay circuit and a device, which relate to the field of automobiles, wherein an output switch is conducted when receiving a fault signal to enable the fault delay circuit to output a first level signal corresponding to the fault signal, meanwhile, a capacitor is charged through the conducted output switch, a delay switch is conducted when the capacitor starts to charge, when the voltage at two ends of the capacitor is charged to reach a preset voltage, a control device controls the delay switch to be turned off based on the voltage lifted at the two ends of the capacitor, and then the output switch is turned off, so that the level signal output by the fault delay circuit is turned over, the condition that the first level signal is latched and delayed to be output by the charging process of the capacitor is realized, the situation that the main controller cannot timely detect the fault signal and cannot trigger protection is avoided, meanwhile, the control pin resource of the main controller is saved, the complexity of software is reduced, the resources and the cost are saved, the fault can be timely processed, and the reliability and the safety of the whole automobile are ensured.
Description
Technical Field
The invention relates to the field of automobiles, in particular to a fault delay circuit and a fault delay device.
Background
With the continuous development of the automobile field, the requirements of users on the safety of automobiles are also higher and higher, and in the application process, when an automobile controller fails, for example, when an over-current or over-voltage fault condition occurs, the change speed of a current or voltage value is higher, so that the main controller of the automobile needs to have enough time to receive a fault signal and process the fault.
In the prior art, a protection circuit in an automobile controller can control the latch level of a fault signal through a trigger such as a D trigger, when the circuit in the automobile breaks down, the trigger in the protection circuit triggers and maintains the high level, latches the level signal, and the latched signal is enough for a main controller to detect the fault signal, so that the main controller can conveniently receive the fault signal and process the fault, and after the fault is recovered, the main controller can control the trigger to reset again, so that the transmission of the fault signal is stopped. However, in this case, the host controller needs to set a corresponding control pin to control the reset of the flip-flop, which occupies more control pin resources of the host controller, and also increases software complexity.
Disclosure of Invention
The invention aims to provide a fault delay circuit and device, which realize the latching and delay output of a first level signal by utilizing the charging process of a capacitor, avoid the situation that a main controller cannot timely detect a fault signal and cannot trigger protection, save the control pin resource of the main controller, reduce the complexity of software, save the resource and the cost, ensure that the fault can be timely processed and ensure the reliability and the safety of the whole vehicle.
In order to solve the technical problems, the invention provides a fault delay circuit which comprises an output switch, a control device, a delay switch and a capacitor, wherein the control end of the output switch is used for receiving fault signals, the first end of the delay switch is connected with the control end of the output switch, the control end is respectively connected with the first end of the output switch, the first end of the capacitor and the input end of the control device, the second end of the delay switch is connected with the output end of the control device, the first end of the output switch is used as the output end of the fault delay circuit, the second end of the output switch is connected with a power supply, and the second end of the capacitor is grounded;
the output switch is used for being conducted to charge the capacitor when the fault signal is received, and meanwhile, the output ends of the power supply and the fault delay circuit are connected to enable the fault delay circuit to output a first level signal;
the delay switch is used for being conducted when the output switch is conducted, and is turned off based on control of the control device when the voltage at two ends of the capacitor is larger than a preset voltage.
Optionally, the fault delay circuit further includes a first resistor, a first end of the first resistor is connected to the control end of the output switch, and a second end of the first resistor is connected to the second end of the output switch.
Optionally, the fault delay circuit further includes a second resistor, a first end of the second resistor is connected to the first end of the output switch, and a second end of the second resistor is connected to the control end of the delay switch.
Optionally, the fault delay circuit further includes a third resistor, a first end of the third resistor is connected to a second end of the second resistor, and a second end of the third resistor is connected to a second end of the delay switch.
Optionally, the fault delay circuit further includes a fourth resistor, a first end of the fourth resistor is connected to the first end of the output switch, and a second end of the fourth resistor is connected to the first end of the capacitor.
Optionally, the fault delay circuit further comprises a comparator, wherein a first input end of the comparator is connected with a reference voltage, a second input end of the comparator is connected with an output end of the automobile controller, and an output end of the comparator is connected with a control end of the output switch;
the comparator is used for determining the fault condition of the automobile controller based on the output voltage of the automobile controller and the reference voltage, and outputting a corresponding level signal.
Optionally, the control device is a triode, a base electrode of the triode is connected with a first end of the capacitor, an emitter electrode of the triode is connected with a second end of the delay switch, and a collector electrode of the triode is grounded.
Optionally, the fault delay circuit further includes a fifth resistor, a first end of the fifth resistor is connected with the base electrode of the triode, and a second end of the fifth resistor is connected with the emitter electrode of the triode.
In order to solve the technical problems, the invention also provides a fault delay device which comprises a master controller of an automobile and the fault delay circuit, wherein the output end of the fault delay circuit is connected with the input end of the master controller.
The invention provides a fault delay circuit which comprises an output switch, a control device, a delay switch and a capacitor, wherein the output switch is conducted when a fault signal is received, so that the fault delay circuit outputs a first level signal corresponding to the fault signal, meanwhile, the capacitor can be charged through the conducted output switch, the delay switch can be conducted at the same time when the capacitor starts to be charged, when the voltage at two ends of the capacitor reaches a certain degree, the control device controls the delay switch to be turned off based on the voltage lifted at the two ends of the capacitor after the voltage reaches a preset voltage, then the output switch is turned off, the level signal output by the fault delay circuit is turned over, the situation that the main controller cannot timely detect the fault signal and cannot trigger protection is avoided, meanwhile, the control pin resource of the main controller is saved, the complexity of software is reduced, the fault can be timely processed while the resource and the cost are saved, and the reliability and the safety of the whole vehicle are ensured.
The invention also provides a fault delay device which has the same beneficial effects as the fault delay circuit.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required in the prior art and the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a fault delay circuit according to the present invention;
FIG. 2 is a schematic diagram of another fault delay circuit according to the present invention;
fig. 3 is a schematic structural diagram of a fault delay apparatus provided by the present invention.
Detailed Description
The invention has the core of providing a fault delay circuit and device, which realize the latching and delay output of a first level signal by utilizing the charging process of a capacitor, avoid the situation that a main controller cannot timely detect the fault signal and cannot trigger protection, save the control pin resource of the main controller, reduce the complexity of software, save the resource and the cost, ensure that the fault can be timely processed and ensure the reliability and the safety of the whole vehicle.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a fault delay circuit according to the present invention; referring to fig. 2, fig. 2 is a schematic structural diagram of another fault delay circuit according to the present invention; in order to solve the technical problems, the invention provides a fault delay circuit, which comprises an output switch P1, a control device Q3, a delay switch N1 and a capacitor C, wherein the control end of the output switch P1 is used for receiving a fault signal, the first end of the delay switch N1 is connected with the control end of the output switch P1, the control end is respectively connected with the first end of the output switch P1, the first end of the capacitor C and the input end of the control device Q3, the second end is connected with the output end of the control device Q3, the first end of the output switch P1 is used as the output end of the fault delay circuit, the second end of the output switch P1 is connected with a power supply VCC, and the second end of the capacitor C is grounded;
the output switch P1 is used for being conducted to charge the capacitor C when a fault signal is received, and is connected with the power supply and the output end of the fault delay circuit to enable the fault delay circuit to output a first level signal, and is turned off when the fault signal is not received or the delay switch N1 is turned off to enable the fault delay circuit to output a second level signal, wherein the first level signal is opposite to the second level signal;
the delay switch N1 is configured to be turned on when the output switch P1 is turned on, and turned off based on the control of the control device Q3 when the voltage across the capacitor C is greater than a preset voltage.
Specifically, when the signal received by the control end of the output switch P1 is a fault signal, the output switch P1 is turned on under the control of the fault signal, the turned-on output switch P1 connects the power supply with the output end of the fault delay circuit, the fault delay circuit outputs a first level signal, the capacitor C is charged through the power supply connected with the turned-on output switch P1, meanwhile, the control end of the delay switch N1 is connected with the first end of the output switch P1, the turned-on output switch P1 is also turned on, the capacitor C is continuously charged, when the voltage of the two ends of the capacitor C is charged to exceed a preset voltage, the input end of the control device Q3 receives a high-voltage signal at the two ends of the capacitor C, the turned-off delay switch N1 is controlled to be turned off, the signal received by the control end of the output switch P1 is then turned off, the output switch P1 is controlled to be turned off, and the whole level signal of the fault delay circuit is turned over through the turned-on and turned-off of the output switch P1, and the fault delay circuit always outputs the first level signal until the capacitor C is turned over to a certain level, and the first level signal is turned-off, and the capacitor C is turned to be charged to a certain level, and the level signal is latched. On the other hand, when the signal received by the control terminal of the output switch P1 is not a fault signal, the output switch P1 and the delay switch N1 remain in the off state, the capacitor C is not charged, and the fault delay circuit always outputs the second level signal.
The specific implementation of the fault signal is not particularly limited herein, and may be implemented in the form of a level signal, or may be directly implemented in the form of a detected current or voltage signal; the specific types and implementation manners of the output switch P1, the control device Q3, the delay switch N1, the capacitor C, and the like are not particularly limited herein, the specific value of the preset voltage and the like are not particularly limited herein, and the adjustment and the setting of the delay time length of the delay output of the first level signal can be realized by adjusting the value of the preset voltage and the specific parameter of the capacitor C, so that the preset voltage can be adjusted and set according to the actual application requirements.
As a specific embodiment, as shown in fig. 2, the fault signal is implemented by using a comparator U1, the output switch P1 adopts a P-channel MOS transistor (Metal Oxide Semiconductor Field Effect Trans istor, metal oxide semiconductor type field effect transistor), the control device Q3 adopts a PNP transistor, the delay switch N1 adopts an N-channel MOS transistor, the second end of the output switch P1 is connected with the power VCC, and the second end of the capacitor C is grounded; under normal conditions without faults, the signal input in the circuit shown in fig. 2 should be a normal voltage value, the comparator U1 compares the reference voltage Vref serving as a voltage reference value with the normal voltage value of the signal input and then outputs a high level, the control terminal of the output switch P1 receives the high level, the control terminal is not conductive, and the fault delay circuit has no signal output. When the automobile controller has an instantaneous fault condition, the comparator U1 receives a fault signal, compares the voltage value of the received analog signal with the reference voltage and outputs a low level. The node 1 is at a high potential under normal conditions, when a fault condition exists, the voltage of the node 1 is pulled down by the low level output by the comparator U1, the gate voltage of the output switch P1 is pulled down, and at the moment, the gate voltage of the output switch P1 is lower than the source voltage, and the output switch P1 is turned on based on the fault signal received by the comparator U1. After the output switch P1 is conducted, the current of the power supply VCC flows through the node 4 through the conducted output switch P1, so that a high-level signal is output to the main controller of the automobile, at the moment, the main controller can start fault signal processing based on the received high-level signal, and meanwhile, the current flows through the output switch P1 and the fourth resistor R4 from the voltage VCC to charge the capacitor C; meanwhile, the control device Q3 is used as a PNP triode, the voltage of the e pole (emitter) is conducted when being higher than the voltage of the b pole (base) by a certain voltage, and the voltage vec=0.7v is usually turned on. Therefore, when the output switch P1 is turned on, current flows from the pull-up power VCC through the output switch P1, the second resistor R2, and the third resistor R3 to the emitter of the transistor Q3, resulting in a voltage rise at the emitter of the transistor, so that the transistor Q3 is turned on when the capacitor C starts to charge. In the charging process of the capacitor C, the potential of the node 1 is pulled down due to the conduction of the triode Q3, the voltage of the node 2, i.e., the e pole of the PNP triode, is clamped, and the voltage is kept higher than the voltage of the node 3, i.e., the b pole of the PNP triode, i.e., the starting voltage of the triode, so that the control device Q3 clamps the source voltage of the delay switch N1 in a state higher than the voltage of the first end of the capacitor C; and while the output switch P1 is turned on, a current flows through the second resistor R2 from the power VCC to the output switch P1, so that the gate voltage of the delay switch N1 is higher than the clamped source voltage, and at this time, the gate voltage of the delay switch N1 is higher than the source voltage, thereby being turned on; in the charging process of the capacitor C, the voltages of the e pole (emitter) and the b pole (base) of the triode Q3 are raised along with the rise of the voltages at two ends of the capacitor C, when the capacitor C is charged for a certain time, the voltages of the e pole (emitter) and the b pole (base) of the triode Q3 can raise the voltage of the source of the delay switch N1 so that the difference value between the grid voltage and the source voltage of the delay switch N1 is smaller than the starting voltage of the delay switch N1, at the moment, the delay switch N1 is disconnected, the voltage of the node 1 is not pulled down by the delay switch N1 and returns to a high level state, then the grid voltage of the output switch P1 is not lower than the source voltage, the output switch P1 is disconnected, the e pole voltage of the PNP triode Q3 is not greater than the b pole voltage, and the Q3 is cut off to form a circuit breaker; at this time, the whole fault delay circuit is completely disconnected, and the output of the high level is stopped.
It will be appreciated that there are two situations when an automobile fault occurs. The first situation is that the automobile controller will stay in a fault state for a period of time, at this time, the comparator U1 will not stop outputting a low level, the whole fault delay will not stop outputting a high level, and the main controller will always receive a fault signal. Only when the fault is no longer present, the fault delay circuit stops outputting the high level, and the circuit is reset; the second condition is that the automobile controller only has transient faults, the fault delay circuit plays a role in delay, the capacitor C can be used for adjusting delay time, the cooperation of the delay switch N1 and the control device Q3 in the circuit can realize an automatic circuit resetting process after delay, the circuit is not required to be reset by the control of the master controller, the control pin resource of the master controller is saved, and meanwhile, the complexity of software in the master controller is reduced.
It is easy to understand that the fault delay circuit provided by the application can realize the fault delay protection device when the automobile controller breaks down through the circuit structure composed of the comparator, the MOS tube, the capacitor and the like, and is mainly applied to the field of circuit control of the automobile controller. When the automobile controller breaks down and needs to trigger protection, the fault delay circuit provided by the application is utilized to enable the first level signal corresponding to the fault signal to be kept to be output, the output time of the first level signal is prolonged, the main controller is enabled to detect the first level signal for a certain number of times in a task period, accordingly, the fault is judged to realize protection, and normally, the first level signal is realized by adopting a high level signal. The whole circuit is not required to be applied to a trigger, the first level signal can be automatically latched through the design of a circuit structure and the circuit can be automatically reset, and the delay time can be set through adjusting the parameters of components and parts, so that the cost and the control resource of a controller are saved.
The fault delay circuit provides a design method of a fault delay protection device of an automobile controller, and is suitable for the situation that the automobile controller breaks down. Some parameters such as current or voltage in a normal range are required to be ensured to exceed rated values in driving, damage can be caused to elements in a circuit, safety of a driver and a passenger can be endangered when serious, and the circuit design provided by the application can keep delay of a first level signal state corresponding to a fault signal, so that the situation that the main controller cannot timely detect the fault signal and cannot trigger protection is avoided, and driving safety is ensured.
The invention provides a fault delay circuit, which comprises an output switch P1, a control device Q3, a delay switch N1 and a capacitor C, wherein the output switch P1 is conducted when a fault signal is received, so that the fault delay circuit outputs a first level signal corresponding to the fault signal, meanwhile, the capacitor C can be charged through the conducted output switch P1, the delay switch N1 can be conducted at the same time when the capacitor C is charged to a certain extent, after the voltage at two ends of the capacitor C reaches a preset voltage, the control device Q3 controls the delay switch N1 to be turned off based on the voltage lifted at the two ends of the capacitor C, and then the output switch P1 is turned off, thereby realizing the latching and delay output of the first level signal by utilizing the charging process of the capacitor C, avoiding the situation that the main controller cannot timely detect the fault signal and cannot trigger protection, saving the control pin resource of the main controller, reducing the complexity of software, simultaneously ensuring the reliability and the safety of the whole vehicle.
Based on the above embodiments:
as an alternative embodiment, the fault delay circuit further includes a first resistor R1, where a first end of the first resistor R1 is connected to the control end of the output switch P1, and a second end of the first resistor R1 is connected to the second end of the output switch P1.
It should be understood that, in order to ensure implementation of accurate on and off processes of the output switch P1, a first resistor R1 connected between the control end and the second end of the output switch P1 may be further added, where the first resistor R1 may provide a bias voltage for the output switch P1 when turned on, so as to avoid malfunction of the output switch P1, and may be used as a bleeder resistor, so as to ensure rapid release of charges after the output switch P1 is turned off, and specific types and implementation manners of the first resistor R1 are not limited herein.
Specifically, the first resistor R1 arranged between the control end and the second end of the output switch P1 can be added to ensure the accurate action of the output switch P1, so that the error of the output signal of the whole fault delay circuit caused by the misoperation of the output switch P1 is avoided, the accuracy of the signal received by the main controller is ensured, the reliability and the safety of the whole fault delay circuit are improved, the adopted device is easy to realize, the cost is low, the volume is small, and the simple and convenient realization of the whole fault delay circuit is facilitated.
As an alternative embodiment, the fault delay circuit further comprises a second resistor R2, wherein a first end of the second resistor R2 is connected to the first end of the output switch P1, and a second end is connected to the control end of the delay switch N1.
It is to be understood that after the output switch P1 is turned on, current will flow through the control end of the delay switch N1 through the turned-on output switch P1, so as to control the conduction of the delay switch N1, in order to avoid impact damage of large current or large voltage on the control end of the delay switch N1, a second resistor R2 disposed between the first end of the output switch P1 and the control end of the delay switch N1 may be added, where the first end of the second resistor R2 is further connected with the first end of the capacitor C, so as to play a role of current limiting, and further protect the circuit. The specific type and implementation of the second resistor R2 are not particularly limited herein.
Specifically, in order to further ensure the safety of the delay switch N1 and the safety of the whole fault delay circuit, the second resistor R2 arranged between the first end of the output switch P1 and the control end of the delay switch N1 can be further increased to play a role in current limiting protection, avoid the influence of large current on the whole circuit, improve the reliability and safety of the whole fault delay circuit, and adopt devices which are easy to realize, have low cost and small volume and are beneficial to the simple and convenient realization of the whole fault delay circuit.
As an alternative embodiment, the fault delay circuit further comprises a third resistor R3, wherein a first end of the third resistor R3 is connected to a second end of the second resistor R2, and the second end is connected to a second end of the delay switch N1.
It is to be understood that, in order to ensure implementation of accurate on and off processes of the delay switch N1, a third resistor R3 connected between the control end and the second end of the delay switch N1 may be further added, where the first end of the third resistor R3 is further connected to the second end of the second resistor R2, and the second end is further connected to the output end of the control device Q3, where the third resistor R3 may provide a bias voltage for the delay switch N1 when turned on, so as to avoid malfunction of the delay switch N1, and may be used as a bleeder resistor to ensure rapid release of charges after the delay switch N1 is turned off, and specific types and implementation manners of the third resistor R3 are not limited herein.
Specifically, the third resistor R3 arranged between the control end and the second end of the delay switch N1 can be added to ensure the accurate action of the delay switch N1, so that errors of output signals of the whole fault delay circuit caused by misoperation of the delay switch N1 are avoided, the accuracy of signals received by the main controller is ensured, the reliability and safety of the whole fault delay circuit are improved, the adopted device is easy to realize, the cost is low, the volume is small, and the simple and convenient realization of the whole fault delay circuit is facilitated.
As an alternative embodiment, the fault delay circuit further comprises a fourth resistor R4, wherein a first end of the fourth resistor R4 is connected to the first end of the output switch P1, and a second end is connected to the first end of the capacitor C.
It is to be understood that, after the output switch P1 is turned on, the current will also charge the capacitor C through the turned-on output switch P1, in order to further control the charging process of the capacitor C, a fourth resistor R4 disposed between the first end of the output switch P1 and the first end of the capacitor C may be added, where the first end of the fourth resistor R4 is further connected to the first end of the second resistor R2, and the fourth resistor R4 and the capacitor C form an RC circuit, which may further play a role in current limiting and protecting the circuit. The specific type and implementation of the fourth resistor R4 are not particularly limited herein. At this time, the delay time of the first level signal may be adjusted by adjusting the capacitance value of the capacitor C and the resistance value of the fourth resistor R4, where the larger the capacitance value of the capacitor C is, the larger the resistance value of the fourth resistor R4 is, the slower the charging time of the capacitor C is, and the longer the output switch P1 can be kept on, the longer the fault delay circuit can keep the output time of the first level signal.
Specifically, the charging process of the capacitor C is controlled, a fourth resistor R4 arranged between the first end of the output switch P1 and the first end of the capacitor C can be added, the delay time of the first level signal can be controlled by adjusting the capacitance value of the capacitor C and the resistance value of the fourth resistor R4, the fourth resistor R4 can also play a role in current limiting protection, the influence of heavy current on the whole circuit is avoided, the reliability and the safety of the whole fault delay circuit are improved, the adopted device is easy to realize, the cost is low, the volume is small, and the simple and convenient realization of the whole fault delay circuit is facilitated.
As an alternative embodiment, the fault delay circuit further includes a comparator U1, a first input terminal of the comparator U1 is connected to the reference voltage, a second input terminal is connected to an output terminal of the automobile controller, and an output terminal is connected to a control terminal of the output switch P1;
the comparator U1 is configured to determine a fault condition of the vehicle controller based on the output voltage of the vehicle controller and the reference voltage, and output a corresponding level signal.
It should be understood that, considering that the direct connection between the control terminal of the output switch P1 and the voltage or current signal of the vehicle controller may cause a safety problem such as a short service life of the output switch P1, and meanwhile, the direct voltage signal has poor stability and may cause a malfunction of the output switch P1, the comparator U1 is additionally provided to implement a process of receiving and judging a fault signal, the second input terminal of the comparator U1 is directly connected with the vehicle controller, and compares the received voltage signal with the reference voltage of the first input terminal, thereby judging whether an overvoltage or an overcurrent exists in the vehicle controller, and outputting a corresponding level signal to the control terminal of the output switch P1, so as to implement a process of controlling the output switch P1 by the fault signal. The specific type and implementation of the comparator U1 are not particularly limited herein, and the specific value of the reference voltage is not particularly limited herein, and may be adjusted and set according to the normal output voltage corresponding to the normal operation condition of the vehicle controller.
Specifically, the fault signal can be represented by adding the set comparator U1 to the level signal output by the comparator U1, the level signal can realize stable control of the output switch P1, the impact of a direct voltage signal on the control end of the output switch P1 is avoided, the reliability and the safety of the whole fault delay circuit are improved, the adopted device is easy to realize, the cost is low, the volume is small, and the simple and convenient realization of the whole fault delay circuit is facilitated.
As an alternative embodiment, the control device Q3 is a triode, where the base of the triode is connected to the first terminal of the capacitor C, the emitter is connected to the second terminal of the delay switch N1, and the collector is grounded.
It is to be understood that the triode working in the amplifying region can realize the control process of the delay switch N1 by utilizing the voltage change at the two ends of the capacitor C, so that the control device Q3 can be realized by adopting a triode, the triode can play a role of clamping voltage, and the voltage of the source electrode of the delay switch N1 can be clamped based on the voltage of the first end of the capacitor C, thereby realizing the process of controlling the delay switch N1.
Specifically, the delay of signal transmission is realized through the innovative circuit design, different conduction conditions and characteristics of the MOS tube and the triode are utilized, the purposes of latching the level and resetting the circuit are achieved under the condition that a trigger is not used, so that the control port resource and the cost are saved, the fault can be timely processed, and the driving safety is improved. The adopted device is easy to realize, has low cost and small volume, and is beneficial to the simple and convenient realization of the whole fault delay circuit.
As an alternative embodiment, the fault delay circuit further comprises a fifth resistor R5, wherein a first end of the fifth resistor R5 is connected to the base of the triode, and a second end of the fifth resistor R5 is connected to the emitter of the triode.
It will be appreciated that, in order to ensure implementation of accurate on and off processes of the triode, a fifth resistor R5 connected between the base and the emitter of the triode may be further added, where the fifth resistor R5 may provide a bias voltage for the triode when turned on, so as to avoid malfunction of the triode, and may be used as a bleeder resistor, to ensure rapid release of charges after the triode is turned off, and specific types and implementation modes of the fifth resistor R5 are not particularly limited herein.
Specifically, the accurate action of the triode can be ensured by adding the fifth resistor R5 arranged between the base electrode and the emitter electrode of the triode, the error of the output signal of the whole fault delay circuit caused by the misoperation of the triode is avoided, the accuracy of the signal received by the main controller is ensured, the reliability and the safety of the whole fault delay circuit are improved, the adopted device is easy to realize, the cost is low, the volume is small, and the simple and convenient realization of the whole fault delay circuit is facilitated.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a fault delay apparatus provided by the present invention. In order to solve the above technical problems, the present invention further provides a fault delay apparatus, which includes a general controller 22 of an automobile and a fault delay circuit 21 as described above, where an output end of the fault delay circuit 21 is connected to an input end of the general controller 22.
It should be understood that the vehicle controller refers to a controller in each functional module in the vehicle, such as a controller of a vehicle body control unit, a controller of a steering system, and other sub-controllers corresponding to sub-systems in the vehicle, the overall controller 22 of the vehicle refers to an overall controller of the whole vehicle, and the overall controller serves as the overall controller of the whole vehicle, and collects feedback information of the sub-controllers corresponding to the sub-systems and sends control commands to the sub-controllers, thereby realizing a control process of the whole vehicle. The specific type and implementation of the vehicle controller and the overall controller 22 of the vehicle are not particularly limited herein.
For an introduction of the fault delay apparatus provided by the present invention, reference is made to the embodiment of the fault delay circuit, and the description of the present invention is omitted herein.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
1. The fault delay circuit is characterized by comprising an output switch, a control device, a delay switch and a capacitor, wherein the control end of the output switch is used for receiving a fault signal, the first end of the delay switch is connected with the control end of the output switch, the control end is respectively connected with the first end of the output switch, the first end of the capacitor and the input end of the control device, the second end of the delay switch is connected with the output end of the control device, the first end of the output switch is used as the output end of the fault delay circuit, the second end of the output switch is connected with a power supply, and the second end of the capacitor is grounded;
the output switch is used for being conducted to charge the capacitor when the fault signal is received, and meanwhile, the output ends of the power supply and the fault delay circuit are connected to enable the fault delay circuit to output a first level signal;
the delay switch is used for being conducted when the output switch is conducted, and is turned off based on control of the control device when the voltage at two ends of the capacitor is larger than a preset voltage.
2. The fault delay circuit of claim 1, further comprising a first resistor having a first terminal coupled to the control terminal of the output switch and a second terminal coupled to the second terminal of the output switch.
3. The fault delay circuit of claim 2, further comprising a second resistor having a first terminal coupled to the first terminal of the output switch and a second terminal coupled to the control terminal of the delay switch.
4. A fault delay circuit as claimed in claim 3, further comprising a third resistor having a first terminal connected to a second terminal of the second resistor, the second terminal being connected to a second terminal of the delay switch.
5. The fault delay circuit of claim 4, further comprising a fourth resistor having a first terminal coupled to the first terminal of the output switch and a second terminal coupled to the first terminal of the capacitor.
6. The fault delay circuit of claim 1, further comprising a comparator having a first input connected to a reference voltage and a second input connected to an output of the vehicle controller, the output connected to a control terminal of the output switch;
the comparator is used for determining the fault condition of the automobile controller based on the output voltage of the automobile controller and the reference voltage, and outputting a corresponding level signal.
7. A fault delay circuit as claimed in any one of claims 1 to 6, wherein the control device is a transistor having a base connected to a first terminal of the capacitor and an emitter connected to a second terminal of the delay switch and a collector connected to ground.
8. The fault delay circuit of claim 7, further comprising a fifth resistor having a first terminal coupled to the base of the transistor and a second terminal coupled to the emitter of the transistor.
9. A fault delay apparatus comprising a general controller for a vehicle and a fault delay circuit as claimed in any one of claims 1 to 8, the output of the fault delay circuit being connected to the input of the general controller.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311747389.1A CN117724453A (en) | 2023-12-18 | 2023-12-18 | Fault time delay circuit and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311747389.1A CN117724453A (en) | 2023-12-18 | 2023-12-18 | Fault time delay circuit and device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117724453A true CN117724453A (en) | 2024-03-19 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311747389.1A Pending CN117724453A (en) | 2023-12-18 | 2023-12-18 | Fault time delay circuit and device |
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| Country | Link |
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| CN (1) | CN117724453A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118148468A (en) * | 2024-05-07 | 2024-06-07 | 徐州徐工汽车制造有限公司 | Control circuit, control method and control system of vehicle window and vehicle |
-
2023
- 2023-12-18 CN CN202311747389.1A patent/CN117724453A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118148468A (en) * | 2024-05-07 | 2024-06-07 | 徐州徐工汽车制造有限公司 | Control circuit, control method and control system of vehicle window and vehicle |
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