CN117713829A - Variable threshold single-bit ADC chip and SAR system - Google Patents

Abstract

The application belongs to the technical field of data conversion, and provides a variable threshold single-bit ADC chip and an SAR system, wherein an input channel radar echo signal is sampled and held by a front-end receiving circuit, then is input into an I channel and a Q channel at the same time, and carrier modulation is carried out respectively. Under the condition of keeping the original signal data amount unchanged, providing a sine wave threshold value of a specific frequency of 20-DEG phase difference for 18 channels of each of the I, Q two channels, then dividing I, Q two channels of signals into 18 channels of signals by a first channel single-bit ADC circuit and a second channel single-bit ADC circuit, and finally respectively sampling and processing each channel of signals to form the original signals, thereby successfully reducing the sampling rate of each channel of signals, reducing the calculation complexity, improving the efficiency of data processing, achieving the purposes of simplifying the system architecture, reducing the construction cost and improving the imaging efficiency on the premise of ensuring the imaging quality, and promoting the low cost and microminiaturization of a radar imaging system.

Description

Variable threshold single-bit ADC chip and SAR system

Technical Field

The application belongs to the technical field of data conversion, and particularly relates to a variable threshold single-bit ADC chip and an SAR system.

Background

Synthetic aperture radar (Synthetic aperture radar, SAR) employs active detection to enable high-precision long-range surveys in complex environments. The detection performance is not influenced by factors such as illumination, cloud rain, haze and the like, and along with the development of miniaturized platforms such as unmanned aerial vehicles, micro robots and the like and the mature detection mode, the detection system can be adjusted according to different scenes, and the detection system can meet more rich and changeable modern application scenes, so that the detection system can play an irreplaceable role in various fields such as urban survey, public security anti-terrorism, disaster rescue and the like.

With the development and maturity of miniaturized platforms such as unmanned aerial vehicles, micro robots and the like, the unmanned aerial vehicles and the micro robots can enable SAR systems to detect in a more flexible mode, but limited platform volume and loading capacity also put higher demands on the miniaturization of SAR systems. However, in order to realize high resolution imaging, SAR systems generally need to acquire echo signals with large bandwidth with high precision, and the huge data volume generated by the SAR systems can bring great stress to subsequent storage, transmission and processing. And along with the improvement of imaging resolution and the expansion of an observation scene, the data volume required to be processed by the SAR system still has a continuous increasing trend. In order to reduce the complexity of the system for SAR data acquisition, storage, transmission, processing and the like, the purposes of reducing the cost and the system volume are achieved. In recent years, the advantages of the single-bit sampling quantization theory in terms of simplification of system architecture and improvement of efficiency have again attracted widespread attention in the field of signal processing. The project team of the application forms a single bit quantization strategy and a rapid processing algorithm of the project team by optimizing and developing a single bit sampling algorithm, and a data converter chip which can provide a single frequency threshold value and rapidly process radar echo signals in real time is needed in the algorithm system.

Disclosure of Invention

In order to solve the technical problems, the embodiment of the application provides a variable threshold single-bit ADC chip and an SAR system, and aims to provide the variable threshold single-bit ADC chip which can reduce the calculation complexity of radar echo signals, improve the efficiency of data processing, achieve the purposes of simplifying the system architecture, reducing the construction cost and improving the imaging efficiency on the premise of ensuring the imaging quality, and promote the low cost and miniaturization of a radar imaging system.

A first aspect of the embodiments of the present application provides a variable threshold single-bit ADC chip, the variable threshold single-bit ADC chip comprising:

the first front-end receiving circuit is used for receiving the first channel radar echo signal and outputting 18 paths of first sampling signals in a time-sharing way;

the second front-end receiving circuit is used for receiving the second channel radar echo signal and outputting 18 paths of second sampling signals in a time-sharing way;

a threshold data memory for storing a first digital code sequence and a second digital code sequence;

the first DAC circuit is used for acquiring the first digital code sequence and converting the first digital code sequence into 18 paths of first analog sine wave thresholds; wherein the phase difference between adjacent first analog sine wave thresholds is 20 degrees;

The second DAC circuit is used for acquiring the second digital code sequence and converting the second digital code sequence into 18 paths of second analog sine wave thresholds; wherein the phase difference between adjacent second analog sine wave thresholds is 20 degrees;

the first channel single-bit ADC circuit is used for receiving 18 paths of first sampling signals and 18 paths of first analog sine wave thresholds and converting the corresponding first sampling signals into 18 paths of first digital codes according to the first analog sine wave thresholds;

the second channel single-bit ADC circuit is used for receiving 18 paths of second sampling signals and 18 paths of second analog sine wave thresholds and converting the corresponding second sampling signals into 18 paths of second digital codes according to the second analog sine wave thresholds;

the first multiplexer is used for converting 18 paths of the first digital codes into a first path of digital signals;

and the second multiplexer is used for converting 18 paths of the second digital codes into a second path of digital signals.

In one embodiment, the first channel single-bit ADC circuit includes 18 first single-bit ADC units, where 18 first single-bit ADC units are in one-to-one correspondence with 18 first sampling signals, and 18 first single-bit ADC units are in one-to-one correspondence with 18 first analog sine wave thresholds;

Each channel of the first single-bit ADC unit is used for receiving the corresponding first sampling signal and the first analog sine wave threshold value and generating the corresponding first digital code according to the first sampling signal and the first analog sine wave threshold value.

In one embodiment, the second channel single-bit ADC circuit includes 18 second single-bit ADC units, where 18 second single-bit ADC units are in one-to-one correspondence with 18 second sampling signals, and 18 second single-bit ADC units are in one-to-one correspondence with 18 second analog sine wave thresholds;

each path of the second single-bit ADC unit is used for receiving the corresponding second sampling signal and the second analog sine wave threshold value and generating the corresponding second digital code according to the second sampling signal and the second analog sine wave threshold value.

In one embodiment, the first digital code sequence includes at least 4 threshold frequency digital codes and at least 4 initial phase digital codes;

the second sequence of digital codes includes at least 4 threshold frequency digital codes and at least 4 initial phase digital codes.

In one embodiment, the variable threshold single bit ADC chip further comprises:

The phase-locked loop circuit is used for receiving the external crystal oscillator frequency and generating a preset clock frequency according to the crystal oscillator frequency;

and the clock distribution circuit is used for providing a sampling clock frequency for the front-end receiving circuit according to the clock frequency and providing corresponding working clock frequencies for the first DAC circuit, the second DAC circuit, the first channel single-bit ADC circuit and the second channel single-bit ADC circuit.

In one embodiment, the variable threshold single bit ADC chip further comprises:

and the error correction circuit is used for carrying out static error correction on the first DAC circuit and the second DAC circuit.

In one embodiment, the first DAC circuit includes 18 first DAC units; the error correction circuit is used for inputting a first preset digital code to the corresponding first DAC unit so as to gate a corresponding current source in the first DAC unit; the first single-bit ADC unit corresponding to the first DAC unit generates a first feedback signal according to the output signal of the first DAC unit; the error correction circuit is further used for correcting a corresponding current source in the first DAC unit according to the first feedback signal;

The second DAC circuit comprises 18 paths of second DAC units; the error correction circuit is used for inputting a second preset digital code to the corresponding second DAC unit so as to gate a corresponding current source in the second DAC unit; the second single-bit ADC unit corresponding to the second DAC unit generates a second feedback signal according to the output signal of the second DAC unit; the error correction circuit is further configured to correct a corresponding current source in the second DAC cell according to the second feedback signal.

In one embodiment, the first DAC cell and the second DAC cell are each eight-bit DAC converters; the eight-bit DAC converter includes: the device comprises an input register, a high-level thermometer decoding unit, a low-level delay chain unit, a switch driving circuit, a switch array circuit, a first output resistor, a second output resistor, a first inverter Z1, a second inverter Z2, a voltage band gap reference source, a voltage-to-current unit, a bias circuit and a current source array;

the input end of the input register is used for receiving 8-bit digital codes, the clock signal end of the input register is commonly connected with the input end of the first inverter Z1 and is used for receiving clock signals, the output end of the input register is respectively connected with a high-bit thermometer decoding unit and a low-bit delay chain unit, the high-bit thermometer decoding unit is used for performing binary weight processing on the first four-bit digital code output by the input register, the low-bit delay chain unit is used for performing thermometer code processing on the last four-bit digital code output by the input register, the output ends of the high-bit thermometer decoding unit and the low-bit delay chain unit are connected with the switch driving circuit, the output end of the first inverter Z1 is connected with the input end of the second inverter Z2, and the output end of the second inverter Z2 is connected with the switch driving circuit;

The switch driving circuit is connected with the switch array circuit, the voltage band gap reference source is connected with the input end of the voltage-to-current unit, the output end of the voltage-to-current unit is connected with the input end of the bias circuit, the output end of the bias circuit is connected with the current source array, the first end of the first output resistor is connected with the power supply end, the first end of the second output resistor is connected with the power supply end, the second end of the first output resistor and the first end of the switch array circuit are connected together to serve as a first voltage signal output end, and the second end of the second output resistor and the second end of the switch array circuit are connected together to serve as a second voltage signal output end; the voltage band gap reference source is used for generating a reference voltage signal, the voltage-to-current unit is used for converting the reference voltage signal into a reference current signal, and the bias circuit is used for converting the reference current signal into bias voltage and outputting the bias voltage to the current source array; the switch driving circuit is used for controlling the switch state of the switch array circuit so as to control the current source array to switch the current according to the bias voltage.

In one embodiment, the phase-locked loop circuit includes: the circuit comprises a phase frequency detector, a charge pump, a filter, a voltage-controlled oscillator, a buffer and a frequency divider;

The input end of the phase frequency detector is connected with an external crystal oscillator, the output end of the phase frequency detector is connected with the input end of the charge pump, the output end of the charge pump is connected with the input end of the filter, the output end of the filter is connected with the input end of the voltage-controlled oscillator, the output end of the voltage-controlled oscillator is connected with the input end of the buffer, the output end of the buffer is used as the output end of the phase-locked loop circuit, the output end of the buffer is also connected with the input end of the frequency divider, and the output end of the frequency divider is connected with the feedback end of the phase frequency detector.

A second aspect of the embodiments of the present application also provides a SAR system comprising a variable threshold single bit ADC chip according to any of the embodiments described above.

The beneficial effects of the embodiment of the application are that: the front-end receiving circuit is used for sampling and holding the input channel radar echo signals, then inputting the input channel radar echo signals into the I channel and the Q channel at the same time, respectively modulating the carriers, and mutually orthogonalizing the two channels of carriers. Under the condition of keeping the original signal data amount unchanged, providing a sine wave threshold value of a specific frequency of 20-DEG phase difference for 18 channels of each of the I, Q two channels, then dividing I, Q two channels of signals into 18 channels of signals by a first channel single-bit ADC circuit and a second channel single-bit ADC circuit, and finally respectively sampling and processing each channel of signals to form the original signals, thereby successfully reducing the sampling rate of each channel of signals, reducing the calculation complexity, improving the efficiency of data processing, achieving the purposes of simplifying the system architecture, reducing the construction cost and improving the imaging efficiency on the premise of ensuring the imaging quality, and promoting the low cost and microminiaturization of a radar imaging system.

Drawings

FIG. 1 is a schematic diagram I of a variable threshold single-bit ADC chip provided in an embodiment of the present application;

FIG. 2 is a schematic diagram II of a variable threshold single-bit ADC chip according to an embodiment of the present application;

FIG. 3 is a schematic diagram III of a variable threshold single-bit ADC chip provided by an embodiment of the present application;

FIG. 4 is a schematic diagram of an 8-bit DAC converter provided by an embodiment of the present application;

fig. 5 is a schematic diagram of a phase-locked loop circuit according to an embodiment of the present application;

fig. 6 is a schematic diagram of a voltage controlled oscillator provided in an embodiment of the present application;

fig. 7 is a schematic diagram of a phase frequency detector according to an embodiment of the present application.

Detailed Description

In order to make the technical problems, technical schemes and beneficial effects to be solved by the present application more clear, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.

It will be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.

It is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate or are based on the orientation or positional relationship shown in the drawings, merely to facilitate description of the present application and simplify description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be configured and operated in a particular orientation, and therefore should not be construed as limiting the present application.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is one or more than one unless specifically defined otherwise.

In order to solve the problem of miniaturization of a radar imaging system, the project is based on a millimeter wave radar platform and a single bit sampling quantization theory as a core, aims at solving the problems of serious imaging scene distortion, large threshold storage amount, strong dependence of an algorithm on scene sparsity and the like in the prior art, builds a signal model according to a specific application scene of the miniaturized SAR imaging system, deeply analyzes a formation mechanism of error accumulation and nonlinear distortion in single bit sampling quantization, designs an effective single bit quantization strategy and a corresponding rapid processing algorithm, achieves the purposes of simplifying a system architecture, reducing construction cost and improving imaging efficiency on the premise of guaranteeing imaging quality, and promotes low cost and microminiaturization of the radar imaging system.

The embodiment of the present application provides a variable threshold single-bit ADC chip, as shown in fig. 1, where the variable threshold single-bit ADC chip in the embodiment includes: the first front-end receiving circuit 110, the second front-end receiving circuit 120, the threshold data memory 500, the first DAC circuit 210, the second DAC circuit 220, the first channel single-bit ADC circuit 310, the second channel single-bit ADC circuit 320, the first multiplexer 410, and the second multiplexer 420.

In this embodiment, the first front-end receiving circuit 110 is configured to receive the first channel radar echo signal, and output 18 paths of first sampling signals in a time-sharing manner; the second front-end receiving circuit 120 is configured to receive the second channel radar echo signal, and output 18 paths of second sampling signals in a time-sharing manner; the threshold data memory 500 is used to store a first digital code sequence and a second digital code sequence. The first DAC circuit 210 is connected to the threshold data memory 500, and the first DAC circuit 210 is configured to acquire a first digital code sequence and convert the first digital code sequence into 18 paths of first analog sine wave thresholds; wherein the phase difference of adjacent first analog sine wave thresholds is 20 degrees; the second DAC circuit 220 is connected to the threshold data storage 500, and the second DAC circuit 220 is configured to acquire a second digital code sequence and convert the second digital code sequence into 18 paths of second analog sine wave thresholds; wherein the phase difference of the adjacent second analog sine wave threshold is 20 degrees. The first channel single-bit ADC circuit 310 is configured to receive 18 first sampling signals and 18 first analog sine wave thresholds, and convert the corresponding first sampling signals into 18 first digital codes according to the first analog sine wave thresholds; the second channel single-bit ADC circuit 320 is configured to receive 18 second sampling signals and 18 second analog sine wave thresholds, and convert the corresponding second sampling signals into 18 second digital codes according to the second analog sine wave thresholds; the first multiplexer 410 is connected to the first channel single-bit ADC circuit 310, and the first multiplexer 410 is configured to convert 18 first digital codes into a first digital signal; the second multiplexer 420 is connected to the second channel single-bit ADC circuit 320, and the second multiplexer 420 is configured to convert 18 second digital codes into a second digital signal.

In this embodiment, the first front-end receiving circuit 110, the first DAC circuit 210, the first channel single-bit ADC circuit 310, and the first multiplexer 410 form an I channel, the second front-end receiving circuit 120, the second DAC circuit 220, the second channel single-bit ADC circuit 320, and the second multiplexer 420 form a Q channel, the radar system samples and holds the input echo signal and then inputs the echo signal into the I channel and the Q channel at the same time, the I channel and the Q channel modulate the respective input signals, and the two carriers are orthogonal to each other. The first DAC circuit 210 and the second DAC circuit 220 obtain corresponding digital code sequences from the threshold data memory 500, and the first DAC circuit 210 is configured to obtain a first digital code sequence and convert the first digital code sequence into 18 first analog sine wave thresholds, so as to provide sine wave thresholds of specific frequencies for 18 sub-channels in the I channel, and there is a fixed phase difference of 20 degrees between the sine wave thresholds required by the 18 sub-channels. The second DAC circuit 220 is configured to obtain the second digital code sequence and convert the second digital code sequence into 18 second analog sine wave thresholds, so as to provide sine wave thresholds of specific frequencies for 18 sub-channels in the Q two channels, and a fixed 20-degree phase difference is provided between the sine wave thresholds required by the 18 sub-channels.

In this embodiment, with the variable-threshold single-bit ADC chip, under the condition of keeping the data amount of the original signal unchanged, the signals received by the two channels I, Q are respectively divided into 18 channels, after the 18 channels in each channel are sampled, each channel signal is finally processed by a corresponding multiplexer to form the original signal, so that the sampling rate of each channel signal is successfully reduced, the computation complexity is reduced, and the efficiency of data processing is improved.

In one embodiment, the sampling frequency F is set at a total sampling frequency of 300MHz and an oversampling rate of 11 _s ＝11*B _r Threshold frequency f ₀ ＝3.04*B _r Sampling rate F 'of each channel' _s ＝f ₀ -round(f ₀ /F _s ′)F _s ' 0.015555 x Br, wherein br= 27.2727MHz.

In one embodiment, the threshold for channel n in the I channel is

Wherein,for the frequency term, m represents the time sampling point number, +.>In the event of a time-offset term,is a phase term.

In one embodiment, the threshold for channel n in the Q channel is Wherein 2 pi f0' mFs ' is a frequency term, m represents a time sampling point sequence number, 2 pi f0' n-1NFs is a time offset term, and 2 pi n-1NK is a phase term.

In one specific application embodiment, the sample rate index of the variable threshold single bit ADC chip is shown in table 1.

Table 1:

in one embodiment, the first channel single-bit ADC circuit 310 includes 18 first single-bit ADC units, where the 18 first single-bit ADC units are in one-to-one correspondence with 18 first sampling signals, and the 18 first single-bit ADC units are in one-to-one correspondence with 18 first analog sine wave thresholds.

In this embodiment, each first single-bit ADC unit is configured to receive a corresponding first sampling signal and a first analog sine wave threshold, and generate a corresponding first digital code according to the first sampling signal and the first analog sine wave threshold.

In one embodiment, the second channel single-bit ADC circuit 320 includes 18 second single-bit ADC units, where the 18 second single-bit ADC units are in one-to-one correspondence with 18 second sampling signals, and the 18 second single-bit ADC units are in one-to-one correspondence with 18 second analog sine wave thresholds.

In this embodiment, each second single-bit ADC unit is configured to receive a corresponding second sampling signal and a second analog sine wave threshold, and generate a corresponding second digital code according to the second sampling signal and the second analog sine wave threshold.

In one embodiment, the first digital code sequence includes at least 4 threshold frequency digital codes and at least 4 initial phase digital codes; the second sequence of digital codes includes at least 4 threshold frequency digital codes and at least 4 initial phase digital codes.

In one embodiment, the first DAC circuit 210 includes 18 first DAC cells, which 18 first DAC cells retrieve the corresponding first digital code sequence from the threshold data memory 500 as 18 sub-channels (channel I1 through channel I18). The second DAC circuit 220 includes 18 second DAC cells, and the 18 second DAC cells acquire corresponding second digital code sequences from the threshold data memory 500 as 18 sub-channels (channel Q1 to channel Q18).

In the operation process of the variable threshold single-bit ADC chip, first, four kinds of threshold frequencies and digital code sequences corresponding to the four kinds of initial phases are stored in the threshold data memory 500 according to the difference between the threshold frequencies and the initial phases. The externally input control signal may select a corresponding digital code sequence to be output to the first DAC circuit 210 and the second DAC circuit 220. And then, under the control of a sampling clock, corresponding digital codes are respectively provided for a first DAC unit of 18 sub-channels from I1 to I18 and a second DAC unit of 18 channels from Q1 to Q18, and then the DAC units convert the digital codes into corresponding analog sine wave thresholds.

The two front-end receiving circuits (the first front-end receiving circuit 110 and the second front-end receiving circuit 120) of the front end sample and hold the external radar echo signals and then time-share input the external radar echo signals to the corresponding sub-channels (i.e., the corresponding first ADC unit or the corresponding second ADC unit). For example, the first front-end receiving circuit 110 receives the radar echo signal of the I channel and then inputs it to the sub-channels I1, I2, I3 in a time-sharing manner until the sub-channel I18, and then continuously circulates, and the second front-end receiving circuit 120 receives the radar echo signal of the Q channel and then inputs it to the sub-channels Q1, Q2, Q3 in a time-sharing manner until the sub-channel Q18, and then continuously circulates. The 18 first single-bit ADC units of the I channel are also in a time-sharing working state, for example, the first single-bit ADC unit of the sub-channel I1 receives an analog sine wave threshold provided by the first DAC unit of the sub-channel I1, and the first front end receives the echo signal sampled and held by the circuit 110, and then generates a corresponding digital code output of 0 or 1 through comparison, then the first ADC unit of the sub-channel I1 is in a holding state, the first ADC unit of the sub-channel I2 is in a working state, and then the sub-channels I3 and I4 continuously and circularly work until the first single-bit ADC unit of the sub-channel I18. Similarly, the Q channel also cycles. The 18-way 1-selecting multiplexer behind the I-way and Q-way integrates the output of the 18-way single-bit ADC digital codes into one-way output, and then outputs the output to the outside for processing.

In some embodiments, sine wave thresholds are provided in the threshold data memory 500 by using a DAC in combination with a memory lookup table, if a sine wave generator is used to provide sine waves, the phase difference of the sine wave thresholds between different channels is difficult to adjust if not correct, and the subroutine return (migach) that exists between different channels of the sine wave generator is also difficult to eliminate, and the sine wave generator circuit becomes very sensitive to noise. The use of a memory to store the corresponding digital code sequence and then generating the corresponding sine wave based on the digital code sequence via the DAC unit results in a significant improvement in the accuracy of the provided threshold.

In the variable threshold single-bit ADC chip, the radar system requires the variable threshold single-bit ADC chip to provide four sine wave thresholds with different frequencies and requires that the initial phases of the channels are adjustable, and if the variable threshold single-bit ADC chip is generated by a sine wave generator, the variable threshold single-bit ADC chip requires four sine wave generators with different frequencies, which makes the hardware implementation of the system more difficult. By adopting the mode of the method, only a plurality of groups of different cyclic character code sequences are needed to be stored, and four sine wave thresholds with different frequencies and different initial phases can be generated, so that the system becomes flexible and adjustable. By adopting the method, not only the digital code sequence corresponding to the sine wave can be stored, but also the thresholds of different waveforms such as triangular wave, square wave and the like can be provided by storing different digital code sequences, so that good flexibility is provided for the algorithm upgrading of a subsequent system.

In one embodiment, the first multiplexer 410 and the second multiplexer 420 may be 18-to-1 multiplexers.

In one embodiment, referring to fig. 2, the variable threshold single bit ADC chip further comprises a phase locked loop circuit 610 and a clock distribution circuit 620.

In this embodiment, the pll circuit 610 is configured to receive an external crystal oscillator frequency and generate a preset clock frequency according to the crystal oscillator frequency, for example, in an actual application, the pll circuit 610 is configured to receive an external crystal oscillator frequency of 18.75MHz and generate a clock frequency of 300MHz according to the crystal oscillator frequency; the clock distribution circuit 620 is configured to provide the sampling clock frequency to the front-end receiving circuit according to the clock frequency, and the clock distribution circuit 620 is further configured to provide the corresponding operating clock frequencies to the first DAC circuit 210, the second DAC circuit 220, the first channel single-bit ADC circuit 310, and the second channel single-bit ADC circuit 320.

In some embodiments, the phase-locked loop circuit 610 may be a charge pump phase-locked loop structure that is used to generate a global clock at a 300MHz center frequency at a reference frequency of an input crystal oscillator. While the sampling clock required for each path is generated by clock distribution circuit 620 as a clock supply source for integrated circuits, particularly digital-to-analog hybrid circuits. The phase-locked loop frequency synthesis technology in the embodiment has the advantages of very rapid development due to simple circuit and excellent performance, good stability, strong spurious suppression and good noise suppression performance of the frequency generated by the method.

In one embodiment, referring to fig. 3, the variable threshold single-bit ADC chip further comprises an error correction circuit 630, the error correction circuit 630 being configured to perform static error correction on the first DAC circuit 210 and the second DAC circuit 220.

In one embodiment, the first DAC circuit 210 includes 18 first DAC units; the error correction circuit 630 is configured to input a first preset digital code to a corresponding first DAC unit, so as to gate a corresponding current source in the first DAC unit; a first single-bit ADC unit corresponding to the first DAC unit generates a first feedback signal according to an output signal of the first DAC unit; the error correction circuit 630 is further configured to correct a corresponding current source in the first DAC cell according to the first feedback signal.

The second DAC circuit 220 includes 18 second DAC cells; the error correction circuit 630 is configured to input a second preset digital code to the corresponding second DAC unit, so as to gate a corresponding current source in the second DAC unit; a second single-bit ADC unit corresponding to the second DAC unit generates a second feedback signal according to the output signal of the second DAC unit; the error correction circuit 630 is further configured to correct a corresponding current source in the second DAC cell according to the second feedback signal.

In this embodiment, the error correction circuit 630 in this embodiment may be a successive approximation DAC static error correction system built using an off-chip ADC. In the DAC circuit, the static error of the current steering DAC mainly originates from the current value error of the current source array 709, and the error correction system in this embodiment is used for correcting the current source error, and the working process is as follows: and inputting a specific digital code to the current steering DAC through an error correction system, and then gating a corresponding current source. And then the output of the DAC and the external reference voltage are input into the single-bit ADC at the same time, and then the error correction system can judge whether to access the compensation current source, bypass the current source or perform the next correction according to the 0 and 1 values fed back by the single-bit ADC.

In one embodiment, the first DAC cell and the second DAC cell are each eight-bit DAC converters.

Referring to fig. 4, the eight-bit DAC converter includes: an input register 701, a high-order thermometer decoding unit 702, a low-order delay chain unit 703, a switch driving circuit 704, a switch array circuit 705, a first output resistor R1, a second output resistor R2, a first inverter Z1710, a second inverter Z2711, a voltage bandgap reference source 706, a voltage-to-current unit 707, a bias circuit 708, and a current source array 709; the input end of the input register 701 is used for receiving an 8-bit digital code, the clock signal end of the input register 701 is commonly connected with the input end of the first inverter Z1710 and is used for receiving a clock signal, the output end of the input register 701 is respectively connected with the high-order thermometer decoding unit 702 and the low-order delay chain unit 703, the high-order thermometer decoding unit 702 is used for performing binary weight processing on the first four-bit digital code output by the input register 701, the low-order delay chain unit 703 is used for performing thermometer code processing on the last four-bit digital code output by the input register 701, the output end of the high-order thermometer decoding unit 702 is connected with the switch driving circuit 704, the output end of the low-order delay chain unit 703 is connected with the switch driving circuit 704, the output end of the first inverter Z1710 is connected with the input end of the second inverter Z2711, and the output end of the second inverter Z2711 is connected with the switch driving circuit 704.

The switch driving circuit 704 is connected with the switch array circuit 705, the voltage band gap reference source 706 is connected with the input end of the voltage-to-current unit 707, the output end of the voltage-to-current unit 707 is connected with the input end of the bias circuit 708, the output end of the bias circuit 708 is connected with the current source array 709, the first end of the first output resistor R1 is connected with the power supply end VDD, the first end of the second output resistor R2 is connected with the first end of the switch array circuit 705 to serve as a first voltage signal output end VP, and the second end of the second output resistor R2 is connected with the second end of the switch array circuit 705 to serve as a second voltage signal output end VN. The voltage bandgap reference source 706 is used for generating a reference voltage signal, the voltage-to-current unit 707 is used for converting the reference voltage signal into a reference current signal, and the bias circuit 708 is used for converting the reference current signal into a bias voltage and outputting the bias voltage to the current source array 709; the switch driving circuit 704 is configured to control a switching state of the switch array circuit 705 to control the current source array 709 to perform current switching according to a bias voltage.

In this embodiment, the switch array circuit 705 may include a plurality of switch tubes, where the switch tubes are in one-to-one correspondence with a plurality of current sources in the current source array 709, the switch tubes respectively control on or off of the plurality of current sources, the plurality of current sources may generate different currents according to the bias voltage, and the first output resistor R1 and the second output resistor R2 generate corresponding voltage signals according to the currents flowing through the resistors and output the corresponding voltage signals through the corresponding voltage signal output ends when the corresponding switch tubes are turned on. In the case that the resolution of the variable threshold single-bit ADC chip is 8 bits, in the eight-bit DAC converter of this embodiment, the first four bits use binary weight current sources (low-bit delay chain units 703), and the second four bits use mixed current rudder DACs (high-bit thermometer decoding units 702) of the thermometer code type, so that the defects of serious burr phenomenon, poor linearity, complicated circuit and too large chip area caused by completely using the thermometer code type structure can be avoided.

In the eight-bit DAC converter in the present embodiment, the DAC circuit may be divided into a digital circuit portion and an analog circuit portion as a whole. In the high-speed DAC circuit design, an error code may be generated when the input digital signal is not synchronized, so that the input register 701 is designed to perform synchronization processing on the 8-bit input binary symbol signal. In the output stage of the current steering DAC, the current source array 709 needs to be controlled by the switch driving circuit 704 to switch the current. The voltage bandgap reference 706 refers to a dc voltage or current that is process, power supply independent and has certain defined temperature characteristics, and in DAC circuits, the voltage bandgap reference 706 is required to provide a stable bias to the DAC circuit. Since the voltage signal is relatively sensitive to circuit noise, if the reference voltage generated by the DAC circuit is directly applied to the current source array 709 as a bias voltage, the bias voltage is not stable, and thus the value of the unit current may also be randomly deviated. The current signal is less sensitive to noise than voltage, so that the reference voltage signal generated by the voltage bandgap reference source 706 may be converted into a reference current signal by the voltage-to-current unit 707 (e.g., the voltage-to-current unit 707 may be an operational amplifier), then the constant reference current signal is converted into a desired bias voltage by the bias circuit 708, and the current source array 709 generates corresponding currents under the control of the switch array circuit 705 to flow through the first output resistor R1 and the second output resistor R2 at the output terminals to generate corresponding output voltages (the first output voltage VP and the second output voltage VN).

In one embodiment, design simulation and verification of the circuits of the digital portion (e.g., input registers 701; high-order thermometer decode units 702; switch drive circuits 704, etc.) and analog circuit portions (e.g., voltage bandgap reference source 706; voltage to current unit 707; bias circuits 708; switch current source array 709, etc.) in the above embodiments are performed by employing a tsmc65nm process library in cadence select software, and joint debugging of the overall DAC circuit has been completed. The whole DAC circuit can correctly process input and obtain correct output, and through simulation test of the whole DAC circuit, the result shows that the DAC circuit has very low DNL and INL, quite good accuracy and static performance, and meanwhile, the circuit has very good dynamic performance without spurious dynamic range SFDR being larger than or equal to 56 db.

In one embodiment, referring to fig. 5, a phase-locked loop circuit 610 includes: a phase frequency detector 611, a charge pump 612, a filter 613, a voltage controlled oscillator 614, a buffer 616, and a frequency divider 615; the input end of the phase frequency detector 611 is connected with an external crystal oscillator, the output end of the phase frequency detector 611 is connected with the input end of the charge pump 612, the output end of the charge pump 612 is connected with the input end of the filter 613, the output end of the filter 613 is connected with the input end of the voltage-controlled oscillator 614, the output end of the voltage-controlled oscillator 614 is connected with the input end of the buffer 616, the output end of the buffer 616 is used as the output end of the phase-locked loop circuit 610, the output end of the buffer 616 is also connected with the input end of the frequency divider 615, and the output end of the frequency divider 615 is connected with the feedback end of the phase frequency detector 611.

In this embodiment, the basic operating principle of the phase-locked loop circuit 610 is that the output phase and the input phase are compared by a feedback control system, so that a signal of a specific frequency and phase can be generated. The phase frequency detector 611 (PFD) in this embodiment can linearly convert the input phase difference value into a voltage, and the phase frequency detector 611 is designed to have a linear operating range as wide as possible. The charge pump 612 is a "bridge" between the PFD and the filter 613 (the filter 613 may be a loop filter) that is charged and discharged under the control of the PFD, thereby effecting conversion of the phase signal to a voltage signal. The loop filter may convert the charge-discharge current of the charge pump 612 into a control voltage of a voltage-controlled oscillator 614 (VCO), followed by filtering out high frequency signals from the higher-level circuit. The VCO generates an oscillating wave of a corresponding frequency at the control voltage of the loop filter. The output waveform of the VCO is usually neither square wave nor sine wave, and the duty cycle of the output waveform is related to the swing and the oscillation frequency, so in the embodiment, the output waveform of the VCO is shaped by providing a buffer 616 at the output end of the VCO, and the frequency divider 615 is used to output the signal frequency division processed after the shaping of the buffer 616 to the phase frequency detector 611, so as to provide a corresponding feedback signal for the phase frequency detector 611.

In this embodiment, the generation of the clock frequency is achieved by using an analog pll with a charge pump 612 structure, which aims to generate a pll circuit 610 with a center frequency of 600MHz at a crystal input frequency of 18.75 MHz. Based on the oscillator structure using differential feedback, the present method uses tsmc65nm process library to complete each part of sub-circuit in cadence select, and uses the duty cycle function to simulate the duty cycle when outputting 600MHz square wave, the result shows that the duty cycle of the high clock and the low clock is 50% ± 1.5%, and the spurious test reaches-71 db, which indicates that the phase-locked loop circuit 610 in this embodiment can generate a global clock with higher quality.

Fig. 6 is a schematic diagram of a voltage-controlled oscillator 614 according to an embodiment of the present application, referring to fig. 6, the voltage-controlled oscillator 614 in the embodiment includes: the switching device comprises a first switching tube Q1, a second switching tube Q2, a third switching tube Q3, a fourth switching tube Q4, a fifth switching tube Q5, a sixth switching tube Q6, a seventh switching tube Q7, an eighth switching tube Q8, a ninth switching tube Q9, a tenth switching tube Q10, an eleventh switching tube Q11, a twelfth switching tube Q12, a thirteenth switching tube Q13, a fourteenth switching tube Q14, a fifteenth switching tube Q15, a sixteenth switching tube Q16, a seventeenth switching tube Q17, an eighteenth switching tube Q18, a nineteenth switching tube Q19, a twentieth switching tube Q20 and a twenty first switching tube Q21.

In this embodiment, the first voltage source VDC provides a first power source for the first power supply terminal VDD1, and the voltage of the first power source may be 3.3V. The second voltage source VDC2 and the third voltage source VDC3 may be a first input voltage and a second input voltage, for example, in one embodiment, the first input voltage may be 1.35V, the second input voltage may be 2V, the drain of the nineteenth switching transistor Q19 may be a first output terminal, the drain of the twentieth switching transistor Q20 may be a second output terminal, and the drain of the twenty first switching transistor Q21 may be a third output terminal. As shown in fig. 6, the circuit structure of the voltage-controlled oscillator 614 is that the first switching tube Q1 and the second switching tube Q2 are connected in parallel to form a current mirror, the third switching tube Q3 and the fourth switching tube Q4 are connected in parallel to form a current mirror, the fifth switching tube Q5 and the sixth switching tube Q6 are connected in parallel to form a current mirror, the seventh switching tube Q7 and the eighth switching tube Q8 are connected in parallel to form a current mirror, the ninth switching tube Q9 and the tenth switching tube Q10 are connected in parallel to form a current mirror, and the eleventh switching tube Q11 and the twelfth switching tube Q12 are connected in parallel to form a current mirror. The first switching tube Q1, the second switching tube Q2, the third switching tube Q3, the fourth switching tube Q4, the fifth switching tube Q5, the sixth switching tube Q6, the seventh switching tube Q7, the eighth switching tube Q8, the ninth switching tube Q9, the tenth switching tube Q10, the eleventh switching tube Q11, the twelfth switching tube Q12 are PMOS tubes, the thirteenth switching tube Q13, the fourteenth switching tube Q14, the fifteenth switching tube Q15, the sixteenth switching tube Q16, the seventeenth switching tube Q17, the eighteenth switching tube Q18, the nineteenth switching tube Q19, the twenty-first switching tube Q20, the twenty-first switching tube Q21 are NMOS tubes, the drain of the thirteenth switching tube Q13 is commonly connected with the grid electrode of the seventeenth switching tube Q17, the drain electrode of the fourteenth switching tube Q14 is commonly connected with the grid electrode of the eighteenth switching tube Q18, the drain electrode of the fifteenth switching tube Q15 is commonly connected with the grid electrode of the seventeenth switching tube Q18, the drain electrode of the thirteenth switching tube Q15 is commonly connected with the drain electrode of the seventeenth switching tube Q13, the drain electrode of the seventeenth switching tube Q14 is commonly connected with the drain electrode of the drain electrode Q16 is commonly connected with the drain electrode of the seventeenth switching tube Q13, the drain electrode of the thirteenth switching tube Q14 is commonly connected with the drain electrode of the seventeenth switching tube Q13, the drain electrode of the seventeenth switching tube Q14 is commonly connected with the drain electrode Q12 is commonly connected with the drain electrode of the seventeenth switching tube Q13.

The source of the thirteenth switching tube Q13 and the source of the fourteenth switching tube Q14 are commonly connected with the drain of the nineteenth switching tube Q19, the source of the fifteenth switching tube Q15 and the source of the sixteenth switching tube Q16 are commonly connected with the drain of the twentieth switching tube, the source of the seventeenth switching tube Q17 and the source of the eighteenth switching tube Q18 are commonly connected with the drain of the twenty first switching tube Q21, the gates of the nineteenth switching tube Q19, the twentieth switching tube Q20 and the twenty first switching tube Q21 are commonly connected with the third voltage source ADC3, and the sources of the nineteenth switching tube Q19, the twentieth switching tube Q20 and the twenty first switching tube Q21 are commonly connected with the ground.

In the present embodiment, the first switching tube Q1, the second switching tube Q2, the third switching tube Q3, the fourth switching tube Q4, the fifth switching tube Q5, the sixth switching tube Q6, the seventh switching tube Q7, the eighth switching tube Q8, the ninth switching tube Q9, the tenth switching tube Q10, the eleventh switching tube Q11, the twelfth switching tube Q12, the thirteenth switching tube Q13, the fourteenth switching tube Q14, the fifteenth switching tube Q15, the sixteenth switching tube Q16, the seventeenth switching tube Q17, the eighteenth switching tube Q18, the nineteenth switching tube Q19, the twentieth switching tube Q20, the twenty first switching tube Q21 constitute three sets of oscillation circuits, and the output signals of each set of oscillation circuits are respectively used as input control signals of the other two sets of oscillation circuits, so that the ring oscillator in the present embodiment generates an oscillation waveform of a corresponding frequency under the control voltage of the ring filter, and the ring oscillator normally has an output sine wave or a sine wave waveform, and the output duty ratio of which is neither duty ratio nor swing wave.

Fig. 7 is a schematic diagram of a phase frequency detector 611 according to an embodiment of the present application, referring to fig. 7, the phase frequency detector 611 in this embodiment includes: twenty-second switching tube Q22, twenty-third switching tube Q23, twenty-fourth switching tube Q24, twenty-fifth switching tube Q25, twenty-sixth switching tube Q26, twenty-seventeenth switching tube Q27, twenty-eighth switching tube Q28, twenty-ninth switching tube Q29, thirty-first switching tube Q30, thirty-second switching tube Q31, thirty-second switching tube Q32, thirty-third switching tube Q33, thirty-fourth switching tube Q34, thirty-fifth switching tube Q35, thirty-sixteen switching tube Q36, thirty-seventeenth switching tube Q37, and gate Z4, first inverter Z1, second inverter Z2, and third inverter Z3.

In the present embodiment, as shown in fig. 7, the circuit structure of the phase frequency detector 611 is that the twenty-second switching tube Q22, the twenty-sixth switching tube Q26, and the twenty-seventh switching tube Q27 are connected in series, the twenty-third switching tube Q23, the twenty-fifth switching tube Q25, and the twenty-eighth switching tube Q28 are connected in series, the twenty-fourth switching tube Q24, and the twenty-ninth switching tube Q29 are connected in series, wherein the gates of the twenty-fifth switching tube Q25 and the twenty-second switching tube Q22 are commonly connected to the fourth voltage source VDC4, and the gates of the thirty-third switching tube Q33 and the thirty-fifth switching tube Q35 are commonly connected to the fifth voltage source VDC5. The second power supply terminal VDD2 supplies power to the first inverter Z1, the second inverter Z2, the third inverter Z3, and the and gate Z4, and connects sources of the twenty-second switching transistor Q22, the twenty-third switching transistor Q23, the twenty-fourth switching transistor Q24, and sources of the thirty-fifth switching transistor Q35, the thirty-sixteen switching transistor Q36, and the thirty-seventh switching transistor Q37.

In one embodiment, the twenty-second switching tube Q22, the twenty-third switching tube Q23, the twenty-fourth switching tube Q24, the twenty-sixth switching tube Q26, the thirty-first switching tube Q31, the thirty-fifth switching tube Q35, the thirty-sixth switching tube Q36, and the thirty-seventh switching tube Q37 are PMOS tubes, and the twenty-fifth switching tube Q25, the twenty-seventh switching tube Q27, the twenty-eighth switching tube Q28, the twenty-ninth switching tube Q29, the thirty-second switching tube Q30, the thirty-second switching tube Q32, the thirty-third switching tube Q33, and the thirty-fourth switching tube Q34 are NMOS tubes.

Referring to fig. 7, the drain of the twenty-second switching transistor Q22 is connected to the source of the twenty-sixth switching transistor Q26, the drain of the twenty-sixth switching transistor Q26 and the drain of the twenty-seventh switching transistor Q27 are commonly connected to the gate of the twenty-third switching transistor Q23 and the gate of the twenty-eighth switching transistor Q28, and the drain of the twenty-third switching transistor Q23 is commonly connected to the drain of the twenty-fifth switching transistor Q25, the gate of the twenty-fourth switching transistor Q24, the gate of the twenty-ninth switching transistor Q29, and the first input terminal of the and gate Z4. The drain electrode of the twenty-fourth switching tube Q24 and the drain electrode of the twenty-ninth switching tube Q29 are commonly connected to the input end of the first inverter Z1, and the output end of the first inverter Z1 is used as the first output end. The drain electrode of the thirty-fourth switching tube Q34 and the drain electrode of the thirty-seventh switching tube Q37 are connected to the input end of the third inverter Z3, and the output end of the third inverter Z3 serves as a second output end. The gate of the thirty-fourth switching tube Q34, the gate of the thirty-seventh switching tube Q37, the drain of the thirty-third switching tube Q33, and the drain of the thirty-sixth switching tube Q36 are commonly connected to the second input terminal of the and gate Z4. The output end of the AND gate Z4 is connected with the input end of the second inverter Z2, and the output end of the second inverter Z2, the grid electrode of the twenty-sixth switching tube Q26, the grid electrode of the twenty-seventh switching tube Q27, the grid electrode of the thirty-first switching tube Q30 and the grid electrode of the thirty-first switching tube Q31 are connected together. The ground of the second inverter Z2, the source of the thirty-second switching transistor Q30, the source of the thirty-second switching transistor Q32, and the source of the thirty-fourth switching transistor Q34 are commonly grounded.

In this embodiment, the fourth voltage source VDC4 may be used as an input source of an external crystal oscillator, the fifth voltage source VDC5 may be used as a feedback output of the frequency divider 615, the twenty-second switching tube Q22, the twenty-third switching tube Q23, the twenty-fourth switching tube Q24, the twenty-sixteen switching tube Q26, the twenty-fifth switching tube Q25, the twenty-seventeenth switching tube Q27, the twenty-eighth switching tube Q28, and the twenty-ninth switching tube Q29 may form a group of frequency discrimination circuits, the thirty-first switching tube Q31, the thirty-fifth switching tube Q35, the thirty-seventeenth switching tube Q36, the thirty-seventh switching tube Q37, the thirty-second switching tube Q30, the thirty-third switching tube Q32, the thirty-third switching tube Q33, and the thirty-fourth switching tube Q34 may form a group of phase discrimination circuits, and the second group of frequency discrimination circuits is symmetrical to the first group of frequency discrimination circuits. The phase frequency detector 611 may generate an output signal proportional to the phase difference between two input signals, one of which is of very stable frequency, i.e., generated by an external crystal oscillator, and the other of which is variable and of poor stability, obtained by passing the output signal of the voltage controlled oscillator 614 through the frequency divider 615. The phase frequency detector 611 corrects the difference between the two input signals in the loop and frequency-locks by slightly varying the control voltage of the voltage-controlled oscillator 614.

Embodiments of the present application also provide a SAR system comprising a variable threshold single bit ADC chip according to any of the embodiments above.

The beneficial effects of the embodiment of the application are that: the front-end receiving circuit is used for sampling and holding the input channel radar echo signals, then inputting the input channel radar echo signals into the I channel and the Q channel at the same time, respectively modulating the carriers, and mutually orthogonalizing the two channels of carriers. Under the condition of keeping the original signal data amount unchanged, providing a sine wave threshold value of a specific frequency of 20-DEG phase difference for 18 channels of each of the I, Q two channels, then dividing I, Q two channels of signals into 18 channels of signals by a first channel single-bit ADC circuit and a second channel single-bit ADC circuit, and finally respectively sampling and processing each channel of signals to form the original signals, thereby successfully reducing the sampling rate of each channel of signals, reducing the calculation complexity, improving the efficiency of data processing, achieving the purposes of simplifying the system architecture, reducing the construction cost and improving the imaging efficiency on the premise of ensuring the imaging quality, and promoting the low cost and microminiaturization of a radar imaging system.

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-described functions. The functional units and modules in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.

In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.

Claims (10)

1. A variable threshold single-bit ADC chip, the variable threshold single-bit ADC chip comprising:

the first front-end receiving circuit is used for receiving the first channel radar echo signal and outputting 18 paths of first sampling signals in a time-sharing way;

the second front-end receiving circuit is used for receiving the second channel radar echo signal and outputting 18 paths of second sampling signals in a time-sharing way;

a threshold data memory for storing a first digital code sequence and a second digital code sequence;

the first DAC circuit is used for acquiring the first digital code sequence and converting the first digital code sequence into 18 paths of first analog sine wave thresholds; wherein the phase difference between adjacent first analog sine wave thresholds is 20 degrees;

the second DAC circuit is used for acquiring the second digital code sequence and converting the second digital code sequence into 18 paths of second analog sine wave thresholds; wherein the phase difference between adjacent second analog sine wave thresholds is 20 degrees;

the first channel single-bit ADC circuit is used for receiving 18 paths of first sampling signals and 18 paths of first analog sine wave thresholds and converting the corresponding first sampling signals into 18 paths of first digital codes according to the first analog sine wave thresholds;

The second channel single-bit ADC circuit is used for receiving 18 paths of second sampling signals and 18 paths of second analog sine wave thresholds and converting the corresponding second sampling signals into 18 paths of second digital codes according to the second analog sine wave thresholds;

the first multiplexer is used for converting 18 paths of the first digital codes into a first path of digital signals;

and the second multiplexer is used for converting 18 paths of the second digital codes into a second path of digital signals.

2. The variable threshold single-bit ADC chip of claim 1, wherein the first channel single-bit ADC circuit comprises 18 first single-bit ADC units, the 18 first single-bit ADC units corresponding one-to-one to the 18 first sampling signals, the 18 first single-bit ADC units corresponding one-to-one to the 18 first analog sine wave thresholds;

each channel of the first single-bit ADC unit is used for receiving the corresponding first sampling signal and the first analog sine wave threshold value and generating the corresponding first digital code according to the first sampling signal and the first analog sine wave threshold value.

3. The variable threshold single-bit ADC chip of claim 1, wherein the second channel single-bit ADC circuit comprises 18 second single-bit ADC units, the 18 second single-bit ADC units being in one-to-one correspondence with the 18 second sampling signals, the 18 second single-bit ADC units being in one-to-one correspondence with the 18 second analog sine wave thresholds;

Each path of the second single-bit ADC unit is used for receiving the corresponding second sampling signal and the second analog sine wave threshold value and generating the corresponding second digital code according to the second sampling signal and the second analog sine wave threshold value.

4. The variable threshold single bit ADC chip of claim 1, wherein the first digital code sequence comprises at least 4 threshold frequency digital codes and at least 4 initial phase digital codes;

the second sequence of digital codes includes at least 4 threshold frequency digital codes and at least 4 initial phase digital codes.

5. The variable threshold single bit ADC chip of any of claims 1-4, wherein the variable threshold single bit ADC chip further comprises:

the phase-locked loop circuit is used for receiving the external crystal oscillator frequency and generating a preset clock frequency according to the crystal oscillator frequency;

and the clock distribution circuit is used for providing a sampling clock frequency for the front-end receiving circuit according to the clock frequency and providing corresponding working clock frequencies for the first DAC circuit, the second DAC circuit, the first channel single-bit ADC circuit and the second channel single-bit ADC circuit.

6. The variable threshold single bit ADC chip of any of claims 1-4, wherein the variable threshold single bit ADC chip further comprises:

and the error correction circuit is used for carrying out static error correction on the first DAC circuit and the second DAC circuit.

7. The variable threshold single bit ADC chip of claim 6, wherein said first DAC circuit comprises 18 first DAC cells; the error correction circuit is used for inputting a first preset digital code to the corresponding first DAC unit so as to gate a corresponding current source in the first DAC unit; the first single-bit ADC unit corresponding to the first DAC unit generates a first feedback signal according to the output signal of the first DAC unit; the error correction circuit is further used for correcting a corresponding current source in the first DAC unit according to the first feedback signal;

the second DAC circuit comprises 18 paths of second DAC units; the error correction circuit is used for inputting a second preset digital code to the corresponding second DAC unit so as to gate a corresponding current source in the second DAC unit; the second single-bit ADC unit corresponding to the second DAC unit generates a second feedback signal according to the output signal of the second DAC unit; the error correction circuit is further configured to correct a corresponding current source in the second DAC cell according to the second feedback signal.

8. The variable threshold single bit ADC chip of claim 7, wherein said first DAC cell and said second DAC cell are each eight bit DAC converters; the eight-bit DAC converter includes: the device comprises an input register, a high-level thermometer decoding unit, a low-level delay chain unit, a switch driving circuit, a switch array circuit, a first output resistor, a second output resistor, a first inverter Z1, a second inverter Z2, a voltage band gap reference source, a voltage-to-current unit, a bias circuit and a current source array;

the input end of the input register is used for receiving 8-bit digital codes, the clock signal end of the input register is commonly connected with the input end of the first inverter Z1 and is used for receiving clock signals, the output end of the input register is respectively connected with a high-bit thermometer decoding unit and a low-bit delay chain unit, the high-bit thermometer decoding unit is used for performing binary weight processing on the first four-bit digital code output by the input register, the low-bit delay chain unit is used for performing thermometer code processing on the last four-bit digital code output by the input register, the output ends of the high-bit thermometer decoding unit and the low-bit delay chain unit are connected with the switch driving circuit, the output end of the first inverter Z1 is connected with the input end of the second inverter Z2, and the output end of the second inverter Z2 is connected with the switch driving circuit;

The switch driving circuit is connected with the switch array circuit, the voltage band gap reference source is connected with the input end of the voltage-to-current unit, the output end of the voltage-to-current unit is connected with the input end of the bias circuit, the output end of the bias circuit is connected with the current source array, the first end of the first output resistor is connected with the power supply end, the first end of the second output resistor is connected with the power supply end, the second end of the first output resistor and the first end of the switch array circuit are connected together to serve as a first voltage signal output end, and the second end of the second output resistor and the second end of the switch array circuit are connected together to serve as a second voltage signal output end; the voltage band gap reference source is used for generating a reference voltage signal, the voltage-to-current unit is used for converting the reference voltage signal into a reference current signal, and the bias circuit is used for converting the reference current signal into bias voltage and outputting the bias voltage to the current source array; the switch driving circuit is used for controlling the switch state of the switch array circuit so as to control the current source array to switch the current according to the bias voltage.

9. The variable threshold single bit ADC chip of claim 5, wherein said phase locked loop circuit comprises: the circuit comprises a phase frequency detector, a charge pump, a filter, a voltage-controlled oscillator, a buffer and a frequency divider;

The input end of the phase frequency detector is connected with an external crystal oscillator, the output end of the phase frequency detector is connected with the input end of the charge pump, the output end of the charge pump is connected with the input end of the filter, the output end of the filter is connected with the input end of the voltage-controlled oscillator, the output end of the voltage-controlled oscillator is connected with the input end of the buffer, the output end of the buffer is used as the output end of the phase-locked loop circuit, the output end of the buffer is also connected with the input end of the frequency divider, and the output end of the frequency divider is connected with the feedback end of the phase frequency detector.

10. A SAR system comprising a variable threshold single bit ADC chip of any of claims 1-9.