CN117693784A

CN117693784A - Pixel circuit and display device using pulse width modulation generator

Info

Publication number: CN117693784A
Application number: CN202180098099.1A
Authority: CN
Inventors: 曾世宪; 卢志文
Original assignee: Individual
Current assignee: Individual
Priority date: 2021-05-11
Filing date: 2021-05-11
Publication date: 2024-03-12
Also published as: WO2022236676A1

Abstract

A pixel circuit (100A) and a display device (300) are provided that use a pulse width modulation generator (104A). The pixel circuit (100A) has a data latch (102); and a pulse width modulation generator (104A) electrically coupled to the data latch (102), a Scan Line (SL) and a counter (C1); wherein the pulse width modulation generator (104A) generates a pulse width modulated signal (PMS) from the Pixel Data (PD), the Scanning Signal (SS) and a counter code (CC 1) generated by the counter (C1). Accordingly, the Pixel Signal (PS) may be generated in a voltage and/or current mode according to the signal (PMS) of the PWM and connected to the corresponding pixel electrode (E1) of the pixel Display Medium Module (DMM) such that the gray scale function of the display is precisely provided by precisely controlling the cycle time of the voltage and/or current to drive the display medium.

Description

Pixel circuit and display device using pulse width modulation generator

Technical Field

The present invention relates to a pixel circuit and a display device, and more particularly, to a digital driving pixel circuit and a display device using a pulse width modulation generator.

Background

Technological advances have led to demands for visual perception of images, and display devices having the advantages of light weight, high contrast, high dynamic, high color saturation, high aperture ratio, large-size display, low cost, low power consumption, high quality, and easy maintenance have been desired.

Current display devices can be classified into self-luminous type and non-self-luminous type. Liquid Crystal Displays (LCDs) are currently the most popular type of non-self-luminous flat panel display device. The amount of light passing through the liquid crystal medium is modulated by controlling the voltages of the upper and lower electrodes of the liquid crystal medium. If a constant voltage is continuously applied to the lower electrode and the upper electrode of the liquid crystal, blurring of an LCD image and deterioration of display quality are easily caused. The characteristic of polarity inversion with alternating voltages is generally used to apply the difference between the upper and lower electrodes to alternate positive and negative polarities. The liquid crystal display adopts four inversion driving methods, namely frame inversion, row inversion, column inversion and dot inversion driving modes, and is combined with a color filter layer, a polaroid, a plurality of functional optical films, a backlight source and the like to achieve the effect of color display.

Self-luminous flat panel displays can be classified into field emission displays, plasma displays, electroluminescent displays, photoluminescent displays, organic light emitting diode displays, and the like. In an organic light emitting diode display (OLED), a light emitting polymer is deposited between an upper electrode layer and a lower electrode layer. By further adopting the electron and hole conducting layers, the carriers are moved by increasing the electric field, so that the recombination phenomenon of the electrons and the hole carriers is generated, and the luminous display is generated. In contrast, the organic light emitting diode display device has the characteristics of wide viewing angle, rapid response speed, thin panel, flexibility and the like; further, the organic light emitting diode display device does not need a backlight nor a color filter, and can be made larger in size.

The display device of the liquid crystal and the organic light emitting diode usually uses transparent glass as a substrate, and then components such as a thin film transistor, a lower electrode layer, a display medium layer, an upper electrode layer and the like are formed on the substrate in sequence. The state of the display medium can be controlled by controlling the voltage or current applied to the upper electrode layer and/or the lower electrode layer by the thin film transistor.

In the above display device, gray scale representation is achieved by controlling the drive transistor of each pixel circuit and the magnitude of the voltage or current supplied to the display medium. In different display pixel units in the display device, the characteristic of the driving transistor can be changed due to the deviation of boundary voltages of the driving thin film transistors, and the gray scale performance can not be accurately controlled by the voltage or current, so that the gray scale difference is inconsistent when displaying images and the brightness of the images is uneven. In order to mitigate the effect of variations in the drive transistors on the gray scale performance of the display, a novel and accurate digital drive pixel circuit and display device are provided to improve the performance of displaying gray scales.

Disclosure of Invention

An embodiment of a providing pulse width modulated voltage and/or current driven pixel circuit includes a data latch coupled to a data line for receiving pixel data, and a scan line for receiving a scan signal, a Pulse Width Modulation (PWM) generator coupled to the data latch, the scan line and counter configured to generate PWM signals from the pixel data, the scan signal and counter code generated by the counter generating PWM signals to accurately present gray scale of a display by accurately controlling timing of voltage and/or current driving pixel brightness.

Another embodiment provides a pulse width modulated voltage and/or current driven pixel circuit including a scan line coupled to receive a scan signal, a data line to receive pixel data, a start line to receive a start signal of the PWM generator, a Pulse Width Modulated (PWM) generator to receive a clock line of a clock signal, the clock signal and the pixel data configured to generate Pulse Width Modulated (PWM) signals according to the scan signal, the start signal, the clock signal and the pixel data to accurately represent gray scales of a display with precisely controlling a time length of voltage and/or current driving pixel brightness. The data latches, various Pulse Width Modulation (PWM) generators, counters, etc., are fabricated by a series of semiconductor fabrication processes (exposure, development, etching, diffusion, deposition, ion implantation, cleaning, inspection, and other process steps) on at least silicon wafers, III-V compounds, glass, quartz, flexible organics, inorganics, metals, metal compounds, polymers, graphite substrates, and combinations thereof.

Another embodiment provides a display device including a plurality of data lines, a source driver coupled to the plurality of data lines and configured to output pixel data to the plurality of data lines, a plurality of scan lines, a scan driver coupled to the plurality of scan lines for outputting scan signals to the plurality of scan lines, and a plurality of pixel circuits. Each pixel circuit includes a transistor coupled to a corresponding data line for receiving pixel data and a corresponding scan line for receiving a scan signal, and a data latch coupled to the transistor and configured to receive and latch the pixel data.

These and other objects of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures and the accompanying drawings. These and other objects of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.

Drawings

Fig. 1 is a schematic diagram of a pixel circuit according to an embodiment of the invention.

Fig. 1A is a detailed diagram of the pixel circuit of the embodiment of the invention in fig. 1.

Fig. 2 is a schematic diagram of a pixel circuit according to another embodiment of the invention.

Fig. 2A is a detailed view of the pixel circuit of fig. 2 according to another embodiment of the present invention.

Fig. 3A is a voltage driving diagram of the pixel circuit according to the present invention in fig. 1 and 2.

Fig. 3B is a current driving diagram of the pixel circuit according to the present invention in fig. 1 and 2.

Fig. 4A is an operation waveform diagram of a frame period of the pixel circuit according to the present invention in fig. 1.

Fig. 4B is an operation waveform diagram of a frame period of the pixel circuit according to the present invention in fig. 2.

Fig. 5 is an operation waveform diagram of the reverse operation of the pixel circuit according to the present invention in fig. 1A.

Fig. 6 is a schematic diagram of a display device according to an embodiment of the invention.

Fig. 7A is a schematic cross-sectional view of a pixel unit of the display device in fig. 6 according to an embodiment of the invention.

Fig. 7B is another schematic cross-sectional view of the pixel unit of the display device in fig. 6 according to an embodiment of the invention.

Fig. 8 is a schematic diagram of a display device according to another embodiment of the invention.

Fig. 9A is a schematic diagram illustrating a source driver of a display device according to an embodiment of the present invention in fig. 8.

Fig. 9B is a schematic diagram of fig. 8 showing a source driver of a display device according to another embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be provided in terms of various implementations, but it should be noted that the embodiments described below are merely illustrative and exemplary, and are not intended to limit the present invention to the environments, applications, structures, processes or steps described herein. In the drawings, elements not directly related to the present invention have been omitted. In the drawings, the dimensional relationships between the components are for ease of description only and are not intended to limit the actual dimensional scale of the invention. In the following description, identical (similar or analogous) reference numerals correspond to identical (similar or analogous) components, unless otherwise specified.

Fig. 1 is a diagram of a pixel circuit 100A according to an embodiment of the present invention. The pixel circuit 100A may include a data latch 102 coupled to a data line DL for receiving pixel data PD and a scan line SL for receiving a scan signal SS, and a pulse width modulation (pulse width modulation, PWM) generator 104A coupled to the data latch 102, the scan line SL, and a counter C1 for generating a pulse width modulation generator (PWM) signal PWS based on the pixel data PD, the scan signal SS, and a counter code CC1 generated by the counter. The data latch 102 controls transmission of the pixel data PD according to the scan signal SS. The counter C1 may generate a counter code CC1 according to a clock signal CLK. Further, the counter C1 may receive a reset signal RSTB to start a counting period. The PWM-generated PWM signal PMS may be directly electrically connected to the pixel display medium module DMM whenever the PWM generator 104A has sufficient driving capability to fully control the display state of the smaller load of the pixel electrode. The pixel circuit 100A may further include a driving circuit 108, the driving circuit 108 being configured to generate a pixel signal PS for increasing driving capability to control a display state of the larger load pixel electrode E1 (refer to fig. 7A/7B), the driving circuit 108 being electrically coupled to the PWM generator 104A may include a CMOS (complementary metal oxide semiconductor, N-type and/or P-type MOS (metal oxide semiconductor, metal oxide semiconductor) transistor and combinations thereof, and the pixel electrode E1 of the pixel display medium module DMM may be generated according to the PWM signal PMS. The driving circuit 108 may select a liquid crystal display medium using a voltage mode or a voltage-current mode, for example, the organic light emitting diode OLED may be electrically coupled to the pixel electrode of the display medium module DMM according to characteristics of the display medium in the display medium module DMM, to drive the display medium for a period of time by precisely controlling a voltage and/or a current value, so as to accurately represent a gray scale of the display.

Fig. 1A is a detailed schematic diagram of the pixel circuit 100A of the embodiment of the invention in fig. 1. The PWM generator 104A includes a data comparator 110, an inversion controller 111, a latch 112, and a voltage level converter 113. The power supply voltage is a low power supply voltage VDDL for the data latch 102, the counter C1, the data comparator 110, the inversion controller 111, the latch 112, and the like, and the power supply voltage of the voltage level shifter 113 is a high power supply voltage VDDH. The counter C1 is electrically coupled to the reset signal line RSTBL for receiving the reset signal RSTB and the clock signal line CLK for receiving the clock signal CLK, and the counter code CC1 is generated according to the reset signal RSTB and the clock signal CLK, and the counter code CC1 is continuously counted up or down, for example, "0000000000" is CC1_0, "0000000001" is CC1_1.cc1_256"0100000000" …, CC1_512"1000000000" …, and CC1_1023 is "1111111111", but is not limited thereto.

The inversion controller 111 of the pixel circuit 100A of the embodiment may selectively drive the LCD display using row, column and dot inversion frame modes. The data comparator 110 includes a first input node electrically coupled to the data latch 102 for receiving pixel data PD, and the counter C1 is electrically connected to a second input node for receiving the counter code CC1 and an output node for outputting a PWM STOP signal STOP. The inverter controller 111 includes a first input node electrically coupled to the scan line SL for receiving the scan signal SS, a second input node electrically coupled to the data comparator 110 for receiving the PWM STOP signal STOP, the first output node for outputting a SET signal set_latch, and a second output node for outputting a RESET signal reset_latch. The latch 112 includes a signal PMS electrically coupled to a SET node of the inversion controller 111 for receiving the SET signal set_latch to enable pulse width modulation PWM; a RESET node electrically connected to receive the RESET signal reset_latch for stopping the PWM signal PMS of the inversion controller 111. A first output node Q for outputting the latch signal q_latch to the non-inverting input node of the voltage level shifter 113 and a second output node QB for outputting the inverted latch signal qb_latch to the inverting input node of the voltage level shifter 113. The latch signal q_latch is a PWM signal and the inverted latch signal qb_latch is an inverted PWM signal. The output node Q may be directly electrically connected to the pixel display medium module DMM, for example, a smaller pixel electrode load (not shown) of the pixel display medium module DMM, or a shift from the low power supply VDDL to the high power supply VDDH of the level shifter 113 to increase the driving voltage level of the load to control the display state pixel electrode E1 of the higher load in the display medium module DMM (refer to fig. 7A and 7B), as long as the voltage level of the latch signal q_latch is sufficiently large enough to fully control the state of the pixel electrode. In addition, the other digital circuit includes a set signal for activating the PWM signal and a reset signal for terminating the PWM signal, the width that can be used to generate the PWM output signal PMS is not limited to the width that the PWM output signal PMS is generated using only the latch 112. The level shifter 113 includes a non-inverting input node electrically coupled to the latch 112 for receiving the latch signal Q_latch, an inverting input node electrically coupled to the latch 112 for receiving the inverted latch signal QB_latch, and an output node electrically coupled to the driving circuit 108 for increasing the PMS output voltage level of the PWM.

Fig. 2 is a schematic diagram of a pixel circuit 100B according to another embodiment of the invention. The pixel circuit 100B includes: a Pulse Width Modulation (PWM) generator 104B, wherein the PWM generator 104B comprises: the display device comprises a scanning line SL electrically coupled to receive a scanning signal SS, a plurality of data lines DL for receiving pixel data PD, a START line STARTL for receiving a START signal START of the (PWM) generator, and electrically connected with a clock line CLKL for receiving a clock signal CLK, and generates pulse width according to the scanning signal SS, the START signal START, the clock signal CLK and the pixel data PD to adjust the PMS signal of the PWM, and the gray scale of the display device is accurately presented by precisely controlling the magnitude of voltage and/or current values for driving the display medium for a period of time. The PWM-generated pulse width modulation signal PMS may then be directly electrically coupled to the pixel display media module DMM whenever the PWM generator 104B has sufficient driving capability to fully control the display state of the smaller pixel electrode load (refer to fig. 7A and 7B). Wherein the pixel circuit 100B further comprises: the driving circuit 108, wherein the driving circuit 108 is electrically coupled to the PWM generator 104B and generates a pixel signal PS electrically coupled to the pixel electrode of the display media module DMM according to the PWM signal of the PWM in the voltage and/or current mode (as previously shown in fig. 1).

Fig. 2A is a detailed diagram of a pixel circuit 100B according to another embodiment of the invention shown in fig. 2. The PWM generator 104B includes a counter C2, a digital code detector 103, a 111, a latch 112 and a voltage level converter 113. Wherein the counter C2 includes: a connection node electrically connected to the clock signal line CLKL for receiving the clock signal CLK, a connection node electrically connected to the START signal line STARTL for receiving the START signal START, another connection node electrically connected to the plurality of data lines DL for receiving the pixel data PD, and an output node for generating the counter code CC2 according to the pixel data PD and the clock signal CLK. The counter C2 may continuously increment or decrement the count. For example, the counter code CC2 continues to increment, for example, CC2_0 is "0000000000", CC2_1 is "0000000001" … CC2_2256 is "0100000000" … CC2_512 is "1000000000" … CC2_1023 is "1111111111", but is not limited thereto. The digital code detector 103 includes a plurality of nodes electrically coupled to the counter C2 for receiving count code detection, and generates the output node root of the PWM STOP signal STOP according to the counter code CC 2. For example, the pixel data PD is 10 bits of data, the binary bit component is "0100000000", 256 is indicated by the decimal bit component, the binary bit component of the pixel data PD is loaded into the counter, and then the counter code CC2 is reduced from 256 counts to 0. The PWM STOP signal STOP is generated in the output node of the digital code detector 103 every time the counter code CC2 counts to 0. The inversion controller 111 is electrically coupled to the digital code detector 103, and is configured to receive the PWM stop signal stop as a second input node, and the other connection and operation mode have the same function as the inversion controller 111. The connection and operation of the latch 112 and the voltage level shifter 113 are the same as those described in fig. 1A, and duplicate illustration is omitted.

Fig. 3A is a voltage driving diagram of the pixel circuits 100A and 100B in fig. 1 and 2 according to the embodiment of the present invention. The driving circuit 108 includes, but is not limited to, a CMOS (complementary metal oxide semiconductor) inverter 108A for controlling the transmission of PWM signals and generating a pixel signal PS electrically coupled to the pixel electrode of the pixel display medium module DMM. In addition, it may comprise at least one drive circuit of a combination of N-type or P-type MOS (metal oxide semiconductor) transistors and other drive circuits.

The source node VP of the PMOS transistor of the CMOS inverter 108A is driven by the high supply voltage VDDH or the common voltage Vcom, and the other source node VN of the NMOS transistor of the inverter is driven by the common voltage Vcom or the low voltage VSS. The common voltage Vcom may be an average value of the high power supply voltage VDDH and the low voltage VSS. For example, the high power supply voltage VDDH may be 5V. The low voltage VSS may be 0V and the common voltage Vcom may be 2.5V.

Fig. 3B is a current driving diagram of the pixel circuits 100A and 100B in fig. 1 and 2 according to the embodiment of the present invention. The driving circuit 108 includes a voltage-to-current conversion driver 108B having a current source/sink Idc and converts the PWM voltage signal to a current pixel signal PS electrically coupled to the pixel display medium module DMM, but is not limited thereto. Still further, a driver circuit may include at least one of N-type or P-type MOS (metal oxide semiconductor ) transistors in combination with other driver circuits.

Fig. 4A is a waveform diagram of the operation of the pixel circuit 100A of fig. 1 for two frame periods in the present invention. In this embodiment, the input pixel data PD is 10 bits of data, for example, 256 bits in decimal bit composition when binary bits are "0100000000". In the first frame period and the second frame period, the input pixel data PD has a binary bit composition of "0100000000" when expressed as 256 decimal and has a binary bit composition of "1000000000" when expressed as 512 decimal. At time t0, the counter C1 receives the low pulse reset signal RSTB to reset the counter code CC1 and starts a count period of the first frame driving operation. The data latch 102 receives a scan signal SS pulse during a period from t0 to t1 to collect the pixel data PD and maintain the pixel data until a next scan signal SS pulse is received at instant t 3. The pulse scan signal SS is also sent to the PWM generation 104A, the PWM pulse signal PMS is pulled to the high voltage VDD at the timing of t0, and the driving circuit 108 also drives the corresponding pixel signal PS to the high voltage VDD. The counter C1 may continue to increment or decrement the count throughout the count period, e.g., the counter code CC1 continues to increment, cc1_0 is "0000000000", cc1_1 is "0000000001" … cc1_256 is "0100000000" … cc1_512 is "1000000000" … cc1_1023 is "1111111111". At time t2, when the counter code CC1 matches the pixel data PD (in the case of 256 for the first frame period), the PWM generator 104A completes the PWM pulse and pulls the PWM signal PMS from the high voltage VDD to the low voltage VSS low voltage. The VSS is sent to the driving circuit 108, and then the driving circuit 108 outputs the pixel signal PS in a voltage mode or a voltage-to-current mode to drive the corresponding display pixel to the low voltage VSS. As shown in fig. 4A, the width of the PWM pulse is a period from t0 to t 2. At time t3, the counter C1 receives another low pulse reset signal RSTB to reset the counter C1 and start another counting period of another frame period. The data latch 102 receives new next pixel data PD from t3 to t4 and latches the next pixel data until the next pulse scan signal SS is received at instant t 6. The data latch 102 sends the next new pixel data PD to the PWM generator 104A. The pulse scan signal SS is also sent to the PWM generator 104A, which starts the PWM pulse signal PMS to be pulled to the high voltage VDD at time t3, and the driving circuit 108 drives the corresponding display pixel signal PS to the high voltage VDD. The counter code CC1 continues to increment throughout the counting cycle as described above. At time t5, when the counter code CC1 matches the pixel data PD (512 in the case of the second frame period), the PWM generator 104A completes the PWM pulse and pulls the PWM signal PMS from the high voltage VDD to the low voltage VSS low voltage. The VSS is sent to the driving circuit 108, and then the driving circuit 108 outputs the output pixel signal PS in the voltage mode or the voltage-to-current mode, driving the corresponding display pixel to the low voltage VSS. As shown in fig. 4A, the PWM pulse has a width from t3 to t5. At time t6, the counter C1 receives another low pulse reset signal RSTB to reset the counter C1 and starts another counting period of another frame period. This operation repeats the frame cycle count as described above.

In the embodiment of fig. 4A, the period of the entire pulse frame of the PWM signal PMS is from time t0 to time t3, and then from time t3 to time t6, each of the entire pulse frame periods is 1024 units. An example of the PWM pulse width of the first frame period is 256 units from time t0 to time t2, and an example of the PWM pulse width of the second frame period is 512 units from time t3 to time t5. In the present embodiment, one unit represents a clock cycle in the clock signal CLK, and thus 1024 units may be 1024 clock cycles. Each clock width may be converted to a pixel gray level or a plurality of clock widths may be converted to a pixel gray level, but is not limited thereto. The 256 cells may be presented as relatively dark gray scale pixels (lower pixel brightness) and 768 cells may be presented as relatively bright gray scale pixels (higher pixel brightness) and vice versa.

Fig. 4B is a waveform diagram of the operation of the pixel circuit 100B of fig. 2 for two frame periods in the present invention. The input pixel data PD corresponds to "0100000000" and "1000000000" in the first frame period and the second frame period, respectively. At time t0, the PWM generator 104B receives a START signal START to START the PWM pulse signal PMS and counts the frame period of the first frame cycle operation. The driving circuit 108 pulls the corresponding display pixel drive to the high voltage VDD. During the period t0 to t1, the PWM generator 104B receives the scan signal SS, and then loads the pixel data PD to determine the width of the PWM pulse. At time t2, when a clock period is counted by PWM generator 104B and matches the pixel data PD (256 in the case of the first frame period), the PWM generator 104B ends the PWM pulse and pulls the PWM signal PMS from high voltage VDD to low voltage VSS. The low voltage VSS is transmitted to the driving circuit 108, and then the driving circuit 108 outputs the pixel signal PS in the voltage mode or the voltage-to-current mode to drive the corresponding display pixel to the low voltage VSS. As shown in fig. 4B, the PWM pulse width and the pixel signal PS width are the cycle times from t0 to t 2. At time t3, the PWM generator 104B receives another START signal START to START the PWM pulse signal PMS and STARTs the operation of generating another PWM signal in another frame. The following is similar to the first frame period PWM described above. The PWM generator 104B receives new pixel data PD during a period from t3 to t 4. The PWM generator 104B initiates a PWM pulse at time t3 and the driver circuit 108 drives the corresponding display to the high voltage VDD. At time t5, the clock period is counted by PWM generator 104B and matches pixel data PD (512 in the case of the first frame period). The PWM generator 104B ends the PWM pulse and pulls the PWM signal PMS from the high voltage VDD to the low voltage VSS. The low voltage VSS is transmitted to the driving circuit 108, and then the driving circuit 108 outputs the pixel signal PS in the voltage mode or the voltage-to-current mode to drive the corresponding display pixel to the low voltage VSS. As shown in fig. 4B, the PWM pulse width and the pixel signal PS width are t3 to t5. At time t6, the PWM generator 104B receives another START signal START to START the PWM pulse signal PMS and STARTs generating another PWM period, which is a repetition period count as described above.

Fig. 5 is a waveform diagram illustrating two frame periods of operation of the pixel circuit 100A of fig. 1 according to another embodiment of the present invention. In a first frame period from t0 to t4, the inversion signal INV is a low voltage and the pixel circuit 100A performs a negative polarity driving operation; during the second frame period from t5 to t8, the inversion signal INV is at a high level and the pixel circuit 100A performs a positive polarity driving operation. During a negative polarity driving operation, the source node VP of the PMOS transistor of the driving circuit 108 is driven by the common voltage Vcom, and the other source node VN of the NMOS transistor of the driving circuit 108 is driven by the low voltage VSS; during a positive polarity driving operation, the source node VP of the PMOS transistor of the driving circuit 108 is driven by the high power supply voltage VDDH, and the other source node VN of the NMOS transistor of the driving circuit 108 is driven by the common voltage Vcom. In the present embodiment, the input pixel data PD is 10 bits of data, for example, "0100000000" is binary and its decimal is 256. At time t0, the counter C1 receives the low pulse reset signal RSTB to reset the counter code CC1 and starts the counting period of the first frame driving operation. The pulse scan signal SS is transmitted to the data latch 102 during a period from t0 to t 1. When the inversion signal INV is VSS, the pulse scan signal SS is also transmitted to the Set Latch node set_latch of the Latch 112 through the inverter controller 111 in the period t0 to t 1. The latch 112 outputs the low power supply voltage VDDL at the output node Q and the low voltage VSS at the output node QB. The non-inverting input node and the inverting input node of the voltage level shifter 113 receive the low power supply voltage VDDL and the low voltage signal VSS, respectively. The voltage level shifter 113 boosts the output signal PMS from the low voltage VSS to the high power supply voltage VDDH. Since the driving circuit 108 outputs the pixel signal PS according to the PWM signal PMS, the pixel signal PS is pulled from the common voltage Vcom to the low voltage VSS at time t0 for negative polarity driving. The data latch 102 receives the pixel data PD during a period from t0 to t1, and latches the pixel data until the next pulse scanning signal SS is received at time t 4. At the same time, the data latch 102 transfers the pixel data PD to the data comparator 110.

At time t2, when the counter code CC1 matches the pixel data PD (in the case where the first frame period is 256), the data comparator 110 outputs a STOP pulse width signal during times t2 and t 3. As shown in fig. 5, the data comparator 110 pulls the STOP signal of the comparator from the low voltage VSS to the low power supply voltage VDDL at time t2, and pulls the STOP signal of the comparator from the low power supply voltage VDDL to the low voltage VSS at time t 3. The pulse of the comparator STOP signal is transferred to the reset node of latch 112. The latch 112 resets the output node Q to the low voltage VSS and pulls up the output node QB to the low supply voltage VDDL. The non-inverting input node and the inverting input node of the voltage level shifter 113 receive the low voltage VSS and the low power supply voltage VDDL, respectively. The voltage level shifter 113 pulls the output signal PMS from the high power supply voltage VDDH to the low voltage VSS. The driving circuit 108 pulls the output signal PS from the low voltage VSS to the common voltage Vcom to be negative polarity-driven at time t 2. The period from t0 to t2 is the PWM width time of the negative polarity driving operation, at which the driving voltage PS is the low voltage VSS.

At time t4, the counter C1 receives another low pulse reset signal RSTB to reset the counter C1 and starts adjusting another frame cycle driving operation. The pulse scan signal SS is transmitted to the data latch 102 during the period of t4 to t 5. And the inversion signal INV is VDDL, the pulse scan signal SS is also transmitted to the reset node of the latch 112 through the inversion controller 111 in the period from t4 to t 5. The latch 112 outputs a low signal VSS at the output node Q and a low power supply voltage VDDL at the output node QB. Since the non-inverting input node and the inverting input node of the voltage level shifter 113 receive the low voltage VSS and the low power supply voltage VDDL, respectively, the voltage level shifter 113 maintains the output signal PMS at the low voltage VSS. The PMOS transistor of the driver circuit 108 is still on, but the source node VP of the PMOS transistor is driven by the high supply voltage VDDH. Therefore, the pixel signal PS will be pulled up to the high supply voltage VDDH at time t4 in the positive polarity driving operation. The data latch 102 receives the pixel data PD during a period from t4 to t5, and latches the pixel data PD before receiving the next pulse scan signal SS. The data latch 102 sends the pixel data PD to the data comparator 110. At time t6, when the counter code CC1 matches the pixel data PD (256 in the case of the second frame period), the data comparator 110 outputs a comparator signal STOP pulse between t6 and t 7. As shown in fig. 5, the data comparator 110 pulls the comparator signal STOP from the low voltage VSS to the low power supply voltage VDDL at time t6, and pulls the comparator signal STOP from the low power supply voltage VDDL to the low voltage VSS at time t 7. The comparator signal STOP pulse is transmitted to the set node of latch 112. The latch 112 sets the output node Q to the low supply voltage VDDL and pulls down the output node QB to the voltage VSS. The non-inverting input node and the inverting input node of the voltage level shifter 113 receive the low power supply voltage VDDL and the low voltage VSS, respectively. The voltage level shifter 113 pulls the output signal PMS from the low voltage VSS to the high power supply voltage VDDH. At time t6, the driving circuit 108 pulls the output signal PS from the high power voltage VDDH to the common voltage Vcom to drive in positive polarity. The period PWM from the period between t4 and t6 is used for the positive polarity driving operation, during which the driving voltage PS is the high power supply voltage VDDH. The following period is similar to the previous counting period. At time t8, the counter C1 receives another low pulse reset signal RSTB to reset the counter C1 and starts another counting period. The operations described above are replicated.

In the embodiment of fig. 5, the pulse frame period of the pixel signal PS is 1024 units from time t0 to time t4 and then from time t4 to time t 8. The pulse width is 256 units from time t0 to time t2 and from time t4 to time t 6. In the present embodiment, one unit represents a clock cycle in the clock signal CLK, and thus 1024 units may be 1024 clock cycles. Each clock width may be converted into a pixel gray scale or a plurality of clock widths may be converted into a pixel gray scale, but is not limited thereto. Although in the present embodiment the pixel data for both count periods is the same, in some other embodiments the pixel data may be different for different count periods. For example, a clock width of 256 cells may appear as relatively dark gray scale pixels (lower pixel brightness) during a first frame period, and a clock width of 768 cells appear as relatively bright gray scale pixels (higher pixel brightness) during a second frame period, and vice versa.

Fig. 6 is a diagram of an exemplary display device 200 of the pixel circuit 100A of fig. 1 and the second pixel circuit 100B of fig. 2 in the present invention. The display device 200 includes a plurality of data lines DL1 to DL4, a plurality of scan lines SL1 to SL2, a scan driver 220, a source driver 210, a power driver 230, a plurality of pixel circuits 100 (1, 1) to 100 (2, 4), and a plurality of counters C1 to C2. The source driver 210 is electrically coupled to the plurality of data lines DL1 to DL4 and configured to output the pixel data PD to the plurality of data lines DL1 to DL4. The scan driver 220 is electrically coupled to the plurality of scan lines SL1 to SL2 and configured to output a scan signal SS to the plurality of scan lines SL1 to SL2. The plurality of counters C1 to C2 are set to generate a plurality of counter codes CC1 and CC2. Each pixel circuit 100 controls the brightness of a pixel cell on the display device 200.

The power driver 230 is electrically coupled to the plurality of pixel circuits 100 (1, 1) to 100 (2, 4) of the driving circuit 108. The power driver 230 supplies a high power supply voltage VDDH, a common voltage Vcom, and a low voltage VSS to drive the plurality of pixel circuits from 100 (1, 1) to 100 (2, 4). The source driver 210 includes a plurality of shift registers 212 shifted by a clock signal CLK; a plurality of input registers 214 electrically coupled to the shift register 212, and a plurality of data latches 216 electrically coupled to the input registers 214 and receiving image data according to a clock signal CLK, and latching the image data received from the input registers 214 according to a load signal.

Fig. 7A is a cross-sectional view of the pixel unit 12PU of the display device 200 in accordance with the embodiment of the present invention in fig. 6. The pixel unit 12PU comprises a display medium module DMM and a pixel circuit 100. The pixel circuit 100 of the pixel unit is prefabricated and then assembled to the display medium module DMM of the pixel unit 12PU to complete the pixel unit 12PU. In other words, the pixel circuit 100 is not directly manufactured on a portion of the display medium module DMM, but the pixel circuit 100 is manufactured separately on another substrate; therefore, the manufacturing process conditions of the pixel circuit 100 are not limited by the substrate characteristics (e.g., heat resistance of the substrate material) of the display medium module DMM. The substrate of the pixel circuit 100 may allow for more flexibility in integrating other functional component transistors, such as, but not limited to, touch sensing functionality, image capturing functionality, memory functionality, control functionality, wireless communication functionality, self-luminescence functionality, passive components (inductors, resistors, capacitors, or combinations thereof), photovoltaic functionality, and any combination thereof, on the pixel circuit 100 substrate. In addition, the transistor characteristics of the pixel circuit 100 may be optimized to improve uniformity, functionality, lower manufacturing cost and production time, etc., to realize a high performance display device by a semiconductor manufacturing process. The display medium module DMM includes a first electrode E1, a second electrode E2, and a display medium DMU controlled by the pixel circuit 100 using voltage or current modulation (only one pair of electrodes and display medium is shown in fig. 7A, but not limited thereto, and a plurality of pairs of electrodes and display medium may be employed). The first electrode E1 and the second electrode E2 are separated from each other, and the display medium DMU is disposed between the first electrode E1 (pixel electrode) and the second electrode E2 (common electrode or reference electrode). The pixel signal PMS may be selectively electrically coupled to the first electrode E1 (pixel electrode) of the smaller load directly via the output node of the pulse width modulation generator (PWM) 104A or 104B, or electrically connected to the first electrode E1 of the display media module DMM using the voltage or current driving mode via the pixel signal output node PS of the driving circuit 108.

Fig. 7B is a schematic cross-sectional view of the pixel unit 12PU of the display device 200 in fig. 6 according to the embodiment of the invention. The pixel unit 12PU comprises a display medium module DMM and a pixel circuit 100. The display medium module DMM of the pixel unit 12PU is manufactured directly and sequentially according to the manufacturing steps on the same substrate of the pixel circuit 100, and compared with fig. 7A, the pixel unit 12PU is manufactured integrally. In other words, all the composite materials of the display medium module DMM are manufactured completely continuously on the pixel circuit 100 substrate in sequence directly according to the manufacturing steps. The substrate of the pixel circuit 100 is allowed to integrate more flexibly other functional component transistors such as, for example, touch sensing functional elements, image capturing functional elements, memory functional elements, control functional elements, wireless communication functional elements, self-luminous functional elements, passive elements (inductors, resistors, capacitors, or combinations thereof), photovoltaic functional elements, and any combination thereof (but not limited thereto) on the pixel circuit 100 substrate. In addition, transistor characteristics of the pixel circuit 100 may be optimized to improve uniformity, functionality, lower manufacturing costs, production time, etc., to achieve a high performance display device. The display medium module DMM includes a first electrode E1, a second electrode E2, and a display medium DMU controlled by the pixel circuit 100 using voltage or current modulation (only one pair of electrodes and display medium is shown in fig. 7A, but not limited thereto, and a plurality of pairs of electrodes and display medium may be employed). The first electrode E1 and the second electrode E2 are separated from each other, and the display medium DMM is disposed between the first electrode E1 (pixel electrode) and the second electrode E2 (common electrode or reference electrode). The pixel signal PMS may be selectively electrically coupled to the first electrode E1 (pixel electrode) of the smaller load directly via the output node of the pulse width modulation generator (PWM) 104A or 104B, or electrically connected to the first electrode E1 (refer to fig. 7A/7B) of the display media module DMM using the voltage or current driving mode via the pixel signal output node PS of the driving circuit 108.

The display medium DMU of fig. 7A and 7B includes a self-luminous medium material, a non-self-luminous material, a filter material, a conductive material, an insulating material, a light absorbing material, a reflective material, a light refracting material, a polarizing material, a light diffusing material, and at least one of the foregoing materials. Wherein the non-self-luminescent dielectric material may comprise at least one of an electrophoretic material, an electrofluidic material, a liquid crystal material, a microelectromechanical reflective material, an electrowetting material, an electroink material, a magnetic fluidic material, an electrochromic material, and a thermochromic material. The self-luminescent dielectric material may comprise at least one of an electroluminescent material, a photoluminescent material, a cathodoluminescent material, a field emission luminescent material, a phosphorescent material, a fluorescent material, and a light emitting diode material for producing white, green, blue, orange, indigo, violet, and yellow or combinations thereof.

Fig. 8 is a schematic diagram of a display device 300 according to another embodiment of the invention. The display device 300 includes a plurality of data lines DL1-DL3, a source driver 310 electrically coupled to the data lines DL1 to DL3 to output pixel data PD from DL1 to DL3 to the data lines, a plurality of scan lines SL1 to SL3, a scan driver 320 electrically coupled to the scan lines SL1 to SL3, and outputting the scan signal SS to the scan lines SL1 to SL3 having a plurality of pixel circuits 400 (1, 1) to 400 (3, 3). Each pixel circuit 400 (1, 1) through 400 (3, 3) includes a transistor 401 electrically coupled to the corresponding data line DL for receiving pixel data PD and the corresponding scan line SL for receiving scan signal SS, and a latch 402 (which may be any digital circuit of a basic capacitor, a NAND logic gate, a NOR logic gate, a register, a memory, or a combination thereof, but is not limited thereto) electrically coupled to the transistor 401 for receiving and latching pixel data PD. The pixel circuits 400 (1, 1) through 400 (3, 3) may include a drive circuit 404 electrically coupled to the data latch 402, the drive circuit 404 generating the pixel signal PS based on the pixel data PD. In this embodiment, the driving circuit 404 may be at least one of CMOS (complementary metal oxide semiconductor), N-type and/or P-type MOS (metal oxide semiconductor) transistors, and combinations thereof. The display device 300 further includes a power driver 330 electrically coupled to the driving circuits 404 of the pixel circuits 400 (1, 1) to 400 (3, 3) to provide the high supply voltage VDDH, the common voltage Vcom and the low voltage VSS to the driving circuits 404. The common voltage Vcom may be an average value of the high power supply voltage VDDH and the low voltage VSS.

Fig. 9A is a schematic diagram of the source driver 310 of fig. 8 according to the present invention. The source driver 310 includes a plurality of shift registers 312, a plurality of input registers 314, a plurality of data latches 316, a counter 317, a plurality of Pulse Width Modulation (PWM) generators 318, and a plurality of driving circuits 319 (optional). The shift register 312 is configured to receive a shift clock signal CLK. The input register 314 is electrically coupled to the shift register 312 and receives image data according to a clock signal CLK. The data latch 316 is electrically coupled to the input register 314, and latches image data from the input register 314 according to a loading signal. The counter 317 generates a count code CC. The PWM generator 318 is electrically coupled to the data latch 316 and the counter 317 for generating PWM signals based on the image data and the counter code CC. The driving circuit 319 is electrically coupled to the PWM generator 318 and the data lines DL1-DL3 (as shown in FIG. 8), and the pixel data PD is generated according to the PWM signal PWM. If the source driver 310 does not include a plurality of driving circuits 319, the PWM generator 318 will directly generate the pixel data PD from the image data and the counter code CC. Similarly, the pixel circuits 400 (1, 1) to 400 (3, 3) of the pixel circuit 100 in fig. 7A can also output the pixel signal PS to the first electrode E1 of the display medium module DMM of fig. 7A. The pixel circuits 400 (1, 1) to 400 (3, 3) may drive the pixel unit 12PU according to similar operation waveforms from fig. 4A to 5.

Fig. 9B is a schematic diagram of another source driver 310A according to another embodiment of the invention. The source driver 310 in fig. 8 may be implemented by the source driver 310A in fig. 9B. The source driver 310A includes: a plurality of shift registers 312, a plurality of input registers 314, a plurality of data latches 316, a plurality of pulse width modulation generators (PWM) 318 including a counter, a digital code detector, and a START signal line for receiving a START signal; which may be an incremented or decremented counter, if the incremented counter code CC2 is to be incremented, the digital code detector includes a plurality of nodes electrically coupled to the counter C2 for code detection, and a plurality of driving circuits 319 (optional) for generating a PWM STOP signal STOP (as shown in fig. 2A) based on the output node of the counter C2. The shift register 312 is configured to receive a shift clock signal CLK. The input register 314 is electrically coupled to the shift register 312 and receives the image data according to the clock signal CLK. The data latch 316 is electrically coupled to the input register 314 and latches the image data from the input register 314 according to the loading signal. The PWM generator 318 is electrically coupled to the data latch 316 for generating a PWM signal based on the image data and a START signal START of the PWM generator. The driving circuit 319 is electrically coupled to the PWM generator 318 and the data lines DL1-DL3 (shown in FIG. 8), and the pixel data PD generated according to the PWM signal. If the source driver 310 does not include a plurality of driving circuits 319, the PWM generator 318 will directly generate the pixel data PD from the image data and the counter code CC. Similarly, the pixel circuits 400 (1, 1) to 400 (3, 3) of the pixel circuit 100 in fig. 7A can also output the pixel signal PS to the first electrode E1 of the display medium module DMM of fig. 7A. The pixel circuits 400 (1, 1) to 400 (3, 3) may drive the pixel unit 12PU according to similar operation waveforms from fig. 4A to 5.

In summary, embodiments provide a new type of pixel circuit and display device. By employing the operation and control of most digital electronic components and digital signals, the gray scale and brightness accuracy control of the display device is greatly improved.

The foregoing shows technical contents of the pixel circuit and the display device according to the embodiments of the present invention, which are not intended to limit the scope of the present invention. Many modifications and variations of the apparatus and methods will be readily apparent to those skilled in the art while maintaining the teachings of the present invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims

1. A pixel circuit, comprising:

a data latch coupled to a data line for receiving pixel data and a scan line for receiving a scan signal; and

a Pulse Width Modulation (PWM) generator coupled to the data latch, the scan line and the counter and configured to generate a counter code from the scan signal and the counter for generating a pulse width modulated PWM signal based on the pixel data.

2. A pixel cell, comprising:

A pixel circuit as claimed in claim 1; and

a display medium module comprising a first electrode, a second electrode and a display medium;

wherein the first electrode and the second electrode are separated from each other, and the display medium is disposed between the first electrode and the second electrode; and

wherein the PWM signal is output to the first electrode.

3. The pixel cell of claim 2, wherein the display medium comprises at least one of a self-emissive dielectric material, a non-self-emissive dielectric material, a filter material, a conductive material, an insulating material, a light absorbing material, a light reflecting material, a light refracting material, a light deflecting material, a light polarizing material, and a light diffusing material.

4. The pixel circuit of claim 1, further comprising a driver circuit coupled to the PWM generator and configured to generate a pixel signal based on the PWM signal.

5. The pixel circuit according to claim 4, wherein the driving circuit is a CMOS (complementary metal oxide semiconductor) inverter.

6. A pixel cell, comprising:

a pixel circuit as claimed in claim 4; and

wherein the pixel signal is output to the first electrode via the driving circuit.

7. The pixel cell of claim 6, wherein the display medium comprises at least one of a self-emissive dielectric material, a non-self-emissive dielectric material, a filter material, a conductive material, an insulating material, a light absorbing material, a light reflecting material, a light refracting material, a light deflecting material, a light polarizing material, and a light diffusing material.

8. A display device, comprising:

a plurality of data lines;

a source driver coupled to the plurality of data lines and configured to output pixel data to the plurality of data lines;

a plurality of scan lines;

a scan driver coupled to the plurality of scan lines and configured to output scan signals to the plurality of scan lines;

a plurality of counters configured to generate a plurality of counter codes; and

a plurality of pixel cells of the pixel cell of claim 2.

9. The display device of claim 8, further comprising a power driver coupled to the drive circuits of the plurality of pixel circuits configured to provide a high voltage, a common voltage, and a low voltage to the drive circuits of the plurality of pixel circuits;

wherein the common voltage is an average value of the high voltage and the low voltage.

10. The display device according to claim 8, wherein the source driver comprises:

a plurality of shift registers configured to shift a clock signal;

a plurality of input registers coupled to the shift register and configured to receive image data in accordance with the clock signal; and

a plurality of data latches coupled to the input registers and configured to latch image data received from the input registers in accordance with a load signal.

11. The display device according to claim 8, wherein the PWM generator comprises:

a data comparator, comprising:

a first input node coupled to the data latch;

a second input node coupled to the counter; and

an output node; and

A latch, comprising:

a set node coupled to the scan line;

a reset node coupled to the output node of the data comparator; and

an output node coupled to the input node of the drive circuit;

wherein the power driver is further coupled to the data latch, the data comparator and the latch, and is configured to provide the high voltage and the low voltage to the data latch, the data comparator and the latch.

12. A display device, comprising:

a plurality of data lines;

a plurality of scan lines;

a scan driver coupled to the plurality of scan lines and configured to output scan signals to the plurality of scan lines; and

a plurality of pixel units, each of the pixel units comprising:

a pixel circuit, comprising:

a transistor coupled to a corresponding data line for receiving pixel data and a corresponding scan line for receiving a scan signal; and

a data latch is coupled to the transistor and configured to receive and latch the pixel data.

13. The display device of claim 12, wherein the pixel circuit further comprises a drive circuit coupled to the data latch and configured to generate a pixel signal based on the pixel data.

14. The display device according to claim 13, wherein the driver circuit is a CMOS (complementary metal oxide semiconductor) inverter.

15. The display device according to claim 12, wherein the pixel unit further includes a display medium module including a first electrode, a second electrode, and a display medium, the display medium is disposed between the first electrode and the second electrode, and the pixel signal is output to the first electrode through the driving circuit.

16. The display device of claim 15, wherein the display medium comprises at least one of a self-luminescent medium material, a non-self-luminescent medium material, a filter material, a conductive material, an insulating material, a light absorbing material, a light reflecting material, a light refracting material, a light deflecting material, a light polarizing material, and a light diffusing material.

17. The display device of claim 12, further comprising a power driver coupled to the driving circuits of the plurality of pixel circuits and configured to provide a high voltage, a common voltage, and a low voltage to the driving circuits of the plurality of pixel circuits;

18. The display device according to claim 12, wherein the source driver comprises:

a plurality of shift registers for shifting clock signals;

a plurality of input registers connected to the shift register and configured to receive image data in accordance with the clock signal;

a plurality of data latches coupled to the input registers and configured to latch image data received from the input registers in accordance with a load signal;

a counter configured to generate a counter code; and

a plurality of Pulse Width Modulation (PWM) generators coupled to the data latches and the counter and configured to generate PWM signals based on the image data and the counter code.

19. The display device according to claim 18, wherein the source driver further comprises: a plurality of driving circuits coupled to the pulse width modulation generator and the data line, and configured to generate the pixel data to the data line according to the PWM signal.

20. The display device according to claim 12, wherein the pixel unit further comprises a display medium module including a first electrode, a second electrode, and a display medium, wherein the first electrode and the second electrode are separated from each other, and the display medium is disposed between the first electrode and the second electrode, and the pixel data is output to the first electrode.

21. The display device of claim 20, wherein the display medium comprises at least one of a self-luminescent medium material, a non-self-luminescent medium material, a filter material, a conductive material, an insulating material, a light absorbing material, a light reflecting material, a light refracting material, a light deflecting material, a light polarizing material, and a light diffusing material.