CN117691695A - Charging circuit and electronic equipment - Google Patents
Charging circuit and electronic equipment Download PDFInfo
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- CN117691695A CN117691695A CN202311052096.1A CN202311052096A CN117691695A CN 117691695 A CN117691695 A CN 117691695A CN 202311052096 A CN202311052096 A CN 202311052096A CN 117691695 A CN117691695 A CN 117691695A
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Abstract
According to the charging circuit and the electronic device, the main board and the daughter board are connected through the cable, the cable comprises the charging circuit, the reflux circuit and the discharging circuit, the control chip of the main board controls the reflux circuit and the discharging circuit to be connected in parallel under the condition of light load of charging, and the first parallel circuit is formed to serve as a charging loop of the secondary battery; and/or, in the discharging condition, the control backflow line is connected with the charging line in parallel, and the formed second parallel circuit is used as a discharging loop of the secondary battery. The idle time period of the charging circuit and the discharging circuit is fully utilized, the idle discharging circuit and the reflux circuit are controlled by the control chip to be connected in parallel to form a charging loop of the secondary battery under the condition of charging light load, and the idle charging circuit and the reflux circuit are connected in parallel to form the discharging loop of the secondary battery under the condition of discharging, so that the impedance of the reflux circuit is reduced, and the impedance of the charging circuit and the impedance of the discharging circuit are reduced under the corresponding scene, so that the charging and discharging performance of the battery can be improved.
Description
Technical Field
The application relates to the technical field of charging, in particular to a charging circuit and electronic equipment.
Background
The quick charging capability of the mobile phone is important for relieving the charging anxiety of users and improving the user experience, and is also an important competition part of various large mobile phone manufacturers. The charging link impedance is one of the key factors influencing the charging power and the charging time, and the design is limited by physical conditions such as battery, device internal resistance, conductor conductivity, line length, thickness and the like.
For the dual-battery architecture of the mobile phone in the folded form, the batteries on two sides along the folded position are full, the length difference of the charging links on two sides is large, and the impedance of the long link side directly influences the charging current distribution and the maximum charging current of the two batteries, so that the charging performance is influenced.
Disclosure of Invention
An object of the embodiment of the application is to provide a charging circuit and an electronic device, so as to achieve improvement of quick charging performance. The specific technical scheme is as follows:
in a first aspect, embodiments of the present application provide a charging circuit, including:
a main board, a daughter board, and a cable; the main board and the daughter board are connected through the cable; the cable comprises a charging circuit, a reflux circuit and a discharging circuit; the main board comprises a control chip; the main board is used for charging the main battery, and the sub-board is used for charging the auxiliary battery;
The control chip is used for:
under the condition of charging light load, the reflux circuit and the discharge circuit are controlled to be connected in parallel, and a first parallel circuit formed by the reflux circuit and the discharge circuit is used as a charging loop of the secondary battery;
and/or the number of the groups of groups,
in the discharging condition, the reflux line is controlled to be connected with the charging line in parallel, and a second parallel circuit is formed to serve as a discharging loop of the secondary battery.
In one possible implementation manner, the main board further comprises: a first switch sub-circuit, the sub-board comprising a second switch sub-circuit;
a first end of the first switch sub-circuit is connected with a first end of the charging circuit;
a second end of the first switch sub-circuit is connected with a first end of the return line;
the third end of the first switch sub-circuit is connected with the first end of the discharge line;
the first end of the second switch sub-circuit is connected with the second end of the charging circuit;
a second end of the second switch sub-circuit is connected with a second end of the return line;
the third end of the second switch sub-circuit is connected with the second end of the discharge line;
the control chip is used for:
under the condition of light charging load, the second end of the first switch sub-circuit is controlled to be conducted with the third end of the first switch sub-circuit, and the second end of the second switch sub-circuit is controlled to be conducted with the third end of the second switch sub-circuit;
And under the discharging condition, controlling the first end of the first switch sub-circuit to be conducted with the second end of the first switch sub-circuit, and controlling the first end of the second switch sub-circuit to be conducted with the second end of the second switch sub-circuit.
In one possible implementation, the first switching sub-circuit includes a first type of transistor and a second type of transistor; the second switch sub-circuit comprises a first type transistor and a second type transistor; the control chip comprises a first control signal end and a second control signal end;
the first type transistor of the first switch sub-circuit comprises at least 1 first transistor, at least 1 fifth transistor, and the second type transistor of the first switch sub-circuit comprises at least 1 second transistor, at least 1 sixth transistor; the first type of crystal of the second switching sub-circuit comprises at least 1 third transistor, at least 1 seventh transistor, and the second type of crystal of the first switching sub-circuit comprises at least 1 fourth transistor, at least 1 eighth transistor;
the control end of the first transistor, the control end of the second transistor, the control end of the third transistor and the control end of the fourth transistor are connected with the first control signal end;
A first end of the first transistor and a first end of the third transistor are connected with the reflux line;
the first end of the second transistor is connected with one end of the charging circuit; the first end of the fourth transistor is connected with the other end of the charging circuit;
the second end of the first transistor, the second end of the second transistor, the second end of the third transistor and the second end of the fourth transistor are connected;
the control end of the fifth transistor, the control end of the sixth transistor, the control end of the seventh transistor and the control end of the eighth transistor are connected with the second control signal end;
a first end of a fifth transistor and a first end of the seventh transistor are connected with the reflux line;
the first end of the sixth transistor is connected with one end of the discharge circuit; the first end of the eighth transistor is connected with the other end of the discharge line;
the second end of the fifth transistor, the second end of the sixth transistor, the second end of the seventh transistor and the second end of the eighth transistor are connected;
the control chip is used for:
under the condition of light load of charging:
outputting a first level signal through the first control signal terminal to control the first end and the second end of the first transistor to be conducted, the first end and the second end of the third transistor to be conducted, the first end and the second end of the second transistor to be disconnected, and the first end and the second end of the fourth transistor to be disconnected;
Outputting a second level signal through the second control signal terminal, wherein the first terminal and the second terminal of the fifth transistor are disconnected, the first terminal and the second terminal of the seventh transistor are disconnected, the first terminal and the second terminal of the sixth transistor are conducted, and the first terminal and the second terminal of the eighth transistor are conducted;
in the case of discharge:
outputting a second level signal through the first control signal terminal to control the first terminal and the second terminal of the fifth transistor to be on, the first terminal and the second terminal of the seventh transistor to be on, the first terminal and the second terminal of the sixth transistor to be off, and the first terminal and the second terminal of the eighth transistor to be off;
and outputting a first level signal through the second control signal end, wherein the first end and the second end of the first transistor are disconnected, the first end and the second end of the third transistor are disconnected, the first end and the second end of the second transistor are conducted, and the first end and the second end of the fourth transistor are conducted.
In one possible implementation, the first type of transistor of the first switching sub-circuit includes a plurality of first transistors, a plurality of fifth transistors, and the second type of transistor of the first switching sub-circuit includes a plurality of second transistors, a plurality of sixth transistors; the first type of crystal of the second switching sub-circuit comprises a plurality of third transistors and a plurality of seventh transistors, and the second type of crystal of the first switching sub-circuit comprises a plurality of fourth transistors and a plurality of eighth transistors.
In one possible implementation manner, the first type transistor is an N-type MOS transistor, and the second type transistor is a P-type MOS transistor;
the control chip is used for:
under the condition of light load of charging, a low-level signal is output through the first control signal end, and a high-level signal is output through the second control signal end;
under the discharging condition, a high-level signal is output through the first control signal end, and a low-level signal is output through the second control signal end.
In a possible implementation manner, the control chip is further used for:
in other special cases, a low-level signal is sent to the first control signal terminal; and transmitting a low-level signal to the second control signal terminal.
In one possible implementation manner, the first type transistor is a P-type MOS transistor, and the second type transistor is an N-type MOS transistor;
the control chip is used for:
under the condition of light load of charging, a high-level signal is output through the first control signal end, and a low-level signal is output through the second control signal end;
and under the discharging condition, outputting a low-level signal through the first control signal end and outputting a high-level signal through the second control signal end.
In a possible implementation manner, the control chip is further used for:
in other special cases, a high level signal is sent to the first control signal terminal; and transmitting a high-level signal to the second control signal terminal.
In one possible implementation manner, the main board comprises a main charging control chip, a first connector, and the daughter board comprises a secondary charging control chip and a second connector;
the first end of the first connector is connected with one end of the charging circuit; the first end of the second connector is connected with the other end of the charging circuit;
the second end of the first connector is connected with one end of the return line; a second end of the second connector is connected with the other end of the return line;
the third end of the first connector is connected with one end of the discharge line; the second end of the second connector is connected with the other end of the discharge line;
a first end of a first transistor is connected with a fifth end of the first connector, and a first end of the third transistor is connected with a fifth end of the second connector;
the first end of the second transistor is connected with the fourth end of the first connector; the first end of the fourth transistor is connected with the fourth end of the second connector;
The second end of the first transistor, the second end of the second transistor, the second end of the third transistor and the second end of the fourth transistor are connected;
a first end of a fifth transistor is connected with a fifth end of the first connector, and a first end of the seventh transistor is connected with a fifth end of the second connector;
a first end of a sixth transistor is connected with a sixth end of the first connector; a first end of an eighth transistor is connected with a sixth end of the second connector;
the second end of the fifth transistor, the second end of the sixth transistor, the second end of the seventh transistor and the second end of the eighth transistor are connected;
the first end of the first connector is communicated with the fourth end, and the second end of the first connector is communicated with the fifth end; the third end and the sixth end of the first connector are communicated;
the first end of the second connector is communicated with the fourth end, and the second end of the second connector is communicated with the fifth end; the third end of the first connector is conducted with the sixth end.
In one possible embodiment, the first transistor, the second transistor, the fifth transistor, the sixth transistor are located on a side close to a main charge control chip, far from the first connector;
The third transistor, the fourth transistor, the seventh transistor, and the eighth transistor are located on a side close to the sub charge control chip and far from the second connector.
In a second aspect, an embodiment of the present application provides an electronic device, including a charging circuit as described in any one of the foregoing.
The beneficial effects of the embodiment of the application are that:
according to the charging circuit and the electronic device provided by the embodiment of the application, the main board and the daughter board are connected through the cable, the cable comprises the charging circuit, the reflux circuit and the discharging circuit, and the control chip of the main board controls the reflux circuit to be connected with the discharging circuit in parallel under the condition of light load of charging, so that a first parallel circuit formed by the reflux circuit and the discharging circuit is used as a charging loop of the secondary battery; and/or, in the discharging condition, the control backflow line is connected with the charging line in parallel, and the formed second parallel circuit is used as a discharging loop of the secondary battery. The idle time period of the charging circuit and the discharging circuit is fully utilized, the idle discharging circuit and the reflux circuit are controlled by the control chip to be connected in parallel to form a charging loop of the secondary battery under the condition of charging light load, and the idle charging circuit and the reflux circuit are connected in parallel to form the discharging loop of the secondary battery under the condition of discharging, so that the impedance of the reflux circuit is reduced, namely the impedance of the charging circuit and the impedance of the discharging circuit are reduced under the corresponding scene, and the charging and discharging performance of the battery can be improved.
Of course, not all of the above-described advantages need be achieved simultaneously in practicing any one of the products or methods of the present application.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following description will briefly introduce the drawings that are required to be used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other embodiments may also be obtained according to these drawings to those skilled in the art.
Fig. 1-1 is a schematic diagram of a first structure of a mobile phone in a folded configuration in the related art;
fig. 1-2 are schematic views of a second structure of a mobile phone in a folded configuration in the related art;
fig. 1-3 are schematic views of a third structure of a mobile phone in a folded configuration in the related art;
fig. 1-4 are schematic diagrams of charge and discharge circuits of an electronic device with a dual-battery architecture in the related art;
fig. 1-5 are schematic diagrams of charging circuits of an electronic device with a dual battery architecture in the related art;
FIGS. 1-6 are schematic diagrams of discharge lines of related art electronic devices having a dual battery architecture;
FIGS. 1-7 are schematic diagrams of partial signal distribution of charging/supplying lines in the related art;
Fig. 2 is a schematic diagram of a first structure of a charging circuit according to an embodiment of the present application;
fig. 3-1 is a schematic diagram of a second structure of a charging circuit according to an embodiment of the present application;
fig. 3-2 is a schematic diagram of a third structure of the charging circuit according to the embodiment of the present application;
fig. 3-3 are a fourth schematic structural diagram of a charging circuit according to an embodiment of the present application;
fig. 4 is a schematic diagram of a fifth configuration of a charging circuit according to an embodiment of the present application.
Detailed Description
In order to clearly describe the technical solutions of the embodiments of the present application, in the embodiments of the present application, the words "first", "second", etc. are used to distinguish the same item or similar items having substantially the same function and effect. For example, the first instruction and the second instruction are for distinguishing different user instructions, and the sequence of the instructions is not limited. It will be appreciated by those of skill in the art that the words "first," "second," and the like do not limit the amount and order of execution, and that the words "first," "second," and the like do not necessarily differ.
In this application, the terms "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.
Furthermore, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a alone, a and B together, and B alone, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b, and c may represent: a, b, or c, or a and b, or a and c, or b and c, or a, b and c, wherein a, b and c can be single or multiple.
For an electronic device with a dual battery architecture, batteries on the left and right sides of the electronic device need to be fully charged simultaneously, refer to fig. 1-1, fig. 1-1-3 are schematic structural diagrams of a mobile phone with a folded configuration in the related art, the mobile phone with a folded configuration has a dual battery architecture, wherein fig. 1-1 is a first schematic diagram when the mobile phone is unfolded, fig. 1-2 is a second schematic diagram when the mobile phone is unfolded, fig. 1-3 is a schematic diagram when the mobile phone is folded, fig. 1-4 is a schematic diagram of a charge-discharge circuit of the electronic device with a dual battery architecture in the related art, and fig. 1-4 is a schematic diagram of a charging/discharging circuit of the electronic device with a dual battery architecture in the related art, wherein a main FPC (flexible printed circuit board) connects a main board and a sub board, and the main board includes a charging interface Type-C, a protection circuit, a main charging control chip (CHG IC 1), a balancing circuit, and a power conversion chip. The sub-board includes a sub-charge control chip (CHG IC 2). The charging circuit of the electronic device with the dual-battery architecture in the related art is shown in fig. 1-5, the discharging circuit is shown in fig. 1-6, and the whole circuit is shown in fig. 1-7. That is, at the time of charging, the charger is connected to the handset Type-C interface, then to the protection circuit, and the main charge control chip (CHGIC 1), the sub charge control chip (CHGIC 2), then to the main battery by the main charge control chip (CHG-IC 1), and to the sub battery by the sub charge control chip (CHG IC 2), are connected via the protection circuit, respectively. The difference of the charging link lengths of the two sides of the main board side and the daughter board side is large, and the impedance of the long link side directly influences the distribution of charging currents of two batteries and the maximum charging current, so that the maximum charging power and the charging duration are influenced. Wherein the PMU (Power Management Unit ) is used to control the power supply function.
I all : total charging current, I main : main battery charging current, I slave : the secondary battery charge current is supplied to the secondary battery,
R2-R4: main battery charging resistance, R1-R3: secondary battery charging resistance, q is more than 0 and less than 1; i all ＝I main +I slave ；I all ＝I main ×{1+(R1+q×R3)/(R2+q×R4)}。
I main Is determined by the safe charging current of the main battery, I all As the impedance of the secondary battery charging line decreases, the target of the secondary battery charging line is required to meet the charging peak power corresponding current. Under the condition of certain current, the line impedance determines the voltage difference between the battery output and the two ends of the input of the charging control chip, and the insufficient discharging of the battery can be caused by the excessively high impedance.
For the ZD mobile phone charging link, the impedance of the main FPC part is larger, but the impedance design has a larger bottleneck due to the limitation of battery space and shaft penetration space.
In order to greatly reduce the impedance of a charging/power supply link under the condition that the size of the main FPC is unchanged, the quick charging performance is improved. The embodiment of the application provides a charging circuit, as shown in fig. 2, which is a schematic structural diagram of the charging circuit provided in the embodiment of the application, including:
a main board, a daughter board, and a cable; the main board and the daughter board are connected through the cable; the cable comprises a charging circuit, a reflux circuit and a discharging circuit; the main board comprises a control chip; the main board is used for charging the main battery, and the sub-board is used for charging the auxiliary battery;
The control chip is used for:
under the condition of charging light load, the reflux circuit is controlled to be connected with the discharge circuit in parallel, and a first parallel circuit formed by the reflux circuit and the discharge circuit is used as a charging loop of the secondary battery;
and/or the number of the groups of groups,
in the discharging case, the reflux line is controlled to be connected in parallel with the charging line, and a second parallel circuit is formed as a discharging circuit of the secondary battery.
For an electronic device having a dual-battery (main battery, sub-battery) architecture, a charging circuit includes a main board, a sub-board, and a cable, wherein the cable is used for connecting the main board and the sub-board, and the cable includes a charging circuit, a reflow circuit, and a discharging circuit. The main board comprises a control chip, wherein the control chip is connected with the charging circuit, the reflux circuit and the discharging circuit. The control chip can be any circuit and any component with a switching function. For example, the control chip may be a circuit with a switching function designed based on a power switching transistor, for example, a circuit with a switching function designed based on a triode, or the control chip may be a contactor, a relay, or the like. The setting may be specifically performed based on actual conditions, and is not limited herein. For clarity of solution and clarity of layout, a detailed description is provided below in connection with another embodiment. In one example, the cable may be a flexible circuit board, in other examples, the cable may be a collection of multiple wires, and may also be other module boards, which are all within the scope of the present application.
The charging light-load condition is independent of battery power supply (can directly supply power through a charging interface), and the corresponding scene can be standby charging, light-load charging and the like; the scene corresponding to the discharging condition is a state in which the charging wire is not connected. Other special cases refer to application scenes of starting and stopping, dead halt, system abnormality and reloading operation and charging at the same time.
In a charging light-load application scene, the electric quantity required by the system operation is provided by a charging power supply without a battery, and a power supply circuit is idle at the moment; in a non-charging scene, a charging circuit is idle, so that the control chip can control the parallel connection of the reflux circuit and the discharging circuit under the condition of charging light load, and a first parallel circuit is formed to serve as a charging circuit of the secondary battery; and/or, in the discharging condition, the control backflow line is connected with the charging line in parallel, and the formed second parallel circuit is used as a discharging loop of the secondary battery.
The idle time period of the charging circuit and the discharging circuit is fully utilized, the idle discharging circuit and the reflux circuit are controlled by the control chip to be connected in parallel to form a charging loop of the secondary battery under the condition of charging light load, and the idle charging circuit and the reflux circuit are connected in parallel to form the discharging loop of the secondary battery under the condition of discharging, so that the impedance of the reflux circuit is reduced, and the impedance of the charging circuit and the impedance of the discharging circuit are reduced under the corresponding scene, so that the charging and discharging performance of the battery can be improved.
In one possible implementation manner, referring to fig. 3-1, fig. 3-1 is a schematic diagram of a second structure of the charging circuit provided in the embodiment of the present application, where the main board further includes: a first switch sub-circuit, the sub-board including a second switch sub-circuit;
a first end of the first switch sub-circuit is connected with a first end of the charging circuit;
a second end of the first switch sub-circuit is connected with a first end of the return line;
the third end of the first switch sub-circuit is connected with the first end of the discharge circuit;
the first end of the second switch sub-circuit is connected with the second end of the charging circuit;
a second end of the second switch sub-circuit is connected with a second end of the return line;
a third end of the second switch sub-circuit is connected with a second end of the discharge circuit;
the control chip is used for:
under the condition of light charging load, the second end of the first switch sub-circuit is controlled to be conducted with the third end of the first switch sub-circuit, and the second end of the second switch sub-circuit is controlled to be conducted with the third end of the second switch sub-circuit;
and under the discharge condition, controlling the first end of the first switch sub-circuit to be conducted with the second end of the first switch sub-circuit, and controlling the first end of the second switch sub-circuit to be conducted with the second end of the second switch sub-circuit.
The first switch sub-circuit and the second switch sub-circuit can be any circuits and components with switch functions. For example, the first and second switch sub-circuits may be circuits having a switching function, which are designed based on power switching transistors, for example, circuits having a switching function, which are designed based on transistors, or may be contactors, relays, or the like. The first switch sub-circuit and the second switch sub-circuit may be the same or different. The setting may be specifically performed based on actual conditions, and is not limited herein.
As shown in fig. 3-1, wherein a represents a first end of the first switching sub-circuit, B represents a second end of the first switching sub-circuit, B represents a third end of the first switching sub-circuit, a represents a first end of the second switching sub-circuit, B represents a second end of the second switching sub-circuit, and c represents a third end of the second switching sub-circuit.
The first end A of the first switch sub-circuit is connected with the first end of the charging circuit, the second end B of the first switch sub-circuit is connected with the first end of the reflow circuit, the third end C of the first switch sub-circuit is connected with the first end of the discharging circuit, the first end a of the second switch sub-circuit is connected with the second end of the charging circuit, the second end B of the second switch sub-circuit is connected with the second end of the reflow circuit, and the third end C of the second switch sub-circuit is connected with the second end of the discharging circuit.
Under the condition of light load of charging, the control chip controls the second end B of the first switch sub-circuit to be conducted with the third end C of the first switch sub-circuit, and the second end B of the second switch sub-circuit is conducted with the third end C of the second switch sub-circuit, as shown in the specific figure 3-2.
In the discharging situation, the first terminal a of the first switch sub-circuit is controlled to be conducted with the second terminal B of the first switch sub-circuit, and the first terminal a of the second switch sub-circuit is controlled to be conducted with the second terminal B of the second switch sub-circuit, as shown in fig. 3-3.
The idle time periods of the charging circuit and the discharging circuit are fully utilized, the paths of the charging circuit and the discharging circuit are connected in parallel with the reflow paths through the control chip, that is, the charging circuit and the discharging circuit are switched to GND in the idle time periods of the charging circuit and the discharging circuit, so that the impedance of the reflow circuit is reduced, the impedance of the charging circuit and the impedance of the discharging circuit can be reduced under corresponding scenes, and the charging and discharging performance of the battery can be improved.
In one possible implementation manner, the first switch sub-circuit includes a first type of transistor and a second type of transistor; the second switch sub-circuit comprises a first type transistor and a second type transistor; the control chip comprises a first control signal end and a second control signal end;
The first type transistor of the first switch sub-circuit comprises at least 1 first transistor, at least 1 fifth transistor, and the second type transistor of the first switch sub-circuit comprises at least 1 second transistor, at least 1 sixth transistor; the first type of crystal of the second switch sub-circuit comprises at least 1 third transistor, at least 1 seventh transistor, and the second type of crystal of the first switch sub-circuit comprises at least 1 fourth transistor, at least 1 eighth transistor;
wherein the control terminal of the first transistor, the control terminal of the second transistor, the control terminal of the third transistor, and the control terminal of the fourth transistor are connected to the first control signal terminal;
a first terminal of the first transistor and a first terminal of the third transistor are connected to the return line;
the first end of the second transistor is connected with one end of the charging circuit; the first end of the fourth transistor is connected with the other end of the charging circuit;
the second end of the first transistor, the second end of the second transistor, the second end of the third transistor and the second end of the fourth transistor are connected;
wherein the control terminal of the fifth transistor, the control terminal of the sixth transistor, the control terminal of the seventh transistor, and the control terminal of the eighth transistor are connected to the second control signal terminal;
A first terminal of a fifth transistor and a first terminal of the seventh transistor are connected to the return line;
the first end of the sixth transistor is connected with one end of the discharge circuit; the first end of the eighth transistor is connected with the other end of the discharge line;
the second end of the fifth transistor, the second end of the sixth transistor, the second end of the seventh transistor and the second end of the eighth transistor are connected;
the control chip is used for:
under the condition of light load of charging:
outputting a first level signal through the first control signal terminal to control the first end and the second end of the first transistor to be on, the first end and the second end of the third transistor to be on, the first end and the second end of the second transistor to be off, and the first end and the second end of the fourth transistor to be off;
outputting a second level signal through the second control signal terminal, wherein the first terminal and the second terminal of the fifth transistor are disconnected, the first terminal and the second terminal of the seventh transistor are disconnected, the first terminal and the second terminal of the sixth transistor are conducted, and the first terminal and the second terminal of the eighth transistor are conducted;
in the case of discharge:
outputting a second level signal through the first control signal terminal to control the first terminal and the second terminal of the fifth transistor to be turned on, the first terminal and the second terminal of the seventh transistor to be turned on, the first terminal and the second terminal of the sixth transistor to be turned off, and the first terminal and the second terminal of the eighth transistor to be turned off;
And outputting a first level signal through the second control signal terminal, wherein the first end and the second end of the first transistor are disconnected, the first end and the second end of the third transistor are disconnected, the first end and the second end of the second transistor are conducted, and the first end and the second end of the fourth transistor are conducted.
In one possible implementation manner, the first type of transistor of the first switch sub-circuit includes a plurality of first transistors and a plurality of fifth transistors, and the second type of transistor of the first switch sub-circuit includes a plurality of second transistors and a plurality of sixth transistors; the first type of crystal of the second switching sub-circuit includes a plurality of third transistors, a plurality of seventh transistors, and the second type of crystal of the first switching sub-circuit includes a plurality of fourth transistors, and a plurality of eighth transistors.
The transistor has on-resistance, which increases the link resistance and reduces the resistance by connecting a plurality of transistors in parallel.
Therefore, a plurality of first transistors, second transistors, third transistors, fourth transistors, a plurality of first transistors are connected in parallel, a plurality of second transistors are connected in parallel, a plurality of third transistors are connected in parallel, and a plurality of fourth transistors are connected in parallel. And then can reduce charging line impedance and discharge line impedance under corresponding scene to can promote battery charge-discharge performance.
In one possible implementation, when selecting a transistor, a transistor with a smaller area and lower on-resistance may also be used to reduce the on-resistance of the transistor.
In one possible implementation manner, the first type transistor is an N-type MOS transistor, and the second type transistor is a P-type MOS transistor;
the control chip is used for:
under the condition of light load of charging, a low-level signal is output through the first control signal end, and a high-level signal is output through the second control signal end;
in the discharging condition, a high-level signal is output through the first control signal end, and a low-level signal is output through the second control signal end.
As shown in fig. 4, M1 is a first transistor, M2 is a second transistor, M3 is a third transistor, M4 is a fourth transistor, M5 is a fifth transistor, M6 is a sixth transistor, M7 is a seventh transistor, and M8 is an eighth transistor.
The characteristics of the P-type MOS tube (P-type MOS tube) are as follows: when the grid voltage is lower than the source voltage and the voltage is equal to the voltage of the grid electrode and the voltage of the grid electrode is equal to the voltage of the source electrode, wherein the voltage of the grid electrode is equal to the voltage of the grid electrode, the voltage of the grid electrode is equal to the voltage of the source electrode, and the voltage of the grid electrode is equal to the voltage of the grid electrode.
The characteristics of the N-type MOS tube (N-type MOS tube) are as follows: when the gate voltage is higher than the source voltage and |vgs| > Vgs (th) | (i.e., vgs > Vgs (th)), the NMOS transistor is turned on, where Vgs is the voltage between the gate and source of the NMOS transistor and Vgs (th) is the threshold voltage of the NMOS transistor.
Under the condition of light load of charging, the first control signal end outputs a low-level signal, the second control signal end outputs a high-level signal, and the second control signal end is connected with the control end of the fifth transistor, the control end of the sixth transistor, the control end of the seventh transistor and the control end of the eighth transistor, the sixth transistor and the eighth transistor are PMOS transistors, the fifth transistor and the seventh transistor are NMOS transistors, the fifth transistor and the seventh transistor are turned on, the sixth transistor and the eighth transistor are turned off, namely, the control signal controls the discharge line to be switched into a backflow line at the moment, namely, the idle discharge line is connected with the backflow line in parallel to form a new backflow line, namely, the idle discharge line bears the GND backflow effect. Because the idle discharging line is connected with the reflux line in parallel, the impedance of the reflux line can be reduced, and then the impedance of the charging line is reduced in a charging light-load scene, so that the discharging performance of the battery can be improved.
Under the discharging condition, the first control signal end outputs a high-level signal, the second control signal end outputs a low-level signal, and the first control signal end is connected with the control end of the first transistor, the control end of the second transistor, the control end of the third transistor and the control end of the fourth transistor, the second transistor and the fourth transistor are PMOS transistors, the first transistor and the third transistor are NMOS transistors, the first transistor and the third transistor are turned on, the fourth transistor and the sixth transistor are turned off, namely, the control signal controls the charging circuit to be switched into a backflow circuit, namely, the idle charging circuit is connected with the backflow circuit in parallel, so that a new backflow circuit is formed, namely, the idle charging circuit GND plays a role of backflow. Because the idle charging line is connected in parallel with the return line, the impedance of the return line can be reduced, and the impedance of the discharge line can be further reduced in a discharge scene, so that the discharge performance of the battery can be improved.
In one possible implementation manner, the control chip is further configured to:
in other special cases, a low level signal is sent to the first control signal terminal; and transmitting a low-level signal to the second control signal terminal.
The first type transistor is an N-type MOS transistor, and the second type transistor sends a low-level signal to the first control signal end under other special conditions when the first type transistor is a P-type MOS transistor; and transmitting a low-level signal to the second control signal terminal. The NMOS transistors M1, M3, M5, M7 are turned off, and the PMOS transistors M2, M4, M6, M8 are turned on. That is, the charging line and the discharging line maintain an initial state and play a role of transmitting a charging power source and a discharging power source.
In one possible implementation manner, the first type transistor is a P-type MOS transistor, and the second type transistor is an N-type MOS transistor;
the control chip is used for:
under the condition of light load of charging, a high-level signal is output through the first control signal end, and a low-level signal is output through the second control signal end;
in the discharging condition, a low-level signal is output through the first control signal end, and a high-level signal is output through the second control signal end.
The first type transistor is a P-type MOS transistor, the second type transistor is an N-type MOS transistor, and in order to control the connection and disconnection of MA-M8, a high-level signal is output through a first control signal end under the condition of light charge load, a low-level signal is output through a second control signal end, and a low-level signal is output through the first control signal end under the condition of discharge, and a high-level signal is output through the second control signal end. So can only be under the light load condition of charging: controlling the first end and the second end of the first transistor to be conducted, controlling the first end and the second end of the third transistor to be conducted, disconnecting the first end and the second end of the second transistor, and disconnecting the first end and the second end of the fourth transistor; the first and second terminals of the fifth transistor are turned off, the first and second terminals of the seventh transistor are turned off, the first and second terminals of the sixth transistor are turned on, and the first and second terminals of the eighth transistor are turned on. In a discharging condition, the first end and the second end of the fifth transistor are controlled to be conducted, the first end and the second end of the seventh transistor are controlled to be conducted, the first end and the second end of the sixth transistor are disconnected, and the first end and the second end of the eighth transistor are disconnected; the first end and the second end of the first transistor are controlled to be disconnected, the first end and the second end of the third transistor are controlled to be disconnected, the first end and the second end of the second transistor are controlled to be conducted, and the first end and the second end of the fourth transistor are controlled to be conducted.
And then can make full use of the idle time period of charging circuit and discharging circuit, control the idle discharging circuit and return line to connect in parallel and form the charging circuit of the secondary battery through the control chip under the condition of charging light load, connect idle charging circuit and return line in parallel and form the discharging circuit of the secondary battery under the condition of discharging to reduce the impedance of the return line, and then reduce charging circuit impedance, discharging circuit impedance under corresponding scene, thus can promote the battery and charge and discharge performance.
In one possible implementation manner, the control chip is further configured to:
in other special cases, a high level signal is sent to the first control signal terminal; and transmitting a high-level signal to the second control signal terminal.
The first type transistor is a P-type MOS transistor, the second type transistor is an N-type MOS transistor, and under other special conditions, a high-level signal is sent to a first control signal end; and transmitting a high-level signal to the second control signal terminal. The NMOS transistors M1, M3, M5, M7 are turned off, and the PMOS transistors M2, M4, M6, M8 are turned on. That is, the charging line and the discharging line maintain an initial state and play a role of transmitting a charging power source and a discharging power source.
In one possible implementation manner, the main board comprises a main charging control chip, the first connector, the daughter board comprises a secondary charging control chip and the second connector;
The first end of the first connector is connected with one end of the charging circuit; the first end of the second connector is connected with the other end of the charging circuit;
the second end of the first connector is connected with one end of the return line; a second end of the second connector is connected with the other end of the return line;
the third end of the first connector is connected with one end of the discharge circuit; the second end of the second connector is connected with the other end of the discharge circuit;
a first end of the first transistor is connected with a fifth end of the first connector, and a first end of the third transistor is connected with a fifth end of the second connector;
the first end of the second transistor is connected with the fourth end of the first connector; the first end of the fourth transistor is connected with the fourth end of the second connector;
the second end of the first transistor, the second end of the second transistor, the second end of the third transistor and the second end of the fourth transistor are connected;
a first terminal of a fifth transistor is connected to the fifth terminal of the first connector, and a first terminal of the seventh transistor is connected to the fifth terminal of the second connector;
a first terminal of a sixth transistor is connected to the sixth terminal of the first connector; a first end of the eighth transistor is connected with a sixth end of the second connector;
The second end of the fifth transistor, the second end of the sixth transistor, the second end of the seventh transistor and the second end of the eighth transistor are connected;
wherein the first end of the first connector is communicated with the fourth end, and the second end of the first connector is communicated with the fifth end; the third end and the sixth end of the first connector are communicated;
the first end of the second connector is communicated with the fourth end, and the second end of the second connector is communicated with the fifth end; the third end of the first connector is conducted with the sixth end.
The main board comprises a main charging control chip, a first connector, a daughter board comprises a secondary charging control chip, and a second connector, wherein the first end of the first connector is connected with one end of a charging circuit; the first end of the second connector is connected with the other end of the charging circuit; the second end of the first connector is connected with one end of the reflux line; the second end of the second connector is connected with the other end of the reflux line; the third end of the first connector is connected with one end of the discharge line; the second end of the second connector is connected with the other end of the discharge line; the first end of the first transistor is connected with the fifth end of the first connector, and the first end of the third transistor is connected with the fifth end of the second connector; the first end of the second transistor is connected with the fourth end of the first connector; the first end of the fourth transistor is connected with the fourth end of the second connector; the second end of the first transistor, the second end of the second transistor, the second end of the third transistor and the second end of the fourth transistor are connected; the first end of the fifth transistor is connected with the fifth end of the first connector, and the first end of the seventh transistor is connected with the fifth end of the second connector; the first end of the sixth transistor is connected with the sixth end of the first connector; the first end of the eighth transistor is connected with the sixth end of the second connector; the second end of the fifth transistor, the second end of the sixth transistor, the second end of the seventh transistor and the second end of the eighth transistor are connected; the first end of the first connector is communicated with the fourth end, and the second end of the first connector is communicated with the fifth end; the third end and the sixth end of the first connector are communicated; the first end of the second connector is communicated with the fourth end, and the second end of the second connector is communicated with the fifth end; the third end of the first connector is conducted with the sixth end. Under the condition of charging light load, the control chip controls the free discharging circuit and the reflux circuit to be connected in parallel to form a charging circuit of the secondary battery, and under the condition of discharging, the free discharging circuit and the reflux circuit are connected in parallel to form the discharging circuit of the secondary battery, so that the impedance of the reflux circuit is reduced, and the impedance of the charging circuit and the impedance of the discharging circuit are reduced under the corresponding scene, so that the charging and discharging performances of the battery can be improved.
In one possible embodiment, the first transistor, the second transistor, the fifth transistor, and the sixth transistor are located on a side closer to the main charge control chip than the first connector;
the third transistor, the fourth transistor, the seventh transistor, and the eighth transistor are located on a side closer to the sub charge control chip and farther from the second connector.
The first transistor, the second transistor, the fifth transistor and the sixth transistor are positioned on the side close to the main charging control chip and far from the first connector; the third transistor, the fourth transistor, the seventh transistor and the eighth transistor are positioned on the side close to the secondary charging control chip and far from the second connector. Therefore, under the condition of charging light load, more idle discharging lines and the reflux line can be utilized to be connected in parallel to form a charging loop of the secondary battery, so that the charging link impedance is reduced under the condition of not increasing the space, and the charging and discharging performance of the battery is improved. Under the discharging condition, a discharging loop of the secondary battery is formed by connecting more idle charging circuits and backflow circuits in parallel, so that the discharging link impedance is reduced under the condition of not increasing the space, and the charging and discharging performance of the battery is improved.
An embodiment of the present application further provides an electronic device, including the charging circuit described in any one of the above.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments.
The foregoing description is merely a preferred embodiment of the present application, and is not intended to limit the scope of the present application. Any modifications, equivalent substitutions, improvements, etc. that are within the spirit and principles of the present application are intended to be included within the scope of the present application.
Claims (11)
1. A charging circuit, comprising:
a main board, a daughter board, and a cable; the main board and the daughter board are connected through the cable; the cable comprises a charging circuit, a reflux circuit and a discharging circuit; the main board comprises a control chip; the main board is used for charging the main battery, and the sub-board is used for charging the auxiliary battery;
the control chip is used for:
under the condition of charging light load, the reflux circuit and the discharge circuit are controlled to be connected in parallel, and a first parallel circuit formed by the reflux circuit and the discharge circuit is used as a charging loop of the secondary battery;
and/or the number of the groups of groups,
in the discharging condition, the reflux line is controlled to be connected with the charging line in parallel, and a second parallel circuit is formed to serve as a discharging loop of the secondary battery.
2. The circuit of claim 1, wherein the motherboard further comprises: a first switch sub-circuit, the sub-board comprising a second switch sub-circuit; a first end of the first switch sub-circuit is connected with a first end of the charging circuit; a second end of the first switch sub-circuit is connected with a first end of the return line; the third end of the first switch sub-circuit is connected with the first end of the discharge line; the first end of the second switch sub-circuit is connected with the second end of the charging circuit; a second end of the second switch sub-circuit is connected with a second end of the return line; the third end of the second switch sub-circuit is connected with the second end of the discharge line;
The control chip is used for:
under the condition of light charging load, the second end of the first switch sub-circuit is controlled to be conducted with the third end of the first switch sub-circuit, and the second end of the second switch sub-circuit is controlled to be conducted with the third end of the second switch sub-circuit;
and under the discharging condition, controlling the first end of the first switch sub-circuit to be conducted with the second end of the first switch sub-circuit, and controlling the first end of the second switch sub-circuit to be conducted with the second end of the second switch sub-circuit.
3. The circuit of claim 2, wherein the first switching sub-circuit comprises a first type of transistor and a second type of transistor; the second switch sub-circuit comprises a first type transistor and a second type transistor; the control chip comprises a first control signal end and a second control signal end;
the first type transistor of the first switch sub-circuit comprises at least 1 first transistor, at least 1 fifth transistor, and the second type transistor of the first switch sub-circuit comprises at least 1 second transistor, at least 1 sixth transistor; the first type of crystal of the second switching sub-circuit comprises at least 1 third transistor, at least 1 seventh transistor, and the second type of crystal of the first switching sub-circuit comprises at least 1 fourth transistor, at least 1 eighth transistor;
The control end of the first transistor, the control end of the second transistor, the control end of the third transistor and the control end of the fourth transistor are connected with the first control signal end; the first end of the first transistor and the first end of the third transistor are connected with the reflux line; the first end of the second transistor is connected with one end of the charging circuit; the first end of the fourth transistor is connected with the other end of the charging circuit; the second end of the first transistor, the second end of the second transistor, the second end of the third transistor and the second end of the fourth transistor are connected;
the control end of the fifth transistor, the control end of the sixth transistor, the control end of the seventh transistor and the control end of the eighth transistor are connected with the second control signal end; a first end of a fifth transistor and a first end of the seventh transistor are connected with the reflux line; the first end of the sixth transistor is connected with one end of the discharge circuit; the first end of the eighth transistor is connected with the other end of the discharge line; the second end of the fifth transistor, the second end of the sixth transistor, the second end of the seventh transistor and the second end of the eighth transistor are connected;
The control chip is used for:
under the condition of light load of charging: outputting a first level signal through the first control signal terminal to control the first end and the second end of the first transistor to be conducted, the first end and the second end of the third transistor to be conducted, the first end and the second end of the second transistor to be disconnected, and the first end and the second end of the fourth transistor to be disconnected; outputting a second level signal through the second control signal terminal, wherein the first terminal and the second terminal of the fifth transistor are disconnected, the first terminal and the second terminal of the seventh transistor are disconnected, the first terminal and the second terminal of the sixth transistor are conducted, and the first terminal and the second terminal of the eighth transistor are conducted;
in the case of discharge: outputting a second level signal through the first control signal terminal to control the first terminal and the second terminal of the fifth transistor to be on, the first terminal and the second terminal of the seventh transistor to be on, the first terminal and the second terminal of the sixth transistor to be off, and the first terminal and the second terminal of the eighth transistor to be off; and outputting a first level signal through the second control signal end, wherein the first end and the second end of the first transistor are disconnected, the first end and the second end of the third transistor are disconnected, the first end and the second end of the second transistor are conducted, and the first end and the second end of the fourth transistor are conducted.
4. The circuit of claim 3, wherein the first type of transistor of the first switching sub-circuit comprises a plurality of first transistors and a plurality of fifth transistors, and the second type of transistor of the first switching sub-circuit comprises a plurality of second transistors and a plurality of sixth transistors; the first type of crystal of the second switching sub-circuit comprises a plurality of third transistors and a plurality of seventh transistors, and the second type of crystal of the first switching sub-circuit comprises a plurality of fourth transistors and a plurality of eighth transistors.
5. The circuit of claim 3, wherein the first type of transistor is an N-type MOS transistor and the second type of transistor is a P-type MOS transistor;
the control chip is used for:
under the condition of light load of charging, a low-level signal is output through the first control signal end, and a high-level signal is output through the second control signal end;
under the discharging condition, a high-level signal is output through the first control signal end, and a low-level signal is output through the second control signal end.
6. The circuit of claim 5, wherein the control chip is further configured to:
in other special cases, a low-level signal is sent to the first control signal terminal; and transmitting a low-level signal to the second control signal terminal.
7. The circuit of claim 3, wherein the first type of transistor is a P-type MOS transistor and the second type of transistor is an N-type MOS transistor;
the control chip is used for:
under the condition of light load of charging, a high-level signal is output through the first control signal end, and a low-level signal is output through the second control signal end;
and under the discharging condition, outputting a low-level signal through the first control signal end and outputting a high-level signal through the second control signal end.
8. The circuit of claim 7, wherein the control chip is further configured to:
in other special cases, a high level signal is sent to the first control signal terminal; and transmitting a high-level signal to the second control signal terminal.
9. The circuit of claim 3, wherein the motherboard includes a primary charge control chip, a first connector, and the daughter board includes a secondary charge control chip, a second connector;
the first end of the first connector is connected with one end of the charging circuit; the first end of the second connector is connected with the other end of the charging circuit;
the second end of the first connector is connected with one end of the return line; a second end of the second connector is connected with the other end of the return line;
The third end of the first connector is connected with one end of the discharge line; the second end of the second connector is connected with the other end of the discharge line;
a first end of a first transistor is connected with a fifth end of the first connector, and a first end of the third transistor is connected with a fifth end of the second connector;
the first end of the second transistor is connected with the fourth end of the first connector; the first end of the fourth transistor is connected with the fourth end of the second connector;
the second end of the first transistor, the second end of the second transistor, the second end of the third transistor and the second end of the fourth transistor are connected;
a first end of a fifth transistor is connected with a fifth end of the first connector, and a first end of the seventh transistor is connected with a fifth end of the second connector;
a first end of a sixth transistor is connected with a sixth end of the first connector; a first end of an eighth transistor is connected with a sixth end of the second connector;
the second end of the fifth transistor, the second end of the sixth transistor, the second end of the seventh transistor and the second end of the eighth transistor are connected;
the first end of the first connector is communicated with the fourth end, and the second end of the first connector is communicated with the fifth end; the third end and the sixth end of the first connector are communicated;
The first end of the second connector is communicated with the fourth end, and the second end of the second connector is communicated with the fifth end; the third end of the first connector is conducted with the sixth end.
10. The circuit of claim 9, wherein the circuit further comprises a logic circuit,
the first transistor, the second transistor, the fifth transistor and the sixth transistor are positioned on the side close to the main charging control chip and far from the first connector;
the third transistor, the fourth transistor, the seventh transistor, and the eighth transistor are located on a side close to the sub charge control chip and far from the second connector.
11. An electronic device comprising a charging circuit as claimed in any one of the preceding claims 1 to 10.
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| CN202311052096.1A CN117691695A (en) | 2023-08-18 | 2023-08-18 | Charging circuit and electronic equipment |
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