CN117690943A - Manufacturing method of image sensor - Google Patents
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Abstract
The invention provides a manufacturing method of an image sensor, which belongs to the technical field of semiconductor manufacturing and comprises the following steps: providing a substrate comprising a device region and a non-device region; forming a first oxide layer on the substrate, wherein the first oxide layer covers the device region and extends to part of the non-device region; forming a step on the substrate of the non-device region; forming a second oxide material layer on the substrate, wherein the second oxide material layer covers the first oxide layer, the surface of the step and the side wall; forming a sacrificial layer on the surface of the second oxide material layer; flattening the sacrificial layer at least twice to remove the sacrificial layer and a part of the second oxide material layer, and polishing to form a second oxide layer; forming a bonding contact layer with high bonding strength on the second oxide layer; and bonding the bonding contact layer with the bearing substrate to form the image sensor. The manufacturing method of the image sensor provided by the invention can effectively improve the quality and yield of the image sensor.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of an image sensor.
Background
The image sensor converts an optical signal irradiated on its own light sensing surface into a corresponding electrical signal by photoelectric conversion and outputs a corresponding image according to the converted electrical signal, and is widely used in various photoelectric devices such as digital cameras, video recorders, facsimile machines, image scanners, digital televisions, and the like. However, the image sensor has problems of complex process, low yield, and the like.
Disclosure of Invention
The invention provides a manufacturing method of an image sensor, which has the unexpected effects of effectively reducing bubbles at a bonding interface and improving bonding quality so as to improve the yield of the image sensor.
In order to solve the technical problems, the invention is realized by the following technical scheme.
The invention provides a manufacturing method of an image sensor, which at least comprises the following steps:
providing a substrate, wherein the substrate comprises a device region and a non-device region;
forming a first oxide layer on the substrate, wherein the first oxide layer covers the device region and extends to part of the non-device region;
forming a step on the substrate of the non-device region;
forming a second oxide material layer on the substrate, wherein the second oxide material layer covers the first oxide layer, the surface of the step and the side wall;
forming a sacrificial layer on the surface of the second oxide material layer;
flattening the sacrificial layer at least twice to remove the sacrificial layer and part of the second oxide material layer, and polishing to form a second oxide layer;
forming a bonding contact layer with high bonding strength on the second oxide layer; and
and bonding the bonding contact layer with the bearing substrate to form the image sensor.
Further, the bonding contact layer is formed by adopting a high-density plasma chemical vapor deposition process.
Further, the polishing process applies a pressure that is half the pressure applied by the planarization process.
Further, the step of forming the second oxide layer includes:
forming a first sacrificial layer on the surface of the second oxide material layer;
carrying out first planarization treatment on the first sacrificial layer to remove part of the thickness of the first sacrificial layer and form a second sacrificial layer;
performing a second planarization treatment on the second sacrificial layer to remove the second sacrificial layer and a part of the second oxide material layer with the thickness to form an intermediate oxide material layer; and
and performing first polishing treatment on the intermediate oxide material layer to remove part of the thickness of the intermediate oxide material layer, so as to form a second oxide layer, wherein the surface of the second oxide layer is smooth.
Further, the thickness of the first polishing treatment is 70nm-90nm, and the treatment time is 57s-67s.
Further, after the first polishing treatment, the roughness of the surface of the second oxide layer is 0.1nm to 0.3nm.
Further, the step of forming the bonding contact layer includes:
forming a bonding material layer on the surface of the second oxide layer;
and performing secondary polishing treatment on the bonding material layer to remove part of the bonding material layer to form a bonding contact layer.
Further, the thickness of the bonding material layer is 90nm-110nm.
Further, the thickness of the second polishing treatment is 50nm-70nm, and the treatment time is 57s-67s.
Further, after the second polishing treatment, the roughness of the surface of the bonding contact layer is 0.1nm to 0.3nm.
Further, the manufacturing method further comprises the following steps: and after the bonding contact layer is formed, carrying out particle removal and cleaning treatment on the substrate.
The invention provides a manufacturing method of an image sensor, which has the unexpected effects that by adding polishing treatment after planarization treatment: the process flow is simplified, the process time is greatly reduced, and the production efficiency is improved; and the formed bonding interface film layer has high uniformity, good compactness, high surface roughness and high bonding strength, reduces the generation of bubbles in the bonding process, and improves the bonding quality of the image sensor and the bearing substrate, thereby improving the reliability and the yield of the image sensor.
Drawings
Fig. 1 is a flowchart of a method for manufacturing an image sensor according to the present invention.
Fig. 2 is a schematic structural diagram of a first oxide material layer according to an embodiment of the invention.
Fig. 3 is a schematic structural diagram of a polishing unit according to an embodiment of the invention.
Fig. 4 is a schematic structural view of a step according to an embodiment of the present invention.
Fig. 5 is a schematic structural diagram of a second oxide material layer according to an embodiment of the invention.
FIG. 6 is a schematic diagram illustrating a structure of a first sacrificial layer according to an embodiment of the invention.
FIG. 7 is a schematic diagram illustrating a structure of a second sacrificial layer according to an embodiment of the invention.
FIG. 8 is a schematic diagram illustrating an intermediate oxide material layer according to an embodiment of the present invention.
FIG. 9 is a schematic diagram of a structure of a second oxide layer according to an embodiment of the invention.
Fig. 10 is a schematic structural diagram of a bonding material layer according to an embodiment of the invention.
Fig. 11 is a schematic structural diagram of a bonding contact layer according to an embodiment of the invention.
Fig. 12 is a schematic diagram of bonding a CMOS transistor to a carrier substrate according to an embodiment of the invention.
Fig. 13 is an electron microscope image of an image sensor according to another embodiment of the present invention.
Fig. 14 is an electron microscope image of an image sensor according to an embodiment of the present invention.
Description of the drawings:
100. a substrate; 110. a step; 200. a first oxide material layer; 210. a first oxide layer; 300. a second oxide material layer; 310. an intermediate oxide material layer; 320. a second oxide layer; 400. a first sacrificial layer; 410. a second sacrificial layer; 500. a bonding material layer; 510. a bonding contact layer; 511. a contact surface; 600. a carrier substrate; 601. a bonding surface; 700. a rotation shaft; 800. and grinding the blade.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
The technical solution of the present invention will be described in further detail below with reference to several embodiments and the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The back-illuminated image sensor (Back side Illuminated Complementary Metal Oxide Semiconductor, BSI CMOS) has metal interconnect layers and photosensitive layers disposed on both sides of the substrate, respectively, to avoid refraction and obstruction of incident light by the metal interconnect layers. Compared with a front-side image sensor (Front side Illumination CMOS, FSI CMOS) has better quantum efficiency and angular responsiveness, so that the back-side image sensor gradually occupies an important position in industrial application, is widely applied to the fields of digital cameras, interchangeable lens digital cameras, smart phones and the like, and is required to bond a CMOS transistor with a bearing substrate in the preparation process of the back-side image sensor. The manufacturing method of the image sensor can effectively reduce bubbles at the bonding interface of the CMOS transistor and the bearing substrate, improve the bonding quality of the image sensor and improve the performance of the back-illuminated image sensor.
Referring to fig. 1 and 2, in step S10, in an embodiment of the present invention, a substrate 100 is provided, and a semiconductor device is fabricated on the substrate 100 to form a device region (not shown), wherein a region where the semiconductor device is not fabricated is defined as a non-device region (not shown), and the non-device region is disposed around the device region, for example. Taking this substrate 100 for manufacturing a device as an example, a process for manufacturing a backside illuminated image sensor will be described. The invention does not limit the types of the substrates, and can select different types of substrates according to the manufacturing of different types of semiconductor devices. In one embodiment of the present invention, the substrate 100 may be, for example, a silicon (Si) substrate to fabricate complementary metal oxide semiconductor transistors (Complementary Metal Oxide Semiconductor, CMOS). In an embodiment of the present invention, doping the substrate 100 prior to fabrication of the device may reduce the resistance of the substrate 100 and prevent latch-up. In one embodiment of the present invention, boron (B) or gallium (Ga) is doped in the substrate 100 to form a P-doped substrate.
Referring to fig. 1 and 2, in step S10, after devices are fabricated on the substrate 100, two or more substrates 100 are bonded together. In an embodiment of the present invention, a process for fabricating a backside illuminated image sensor is described taking a substrate 100 with CMOS transistors fabricated and a carrier substrate bonded as an example.
Referring to fig. 1 and 2, in step S20, in an embodiment of the present invention, a first oxide material layer 200 is first formed on a substrate 100 on which a CMOS transistor is fabricated, and the first oxide material layer 200 covers the entire device region and non-device region and the sidewalls of the substrate 100. In an embodiment of the present invention, the first oxide material layer 200 is a dense silicon oxide or the like. The method for forming the first oxide material layer 200 is not limited in the present invention, and in this embodiment, the first oxide material layer 200 is formed by, for example, high density plasma chemical vapor deposition (High Density Plasma Chemical Vapor Deposition, HDPCVD). The thickness of the first oxide material layer 200 is, for example, 350nm to 400nm, specifically, 360nm, 380nm, 400nm, or the like.
Referring to fig. 1, 3 and 4, in step S30, after the first oxide material layer 200 is formed, for example, a chemical mechanical polishing (Chemical Mechanical Polishing, CMP) process may be used to perform Edge Trim (Edge Trim) on the substrate 100 in the non-device region to form the step 110, so as to reduce Edge chipping and improve device reliability in an embodiment of the present invention. The trimming process may be performed in two steps, such as planar grinding and edge cutting. Specifically, the entire first oxide material layer 200 is subjected to planar grinding by using a chemical mechanical polishing process, so that the surface of the first oxide material layer 200 is flat, and the edge cutting depth is ensured to be consistent. After the first oxide material layer 200 is planar-polished, the edge of the substrate 100 is polished and cut using the polishing unit in fig. 3. The polishing unit includes a polishing blade 800 and a rotation shaft 700, the polishing blade 800 is fixed on the rotation shaft 700, the rotation shaft 700 drives the polishing blade 800 to rotate in a vertical direction, the substrate 100 rotates in a horizontal direction, the polishing blade 800 contacts with the edge of the substrate 100 and performs polishing cutting on the edge of the substrate 100, and the first oxide material layer 200 and part of the substrate 100 covered on the edge of the substrate 100 are removed to form the step 110. In the trimming process, the first oxide material layer 200 is removed from the side of the substrate 100 simultaneously to form the first oxide layer 210. The chemical mechanical polishing process is adopted to trim the substrate 100, the process flow is simple, the process time is greatly shortened, and the production efficiency is effectively improved.
Referring to fig. 3 and 4, in an embodiment of the present invention, the depth h of the step 110 is, for example, 140 μm to 160 μm, specifically, 140 μm, 150 μm or 160 μm, etc., and the width d of the step 110 is, for example, 1.3mm to 1.5mm, specifically, 1.3mm, 1.4mm or 1.5mm, etc. By setting the size of the step 110 within the above range, abnormality of the device region on the substrate 100 at the time of subsequent deposition of the bonding interface film layer can be effectively prevented.
Referring to fig. 1, 4 and 5, in step S40, after the step 110 is formed, a second oxide material layer 300 is formed on the surface of the first oxide layer 210 and the surface and the sidewall of the step 110, for example, by using a Plasma Enhanced CVD (PECVD) technique to deposit a tetraethyl orthosilicate film (TEOS). Specifically, for example, in tetraethyl orthosilicate (TEOS) and oxygen (O 2 ) As a raw material, a second oxide material layer 300 is deposited on the surface of the step 110. In one embodiment of the present invention, the flow rate of the ethyl orthosilicate liquid is, for example, 500mgm to 1000mgm, and the ethyl orthosilicate liquid is gasified at, for example, 100 ℃ to 120 ℃. The ethyl orthosilicate gas is then delivered into the reaction chamber by an inert gas, such as helium, and oxygen is introduced into the reaction chamber. The tetraethyl orthosilicate gas and oxygen are dissociated in the chamber by radio frequency and react to form silica. In one embodiment of the present invention, the oxygen gas flow rate may be set to 2000sccm-3000sccm, and the RF power may be set to 400W-800W, for example. In one embodiment of the present invention, the reaction pressure in the reaction chamber is, for example, 7T-9T, the reaction temperature is, for example, 400 ℃ to 420 ℃, and further, the reaction pressure is 8T, and the reaction temperature is 410 ℃. The second oxide material layer 300 formed has good coverage, and the mobility of the surface of tetraethyl orthosilicate (TEOS) is large, so that the generation of low density regions or voids can be avoided. And the second oxide material layer 300 is formed through a process of plasma enhanced tetraethyl orthosilicate (PETEOS), the temperature of depositing the second oxide material layer 300 is reduced, and the film quality of the second oxide material layer 300 is ensured, thereby improving the quality of other film layers formed on the surface of the second oxide material layer 300. In an embodiment of the present invention, the thickness of the second oxide material layer 300 is, for example, 1400nm-1450nm, specifically, 1420nm, 1440nm or 1450 nm.
Referring to fig. 1, 5 and 6, in step S50, in an embodiment of the present invention, after forming the second oxide material layer 300, for example, a process of using a plasma enhanced tetraethyl orthosilicate film is performed, a first sacrificial layer 400 is formed on the surface of the second oxide material layer 300. In an embodiment of the present invention, the first sacrificial layer 400 is a dense silicon oxide material, and the thickness of the first sacrificial layer 400 is 1180nm-1220nm, specifically 1190nm, 1200nm or 1210 nm. The second oxide material layer 300 and the first sacrificial layer 400 are respectively formed by adopting a twice plasma enhanced tetraethoxysilane film process, so that the overall thickness and strength of the second oxide material layer 300 and the first sacrificial layer 400 are unchanged, the coverage uniformity of the oxide layer is improved, and the overall quality of the oxide layer is improved. In the manufactured CMOS transistor, the depth of the dicing channel between the exposure region (shot) and the exposure region is about 500nm, and the overall thickness of the second oxide material layer 300 and the first sacrificial layer 400 is controlled to be 2500nm-2700nm, so that the dicing channel between the shot and the shot can be fully filled, and bubbles are prevented from occurring in the subsequent bonding process of the CMOS transistor and the carrier substrate.
Referring to fig. 1, 5 and 6, in step S50, after the first sacrificial layer 400 is formed, the substrate 100 is annealed to improve the quality of the second oxide material layer 300 and the first sacrificial layer 400 and further reduce the interface charges in an embodiment of the invention. In an embodiment of the present invention, oxygen and TEOS are stopped from being introduced into the chamber, nitrogen is injected into the chamber, and then the temperature of the substrate 100 is maintained at 380 ℃ to 420 ℃, and the second oxide material layer 300 and the first sacrificial layer 400 on the substrate 100 are annealed, so that the compactness of the oxide layers and the bonding strength between the oxide layers are improved.
Referring to fig. 1 and fig. 6 to fig. 7, in step S60, after the annealing process is performed on the substrate 100, for example, a first planarization process is performed on the first sacrificial layer 400 on the substrate 100 in an embodiment of the invention. In an embodiment of the present invention, for example, a Chemical Mechanical Polishing (CMP) process is used to perform a first planarization process, and the polishing pad used is, for example, a hard pad, and the service life of the hard pad is, for example, greater than 25 hours, so as to improve the quality of the CMP process, thereby improving the production yield of the semiconductor structure. In an embodiment of the present invention, for example, the polishing unit in fig. 3 is used to planarize the first sacrificial layer 400 on the substrate 100 for the first time to remove a portion of the thickness of the first sacrificial layer 400. In an embodiment of the present invention, the substrate 100 is divided into a device region and a non-device region, where a region near the center of the substrate 100 is the device region, and a region near the edge of the substrate 100 is the non-device region. And during the first planarization process, the pressure of the area of the device region is set to, for example, 2mT to 4mT, the pressure of the area inside the non-device region is set to, for example, 6mT to 8mT, and the pressure of the area outside the non-device region is set to, for example, 8mT to 10mT. In depositing the film, the film build-up in the area of the edge of the substrate 100 results in an actual deposited thickness greater than the preset thickness, by setting a higher pressure to the area of the edge of the substrate 100, thereby ensuring that the surface of the substrate 100 remains planar after grinding. In one embodiment of the present invention, the first planarization process is performed in three stages, for example, a first stage, for example, polishing 45s-55s, a second stage, for example, polishing 45s-55s, and a third stage, for example, polishing 45s-55s. In an embodiment of the present invention, the thickness of the first planarization process is, for example, 800nm to 1000nm, specifically, for example, 800nm, 900nm or 1000nm, and the width is, for example, 1.3mm to 1.5mm. And the first sacrificial layer 400 is planarized for the first time, a second sacrificial layer 410 is formed.
Referring to fig. 1 and 8, in step S60, after forming the second sacrificial layer 410, for example, a CMP process is used to planarize the second sacrificial layer 410 for a second time, and the polishing pad is, for example, a hard pad, and the service life of the hard pad is, for example, greater than 25h. In an embodiment of the present invention, for example, the polishing unit in fig. 3 is used to planarize the second sacrificial layer 410 for the second time to remove the second sacrificial layer 410 and a portion of the thickness of the second oxide material layer 300, thereby forming the intermediate oxide material layer 310. During the second planarization process, the pressure of the region of the device region is set to, for example, 2mT to 4mT, the pressure of the region inside the non-device region is set to, for example, 6mT to 8mT, and the pressure of the region outside the non-device region is set to, for example, 8mT to 10mT. In one embodiment of the present invention, the second planarization process is performed in three stages, for example, a first stage, for example, polishing 45s-55s, a second stage, for example, polishing 45s-55s, and a third stage, for example, polishing 45s-55s. In an embodiment of the present invention, the thickness of the second planarization process is, for example, 800nm to 1000nm, specifically, for example, 800nm, 900nm or 1000nm, and the width is, for example, 1.3mm to 1.5mm.
Referring to fig. 1, 8 and 9, in step S60, in an embodiment of the present invention, an intermediate oxide layer 310 is formed, a first polishing process is performed on the intermediate oxide layer 310, and a portion of the intermediate oxide layer 310 is removed to form a second oxide layer 320. In one embodiment of the present invention, the first polishing process is performed, for example, using a polishing CMP process, and the pressure applied to the substrate 100 during the polishing process is the pressure applied to the substrate 100 during the planarization process. During the first polishing process, the pressure of the region of the device region is set to, for example, 1mT to 2mT, the pressure of the region inside the non-device region is set to, for example, 3mT to 4mT, and the pressure of the region outside the non-device region is set to, for example, 4mT to 5mT. In one embodiment of the invention, the first polishing process is performed in three stages, for example, with the first stage being polished for 1s, the second stage being polished for 1s, and the third stage being polished for 55s-65s. In one embodiment of the present invention, the first polishing treatment has a thickness of, for example, 50nm to 70nm, specifically, for example, 50nm, 60nm, 70nm, or the like, and a width of, for example, 1.3mm to 1.5mm. In one embodiment of the present invention, the polishing pad used in the first polishing process is, for example, a nonwoven fabric-based polishing pad, which is soft and excellent in surface flatness as compared with a hard pad, and less scratches are generated on the oxidized material layer during polishing. In an embodiment of the present invention, the roughness of the surface of the second oxide layer 320 is, for example, 0.4nm to 0.6nm before the first polishing process, and the roughness of the surface of the second oxide layer 320 is, for example, 0.1nm to 0.3nm after the first polishing process, and is, for example, 0.2nm. Through the buffering CMP process, defects such as micro scratch (micro scratch) and roughness (roughess) of the surface of the oxide material layer can be improved, so that the surface of the second oxide layer 320 is flat and smooth, and the uniformity and the deposition quality of the subsequent film layer deposition are ensured.
Referring to fig. 1, 9 and 10, in step S70, after forming the second oxide layer 320, a bonding material layer 500 is formed on the surface of the second oxide layer 320 in an embodiment of the invention. And bonding material layer 500 is, for example, a dense silicon oxide or the like. The method for forming the bonding material layer 500 is not limited in the present invention, in this embodiment, for example, a high density plasma chemical vapor deposition (High Density Plasma Chemical Vapor Deposition, HDPCVD) is used to form the bonding material layer 500, and only deposition (deposition) is performed during the HDPCVD process, and no sputter etching (sputtering) is performed, so that the deposition efficiency of the bonding material layer 500 can be improved, and the coverage effect of the bonding material layer 500 on the step 110 can be improved, so that the bonding strength of the bonding interface film layer of the substrate 100 is further improved, which is beneficial to improving the bubble enhancement effect caused by rapid annealing during the bonding process of the subsequent CMOS transistor and the carrier substrate. In an embodiment of the present invention, the thickness of the bonding material layer 500 is, for example, 90nm to 110nm, specifically, for example, 90nm, 100nm, 110nm, etc. In addition, in an embodiment of the present invention, by setting the first polishing process, the separation of the second oxide layer 320 formed by using the TEOS technology and the bonding material layer 500 formed by using the HDPCVD technology in the subsequent package dicing step is avoided, thereby improving the yield of the image sensor.
Referring to fig. 1, 10 and 11, in step S80, after forming the bonding material layer 500, the bonding material layer 500 is subjected to a second polishing treatment to remove a part of the thickness of the bonding material layer 500, so as to form a bonding contact layer 510, wherein the bonding strength of the bonding contact layer 510 is high. In one embodiment of the present invention, a second polishing process is performed, for example, using a buffering CMP process. During the second polishing process, the pressure of the region of the device region is set to, for example, 1mT to 2mT, the pressure of the region inside the non-device region is set to, for example, 3mT to 4mT, and the pressure of the region outside the non-device region is set to, for example, 4mT to 5mT. In one embodiment of the invention, the second polishing process is performed in three stages, for example, with the first stage being polished for 1s, the second stage being polished for 1s, and the third stage being polished for 55s-65s. In one embodiment of the present invention, the thickness of the second polishing treatment is, for example, 50nm to 70nm, specifically, for example, 50nm, 60nm or 70nm, etc., and the width is, for example, 1.3mm to 1.5mm. In one embodiment of the present invention, the polishing pad used in the first polishing process is, for example, a nonwoven fabric-based polishing pad, which is soft and excellent in surface flatness as compared with a hard pad, and less scratches are generated on the material layer during polishing. In an embodiment of the present invention, the roughness of the surface of the bonding contact layer 510 before the second polishing process is, for example, 0.4nm to 0.6nm, and after the second polishing process, the roughness of the surface of the bonding contact layer 510 is, for example, 0.1nm to 0.3nm, and further, for example, 0.2nm. Through the buffering CMP process, defects such as micro scratch (micro scratch) and roughness (roughess) on the surface of the material layer can be improved, so that the flatness and roughness of the bonding contact layer 510 are further enhanced, the bonding strength of the bonding contact layer 510 is further enhanced, the bubble enhancement effect caused by rapid annealing in the bonding process is suppressed, the bonding quality of the CMOS transistor and the carrier substrate is improved, and the yield of the image sensor is improved.
Referring to fig. 1, 10 and 11, in an embodiment of the present invention, after forming the bonding contact layer 510, a particle removal (partial removal) and cleaning process is performed on the substrate 100. Further, for example, the substrate 100 is cleaned by an RCA cleaning process, so that a large amount of particles generated during the chemical mechanical polishing process are removed, and device contamination is prevented.
Referring to fig. 1, 10 to 12, in step S80, after forming a bonding contact layer 510, in an embodiment of the present invention, a substrate 100 with a CMOS transistor fabricated thereon is turned over to make the bonding contact layer 510 approach to a carrier substrate 600, and a low-temperature fusion bonding process is used to bond the substrate 100 and the carrier substrate 600 to fabricate a backside image sensor. Specifically, the bonding surface 511 on the bonding contact layer 510 and the bonding surface 601 of the carrier substrate 600 are subjected to plasma activation treatment, and the reaction gas used includes Ar and N 2 、O 2 And SF (sulfur hexafluoride) 6 One or more of the following. The substrate 100 is bonded to the carrier substrate 600 by contacting the contact surface 511 of the bonding contact layer 510 with the bonding surface 601 of the carrier substrate 600, and the bonding pressure applied during the bonding process is, for example, 1N to 10N, the bonding time is, for example, 10s to 60s, and the bonding temperature is, for example, 10 ℃ to 50 ℃. Bonding the bonded substrate 100 to a carrierThe carrier substrate 600 is annealed at a temperature of 300-400 ℃ for 40-80 min, for example. The annealing time is controlled within the above range, so that the bonding quality between the substrate 100 and the carrier substrate 600 can be effectively improved, and the annealing time process can lead to continuous growth of bonding bubbles, thereby resulting in poor bonding degree between the substrate 100 and the carrier substrate 600. After the annealing is completed, the substrate 100 is thinned, and steps such as a microlens and a filter layer are performed to form a back-illuminated image sensor.
Referring to fig. 13 and 14, fig. 13 is an electron microscope image of a backside illuminated image sensor manufactured by a method for depositing a bonding interface layer by using a process of depositing a low-k tetraethyl orthosilicate film (Low deposition Tetraethylorthosilicate, LD TEOS) after a second planarization process in an embodiment of the invention, and fig. 14 is an electron microscope image of a backside illuminated image sensor manufactured by a method for manufacturing an image sensor provided in the embodiment. As can be seen from fig. 13 and 14, bonding bubbles in the back-illuminated image sensor manufactured by the manufacturing method of the image sensor provided by the invention are greatly reduced, so that the reliability and yield of the image sensor are ensured.
In summary, the invention provides a method for manufacturing an image sensor, which reduces the process times of annealing and the like, reduces the process time and greatly improves the production efficiency by simplifying the process flow. By forming steps on the substrate, the unexpected effect is to reduce the occurrence of chipping defects during bonding. The bonding material layer is formed through the HDPCVD process, and the unexpected effect is that the bonding strength of the bonding interface film layer of the substrate is enhanced, which is beneficial to improving the bubble enhancement effect caused by rapid annealing in the subsequent bonding process of the CMOS transistor and the bearing substrate. By adding a buffering CMP process after the process of removing the oxide layer by CMP, the unexpected effect is to improve the fine scratch and surface roughness of the oxide layer surface. By newly adding the buffering CMP process after the bonding material layer is formed by the HDPCVD process, the unexpected effect is that the fine scratch and the surface roughness of the surface of the bonding interface film layer are improved, the flatness and the roughness of the bonding interface film layer are improved, the bonding strength is further increased, the bubble enhancement effect caused by rapid annealing in the bonding process is inhibited, the generation of bubbles in the bonding process is reduced, the bonding quality between the CMOS transistor and the bearing substrate is improved, and the reliability and the yield of the image sensor are improved.
The foregoing description is only illustrative of the preferred embodiments of the present application and the technical principles employed, and it should be understood by those skilled in the art that the scope of the invention in question is not limited to the specific combination of features described above, but encompasses other technical solutions which may be formed by any combination of features described above or their equivalents without departing from the inventive concept, such as the features described above and the features disclosed in the present application (but not limited to) having similar functions being interchanged.
Other technical features besides those described in the specification are known to those skilled in the art, and are not described herein in detail to highlight the innovative features of the present invention.
Claims (10)
1. A method for manufacturing an image sensor, comprising at least the steps of:
providing a substrate, wherein the substrate comprises a device region and a non-device region;
forming a first oxide layer on the substrate, wherein the first oxide layer covers the device region and extends to part of the non-device region;
forming a step on the substrate of the non-device region;
forming a second oxide material layer on the substrate, wherein the second oxide material layer covers the first oxide layer, the surface of the step and the side wall;
forming a sacrificial layer on the surface of the second oxide material layer;
flattening the sacrificial layer at least twice to remove the sacrificial layer and part of the second oxide material layer, and polishing to form a second oxide layer;
forming a bonding contact layer on the second oxide layer; and
and bonding the bonding contact layer with the bearing substrate to form the image sensor.
2. The method of claim 1, wherein the bonding contact layer is formed by high-density plasma chemical vapor deposition.
3. The method of claim 1, wherein the polishing process applies a pressure that is half of the pressure applied by the planarization process.
4. The method of manufacturing an image sensor of claim 1, wherein the step of forming the second oxide layer comprises:
forming a first sacrificial layer on the surface of the second oxide material layer;
carrying out first planarization treatment on the first sacrificial layer to remove part of the thickness of the first sacrificial layer and form a second sacrificial layer;
performing a second planarization treatment on the second sacrificial layer to remove the second sacrificial layer and a part of the second oxide material layer with the thickness to form an intermediate oxide material layer; and
and performing first polishing treatment on the intermediate oxide material layer to remove part of the thickness of the intermediate oxide material layer, so as to form a second oxide layer, wherein the surface of the second oxide layer is smooth.
5. The method of manufacturing an image sensor according to claim 4, wherein the first polishing process is performed at a thickness of 70nm to 90nm for a period of 57s to 67s.
6. The method of manufacturing an image sensor according to claim 4, wherein the roughness of the surface of the second oxide layer after the first polishing process is 0.1nm to 0.3nm.
7. The method of manufacturing an image sensor of claim 4, wherein the step of forming the bonding contact layer comprises:
forming a bonding material layer on the surface of the second oxide layer;
and performing secondary polishing treatment on the bonding material layer to remove part of the bonding material layer to form a bonding contact layer.
8. The method of claim 7, wherein the bonding material layer has a thickness of 90nm-110nm.
9. The method of manufacturing an image sensor according to claim 7, wherein the roughness of the surface of the bonding contact layer after the second polishing process is 0.1nm to 0.3nm.
10. The method of manufacturing an image sensor of claim 7, further comprising: and after the bonding contact layer is formed, carrying out particle removal and cleaning treatment on the substrate.
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