CN117674741A - Power amplifier, power amplifier assembly and signal processing device - Google Patents
Power amplifier, power amplifier assembly and signal processing device Download PDFInfo
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- CN117674741A CN117674741A CN202211040833.1A CN202211040833A CN117674741A CN 117674741 A CN117674741 A CN 117674741A CN 202211040833 A CN202211040833 A CN 202211040833A CN 117674741 A CN117674741 A CN 117674741A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3205—Modifications of amplifiers to reduce non-linear distortion in field-effect transistor amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45051—Two or more differential amplifiers cascade coupled
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Abstract
The disclosure provides a power amplifier, the power amplifier includes first transistor and second transistor, the grid of first transistor with the grid electricity of second transistor is connected, the first pole of first transistor with the positive output of power amplifier is connected, the first pole of second transistor with the negative output of power amplifier is connected, the power amplifier still includes peaking inductance, peaking inductance's first end with the second pole electricity of first transistor is connected, peaking inductance's second end with the second pole electricity of second transistor is connected. The present disclosure also provides a power amplifier assembly and a signal processing apparatus.
Description
Technical Field
The present disclosure relates to the field of communication devices, and in particular to a power amplifier, a power amplifier assembly comprising the power amplifier, and a signal processing device comprising the power amplifier assembly.
Background
With the advent of fifth generation mobile communications, requirements on performance such as transmission rate, time delay, reliability and the like are continuously improved, and besides improvement of a communication frequency band (to a millimeter wave frequency band), a large-scale phased array technology and a Massive MIMO technology, and a high-order modulation mode such as 256QAM and even 1024QAM are also developed.
The above changes have great influence on the most core Power Amplifier (PA) in the transceiver, and the application of the large-scale phased array technology and the Massive MIMO technology means that the transceiver needs to integrate a large-scale front-end array channel, so that the PA module must be integrated into the transceiver chip to implement the PA by adopting a silicon-based process, and the PA cannot implement the large output Power by adopting a three-five-family process alone like the 4G and 3G communication, but still requires the PA to have a large output Power. In addition, 5G communication requires a higher order modulation scheme, which requires a larger peak-to-average power ratio (PAPR) and a higher linear output power, and thus also puts higher demands on the linearity of the PA.
Disclosure of Invention
It is an object of the present disclosure to provide a power amplifier, a power amplifier assembly including the power amplifier, and a signal processing apparatus including the power amplifier assembly.
As one aspect of the present disclosure, there is provided a power amplifier including a first transistor and a second transistor, a gate of the first transistor being electrically connected to a gate of the second transistor, a first pole of the first transistor being electrically connected to a positive output terminal of the power amplifier, a first pole of the second transistor being electrically connected to a negative output terminal of the power amplifier, wherein the power amplifier further includes a peaking inductor, a first end of the peaking inductor being electrically connected to a second pole of the first transistor, and a second end of the peaking inductor being electrically connected to a second pole of the second transistor.
As a second aspect of the present disclosure, there is provided a power amplifier assembly comprising a driver stage amplifier, at least one power stage amplifier, wherein the driver stage amplifier is a power amplifier according to one embodiment of the first aspect of the present disclosure, and the power stage amplifier is a power amplifier according to another embodiment of the first aspect of the present disclosure.
As a third aspect of the present disclosure, there is provided a signal processing apparatus comprising a power amplifier assembly, wherein the power amplifier assembly comprises the power amplifier assembly of the second aspect of the present disclosure.
In the power amplifier provided by the disclosure, the peaking inductor connected in parallel in a bridging way can resonate out the influence of parasitic capacitance, so that the output power of the power amplifier can be improved.
In some embodiments, the power amplifier includes a first auxiliary capacitor, a second auxiliary capacitor and a resonant inductor, and the LC network resonates at a second harmonic, and the linearity of the power amplifier can be further improved by combining the LC network of the input stage matching circuit.
Drawings
FIG. 1 is a schematic diagram of one embodiment of a power amplifier provided by a first aspect of the present disclosure;
fig. 2 is a schematic diagram of another embodiment of a power amplifier provided by the first aspect of the present disclosure;
fig. 3 is a circuit schematic of a power amplifier assembly provided by the present disclosure;
fig. 4 is a schematic diagram of two third transformers.
Detailed Description
In order to better understand the technical solutions of the present disclosure, the power amplifier assembly including the power amplifier, and the signal processing apparatus including the power amplifier assembly provided by the present disclosure are described in detail below with reference to the accompanying drawings.
Example embodiments will be described more fully hereinafter with reference to the accompanying drawings, but may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
Embodiments of the disclosure and features of embodiments may be combined with each other without conflict.
As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The inventor of the present disclosure has studied and found that the reason why the output power of the power amplifier is not high is that the power amplifier is an integrated circuit, conductive elements of different devices are located in different layers, parasitic capacitance is formed, and the output power of the power amplifier is reduced due to the parasitic capacitance.
For example, when the operating frequency reaches the millimeter wave band, considering the performance of the process itself, a process with a characteristic frequency (ft) greater than 200GHz needs to be selected, and in general, the process is Dou Xiao at 65nm, and the breakdown voltage of these advanced processes is low, so that the PA is difficult to achieve a large output power, and in addition, in the millimeter wave band, the parasitic effect and the electromagnetic coupling are more serious, which further worsens the output power of the PA. Based on the background, the design of the high-output-power high-linearity PA has wide market prospect and application value.
Conventional PA circuits typically employ a one-way architecture. Because the differential structure has better linearity, output power and anti-interference capability than the single-end structure, most of the current PAs adopt the differential structure, and the main structure is divided into the following types: differential cascode, differential stack structure. For the differential common source structure, the differential common source structure has higher linearity, but lower output power, and in addition, the common source structure has breakdown risk under the high output power state, and the reliability is lower; for a differential cascode structure, it has moderate linearity and output power. However, for 5G communication, the single-stage differential cascode structure still cannot meet the requirements. In order to further increase the output power of the single-stage amplifier, a differential stacked transistor structure has been proposed in recent years, wherein the output power can meet the 5G communication requirement, but the more the stacked transistors, the more serious the parasitic effect, and each transistor compresses the voltage margin, so that the linearity is poor and the requirement cannot be met. In order to compromise the contradiction between output power and linearity, a power combining architecture has been proposed. Theoretically, each multiple path is synthesized, the output power is more (10 log N) dB, N is the number of synthesized paths, but as N increases, the loss of the synthesized network is also greater, the synthesis gain is significantly reduced, so in practical design, N generally does not exceed 4. In addition, because the 5G communication adopts large-scale array integration, the channel size is smaller, the PA size is required to be miniaturized, the scale of power synthesis is limited, and when the power synthesis is adopted under the size limitation, serious electromagnetic coupling is often suffered, the balance of a synthesis network is greatly deteriorated, so that the loss of the synthesis network is increased, and the income of power synthesis is reduced. Therefore, the PA with high output power and high linearity remains a bottleneck in the industry on the premise of compromising the size and power consumption.
In view of this, as an aspect of the disclosure, there is provided a power amplifier, as shown in fig. 1, the power amplifier includes a first transistor M1 and a second transistor M2, a gate of the first transistor M1 is electrically connected to a gate of the second transistor M2, a first pole of the first transistor M1 is electrically connected to a positive output out+ of the power amplifier, and a first pole of the second transistor M2 is electrically connected to a negative output Out of the power amplifier. The power amplifier further includes a peaking inductor L2, a first end of the peaking inductor L2 is electrically connected to the second pole of the first transistor M1, and a second end of the peaking inductor L2 is electrically connected to the second pole of the second transistor M2.
In the power amplifier provided by the disclosure, the peaking inductor L2 connected in parallel in a bridging manner between the positive output end out+ and the negative output end Out-can resonate Out the influence of parasitic capacitance, so that the output power of the power amplifier can be improved.
As an alternative embodiment, the first transistor M1 and the second transistor M2 are both N-type transistors, and the size of the first transistor M1 is the same as the size of the second transistor M2.
It should be noted that the gate of the first transistor M1 and the gate of the second transistor M2 need to be electrically connected to the Bias input Bias to maintain the normal operation of the power amplifier.
In the present disclosure, the "first transistor M1" and the "second transistor M2" may be transistors, or field effect transistors. The "gate" as described in this disclosure is the electrode from which the base region of the transistor leads. The "gate", "base", "gate electrode", etc. are equivalent to the "gate" shown in the present disclosure.
It should be noted that, in the present disclosure, in the case of power-up, the first transistor M1 is the drain of the first transistor M1, the second transistor M1 is the source of the first transistor M1, the first transistor M2 is the drain of the second transistor M2, and the second transistor M2 is the source of the second transistor M2.
Optionally, the power amplifier further includes a first auxiliary capacitor C1, a second auxiliary capacitor C2, and a resonant inductor L1, where a first end of the first auxiliary capacitor C1 is electrically connected to the first pole of the first transistor M1, a second end of the first auxiliary capacitor C1 is electrically connected to a first end of the second auxiliary capacitor C2, a second end of the second auxiliary capacitor C2 is electrically connected to the first pole of the second transistor M2, a first end of the resonant inductor L1 is electrically connected to a second end of the first auxiliary capacitor C1, and a second end of the resonant inductor L1 is electrically connected to the reference signal end.
The provision of the first auxiliary capacitor C1 and the second auxiliary capacitor C2 can adjust the output impedance of the power amplifier so that the power amplifier has sufficient output power to drive the power amplifier of the subsequent stage.
The first auxiliary capacitor C1, the second auxiliary capacitor C2 and the resonant inductor L1 may form an LC network that resonates at a second harmonic, and the linearity of the power amplifier may be further improved in combination with an LC network of an input stage matching circuit (which will be described later). In the present disclosure, the reference signal terminal electrically connected to the second terminal of the resonant inductor L1 may be a virtual ground node, and the first auxiliary capacitor C1 and the second auxiliary capacitor C2 may be grounded by introducing the resonant inductor L1, thereby avoiding deteriorating other functions of the power amplifier.
In the present disclosure, the size of the first auxiliary capacitor C1 may be the same as the size of the second auxiliary capacitor C2.
In the present disclosure, other structures of the power amplifier are not particularly limited. For example, the power amplifier may be an amplifier having a cascode structure. That is, the power amplifier further includes a third transistor M3 and a fourth transistor M4, the first pole of the third transistor M3 is electrically connected to the first pole of the fourth transistor M4 and to the reference signal terminal, the gate of the third transistor M3 is electrically connected to the input signal positive input terminal in+, the gate of the fourth transistor M4 is electrically connected to the input signal negative input terminal In-, the second pole of the third transistor M3 is electrically connected to the second pole of the first transistor M1, and the second pole of the fourth transistor M4 is electrically connected to the second pole of the second transistor M2.
In the present disclosure, the third transistor M3 and the fourth transistor M4 are both N-type transistors, and the size of the third transistor M3 may be the same as the size of the fourth transistor M4.
It should be noted that, in the present disclosure, in the case of power-up, the second of the third transistor M3 is the drain of the third transistor, the first of the third transistor M3 is the source of the third transistor, the second of the fourth transistor M4 is the drain of the fourth transistor, and the first of the fourth transistor M4 is the source of the fourth transistor.
Optionally, the power amplifier may further include a first neutralization capacitor C3 and a second neutralization capacitor C4. One end of the first neutralization capacitor C3 is electrically connected to the first pole of the third transistor M3, the other end of the first neutralization capacitor C3 is electrically connected to the negative input terminal In of the input signal, one end of the second neutralization capacitor C4 is electrically connected to the first pole of the fourth transistor M4, and the other end of the second neutralization capacitor C4 is electrically connected to the positive input terminal In of the input signal. The provision of the first and second neutralization capacitances C3 and C4 can neutralize parasitic capacitances of the third transistor M3 and the fourth transistor M4, thereby improving stability and gain of the power amplifier.
As an alternative embodiment, the first neutralization capacitor C3 and the second neutralization capacitor C4 are the same size.
As an alternative embodiment, as shown In fig. 2, the power amplifier further includes a variable capacitor, where the variable capacitor includes a first P-type transistor M5 and a second P-type transistor M6, a first pole of the first P-type transistor M5 is electrically connected to a second pole of the second P-type transistor M6, a first pole of the second P-type transistor M6 is electrically connected to a second pole of the second P-type transistor M6, a first pole of the first P-type transistor M5 is electrically connected to a first pole of the second P-type transistor M6, a gate of the first P-type transistor M5 is electrically connected to the input signal positive input terminal in+, and a gate of the second P-type transistor M6 is electrically connected to the input signal negative input terminal In-.
As described above, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 in the power amplifier are all N-type transistors, and after the variable capacitor formed by the P-type transistors is set, the characteristic of the variable capacitor along with the power variation is opposite to the characteristic of the parasitic capacitor formed by the N-type transistors along with the power variation, so that the AM-PM characteristic of the power amplifier can be compensated, and the linearity of the power amplifier can be improved.
Alternatively, the first P-type transistor M5 and the second P-type transistor M6 are the same size.
As a second aspect of the present disclosure, there is provided a power amplifier assembly, as shown in fig. 3, including a driver stage amplifier A1 and at least one power stage amplifier, wherein the driver stage amplifier A1 is a power amplifier provided by one embodiment of the first aspect of the present disclosure, and the power stage amplifier is a power amplifier provided by another embodiment of the first aspect of the present disclosure.
As an alternative embodiment, the driver stage amplifier A1 may be the power amplifier shown in fig. 1, and as described above, the peaking inductance L2 connected across the positive output terminal out+ and the negative output terminal Out-may resonate Out the influence of parasitic capacitance, so that the output power of the power amplifier may be increased.
The provision of the first auxiliary capacitance C1 and the second auxiliary capacitance C2 can adjust the output impedance of the power amplifier so that the power amplifier has sufficient output power to drive the power amplifier of the subsequent stage (i.e., the power stage amplifier).
The power stage amplifier may be the power amplifier shown in fig. 2. In addition to having the advantages of the power amplifier shown in fig. 1, the power stage amplifier has a better linearity.
In the present disclosure, the number of power stage amplifiers is not particularly limited. As an alternative embodiment, the amplifier assembly may comprise two power stage amplifiers, power stage amplifier A2 and power stage amplifier A3, respectively. The two power stage amplifiers are combined, and the two power stage amplifiers have the same structure.
As shown in fig. 3, the power amplifier assembly further includes an input stage matching circuit 100, where the input stage matching circuit 100 includes a first transformer TF1, a first matching capacitor C5, a second matching capacitor C7, and a third auxiliary capacitor C6, the first matching capacitor C5 is connected across the primary winding of the first transformer TF1, the second matching capacitor C7 is connected across the secondary winding of the first transformer TF1, the first end of the third auxiliary capacitor C6 is electrically connected to the tap of the secondary winding of the first transformer TF1, the second end of the third auxiliary capacitor C6 is electrically connected to the reference signal end, and the two ends of the secondary winding of the first transformer TF1 are electrically connected to the positive input end of the driving stage amplifier A1 and the negative input end of the driving stage power amplifier, respectively.
In the disclosure, the first matching capacitor C5 and the second matching capacitor C7 can tune the impedance, so as to realize impedance matching of the driving stage amplifier A1, and the third auxiliary capacitor C6 and the inductance of the secondary coil of the first transformer TF1 form a second harmonic LC network, so that the linearity of the amplifier assembly can be further improved.
Since the center tap of the first transformer TF1 is a virtual point for the desired signal, the addition of the third auxiliary capacitor C6 does not affect other performance of the power amplifier assembly. In the present embodiment, the intermediate tap of the first transformer TF1 is electrically connected to the Bias signal terminal Bias 1. The input of the first transformer TF1 is the input pa_in of the amplifier assembly.
As one embodiment of the disclosure, the power amplifier includes an inter-stage matching circuit 200, where the inter-stage matching circuit 200 includes a second transformer TF2, a third matching capacitor C9, and a fourth auxiliary capacitor C8, two ends of a primary coil of the second transformer TF2 are electrically connected to a positive output terminal and a negative output terminal of the driver stage amplifier A1, two ends of the third matching capacitor C9 are connected across two ends of a secondary coil of the second transformer TF2, a first end of the fourth auxiliary capacitor C8 is electrically connected to a center tap of the secondary coil of the second transformer TF2, a second end of the fourth auxiliary capacitor C8 is electrically connected to a reference signal terminal, and two ends of a secondary coil of the second transformer TF2 are electrically connected to a positive input terminal and a negative input terminal of the power stage amplifier, respectively.
The intermediate tap of the primary winding of the second transformer TF2 is electrically connected to the high-level signal terminal VDD 1. The intermediate tap of the secondary winding of the second transformer TF2 is grounded through a fourth auxiliary capacitor C8, and at the same time, the intermediate tap of the secondary winding of the second transformer TF2 is electrically connected to the Bias voltage signal terminal Bias 3. The two ends of the third matching capacitor C9 are connected with the two ends of the secondary coil of the second transformer TF2 in a bridging mode, impedance adjustment can be achieved, bamboo basket matching between the driving-stage amplifier A1 and the power-stage power amplifier is achieved, and maximum power transmission of the driving-stage amplifier is achieved. The fourth auxiliary capacitor C8 and the inductance of the secondary winding of the second transformer TF2 form a second harmonic LC network, improving linearity.
In the present disclosure, how the second transformer TF2 is electrically connected to the power stage amplifier is not particularly limited. When the power amplifier assembly includes a plurality of power stage amplifiers, both ends of the secondary winding of the second transformer TF2 are electrically connected to the power divider PD 1. Alternatively, the power divider PD1 may adopt a zero degree power dividing structure, and adopt a fully symmetrical layout, so as to ensure the balance of the amplitude and the phase of the multi-path power stage amplifier.
In the present disclosure, the power amplifier further includes a power combiner PC1 and at least one output stage matching circuit 300, and the at least one output stage matching circuit 300 corresponds to at least one of the power stage amplifiers one by one. The output stage matching circuit 300 includes a third transformer TF3 and a fourth matching capacitor C10, two ends of a primary coil of the third transformer TF3 are electrically connected to a positive output end and a negative output end of a corresponding power stage amplifier, a first end of a secondary coil of the third transformer TF3 is electrically connected to a reference signal end, a second end of a secondary coil of the third transformer TF3 is electrically connected to an input end of the power combiner PC1, and the fourth matching capacitor C10 is connected across two ends of the secondary coil of the third transformer TF 3.
The intermediate tap of the primary winding of the third transformer TF3 is electrically connected to the high level signal terminal VDD 2. The fourth matching capacitor C10 can adjust the impedance of the output match so that the output impedance is at the maximum output load impedance point of the power stage.
In the embodiment shown in fig. 3, the power amplifier assembly comprises two power stage amplifiers, power stage amplifier A2 and power stage amplifier A3, respectively. That is, the power stage adopts two-way synthesis, and the power stage amplifier A2 and the power stage amplifier A3 are also biased in the AB type working state, so that the efficiency, the linearity and the output power performance are improved. Because the power stage amplifier comprises a variable capacitor formed by the P-type transistors, AM-PM distortion can be compensated, and linearity is improved.
As an alternative embodiment, as shown in fig. 4, the periphery of the third transformer TF3 is provided with a ground shield.
Since the electromagnetic coupling between the two third transformers TF3 is significantly deteriorated in balance due to the close distance between them within a limited size as shown in fig. 4, a ground shielding layer is added around each transformer to reduce the electromagnetic coupling. In addition, the primary cause of affecting the output matching network resultant power and efficiency is the amplitude and phase imbalance. The amplitude imbalance mainly is due to the fact that the two paths of third transformers are all differential to single-ended balun, the second coil is grounded in one circle, the other end of the third transformer is connected with the load output by the PA, leakage currents Ip1 and Ip2 are caused by parasitic capacitances Cp1 and Cp2 of the primary and secondary coils of the transformers, and the difference of leakage currents at two ends is caused by the difference of loads at two ends of the secondary coils (Ip1 not equal to Ip 2), so that the amplitude imbalance of a differential port is caused, and the synthesized power and efficiency are greatly deteriorated. To improve this problem, in this patent, the parasitic capacitance across the primary and secondary coils is improved by adjusting the overlapping offset position of the primary and secondary coils, i.e., (d±Δ) in the figure, so that the leakage current is uniform (ip1=ip2), and finally the balance of the amplitude is ensured. For phase imbalance, this can be achieved by the position of the intermediate taps of the primary coils of the two third transformers TF3, i.e. s in the figure; on the other hand, the decoupling capacitors with large capacitance are symmetrically connected on the connecting line of the two transformer center taps, so that the phase imbalance can be effectively improved. Based on the improvement method, the amplitude-phase balance of the output matching network can be obviously improved, so that the synthesized power and efficiency are improved, and the loss is reduced.
Shown in table 1 is a comparison of different power amplifier performance at the same power consumption.
TABLE 1
As can be seen from table 1, the power amplifier assembly provided by the present disclosure has better performance.
As a third aspect of the present disclosure, there is provided a signal processing apparatus comprising a power amplifier assembly, wherein the power amplifier comprises a power amplifier assembly provided by the second aspect of the present disclosure.
The signal processing device may be a signal transmitter, a signal receiver in a millimeter wave communication system or a radar system, or may be any one of LNA, VGA, DA and the like.
And are generally meant to be illustrative and not limiting. In some instances, it will be apparent to one skilled in the art that features, characteristics, and/or elements described in connection with a particular embodiment may be used alone or in combination with other embodiments unless explicitly stated otherwise. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the disclosure as set forth in the appended claims.
Claims (10)
1. A power amplifier comprising a first transistor and a second transistor, the gate of the first transistor being electrically connected to the gate of the second transistor, the first pole of the first transistor being electrically connected to the positive output of the power amplifier, the first pole of the second transistor being electrically connected to the negative output of the power amplifier, characterized in that the power amplifier further comprises a peaking inductance, the first end of the peaking inductance being electrically connected to the second pole of the first transistor, the second end of the peaking inductance being electrically connected to the second pole of the second transistor.
2. The power amplifier of claim 1, further comprising a first auxiliary capacitor, a second auxiliary capacitor, and a resonant inductor, wherein a first end of the first auxiliary capacitor is electrically connected to a first pole of the first transistor, a second end of the first auxiliary capacitor is electrically connected to a first end of the second auxiliary capacitor, a second end of the second auxiliary capacitor is electrically connected to a first pole of the second transistor, a first end of the resonant inductor is electrically connected to a second end of the first auxiliary capacitor, and a second end of the resonant inductor is electrically connected to a reference signal.
3. The power amplifier of claim 1 or 2, further comprising a third transistor and a fourth transistor, a first pole of the third transistor being electrically connected to a first pole of the fourth transistor and to a reference signal terminal, a gate of the third transistor being electrically connected to an input signal positive input terminal, a gate of the fourth transistor being electrically connected to an input signal negative input terminal, a second pole of the third transistor being electrically connected to a second pole of the first transistor, and a second pole of the fourth transistor being electrically connected to a second pole of the second transistor.
4. The power amplifier of claim 3 further comprising a variable capacitor comprising a first P-type transistor and a second P-type transistor, a first pole of the first P-type transistor being electrically connected to a second pole of the first P-type transistor, a first pole of the second P-type transistor being electrically connected to a second pole of the second P-type transistor, and a first pole of the first P-type transistor being electrically connected to a first pole of the second P-type transistor, a gate of the first P-type transistor being electrically connected to the input signal positive input terminal, and a gate of the second P-type transistor being electrically connected to the input signal negative input terminal.
5. A power amplifier assembly comprising a driver stage amplifier, at least one power stage amplifier, wherein the driver stage amplifier is the power amplifier of any one of claims 1 to 3, and the power stage amplifier is the power amplifier of claim 4.
6. The power amplifier assembly of claim 5, further comprising an input stage matching circuit comprising a first transformer, a first matching capacitor, a second matching capacitor and a third auxiliary capacitor, the first matching capacitor being connected across a primary winding of the first transformer, the second matching capacitor being connected across a secondary winding of the first transformer, a first end of the third auxiliary capacitor being electrically connected to a tap of the secondary winding, a second end of the third auxiliary capacitor being electrically connected to a reference signal end, the two ends of the secondary winding of the first transformer being electrically connected to a positive input of the driver stage power amplifier and to a negative input of the driver stage power amplifier, respectively.
7. The power amplifier assembly of claim 5, wherein the power amplifier comprises an inter-stage matching circuit comprising a second transformer, a third matching capacitor and a fourth auxiliary capacitor, wherein two ends of a primary coil of the second transformer are respectively electrically connected with a positive output end and a negative output end of the driver stage amplifier, two ends of the third matching capacitor are connected across two ends of a secondary coil of the second transformer, a first end of the fourth auxiliary capacitor is electrically connected with a middle tap of the secondary coil of the second transformer, a second end of the fourth auxiliary capacitor is electrically connected with a reference signal end, and two ends of a secondary coil of the second transformer are respectively electrically connected with a positive input end and a negative input end of the power stage amplifier.
8. The power amplifier assembly of any one of claims 5 to 7, further comprising a power combiner and at least one output stage matching circuit, at least one of the output stage matching circuits being in one-to-one correspondence with at least one of the power stage amplifiers, the output stage matching circuit comprising a third transformer and a fourth matching capacitor, the first end of the secondary winding of the third transformer being electrically connected to the positive output terminal and the negative output terminal, respectively, of the corresponding power stage amplifier, the first end of the secondary winding of the third transformer being electrically connected to the reference signal terminal, the second end of the secondary winding of the third transformer being electrically connected to the input terminal of the power combiner, the fourth matching capacitor being connected across the second end of the secondary winding of the third transformer.
9. The power amplifier assembly of claim 8, wherein a periphery of the third transformer is provided with a ground shield.
10. A signal processing device comprising a power amplifier assembly, characterized in that the power amplifier assembly comprises a power amplifier assembly according to any of claims 5 to 9.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211040833.1A CN117674741A (en) | 2022-08-29 | 2022-08-29 | Power amplifier, power amplifier assembly and signal processing device |
| PCT/CN2023/102633 WO2024045820A1 (en) | 2022-08-29 | 2023-06-27 | Power amplifier, power amplifier assembly and signal processing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211040833.1A CN117674741A (en) | 2022-08-29 | 2022-08-29 | Power amplifier, power amplifier assembly and signal processing device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117674741A true CN117674741A (en) | 2024-03-08 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211040833.1A Pending CN117674741A (en) | 2022-08-29 | 2022-08-29 | Power amplifier, power amplifier assembly and signal processing device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN117674741A (en) |
| WO (1) | WO2024045820A1 (en) |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8779857B2 (en) * | 2009-08-14 | 2014-07-15 | Qualcomm Incorporated | Amplifier with variable matching circuit to improve linearity |
| US10644650B2 (en) * | 2017-09-22 | 2020-05-05 | Qualcomm Incorporated | Amplifier configuration for load-line enhancement |
| CN107681986A (en) * | 2017-10-09 | 2018-02-09 | 东南大学 | Suitable for the neutralization bootstrapping common source and common grid amplifier of millimeter wave power amplification application |
| CN114726325B (en) * | 2022-03-10 | 2023-02-21 | 北京巨束科技有限公司 | Stacking power amplifier, circuit board and electronic equipment |
| CN114844473B (en) * | 2022-04-11 | 2023-06-02 | 电子科技大学 | Double-control-bit type variable gain amplifier adopting compensation capacitance technology |
| CN114826175A (en) * | 2022-05-25 | 2022-07-29 | 上海集成电路研发中心有限公司 | Power amplifying circuit |
-
2022
- 2022-08-29 CN CN202211040833.1A patent/CN117674741A/en active Pending
-
2023
- 2023-06-27 WO PCT/CN2023/102633 patent/WO2024045820A1/en unknown
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| Publication number | Publication date |
|---|---|
| WO2024045820A1 (en) | 2024-03-07 |
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