CN117674051A - High-frequency communication interface static surge protection circuit - Google Patents
High-frequency communication interface static surge protection circuit Download PDFInfo
- Publication number
- CN117674051A CN117674051A CN202311653736.4A CN202311653736A CN117674051A CN 117674051 A CN117674051 A CN 117674051A CN 202311653736 A CN202311653736 A CN 202311653736A CN 117674051 A CN117674051 A CN 117674051A
- Authority
- CN
- China
- Prior art keywords
- diode
- resistor
- electrostatic surge
- npn transistor
- scr current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004891 communication Methods 0.000 title claims abstract description 56
- 230000003068 static effect Effects 0.000 title description 2
- 230000002457 bidirectional effect Effects 0.000 claims abstract description 45
- 230000003071 parasitic effect Effects 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 9
- 230000015556 catabolic process Effects 0.000 claims abstract description 5
- 238000007599 discharging Methods 0.000 claims description 13
- 230000002441 reversible effect Effects 0.000 claims description 13
- 230000008054 signal transmission Effects 0.000 claims description 9
- 230000000694 effects Effects 0.000 claims description 8
- 230000009471 action Effects 0.000 claims description 7
- 230000001105 regulatory effect Effects 0.000 claims description 4
- 230000002708 enhancing effect Effects 0.000 claims description 2
- 230000007246 mechanism Effects 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 5
- 230000004044 response Effects 0.000 abstract description 2
- 230000001960 triggered effect Effects 0.000 abstract description 2
- 230000001629 suppression Effects 0.000 abstract 1
- 230000005540 biological transmission Effects 0.000 description 4
- 230000002829 reductive effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
Landscapes
- Emergency Protection Circuit Devices (AREA)
Abstract
The invention discloses an electrostatic surge protection circuit of a high-frequency communication interface and a parasitic capacitance suppression method. The trigger clamping circuit is used for assisting in triggering the two SCR current release paths, so that the functions of low capacitance, quick starting and strong voltage clamping after conduction of the electrostatic surge protection circuit are realized. When the invention faces to electrostatic surge stress, different breakdown point positions can be triggered and started according to the stress, and electrostatic surge current is discharged in different directions, so that the high-frequency communication interface is protected. On the other hand, the invention also aims at the working characteristics of high frequency response, low working power consumption and high system reliability of the high-frequency communication interface, combines the characteristics of an integrated circuit process platform, develops low capacitance, low electric leakage, strong electrostatic surge robustness and bidirectional electrostatic surge protection circuit design, and improves the electrostatic surge protection efficiency of the high-frequency communication interface.
Description
Technical Field
The invention belongs to the field of integrated circuit design, and particularly relates to a high-frequency communication interface electrostatic surge protection circuit.
Background
In the high-frequency signal transmission process, the parasitic capacitance has a great influence on the signal transmission effect of the high-frequency communication interface. In the high-frequency signal transmission process, the capacitance impedance is lower, and the signal transmission effect is better; in the low-frequency signal transmission process, the capacitance and the impedance are high, and the signal transmission effect is poor. The high-frequency communication interface is commonly used in the fields of Bluetooth, WIF I and other electronic equipment, communication systems, radio spectrum analyzers and the like. High frequency communication interfaces play a very important role in high speed data transmission and radio frequency applications due to their excellent frequency response characteristics, stable transmission performance, reliable connectivity. With the continuous improvement of the working frequency and transmission speed of electronic systems, the requirements of high-frequency communication interfaces on the speed, reliability, power consumption and the like of signal transmission are higher and higher. Particularly in terms of reliability, high frequency communication interfaces are susceptible to electrostatic discharge (ESD), and to over-voltage or over-current effects from surges or what is known as Electrical Overstress (EOS) resulting in failure. The conventional ESD/EOS protection unit may generate a large parasitic capacitance, thereby greatly weakening the performance of the high frequency communication interface for transmitting high frequency signals. Thus, the high frequency communication interface is susceptible to ESD/EOS protection performance and associated parasitic capacitance issues.
The traditional ESD/EOS protection unit such as a diode, a triode, a MOS tube and the like has the defects of large parasitic capacitance, large occupied chip area, large leakage magnitude, poor ESD robustness of circuits on unit area and the like. Silicon Controlled Rectifier (SCR) structures are widely focused in the industry because of the advantages of high ESD robustness, high bleeder capacity, good process compatibility and the like in unit area. However, the SCR structure has the problems of high trigger voltage, high latch-up and parasitic capacitance, and the like, and is difficult to be widely applied to ESD/EOS protection of integrated circuits. The invention utilizes the strong discharging capability of the SCR structure and the voltage clamping capability of the zener diode, reduces parasitic capacitance generated by the electrostatic surge protection circuit by a special circuit design and a cascading capacitance method, and improves the electrostatic surge protection efficiency of the high-frequency communication interface.
Disclosure of Invention
Therefore, the invention aims to solve the technical problems that parasitic capacitance generated by an electrostatic surge protection circuit is difficult to be reduced stably and electrostatic surge protection efficiency of a high-frequency communication interface is improved in the prior art, and provides the electrostatic surge protection circuit of the high-frequency communication interface and electric equipment.
In order to solve the above technical problems, the present invention provides an electrostatic surge protection circuit of a high-frequency communication interface, which includes: the trigger clamping circuit and the two SCR current release paths; the trigger clamping circuit comprises a plurality of diodes, a resistor and a bidirectional zener diode, and the SCR current release path comprises a PNP transistor and an NPN transistor; when a forward electrostatic surge stress acts on the electrostatic surge protection circuit, the trigger clamp circuit includes: resistor Rc1, diode D11, bidirectional zener diode ZD, diode D21, resistor Rc2; the first SCR current bleed path includes: a PNP transistor Tc1, an NPN transistor Tc4; the second SCR current bleed path includes: PNP transistor T21, NPN transistor T31, resistor R31; when the power end VDD of the high-frequency communication interface is connected with high potential and the VSS is connected with low potential, the power end VDD of the high-frequency communication interface is connected with the upper end of the resistor Rc 1; the lower end of the resistor Rc1 is connected with the anode of the diode D11; the cathode of the diode D11 is connected with the cathode of the bidirectional zener diode ZD; the anode of the bidirectional zener diode ZD is connected with the anode of the diode D21; the cathode of the diode D21 is connected with the upper end of the resistor Rc2, and the lower end of the resistor Rc2 is connected with the ground terminal VSS of the high-frequency communication interface; the power supply terminal VDD, the upper end of the resistor Rc1 is connected to the emitter of the PNP transistor Tc1, the base of the PNP transistor Tc1 is connected to the collector of the NPN transistor Tc4, the base of the PNP transistor T21 is connected to the collector of the PNP transistor Tc1, the base of the NPN transistor Tc4 is connected to the emitter of the NPN transistor T31, and the cathode of the diode D21 is connected to the upper end of the resistor Rc2; the emitter of the PNP transistor T21 is connected with the lower end of the resistor Rc1, the anode of the diode D11 is connected with the base of the PNP transistor T21, the collector of the NPN transistor T31 is connected with the collector of the NPN transistor Tc4; the collector of the PNP transistor T21 is connected with the base of the NPN transistor T31, the anode of the bidirectional zener diode is connected with the anode of the diode D21 and the upper end of the resistor R31; the lower end of the resistor R31 is connected with the base electrode of the NPN transistor Tc4, the emitter electrode of the NPN transistor T31, and the cathode of the diode D21 is connected with the upper end of the resistor Rc2; the emitter of the NPN transistor Tc4 is connected with the lower end of the resistor Rc2 and the ground terminal VSS of the high-frequency communication interface; when reverse electrostatic surge stress acts on the electrostatic surge protection circuit, the trigger clamp circuit includes: the resistor Rc1, the diode D12, the bidirectional zener diode ZD, the diode D22 and the resistor Rc2; the third SCR current bleed path includes: the PNP transistor Tc1, the NPN transistor Tc4; the fourth SCR current bleed path includes: a PNP transistor T22, an NPN transistor T32, and a resistor R32; when the ground terminal VSS of the high-frequency communication interface is connected with high potential and the power supply terminal VDD is connected with low potential, the ground terminal VSS of the high-frequency communication interface is connected with the lower end of the resistor Rc2; the lower end of the resistor Rc2 is connected with the anode of the diode D22; the cathode of the diode D22 is connected with the cathode of the bidirectional zener diode ZD; the anode of the bidirectional zener diode ZD is connected with the anode of the diode D12; the cathode of the diode D12 is connected with the lower end of the resistor Rc1, and the upper end of the resistor Rc1 is connected with the power supply end VDD of the high-frequency communication interface; the lower ends of the resistors Rc2 are connected with the emitter of the PNP transistor Tc1, the base of the PNP transistor Tc1 is connected with the collector of the NPN transistor Tc4, the base of the PNP transistor T22 is connected with the collector of the PNP transistor Tc1 is connected with the base of the NPN transistor Tc4, the emitter of the NPN transistor T32 is connected with the cathode of the diode D12 and the lower end of the resistor Rc 1; the emitter of the PNP transistor T22 is connected with the upper end of the resistor Rc2, the anode of the diode D22 is connected, the base of the PNP transistor T22 is connected with the collector of the NPN transistor T32, and the collector of the NPN transistor Tc4 is connected; the collector of the PNP transistor T22 is connected with the base of the NPN transistor T32, the anode of the bidirectional zener diode D12 is connected with the lower end of the resistor R32; the upper end of the resistor R32 is connected with the base electrode of the NPN transistor Tc4, the emitter electrode of the NPN transistor T32, and the cathode of the diode D12 is connected with the lower end of the resistor Rc 1; the emitter of the NPN transistor Tc4 is connected with the upper end of the resistor Rc1 and the power supply end VDD of the high-frequency communication interface.
In one embodiment of the present invention, the trigger clamping circuit can regulate the trigger turn-on voltage and the clamping voltage of the electrostatic surge protection circuit by regulating the cascade number of diodes or zener diodes, so as to meet the electrostatic and surge protection requirements of the high frequency communication interfaces of different power domains.
In one embodiment of the invention, the forward trigger clamp circuit is composed of the diode D11, the diode D21 and the bidirectional zener diode ZD, the reverse trigger clamp circuit is composed of the diode D22, the diode D12 and the bidirectional zener diode ZD, and the trigger clamp circuit reduces the parasitic capacitance of the electrostatic surge protection circuit and reduces the influence of the electrostatic surge protection circuit on the signal transmission capability of a high-frequency communication interface by using a diode and zener diode cascading method; on the other hand, by utilizing different breakdown mechanisms of the bidirectional zener diode ZD, the triggering opening speed and the triggering opening voltage of the electrostatic surge protection circuit are regulated and controlled, and the electrostatic surge discharging efficiency of the high-frequency communication interface is improved.
In one embodiment of the present invention, as the electrostatic surge stress continuously increases, when the forward electrostatic surge stress acts on the electrostatic surge protection circuit, the first SCR current drain path is opened earlier than the second SCR current drain path, the second SCR current drain path is located in the middle of the first SCR current drain path, when the reverse electrostatic surge stress acts on the electrostatic surge protection circuit, the third SCR current drain path is opened earlier than the fourth SCR current drain path, and the fourth SCR current drain path is located in the middle of the third SCR current drain path, so that the current conduction uniformity of the first SCR current drain path and the third SCR current drain path can be improved; thereby enhancing the electrostatic surge protection capability of the high frequency communication interface.
In an embodiment of the present invention, the bidirectional zener is located between the first SCR current drain path and the second SCR current drain path, and the third SCR current drain path and the fourth SCR current drain path, so that latch-up can be avoided after the first SCR current drain path and the second SCR current drain path, and the third SCR current drain path and the fourth SCR current drain path are triggered to open, so as to enhance latch-up resistance of the circuit.
In one embodiment of the invention, under the action of forward and reverse electrostatic surge stress, the layout shape and the relevant dimension parameters of the first SCR current release path and the third SCR current release path in the electrostatic surge protection circuit of the high-frequency communication interface are the same, the current release capacity is the same, the bidirectional zener diode is used for triggering clamping, and the first SCR current release path, the third SCR current release path and the bidirectional zener diode do not need to occupy additional chip area, so that the electrostatic surge protection efficiency can be improved; the second SCR current discharging path and the fourth SCR current discharging path are symmetrical in physical layout and electrical structure, the diode D11 and the diode D12 are also symmetrical in physical layout and electrical structure, the diode D21 and the diode D22 share a P well, and bidirectional protection effect of electrostatic surge can be achieved.
Drawings
In order that the invention may be more readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof that are illustrated in the appended drawings.
FIG. 1 is a schematic diagram of a circuit design according to the present invention.
Detailed Description
As shown in fig. 1, the invention provides a design schematic diagram of a bidirectional electrostatic surge protection circuit suitable for forward and reverse electrostatic surge stress aiming at the electrostatic surge protection requirement of a high-frequency communication interface. The specific circuit structure and the working principle thereof are as follows:
the trigger clamping circuit and the two SCR current release paths; the trigger clamping circuit comprises a plurality of diodes, a resistor and a bidirectional zener diode, and the SCR current release path comprises a PNP transistor and an NPN transistor;
when a forward electrostatic surge stress acts on the electrostatic surge protection circuit, the trigger clamp circuit includes: the resistor Rc1, the diode D11, the bidirectional zener diode ZD, the diode D21 and the resistor Rc2; the first SCR current bleed path includes: the PNP transistor Tc1, the NPN transistor Tc4; the second SCR current bleed path includes: the PNP transistor T21, the NPN transistor T31, the resistor R31;
when the power end VDD of the high-frequency communication interface is connected with high potential and the VSS is connected with low potential, the power end VDD of the high-frequency communication interface is connected with the upper end of the resistor Rc 1; the lower end of the resistor Rc1 is connected with the anode of the diode D11; the cathode of the diode D11 is connected with the cathode of the bidirectional zener diode ZD; the anode of the bidirectional zener diode ZD is connected with the anode of the diode D21; the cathode of the diode D21 is connected with the upper end of the resistor Rc2, and the lower end of the resistor Rc2 is connected with the ground terminal VSS of the high-frequency communication interface; under the auxiliary triggering action of zener breakdown of the bidirectional zener diode ZD, the triggering voltage of the electrostatic surge protection circuit is reduced, and the starting speed is high. At the same time, the voltage drop across the resistor Rc2 may increase rapidly to 0.7V, thereby facilitating the transistor Tc4 to trigger on.
The power supply terminal VDD, the upper end of the resistor Rc1 is connected to the emitter of the PNP transistor Tc1, the base of the PNP transistor Tc1 is connected to the collector of the NPN transistor Tc4, the base of the PNP transistor T21 is connected to the collector of the PNP transistor Tc1, the base of the NPN transistor Tc4 is connected to the emitter of the NPN transistor T31, and the cathode of the diode D21 is connected to the upper end of the resistor Rc2; the emitter of the PNP transistor T21 is connected with the lower end of the resistor Rc1, the anode of the diode D11 is connected with the base of the PNP transistor T21, the collector of the NPN transistor T31 is connected with the collector of the NPN transistor Tc4; the collector of the PNP transistor T21 is connected with the base of the NPN transistor T31, the anode of the bidirectional zener diode is connected with the anode of the diode D21 and the upper end of the resistor R31; the lower end of the resistor R31 is connected with the base electrode of the NPN transistor Tc4, the emitter electrode of the NPN transistor T31, and the cathode of the diode D21 is connected with the upper end of the resistor Rc2; the emitter of the NPN transistor Tc4 is connected with the lower end of the resistor Rc2 and the ground terminal VSS of the high-frequency communication interface;
under the positive feedback action of the SCR formed by the transistor Tc4 and the transistor Tc1, the first SCR current discharging path triggers and starts to discharge ESD current. This further promotes the voltage drop of the resistor R31 to rise, pushes the transistor T31 to trigger and turn on, and under the positive feedback effect of the SCR formed by the transistor T31 and the transistor T21, the second SCR trigger path is turned on, so as to assist the first SCR current discharge path to trigger and discharge the electrostatic surge current, and enhance the robustness of the electrostatic surge protection circuit.
When reverse electrostatic surge stress acts on the electrostatic surge protection circuit, the trigger clamp circuit includes: the resistor Rc1, the diode D12, the bidirectional zener diode ZD, the diode D22 and the resistor Rc2; the third SCR current bleed path includes: the PNP transistor Tc1, the NPN transistor Tc4; the fourth SCR current bleed path includes: the PNP transistor T22, the NPN transistor T32, and the resistor R32;
when the ground terminal VSS of the high-frequency communication interface is connected with high potential and the power supply terminal VDD is connected with low potential, the ground terminal VSS of the high-frequency communication interface is connected with the lower end of the resistor Rc2; the lower end of the resistor Rc2 is connected with the anode of the diode D22; the cathode of the diode D22 is connected with the cathode of the bidirectional zener diode ZD; the anode of the bidirectional zener diode ZD is connected with the anode of the diode D12; the cathode of the diode D12 is connected with the lower end of the resistor Rc1, and the upper end of the resistor Rc1 is connected with the power supply end VDD of the high-frequency communication interface; under the zener breakdown auxiliary triggering action of the bidirectional zener diode ZD, the voltage drop across the resistor Rc1 can be rapidly increased to 0.7V, so as to promote the transistor Tc1 to trigger on.
The lower ends of the resistors Rc2 are connected with the emitter of the PNP transistor Tc1, the base of the PNP transistor Tc1 is connected with the collector of the NPN transistor Tc4, the base of the PNP transistor T22 is connected with the collector of the PNP transistor Tc1 is connected with the base of the NPN transistor Tc4, the emitter of the NPN transistor T32 is connected with the cathode of the diode D12 and the lower end of the resistor Rc 1; the emitter of the PNP transistor T22 is connected with the upper end of the resistor Rc2, the anode of the diode D22 is connected, the base of the PNP transistor T22 is connected with the collector of the NPN transistor T32, and the collector of the NPN transistor Tc4 is connected; the collector of the PNP transistor T22 is connected with the base of the NPN transistor T32, the anode of the bidirectional zener diode D12 is connected with the lower end of the resistor R32; the upper end of the resistor R32 is connected with the base electrode of the NPN transistor Tc4, the emitter electrode of the NPN transistor T32, and the cathode of the diode D12 is connected with the lower end of the resistor Rc 1; the emitter of the NPN transistor Tc4 is connected with the upper end of the resistor Rc1 and the power end VDD of the high-frequency communication interface;
under the positive feedback action of the SCR formed by the transistor Tc1 and the crystal Tc4, the third SCR current discharging path triggers and starts to discharge the ESD current. This further promotes the voltage drop of the resistor R32 to rise, pushes the transistor T32 to trigger and turn on, and under the positive feedback effect of the SCR formed by the transistor T32 and the transistor T22, the fourth SCR current discharging path triggers and turns on, so as to assist the third SCR current discharging path to trigger and discharge the electrostatic surge current, and enhance the robustness of the electrostatic surge protection circuit.
In the integrated circuit layout design, the transistor Tc1 and the transistor Tc4 have completely centrosymmetric physical layout under the action of forward and reverse electrostatic surge stress; the diode D12 and the diode D11 are in a central symmetry physical layout, the electrostatic surge protection circuit has an electrical symmetry characteristic under forward and reverse electrostatic surge stress, the diode D22 and the diode D21 share a P well, and the P well is positioned between the first SCR current discharging path and the third SCR current discharging path, so that a bidirectional protection function of electrostatic surge is realized, and the electrical characteristic has forward and reverse symmetry. The resistor Rc1 and the resistor Rc2 respectively play a role of bias auxiliary triggering under unidirectional electrostatic surge protection stress, so that on one hand, the transistor Tc1 and the transistor Tc4 are helped to be quickly started, on the other hand, parasitic capacitance of the electrostatic surge protection circuit is helped to be reduced, and data transmission efficiency of the high-frequency communication interface is improved.
The above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made thereto without departing from the spirit and scope of the technical solution of the present invention, which is intended to be covered by the scope of the claims of the present invention.
Claims (6)
1. An electrostatic surge protection circuit for a high frequency communication interface, comprising:
a trigger clamping circuit and two SCR current discharge paths; the trigger clamping circuit comprises a plurality of diodes, a resistor and a bidirectional zener diode, and the SCR current release path comprises a PNP transistor and an NPN transistor;
when a forward electrostatic surge stress acts on the electrostatic surge protection circuit, the trigger clamp circuit includes: resistor Rc1, diode D11, bidirectional zener diode ZD, diode D21, resistor Rc2; the first SCR current bleed path includes: a PNP transistor Tc1, an NPN transistor Tc4; the second SCR current bleed path includes: PNP transistor T21, NPN transistor T31, resistor R31;
when the power end VDD of the high-frequency communication interface is connected with high potential and the VSS is connected with low potential, the power end VDD of the high-frequency communication interface is connected with the upper end of the resistor Rc 1; the lower end of the resistor Rc1 is connected with the anode of the diode D11; the cathode of the diode D11 is connected with the cathode of the bidirectional zener diode ZD; the anode of the bidirectional zener diode ZD is connected with the anode of the diode D21; the cathode of the diode D21 is connected with the upper end of the resistor Rc2, and the lower end of the resistor Rc2 is connected with the ground terminal VSS of the high-frequency communication interface;
the power supply terminal VDD, the upper end of the resistor Rc1 is connected to the emitter of the PNP transistor Tc1, the base of the PNP transistor Tc1 is connected to the collector of the NPN transistor Tc4, the base of the PNP transistor T21 is connected to the collector of the PNP transistor Tc1, the base of the NPN transistor Tc4 is connected to the emitter of the NPN transistor T31, and the cathode of the diode D21 is connected to the upper end of the resistor Rc2; the emitter of the PNP transistor T21 is connected with the lower end of the resistor Rc1, the anode of the diode D11 is connected with the base of the PNP transistor T21, the collector of the NPN transistor T31 is connected with the collector of the NPN transistor Tc4; the collector of the PNP transistor T21 is connected with the base of the NPN transistor T31, the anode of the bidirectional zener diode is connected with the anode of the diode D21 and the upper end of the resistor R31; the lower end of the resistor R31 is connected with the base electrode of the NPN transistor Tc4, the emitter electrode of the NPN transistor T31, and the cathode of the diode D21 is connected with the upper end of the resistor Rc2; the emitter of the NPN transistor Tc4 is connected with the lower end of the resistor Rc2 and the ground terminal VSS of the high-frequency communication interface;
when reverse electrostatic surge stress acts on the electrostatic surge protection circuit, the trigger clamp circuit includes: the resistor Rc1, the diode D12, the bidirectional zener diode ZD, the diode D22 and the resistor Rc2; the third SCR current bleed path includes: the PNP transistor Tc1, the NPN transistor Tc4; the fourth SCR current bleed path includes: a PNP transistor T22, an NPN transistor T32, and a resistor R32;
when the ground terminal VSS of the high-frequency communication interface is connected with high potential and the power supply terminal VDD is connected with low potential, the ground terminal VSS of the high-frequency communication interface is connected with the lower end of the resistor Rc2; the lower end of the resistor Rc2 is connected with the anode of the diode D22; the cathode of the diode D22 is connected with the cathode of the bidirectional zener diode ZD; the anode of the bidirectional zener diode ZD is connected with the anode of the diode D12; the cathode of the diode D12 is connected with the lower end of the resistor Rc1, and the upper end of the resistor Rc1 is connected with the power supply end VDD of the high-frequency communication interface;
the lower ends of the resistors Rc2 are connected with the emitter of the PNP transistor Tc1, the base of the PNP transistor Tc1 is connected with the collector of the NPN transistor Tc4, the base of the PNP transistor T22 is connected with the collector of the PNP transistor Tc1 is connected with the base of the NPN transistor Tc4, the emitter of the NPN transistor T32 is connected with the cathode of the diode D12 and the lower end of the resistor Rc 1; the emitter of the PNP transistor T22 is connected with the upper end of the resistor Rc2, the anode of the diode D22 is connected, the base of the PNP transistor T22 is connected with the collector of the NPN transistor T32, and the collector of the NPN transistor Tc4 is connected; the collector of the PNP transistor T22 is connected with the base of the NPN transistor T32, the anode of the bidirectional zener diode D12 is connected with the lower end of the resistor R32; the upper end of the resistor R32 is connected with the base electrode of the NPN transistor Tc4, the emitter electrode of the NPN transistor T32, and the cathode of the diode D12 is connected with the lower end of the resistor Rc 1; the emitter of the NPN transistor Tc4 is connected with the upper end of the resistor Rc1 and the power supply end VDD of the high-frequency communication interface.
2. The circuit of claim 1, wherein the trigger clamp circuit regulates the trigger turn-on voltage and the clamp voltage of the electrostatic surge protection circuit by regulating the cascade number of diodes or zener diodes to meet the electrostatic and surge protection requirements of the high frequency communication interfaces of different power domains.
3. The circuit of claim 1, wherein a forward trigger clamp circuit is formed by the diode D11, the diode D21 and the bidirectional zener diode ZD, and a reverse trigger clamp circuit is formed by the diode D22, the diode D12 and the bidirectional zener diode ZD, and on one hand, the trigger clamp circuit reduces parasitic capacitance of the electrostatic surge protection circuit by using a diode and zener diode cascading method, and reduces influence of the electrostatic surge protection circuit on signal transmission capability of a high-frequency communication interface; on the other hand, by utilizing different breakdown mechanisms of the bidirectional zener diode ZD, the triggering opening speed and the triggering opening voltage of the electrostatic surge protection circuit are regulated and controlled, and the electrostatic surge discharging efficiency of the high-frequency communication interface is improved.
4. The circuit of claim 1, wherein as electrostatic surge stress increases, the first SCR current drain path opens earlier than the second SCR current drain path, the second SCR current drain path being located intermediate the first SCR current drain path, the third SCR current drain path opening earlier than the fourth SCR current drain path, the fourth SCR current drain path being located intermediate the third SCR current drain path, improving current conduction uniformity of the first SCR current drain path and the third SCR current drain path when reverse electrostatic surge stress acts on the electrostatic surge protection circuit; thereby enhancing the electrostatic surge protection capability of the high frequency communication interface.
5. The circuit of claim 1, wherein the bi-directional zener is located intermediate the first SCR current drain path and the second SCR current drain path, the third SCR current drain path and the fourth SCR current drain path, such that latch-up is avoided in the first SCR current drain path and the second SCR current drain path, and the third SCR current drain path and the fourth SCR current drain path, upon triggering on, to enhance latch-up resistance of the circuit.
6. The circuit of claim 1, wherein under the action of forward and reverse electrostatic surge stress, the layout shape and the relevant dimension parameters of the first SCR current leakage path and the third SCR current leakage path in the electrostatic surge protection circuit of the high-frequency communication interface are the same, the current leakage capacity is the same, the bidirectional zener is used for triggering clamping, and the first SCR current leakage path, the third SCR current leakage path and the bidirectional zener do not need to occupy additional chip area, so that the electrostatic surge protection efficiency can be improved; the second SCR current discharging path and the fourth SCR current discharging path are symmetrical in physical layout and electrical structure, the diode D11 and the diode D12 are also symmetrical in physical layout and electrical structure, the diode D21 and the diode D22 share a P well, and bidirectional protection effect of electrostatic surge can be achieved.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311653736.4A CN117674051A (en) | 2023-12-05 | 2023-12-05 | High-frequency communication interface static surge protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311653736.4A CN117674051A (en) | 2023-12-05 | 2023-12-05 | High-frequency communication interface static surge protection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117674051A true CN117674051A (en) | 2024-03-08 |
Family
ID=90063613
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311653736.4A Pending CN117674051A (en) | 2023-12-05 | 2023-12-05 | High-frequency communication interface static surge protection circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117674051A (en) |
-
2023
- 2023-12-05 CN CN202311653736.4A patent/CN117674051A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101392145B1 (en) | Circuit configurations to reduce snapback of a transient voltage suppressor | |
| US9634483B2 (en) | Electrostatic discharge (ESD) protection circuit with EOS and latch-up immunity | |
| CN102195280B (en) | Electro-static discharge protection circuit and semiconductor device | |
| US10587114B2 (en) | Bi-directional electrostatic discharge protection device for radio frequency circuits | |
| US10263419B2 (en) | Transient voltage protection circuits, devices, and methods | |
| US8369053B2 (en) | Discharge protection apparatus and method of protecting an electronic device | |
| CN108899317B (en) | Bidirectional transient voltage suppressor for auxiliary triggering SCR of diode string | |
| CN108807376B (en) | Bidirectional transient voltage suppressor of low-voltage MOS auxiliary trigger SCR | |
| US9536869B2 (en) | Electrostatic discharge protection apparatus and method therefor | |
| CN102227808B (en) | Esd protection | |
| CN108878417B (en) | Transient voltage suppressor with high-maintenance MOS auxiliary trigger SCR structure | |
| CN112599522B (en) | Quick-opening uniform-conduction bidirectional electrostatic surge protection IC | |
| CN113839374A (en) | ESD power protection circuit, working power supply and chip | |
| US8598938B2 (en) | Power switch | |
| US10833064B2 (en) | ESD protection circuit and integrated circuit for broadband circuit | |
| CN117674051A (en) | High-frequency communication interface static surge protection circuit | |
| US7087968B1 (en) | Electrostatic discharge protection circuit and semiconductor circuit therewith | |
| US11303118B2 (en) | Overvoltage protection | |
| EP1482554B1 (en) | Electrostatic discharge protection device | |
| CN114551435A (en) | Bidirectional electrostatic discharge protection device | |
| CN107946299B (en) | Load switch and electronic equipment | |
| CN103199090A (en) | Electrostatic protective circuit and battery protective circuit thereof | |
| US10388647B1 (en) | Transient voltage suppression device | |
| CN203277382U (en) | Electrostatic protection circuit and battery protection circuit thereof | |
| CN107403796B (en) | High-voltage ESD protection circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |